Method for producing a SOI structure, in particular suitable for photonic applications, and carrier substrate for the structure

Abstract

The invention relates to a method for producing a SOI structure, comprising the following steps: a) providing an initial substrate made of monocrystalline silicon, having an interstitial oxygen content of between 15 and 27 ppma according to standard ASTM'79 and a resistivity of less than 200 ohms.cm, the initial substrate being intended to form a carrier substrate for the SOI structure after having undergone the subsequent step b); b) applying a sequence of heat treatments to the initial substrate while it is devoid, at least on a front face, of a silicon oxide layer other than optionally a native oxide layer, the sequence consisting of: - a first heat treatment defined by a plateau at a temperature higher than 1200°C and lower than 1280°C and with a duration of between 1 second and 60 seconds, by a temperature decrease ramp of between 10°C / s and 70°C / s, and by an argon or argon-hydrogen atmosphere; followed by - a second heat treatment defined by a plateau at a temperature of between 900°C and 1100°C, without an intermediate step before this temperature, under a neutral or oxidising atmosphere, in order to form a carrier substrate comprising: - a stripped surface layer, with a thickness greater than 40 μm and having a micro-defect concentration (BMD) of less than 108 / cm3, and - an enriched deep layer, under the stripped surface layer, having a micro-defect concentration (BMD) of between 2.108 / cm3 and 5.1010 / cm3. The invention also relates to a carrier substrate and a SOI structure including the carrier substrate.

Description

Method for manufacturing an SOI structure particularly suitable for photonic applications, and support substrate for said structure

[0001] The present invention relates to the field of semiconductors and microelectronics. It relates to a method for manufacturing an SOI (Silicon on Insulator) structure, particularly suitable for photonic applications. The invention also relates to a support substrate for said structure. TECHNOLOGICAL BACKGROUND OF THE INVENTION:

[0002] In the field of SOI photonics, some techniques for coupling optical fibers with components require the creation of V-grooves by anisotropic chemical etching in the substrate supporting the SOI structure, to a depth of around 50 to 80 µm. In addition, it is increasingly sought to co-integrate components, allowing the front and back faces of the SOI structure to be electrically connected. Such a connection is traditionally made using through-silicon vias (TSVs) produced by dry etching the substrate supporting the SOI structure, typically to a depth of 50 to 100 µm.Note that the support substrate is thicker than 100µm throughout the SOI structure manufacturing and component development processes, but it is usually thinned on the back face in these thickness ranges, which allows the electrical contact to be recovered via the through via(s).

[0003] The presence of defects in the support substrate, such as bulk micro-defects (BMDs) well known in the monocrystalline silicon industry, can disrupt V-trench or via etchings and cause subsequent component failures. These BMDs arise from the precipitation of interstitial oxygen at preferential nucleation sites (e.g., vacancies) and are not favorable when deep etchings such as those described above are planned in the support substrate.

[0004] Furthermore, the manufacturing of SOI structures requires very high temperature thermal budgets. It can notably implement the Smart Cut process TMfor the transfer of the useful layer of monocrystalline silicon (c-Si) onto the support substrate, via a dielectric intermediate layer. The well-known Smart Cut process is based on the implantation of light ions into a c-Si donor substrate to form a buried fragile plane which defines, with the front face of the donor substrate, the useful layer to be transferred. The implanted donor substrate is then assembled on the support substrate. In general, a dielectric layer is formed on the donor substrate, on the support substrate or on both substrates, prior to assembly: this dielectric layer is intended to form the buried insulating layer of the SOI structure. The next step consists of a separation along the buried fragile plane, giving rise, on the one hand, to an intermediate structure comprising the useful layer transferred onto the support substrate via the dielectric layer, and on the other hand, the rest of the donor substrate.

[0005] After the separation of the useful layer and its transfer to the support substrate, heat treatments are required to smooth the free surface of the useful layer and to cure the crystal defects present in the latter. This implies that the support substrate of the SOI structure is resistant to failure modes such as slip lines, marks or other deformations likely to be generated during the heat treatment, due to temperature gradients or contact points between the substrate and holding elements in the oven. To protect the support substrate against these failures, it is advantageous for it to have a sufficient and homogeneous density of BMD micro-defects both radially and in depth, which micro-defects make it robust to mechanical deformation.In addition, BMD micro-defects allow the trapping of species (notably metallic contamination) in the support substrate, limiting the diffusion of contaminants to the useful layer during component manufacturing. SUBJECT OF THE INVENTION:

[0006] To reconcile the various constraints linked to the presence of BMD micro-defects in the support substrate of an SOI structure, the present invention proposes a method for manufacturing an SOI structure, particularly suitable for photonic applications, the support substrate of which comprises: a surface layer depleted in BMD micro-defects, having a thickness greater than 40 µm, typically between 40 µm and 100 µm, and a deep layer rich in BMD micro-defects, to guarantee stable mechanical behavior of the support substrate, and therefore of the SOI structure, during its manufacture and during the development of the components. BRIEF DESCRIPTION OF THE INVENTION:

[0007] The present invention relates to a method of manufacturing an SOI structure, comprising the following steps:

[0008] a) the provision of an initial substrate made of monocrystalline silicon, having an interstitial oxygen content of between 15 and 27 ppma according to the ASTM'79 standard and a resistivity of less than 200 ohms.cm, the initial substrate being intended to form a support substrate for the SOI structure after having undergone the subsequent step b):

[0009] b) applying a sequence of heat treatments to the initial substrate while it is devoid, at least on one front face, of a layer of silicon oxide other than possibly a layer of native oxide, said sequence consisting of:

[0010] - a first heat treatment defined by a plateau at a temperature above 1200°C and below 1280°C and lasting between 1 second and 60 seconds, by a temperature reduction ramp between 10°C / s and 70°C / s, and by an argon or argon-hydrogen type atmosphere, followed by

[0011] - a second heat treatment defined by a plateau at a temperature between 900°C and 1100°C, without a plateau before this temperature, under a neutral or oxidizing atmosphere, to form a support substrate comprising:

[0012] - a bare surface layer, thicker than 40 μm and with a BMD micro-defect concentration of less than 10 8 / cm 3 , And

[0013] - a deep enriched layer, under the bare surface layer, presenting a concentration of micro-defects between 2.10 8 / cm 3 and 5.10 10 / cm 3 .

[0014] According to advantageous characteristics of the invention, taken alone or in any feasible combination: the temperature of the plateau of the first heat treatment is between 1220°C and 1260°C; the second heat treatment is defined by temperature rise and fall ramps of between 0.5°C / min and 10°C / min; the temperature of the plateau of the second heat treatment is between 950°C and 1000°C; the atmosphere of the second heat treatment is oxidizing, at least during the plateau, to form, on the support substrate, all or part of a dielectric layer of silicon oxide, said dielectric layer being intended to be arranged between a useful layer and the support substrate in the SOI structure;the manufacturing method comprises, after step b) of applying the sequence of heat treatments, a step c) of oxidizing the support substrate to form, on the support substrate, all or part of a dielectric layer of silicon oxide, said dielectric layer being intended to be arranged between a useful layer and the support substrate in the SOI structure;the manufacturing method further comprises the following steps:d) the formation of an intermediate structure comprising the useful layer of monocrystalline silicon arranged on the dielectric layer, itself arranged on a front face of the support substrate, by a thin layer transfer technique,e) the application of a third heat treatment to the intermediate structure, at a temperature between 900°C and 1250°C, under a neutral or reducing atmosphere, to form the SOI structure.;

[0015] The invention also relates to a monocrystalline silicon support substrate, having:

[0016] - a resistivity lower than 200 ohm.cm,

[0017] - a bare surface layer, thicker than 40 μm, with a concentration of BMD micro-defects lower than 10 8 / cm 3 ,

[0018] - an enriched deep layer, under the bare surface layer, presenting a concentration of BMD micro-defects between 2.10 8 / cm 3 and 5.10 10 / cm 3 .

[0019] The support substrate may comprise a silicon oxide dielectric layer at least on its front face.

[0020] The invention finally relates to an SOI structure comprising a useful layer arranged on the dielectric layer, itself arranged on a support substrate as mentioned above.

[0021] The dielectric layer advantageously has a thickness of between 500nm and 2000nm.

[0022] Other characteristics and advantages of the invention will emerge from the detailed description which follows with reference to the appended figures in which:

[0023]

[0024]

[0025] Figures 1a, 1b and 1c show the steps of the method for manufacturing a support substrate for an SOI structure, in accordance with the invention;

[0026] The present invention presents an SOI structure comprising a support substrate in accordance with the invention;

[0027] The present sectional images of support substrates in accordance with the invention, obtained by light scattering tomography (LST); the measurement, made on each cleaved support substrate, is based on the collection of light scattered by the BMD micro-defects at the level of the edge of said support substrate;

[0028] The present sectional images of support substrates not in accordance with the invention, images also obtained by LST.

[0029] Some figures are schematic representations which, for readability purposes, are not to scale. In particular, the layer thicknesses along the z axis are not to scale with the lateral dimensions along the x and y axes.

[0030] The invention relates to a method for manufacturing an SOI 100 structure particularly suitable for photonic applications, which require in particular the formation of V-shaped trenches and conductive vias in the support substrate 10 of said structure 100. The SOI 100 structure comprises a thick buried dielectric layer, typically between 500nm and 2000nm.

[0031] The method comprises, firstly, a step a) corresponding to the provision of an initial substrate 10' made of monocrystalline silicon CZ (Czochralski growth process). The initial substrate 10' has a front face 10a and a rear face 10b, substantially parallel to a main plane (x,y) (). It advantageously takes the form of a circular wafer, with a diameter typically between 200mm and 450mm. Its total thickness, along the z axis normal to the main plane (x,y), can vary between a few hundred microns (for example 300 μm) and 1000 μm.

[0032] The initial substrate 10' has an interstitial oxygen content of between 15 and 27 ppma according to the ASTM'79 standard. Its resistivity is less than 200 ohms.cm, typically between 1 ohm.cm and 100 ohms.cm. The initial substrate 10' is intended to form a support substrate 10 for the SOI structure 100 after having undergone the subsequent step b).

[0033] Step b) corresponds to the application of a sequence of heat treatments to the initial bare substrate 10', i.e. devoid, at least on its front face 10a, of any layer of silicon oxide other than possibly a layer of native oxide. The sequence consists of two successive heat treatments, without any other intervening thermal cycle.

[0034] The first heat treatment is carried out in rapid thermal annealing equipment (RTA) and is defined by a temperature plateau, temperature rise and fall ramps and a gas atmosphere. The plateau temperature is above 1200°C and below 1280°C. Advantageously, it is between 1220°C and 1260°C, or even between 1220°C and 1250°C. The duration of the plateau can be from 1 second to 60 seconds. The fall ramp is between 10°C / s and 70°C / s. The rise ramp is also rapid, but can be chosen in a wider range than the fall ramp, in particular between 10°C / s and 100°C / s. The atmosphere during this first heat treatment is of the argon or argon-hydrogen type (typically Ar > 70%).A nitrogen atmosphere is not feasible because too many vacancies are injected into the substrate, particularly through the front face 10a, which does not promote the depletion of vacancies in a very thick surface layer. An oxidizing atmosphere is also to be avoided because it helps to compensate for the injection of vacancies, particularly in a deep layer of the substrate which, on the contrary, we wish to enrich in vacancies.

[0035] This first heat treatment applied to the initial bare substrate 10' makes it possible to generate a profile of vacancies in its depth, namely a low concentration of vacancies in a surface layer 11',13' and a high concentration of vacancies in a deep layer 12'.

[0036] By surface layer 11', 13' is meant a layer whose thickness starts at a free face 10a, 10b of the initial substrate 10' (in particular, its front face 10a, but potentially also its rear face 10b) and extends over a depth greater than or equal to 40μm in the volume of said substrate 10' (). Note that a surface layer 13' with a low concentration of vacancies can be formed on the side of the rear face 10b of the initial substrate 10', if said rear face 10b is – like the front face 10a – bare, during the first heat treatment.

[0037] By deep layer 12' is meant a layer which is located under the surface layer 11', 13' (starting from the free face of the surface layer considered), and which extends into the volume of the initial substrate 10'. This deep layer with a high concentration of vacancies can for example extend between the surface layer 11' on the front face 10a and that 13' on the rear face 10b of the initial substrate 10'. Later in the thermal sequence applied to the initial substrate 10', the vacancies will help to fix oxygen precipitates where they are present, by constituting preferential nucleation sites.

[0038] During the plateau of the first heat treatment, vacancies can be generated everywhere in the initial substrate 10', on the surface as well as in depth, with a density depending on the thermal budget applied. During the temperature decrease, these vacancies diffuse very quickly, the probability that they recombine at the surface is greater if we are close to the surface, we therefore have a gradient of vacancies at the surface, which can be modulated in particular by the speed of temperature decrease: the faster we decrease, the more we will freeze the vacancies in place and recombine at the surface, which gives rise to a surface layer depleted in vacancies of small thickness; the slower we decrease, the more the vacancy concentration gradient will be pronounced, which results in a surface layer of greater thickness.However, below a certain temperature reduction rate, even deep vacancies tend to diffuse and recombine at the surface, which negatively impacts the expected deep vacancy-rich layer. The annealing atmosphere also has an impact: compared to an argon atmosphere, an argon-hydrogen atmosphere adds a participation of hydrogen (which diffuses quickly in the initial substrate 10') to the passivation of vacancies, at the surface but also deeper down, which can increase the thickness of the surface layer. Conversely, under certain application conditions, an Ar / H atmosphere can reduce the vacancy concentration of the deep layer, which is not desirable.

[0039] The above-mentioned conditions of the first heat treatment (plate temperatures, ramps, durations, atmospheres) provide the right compromise to generate a surface layer thickness 11', 13' depleted in vacancies, typically between 40 μm and 100 μm, and a deep layer 12' very rich in vacancies. In addition, these conditions avoid, or at least limit, the creation of defects such as SL slip lines or PM pinmarks in or on the initial substrate 10', which are detrimental to the future SOI structure.

[0040] In the sequence according to the invention, the first heat treatment is followed by a second heat treatment, defined by a plateau at a temperature between 900°C and 1100°C, without a plateau before this temperature. Preferably, the temperature of the plateau is between 950°C and 1000°C. The duration of the plateau is typically between 2 hours and several tens of hours, for example 40 hours. The temperature rise and fall ramps are advantageously between 0.5°C / min and 10°C / min and may optionally be different from each other. The atmosphere of the second heat treatment may be neutral or oxidizing. This second heat treatment is advantageously carried out in a conventional furnace (with vertical or horizontal tube).

[0041] The second heat treatment promotes the precipitation of oxygen on the vacancies distributed in the substrate 10' according to the profile frozen during the first heat treatment. The precipitation is made possible by the presence of interstitial oxygen, which recalls the importance of the choice of the range of interstitial oxygen contents of the initial substrate 10' provided in step a) of the process.

[0042] The second heat treatment is also defined so as not to passivate or recombine the vacancies before they have helped create BMD micro-defects.

[0043] This sequence of heat treatments is essential to form the target support substrate 10, of which a stripped surface layer 11,13 (from the surface layer 11',13'), with a thickness greater than or equal to 40 μm, has a concentration of BMD micro-defects less than 10 8 / cm 3, and of which an enriched deep layer 12 (from the deep layer 12'), under the bare surface layer 11,13, presents a concentration of BMD micro-defects of between 2.10 8 / cm 3 and 5.10 10 / cm 3 . Let us recall that the density and potentially the size of BMD micro-defects are classically measured by light scattering tomography (LST for “Light Scattering Tomography”), at the level of the slice (in the (y,z) plane in the figures) of the support substrate 10.

[0044] The support substrate 10 obtained also has excellent mechanical quality, with a very low density of SL or PM type defects, or even none of these defects, at the end of the heat treatment sequence. The absence (or very low density) of these defects, and the concentration of BMD micro-defects greater than or equal to 2x10 8 / cm 3will give the support substrate 10 great mechanical robustness during subsequent heat treatments at high temperatures, and avoid SL slip line type failures in the future SOI structure (both during its development and during that of the components). The stripped surface layer 11, 13, which can extend over a thickness of between 40 μm and 100 μm, is particularly suitable for the formation of V-shaped trenches or vias, during the manufacture of components on and / or in the SOI structure 100.

[0045] According to a particular embodiment of the method, the atmosphere of the second heat treatment is oxidizing, at least during the plateau, to form, on the support substrate 10, all or part of a dielectric layer of silicon oxide, said dielectric layer 20 being intended to be arranged between a useful layer 30 and the support substrate 10 in the SOI structure 100. This embodiment is advantageous in that it makes it possible to combine two functions of the second heat treatment and to rationalize the thermal steps applied to the support substrate 10.

[0046] For example, to form a 2 μm dielectric layer on the support substrate 10, the second heat treatment may be defined by temperature rise ramps of a few degrees per minute, up to 1000°C, under an argon atmosphere with a low oxygen supply, a plateau at a temperature of 1000°C under an oxidizing atmosphere, and a fall ramp of a few degrees per minute.

[0047] According to another embodiment, the manufacturing method comprises, after step b) of applying the sequence of heat treatments, a step c) of oxidation of the support substrate 10 to form, on said support substrate, all or part of a dielectric layer of silicon oxide; the dielectric layer 20 is intended to be arranged between a useful layer 30 and the support substrate 10 in the SOI structure 100. The oxidation step c) has no negative influence on the stripped surface layer 11, 13 and the enriched deep layer 12, because the precipitation of oxygen on the vacancies took place during the second heat treatment. Step c) can then induce an increase in the size of the BMD micro-defects.

[0048] Let us recall that photonic applications on silicon generally require SOI structures comprising a thick buried dielectric layer, typically between 500nm and 2000nm. This thickness being significant, the dielectric layer 20 is preferably (or at least in the vast majority) grown on the support substrate 10, because a high thickness of dielectric layer on the front face of the donor substrate (in reference to the Smart Cut process) makes it difficult to form the buried fragile plane by ion implantation.

[0049] Lamontre two examples of support substrate 10 produced according to a method in accordance with the invention. In particular, the sequence of step b) consisted of a first heat treatment defined by a plateau at a temperature between 1220°C and 1260°C, lasting between 1 second and 60 seconds, and by a temperature reduction ramp between 10°C / s and 70°C / s, followed by a second heat treatment defined by a plateau at a temperature between 950°C and 1000°C, without a plateau before this temperature, under an oxidizing atmosphere. The images were obtained by LST.In both cases, we observe a stripped surface layer 11 and a deep layer enriched in BMD 12; the thickness of the stripped surface layer 11 can be greater thanks to the implementation of an Ar / H atmosphere during the first heat treatment: in the left image of the, the thickness of the stripped surface layer 11 is approximately 70 μm for an Ar atmosphere, while in the right image, the thickness of the stripped layer 11 is approximately 90 μm for an Ar / H atmosphere, with a hydrogen concentration lower than 30%. The support substrate 10, in both examples, has good mechanical quality with no or very few SL and PM defects.

[0050] The present two examples of support substrates whose manufacturing process is not in accordance with the present invention. A plateau temperature at the first heat treatment of 1200°C (or lower), even under an Ar / H atmosphere and using a temperature reduction ramp of between 10°C / s and 70°C / s, does not allow the expected gap profile to be generated: at the end of the heat treatment sequence, the support substrate (outside the invention) does not have a stripped surface layer (example on the left in the).Furthermore, using a first heat treatment defined by a plateau at a temperature between 1220°C and 1280°C, lasting between 1 second and 60 seconds, even under an Ar / H atmosphere, it appears that a temperature reduction ramp that is too slow during the first heat treatment is detrimental to the preservation of a marked gap profile: for example, with a reduction ramp of 5°C / s, the support substrate at the end of the heat treatment sequence does not present an enriched deep layer (example on the right).

[0051] After obtaining the support substrate 10, the manufacturing method according to the invention further comprises a step d) corresponding to the formation of an intermediate structure comprising the useful layer 30 of monocrystalline silicon arranged on the dielectric layer 20, itself arranged on a front face 10a of said support substrate 10, by a thin layer transfer technique such as the Smart Cut process. TM .

[0052] A monocrystalline silicon donor substrate is implanted by its front face, so as to define a buried fragile plane substantially parallel to said front face and delimiting, with the latter, the thin layer to be transferred. The implantation is usually carried out with light species such as hydrogen ions, helium ions or a combination of these two species. The fragile plane is so named because it includes nano-cracks in lenticular form generated by the implanted light species.

[0053] According to a preferred option, mentioned previously, a dielectric layer 20 is formed at least on the front face 10a of the support substrate 10. It is not excluded, however, that a part of the buried dielectric layer of the future SOI structure is produced on the donor substrate.

[0054] The donor substrate and the support substrate 10 are then assembled, by direct bonding between the front faces of said substrates, to form a bonded assembly. Surface cleaning and / or activation, well known in the field of molecular adhesion bonding, may be applied to the substrates prior to assembly, to obtain excellent bonding quality. Assembly in a controlled atmosphere is also possible.

[0055] Separation at the buried fragile plane is preferably achieved by applying a heat treatment at medium temperature, typically between 350°C and 500°C, due to the growth of microcracks by coalescence and pressurization of gaseous species. Alternatively or jointly, separation can be caused by applying mechanical stress to the bonded assembly.

[0056] At the end of this separation, an intermediate structure of the SOI type is obtained, on the one hand, and the rest of the donor substrate, on the other hand. Finishing sequences, including cleaning, surface treatments (etching, polishing, etc.) and / or heat treatments, are usually applied to the intermediate SOI structure, and aim to remove a superficial part of the transferred useful layer 30. This makes it possible to restore a good surface condition (defectivity and roughness) and a good crystalline quality to the useful silicon layer 30. The useful layer 30 typically has a thickness of between 50 nm and 500 nm.

[0057] The manufacturing method then comprises a step e) of applying a third heat treatment to the intermediate structure, at a temperature between 900°C and 1250°C, under a neutral or reducing atmosphere, to form the SOI structure. Such a heat treatment does not affect the stripped surface layer 11, 13 and the deep layer enriched in BMD 12, induced by the sequence of the first and second heat treatments. It can advantageously induce an increase in the size of the BMD micro-defects.

[0058] As a result, the SOI 100 structure is available.

[0059] The invention also relates to a support substrate 10 made of monocrystalline silicon, particularly suitable for SOI structures aimed in particular at photonic applications, the support substrate 10 having:

[0060] - a resistivity lower than 200 ohm.cm,

[0061] - a bare surface layer 11,13, with a thickness greater than 40 μm, having a concentration of micro-defects (BMD) less than 10 8 / cm 3 ,

[0062] - a deep enriched layer 12, under the surface layer, presenting a concentration of micro-defects (BMD) between 2.10 8 / cm 3 and 5.10 10 / cm 3 .

[0063] The support substrate 10 may further comprise a silicon oxide dielectric layer on its front face 10a and / or on its rear face 10b. Preferably, said dielectric layer has a thickness of between 500nm and 2000nm.

[0064] Finally, the invention relates to an SOI structure comprising a useful layer 30 made of c-Si arranged on the dielectric layer 20, itself arranged on the aforementioned support substrate 10. This SOI structure is particularly suitable for the manufacture of photonic components on and / or in the useful layer 30 as well as in the support substrate 10 (in particular, V-shaped trenches and conductive vias).

[0065] Of course, the invention is not limited to the embodiments described or to the field of photonic applications, and variants of embodiment or use can be made thereto, without departing from the scope of the invention.

Claims

A method of manufacturing an SOI structure (100), comprising the following steps: a) providing an initial substrate (10') made of monocrystalline silicon, having an interstitial oxygen content of between 15 and 27 ppma according to the ASTM'79 standard and a resistivity of less than 200 ohms.cm, the initial substrate (10') being intended to form a support substrate (10) for the SOI structure (100) after having undergone the subsequent step b): b) applying a sequence of heat treatments to the initial substrate (10') while it is devoid, at least on a front face (10a), of a layer of silicon oxide other than possibly a layer of native oxide, said sequence consisting of: - a first heat treatment defined by a plateau at a temperature greater than 1200°C and less than 1280°C and of a duration of between 1 second and 60 seconds, by a temperature reduction ramp between 10°C / s and 70°C / s,and by an argon or argon-hydrogen type atmosphere, followed by- a second heat treatment defined by a plateau at a temperature between 900°C and 1100°C, without a plateau before this temperature, under a neutral or oxidizing atmosphere, to form a support substrate (10) comprising:- a stripped surface layer (11), with a thickness greater than 40 μm and having a micro-defect concentration (BMD) less than 10, 8 / cm 3 , and- an enriched deep layer (12), under the bare surface layer (11), having a concentration of micro-defects (BMD) between 2.10 8 / cm 3 and 5.10 10 / cm 3 . Manufacturing method according to claim 1, wherein the temperature of the plateau of the first heat treatment is between 1220°C and 1260°C. Manufacturing method according to one of claims 1 and 2, in which the second heat treatment is defined by temperature rise and fall ramps of between 0.5°C / min and 10°C / min. Manufacturing method according to one of claims 1 to 3, in which the temperature of the plate of the second heat treatment is between 950°C and 1000°C. Manufacturing method according to one of claims 1 to 4, in which the atmosphere of the second heat treatment is oxidizing, at least during the plateau, to form, on the support substrate (10), all or part of a dielectric layer of silicon oxide, said dielectric layer (20) being intended to be arranged between a useful layer (30) and the support substrate (10) in the SOI structure (100). Manufacturing method according to one of claims 1 to 5, comprising, after step b) of applying the sequence of heat treatments, a step c) of oxidation of the support substrate (10) to form, on the support substrate (10), all or part of a dielectric layer of silicon oxide, said dielectric layer (20) being intended to be arranged between a useful layer (30) and the support substrate (10) in the SOI structure (100). Manufacturing method according to one of claims 5 and 6, further comprising the following steps:d) forming an intermediate structure comprising the useful layer (30) of monocrystalline silicon arranged on the dielectric layer (20), itself arranged on a front face (10a) of the support substrate (10), by a thin layer transfer technique,e) applying a third heat treatment to the intermediate structure, at a temperature between 900°C and 1250°C, under a neutral or reducing atmosphere, to form the SOI structure (100). Support substrate (10) made of monocrystalline silicon, having:- a resistivity of less than 200 ohm.cm,- a stripped surface layer (11,13), with a thickness greater than 40 μm, having a concentration of micro-defects (BMD) of less than 10 8 / cm 3- an enriched deep layer (12), under the bare surface layer (11,13), presenting a concentration of micro-defects (BMD) between 2.10 8 / cm 3 and 5.10 10 / cm 3 . Support substrate (10) according to claim 8, comprising a dielectric layer (20) of silicon oxide at least on its front face (10a). SOI structure (100) comprising a useful layer (30) arranged on the dielectric layer (20), itself arranged on a support substrate (10) according to claim 9. Structure (100) according to the preceding claim, in which the dielectric layer (20) has a thickness of between 500nm and 2000nm.

Images