Output buffer and data driver circuit having same

Abstract

An output buffer, according to one embodiment of the present invention, comprises: an input stage that monitors the difference between an input voltage and an output voltage; a current summing stage that generates amplified currents and control voltages according to the difference between the input voltage and the output voltage monitored by the input stage; an output stage that performs a pull-up or pull-down operation according to the control voltages outputted from the current summing stage so as to generate an output voltage at an output terminal; and a slew boost circuit that monitors the difference between the input voltage and the output voltage to perform a slew boost operation that adjusts some of currents provided by the current summing stage to the input stage according to the difference between the input voltage and the output voltage, and monitors the control voltages to selectively perform the slew boost operation.

Description

Output buffer and data driver circuit having it

[0001] The present invention relates to an output buffer capable of increasing the slew rate of an output voltage to enable high-speed driving and reduce power consumption, and a data driver circuit having the same.

[0002] The display device includes a panel that displays an image through a pixel matrix, a gate driver circuit that drives gate lines of the panel, a data driver circuit that supplies data signals to data lines of the panel, and a timing controller that controls the gate driver circuit and the data driver circuit.

[0003] The data driver circuit includes an output buffer section to prevent the data signal supplied to the data line from being distorted by the load component. Circuits other than the data driver circuit may also include an output buffer to prevent distortion of the output signal.

[0004] As display devices evolve toward high-speed operation, output buffers require high-speed operation methods that can increase the slew rate of the output voltage, as well as methods that can reduce power consumption.

[0005] The present invention provides an output buffer and a data driver circuit having the same, which can increase the slew rate of an output voltage to enable high-speed driving and reduce power consumption.

[0006] An output buffer according to one embodiment of the present invention comprises: an input stage that monitors a difference between an input voltage and an output voltage; a current adding stage that generates amplified currents and control voltages according to the difference between the input voltage and the output voltage monitored by the input stage; an output stage that generates the output voltage at an output terminal by performing a pull-up or pull-down operation according to the control voltages output from the current adding stage; And a slew boost circuit that monitors the difference between the input voltage and the output voltage and performs a slew boost operation for adjusting a portion of the currents provided to the input stage from the current adding stage according to the difference between the input voltage and the output voltage, and monitors the control voltages to selectively perform the slew boost operation, wherein the current adding stage includes a first current mirror including PMOS transistors connected in a current mirror structure to a first power (AVDDH) supply line; and a second current mirror including NMOS transistors connected in a current mirror structure to a second power (AVSS) supply line; and the slew boost circuit includes a third current mirror including NMOS transistors connected in a current mirror structure to the second power (AVSS) supply line; and a fourth current mirror including PMOS transistors connected in a current mirror structure to the first power (AVDDH) supply line; wherein the third current mirror is connected to the second current mirror, and the fourth current mirror is connected to the first current mirror.

[0007] In addition, the slew boost circuit may further increase one sink current that increases according to the difference between the input and output voltages among the currents provided to the input stage from the current adding stage, or further increase one source current that increases according to the difference between the input and output voltages, thereby controlling the current provided to the output stage from the current adding stage and the control voltages.

[0008] In addition, the input stage may include a first input section including PMOS transistors each controlled by the input voltage and the output voltage; a second input section including NMOS transistors each controlled by the input voltage and the output voltage; a first bias circuit including a PMOS transistor controlled by a first bias voltage to provide a bias current to the first input section; and a second bias circuit including an NMOS transistor controlled by a second bias voltage to provide a bias current to the second input section.

[0009] In addition, the current adding stage may include: the first current mirror; a first cascode circuit including PMOS transistors connected in series with the first current mirror and controlled by a third bias voltage; the second current mirror; a second cascode circuit including NMOS transistors connected in series with the second current mirror and controlled by a fourth bias voltage; a third bias circuit connected to a current path between the first cascode circuit and the second cascode circuit, the third bias circuit including a PMOS transistor and an NMOS transistor controlled by a fifth bias voltage and a sixth bias voltage, respectively; and a fourth bias circuit connected to a current path between the first cascode circuit and the second cascode circuit, the fourth bias circuit including a PMOS transistor and an NMOS transistor controlled by a seventh bias voltage and an eighth bias voltage, respectively.

[0010] In addition, the output stage may include a capacitor section including a pull-up PMOS transistor controlled by a first control voltage generated at a first output node between the first cascode circuit and the fourth bias circuit and connected between the first power supply line and the output terminal; a pull-down NMOS transistor controlled by a second control voltage generated at a second output node between the second cascode circuit and the second bias circuit and connected between the output terminal and the second power supply line; a first capacitor connected between a third output node between the first current mirror and the first cascode circuit and the output terminal; and a second capacitor connected between a fourth output node between the second current mirror and the second cascode circuit and the output terminal.

[0011] In addition, the slew boost circuit may include a first current control unit that controls, together with the input stage, one source current provided to the current summing stage according to a difference between the input voltage and the output voltage; a first switching unit that is controlled by the first control voltage and includes a PMOS transistor connected between the first power supply line and the first current control unit; the third current mirror that includes NMOS transistors connected between the first current control unit and the second power supply line; a second current control unit that controls, together with the input stage, one sink current provided from the current summing stage according to a difference between the input voltage and the output voltage; a second switching unit that is controlled by the second control voltage and includes an NMOS transistor connected between the second current control unit and the second power supply line; and the fourth current mirror that includes PMOS transistors connected between the second current control unit and the first power supply line.

[0012] In addition, the first switching unit may include providing a bias current to the first current control unit when the first control voltage is a gate-on voltage and blocking a current flow of the first current control unit when the first control voltage is a gate-off voltage, and the second switching unit may include providing a bias current to the second current control unit when the second control voltage is a gate-on voltage and blocking a current flow of the second current control unit when the second control voltage is a gate-off voltage.

[0013] In addition, the first current control unit may include a third input unit including PMOS transistors each controlled by the input voltage and the output voltage; a fifth bias circuit controlled by the first bias voltage and connected between the first power supply line and the PMOS transistor of the first switching unit; and an NMOS transistor connected in a diode structure between the PMOS transistor controlled by the input voltage in the third input unit and the second power supply line, and the second current control unit may include a fourth input unit including NMOS transistors each controlled by the input voltage and the output voltage; a sixth bias circuit controlled by the second bias voltage and connected between the NMOS transistor of the second switching unit and the second power supply line; and a PMOS transistor connected in a diode structure between the first power supply line and the NMOS transistor controlled by the input voltage in the fourth input unit.

[0014] Additionally, the third current mirror may include regulating the source current provided from the current adding stage together with the third input unit.

[0015] The fourth current mirror may include, together with the fourth input unit, regulating the sink current provided through the input stage in the current adding stage.

[0016] In addition, the slew boost circuit may include performing a slew boost operation when the input voltage and the output voltage have a difference equal to or greater than a predetermined voltage and one of the control voltages is a gate-on voltage, and turning off the slew boost operation when the input voltage and the output voltage are the same and the control voltages are gate-off voltages.

[0017] A data driver circuit according to one embodiment of the present invention includes a digital-to-analog conversion unit that converts input digital data into an analog data signal and outputs the converted analog data signal; and an output buffer unit that includes an output buffer according to any one of claims 1 to 11 for each channel to buffer an input data signal supplied from the digital-to-analog conversion unit and output an output data signal to an output channel.

[0018] An output buffer according to one embodiment of the present invention monitors the control voltage of the output stage together with the input / output voltages by a slew boost circuit, and when the difference between the input / output voltages is greater than a certain voltage and the control voltage of the output stage changes by a certain voltage or more, indirectly controls the output current provided to the output stage by adjusting the sink current and source current of the current adding stage, thereby shortening the rise time and fall time of the output voltage, thereby increasing the slew rate and enabling high-speed driving.

[0019] An output buffer according to one embodiment of the present invention can reduce power consumption by blocking unnecessary current (DC) flow when input and output voltages are the same by turning the slew boost circuit on or off according to the control voltage of the output stage.

[0020] According to one aspect of one embodiment of the present invention, a data driver circuit can be driven at high speed and reduce power consumption by including the above-described output buffer.

[0021] The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

[0022] FIG. 1 is a block diagram showing the configuration of an output buffer according to one embodiment of the present invention.

[0023] Figure 2 is an equivalent circuit diagram showing the configuration of an output buffer according to one embodiment of the present invention.

[0024] Figure 3 is an equivalent circuit diagram showing the configuration of an output buffer according to one embodiment of the present invention.

[0025] Figures 4 to 7 are diagrams showing the current path of an output buffer according to one embodiment of the present invention.

[0026] Figure 8 is a driving waveform diagram of an output buffer according to one embodiment of the present invention.

[0027] FIG. 9 is a block diagram showing the configuration of a data driver circuit according to one embodiment of the present invention.

[0028] Fig. 10 is an equivalent circuit diagram showing the configuration of an output buffer section of a data driver circuit according to one embodiment of the present invention.

[0029] Figure 11 is a block diagram showing the configuration of a display device according to one embodiment of the present invention.

[0030] For example, an output buffer and a data driver having the same according to one embodiment can be applied to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a curved device, an electronic notebook, an electronic book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation, a navigation system, a vehicle navigation system, a vehicle display device, a television, a wallpaper display device, a signage device, a game device, a notebook, a monitor, a camera, a camcorder, and home appliances.

[0031] Since the content of the specification described in the problem to be solved, the means for solving the problem, and the effect described above does not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

[0032] While the embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be implemented without departing from the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims

1. The current mirror is an output buffer connected to the first current mirror.

2. In paragraph 1, The above slew boost circuit, When the input voltage and the output voltage differ by a certain voltage or more, the current adding stage additionally increases one sink current among the currents provided to the input stage that increases according to the difference between the input and output voltages, or An output buffer that additionally increases one of the source currents that increases according to the difference between the input and output voltages, thereby controlling the current provided from the current adding stage to the output stage and the control voltages.

3. In paragraph 1, The above input stage is, A first input section including PMOS transistors each controlled by the input voltage and the output voltage; A second input section including NMOS transistors each controlled by the input voltage and the output voltage; A first bias circuit including a PMOS transistor that provides a bias current to the first input section under control of a first bias voltage; and An output buffer comprising a second bias circuit including an NMOS transistor providing a bias current to the second input section, the second bias circuit being controlled by a second bias voltage.

4. In paragraph 3, The above current adding stage is, The above first current mirror; A first cascode circuit including PMOS transistors connected in series with the first current mirror and controlled by a third bias voltage; The second current mirror; A second cascode circuit including NMOS transistors connected in series with the second current mirror and controlled by a fourth bias voltage; A third bias circuit including a PMOS transistor and an NMOS transistor, which are connected to a current path between the first cascode circuit and the second cascode circuit and are controlled by a fifth bias voltage and a sixth bias voltage, respectively; and An output buffer including a fourth bias circuit connected to a current path between the first cascode circuit and the second cascode circuit and including a PMOS transistor and an NMOS transistor controlled by a seventh bias voltage and an eighth bias voltage, respectively.

5. In paragraph 4, The above output stage, A pull-up PMOS transistor controlled by a first control voltage generated at a first output node between the first cascode circuit and the fourth bias circuit, and connected between the first power supply line and the output terminal; A pull-down NMOS transistor controlled by a second control voltage generated at a second output node between the second cast circuit and the second bias circuit, and connected between the output terminal and the second power supply line; A first capacitor connected between the third output node and the output terminal between the first current mirror and the first cascode circuit; and An output buffer including a capacitor section including a second capacitor connected between the fourth output node and the output terminal between the second current mirror and the second cascode circuit.

6. In paragraph 5, The above slew boost circuit, A first current control unit that controls one source current provided to the current adding stage together with the input stage according to the difference between the input voltage and the output voltage; A first switching unit including a PMOS transistor controlled by the first control voltage and connected between the first power supply line and the first current control unit; The third current mirror including NMOS transistors connected between the first current control unit and the second power supply line; A second current control unit that controls one sink current provided from the current adding stage together with the input stage according to the difference between the input voltage and the output voltage; A second switching unit controlled by the second control voltage and including an NMOS transistor connected between the second current control unit and the second power supply line; and An output buffer including the fourth current mirror including PMOS transistors connected between the second current control unit and the first power supply line.

7. In paragraph 6, The above first switching unit, When the first control voltage is a gate-on voltage, a bias current is provided to the first current control unit, and when the first control voltage is a gate-off voltage, the current flow of the first current control unit is blocked. The above second switching unit, An output buffer that provides a bias current to the second current control unit when the second control voltage is a gate-on voltage and blocks the current flow of the second current control unit when the second control voltage is a gate-off voltage.

8. In paragraph 7, The above first current control unit, A third input section including PMOS transistors each controlled by the input voltage and the output voltage; A fifth bias circuit controlled by the first bias voltage and connected between the first power supply line and the PMOS transistor of the first switching unit; and In the third input section, an NMOS transistor is included, which is connected in a diode structure between the PMOS transistor controlled by the input voltage and the second power supply line, The above second current control unit, A fourth input section including NMOS transistors each controlled by the input voltage and the output voltage; A sixth bias circuit controlled by the second bias voltage and connected between the NMOS transistor of the second switching unit and the second power supply line; and An output buffer including a PMOS transistor connected in a diode structure between the first power supply line and an NMOS transistor controlled by the input voltage in the fourth input section.

9. In paragraph 8, The above third current mirror, Connected to the second current mirror, An output buffer for regulating the source current provided from the current summing stage together with the third input section.

10. In paragraph 9, The above fourth current mirror, Connected to the above first current mirror, An output buffer for regulating the sink current provided through the input stage in the current adding stage together with the fourth input section.

11. In paragraph 1, The above slew boost circuit, When the input voltage and the output voltage have a difference greater than or equal to a predetermined voltage and one of the control voltages is a gate-on voltage, a slew boost operation is performed, An output buffer in which the slew boost operation is turned off when the input voltage and the output voltage are equal and the control voltages are gate-off voltages.

12. A digital-to-analog conversion unit that converts input digital data into an analog data signal and outputs it; and A data driver circuit including an output buffer section having an output buffer according to any one of claims 1 to 11 for each channel to buffer an input data signal supplied from the digital-to-analog conversion section and output an output data signal to an output channel.

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