MOIRÉ synaptic transistors and applications of same

Abstract

The invention relates to moiré synaptic transistors and crossbar array comprising M columns and N rows of moiré synaptic transistors. The moiré synaptic transistor comprises a top gate, a bottom gate, and an asymmetric moiré heterostructure disposed between the top gate and the bottom gate; and a source and a drain spatial-apart formed on the asymmetric moiré heterostructure to define a conductance channel in the asymmetric moiré heterostructure therebetween, and wherein the top gate and the bottom gate are capacitively coupled with the conductance channel.

Description

[0001] Attorney Docket No.: 0116936.300WO2 MOIRÉ SYNAPTIC TRANSISTORS AND APPLICATIONS OF SAME STATEMENT AS TO RIGHTS UNDER FEDERALLY-SPONSORED RESEARCH This invention was made with government support under grant numbers 1720139, 1541959, 2235945, and 1936263 awarded by the National Science Foundation and grant number FA9550-21-1-0319 awarded by the United States Air Force Office of Scientific Research. The government has certain rights in the invention. CROSS-REFERENCE TO RELATED PATENT APPLICATION This application claims priority to and the benefit of U.S. Provisional Application Serial No.63 / 601,965, filed November 22, 2023, which is incorporated herein in its entirety by reference. FIELD OF THE INVENTION The present invention generally relates to electronics, particularly to moiré synaptic transistors and applications of the same. BACKGROUND OF THE INVENTION The background description provided herein is to present the context of the invention generally. The subject matter discussed in the background of the invention section should not be assumed to be prior art merely due to its mention in the background of the invention section. Similarly, a problem mentioned in the background of the invention section or associated with the subject matter of the background of the invention section should not be assumed to have been previously recognized in the prior art. The subject matter in the background of the invention section merely represents different approaches, which in and of themselves may also be inventions. Work of the presently named inventors, to the extent it is described in the background of the invention section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the invention. The ubiquity of artificial intelligence (AI) and machine learning (ML) has created an urgent demand for alternative computing paradigms that can handle vast quantities of data in an energy-efficient manner. Conventional digital computing hardware relies on the von Neumann Attorney Docket No.: 0116936.300WO2 architecture with spatially separated memory and information processing blocks, thus requiring frequent data transfer with severe consequences for power consumption. These concerns about increased power consumption in digital electronics and cloud computing have increased tremendously in the era of big data. Neuromorphic computing is an emerging approach to circumvent the von Neumann bottleneck that takes inspiration from the human brain (e.g., co- location of memory and logic, parallel processing, and hyperconnectivity) to enable low-power operation without requiring access to the cloud. The major bottleneck in neuromorphic hardware is a fast, stable, and scalable non-volatile memory element that can emulate the synaptic behavior of biological neural networks. Common candidates, such as memristors, phase change memories, and synaptic transistors, rely on conductive filament formation and rupture, defect migration, charge trapping, material phase change, and ferroelectricity. The performance metrics of these technologies are limited by these physical mechanisms implying that existing synaptic transistors typically possess drawbacks of limited switching speed and endurance, large device-to-device variations, redundant forming processes, uncontrollable stochasticity, high voltage operation, and a limited number of non-volatile conductance states. In addition, memristive synaptic devices typically do not incorporate the additional functionality that underlies the reconfigurable learning behavior of biological neural networks. Moiré synaptic transistors in this work rely on a purely electronic mechanism that has the potential to overcome these limitations while also enabling bio-realistic neural networks. Therefore, a heretofore unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies. SUMMARY OF THE INVENTION In one aspect, this invention relates to a moiré synaptic transistor (MST) comprising a top gate, a bottom gate, and an asymmetric moiré heterostructure disposed between the top gate and the bottom gate. In one embodiment, the moiré synaptic transistor further comprises a source and a drain spatial-apart formed on the asymmetric moiré heterostructure to define a conductance channel in the asymmetric moiré heterostructure therebetween, and wherein the top gate and the bottom gate are capacitively coupled with the conductance channel. In one embodiment, the asymmetric moiré heterostructure comprises vertically stacked multilayers of first and second two-dimensional (2D) materials with predetermined stacking Attorney Docket No.: 0116936.300WO2 orders and alignment angles. In one embodiment, two 2D material combinations that form moiré heterostructure can be, but not limited to, (1) graphene and hBN; (2) WS2 and MoS2; (3) WSe2 and MoSe2; or (4) WSe2 and MoS2.In one embodiment, the asymmetric moiré heterostructure comprises stacked bilayer graphene (BLG) sandwiched by top and bottom hexagonal boron nitride (hBN) layers, thereby defining a top interface between the BLG and the top hBN layer, and a bottom interface between the BLG and the bottom hBN layer. In one embodiment, the top and bottom hBN layers have a same thickness or different thicknesses in a range of 1-50 nm. In one embodiment, at the top interface, the BLG is closely aligned with the top hBN layer, resulting in a long-range moiré potential that leads to charge localization and enhanced Coulomb interactions, and at the bottom interface, the BLG is purposely misaligned with the bottom hBN layer by the alignment angle in a range of 20-50 degrees, which results in a more uniform and highly mobile charge distribution. In one embodiment, the angle is about 30 degrees. In one embodiment, the top hBN layer and the BLG form a long wavelength moiré superlattice. In one embodiment, the asymmetric moiré heterostructure is configured to have an asymmetric moiré potential landscape that divides the moiré synaptic transistor into localized and itinerant subsystems, and wherein the two subsystems are separated in a vertical z-direction but remain Coulomb-coupled. In one embodiment, the asymmetric moiré potential landscape comprises a long-range moiré potential at the top interface serving as a charge reservoir that localizes charges, which are separated in the z-direction by less than 1 nm from the conducting channel, which serves as an itinerant system for lateral charge transport. In one embodiment, at specific biasing conditions, dynamical interplay between the two subsystems leads to carrier ratcheting that accommodates hysteretic, non-volatile carrier transfers that control the conductance of the moiré synaptic transistor. In one embodiment, when functioning as an electron ratchet, the top gate adds electrons to the channel in the forward scans but does not fully remove them in the backward scans. In one embodiment, gradual increase of the channel conductance is enabled by electron ratchet pulsing. Attorney Docket No.: 0116936.300WO2 In one embodiment, when functioning as a hole ratchet, the top gate adds holes to the channel in the backward scans but does not fully remove them in the forward scans. In one embodiment, gradual decrease of the channel conductance is enabled by hole ratchet pulsing. In one embodiment, the hysteretic carrier ratcheting results in room-temperature tuning of non-volatile conductance states with unique gate-tunable synaptic plasticity. In one embodiment, the gate-tunable synaptic plasticity enables bio-realistic neuromorphic functionalities including tunable synaptic responses, spike-based perceptrons, spatiotemporal-based tempotrons, and input-specific adaptations. In one embodiment, the moiré synaptic transistor is configured such that the top and bottom gates provide differential control over the moiré localization sites and the channel conductance, respectively, which enables bidirectional synaptic threshold sliding that is suitable for implementing input-specific adaptation in neuromorphic hardware. In one embodiment, the moiré synaptic transistor is capable of emulating Hebbian learning of biological synapses when the top gate is connected to the pre-neurons and the source is connected to the post-neurons. In one embodiment, the synaptic functionalities are facilitated by the voltage bias (VTG) of the top gate alone. In one embodiment, the asymmetry of the BLG / hBN moiré heterostructure enables that the voltage biases (VTG and VBG) of the top gate and the bottom gate provide distinct tunability in the dual-gated MST. In one embodiment, the voltage biases (VTGand VBG) of the top gate and the bottom gate have preferential control over the conductance channel and the moiré localization sites, respectively. In one embodiment, only in the ratcheting regime does the voltage bias (VTG) of the top gate induce a unidirectional charge injection into the conductance channel. In one embodiment, the voltage bias (VTG) of the top gate hysteretically controls the non- volatile ratcheting effect at the top BLG / hBN interface, whereas the voltage bias (VBG) of the bottom gate reversibly controls the conductance channel in a manner analogous to a conventional BLG transistor. In one embodiment, by exploiting the combined effects of the voltage biases (VTG and VBG) of the top gate and the bottom gate, the occupation of the moiré localization sites and the Attorney Docket No.: 0116936.300WO2 channel conductance are deterministically programmable, enabling rich and broad tunability of the MST synaptic response. In one embodiment, the contrasting control provided by the voltage biases (VTG and VBG) of the top gate and the bottom gate enables the realization of neuromorphic input-specific adaptation. In one embodiment, the input-specific adaptation is realizable in a biomimetic MST- based Hopfield neural network that associates a prestored pattern with a similar but nonidentical input pattern. In one embodiment, vestibular-ocular reflex and feedforward dentate gyrus-CA3 microcircuits are realizable using the MSTs to efficiently process information from sensory, memory, and motor actions in neuromorphic hardware. In one embodiment, the moiré synaptic transistor has low power consumption that is equal to or less than 20 pW of power to pass a synaptic spike through the moiré synaptic transistor. In one embodiment, the moiré synaptic transistor is compatible with crossbar array architecture for large-scale neural networks including spike-based perceptrons and spatiotemporal-based tempotrons. In one embodiment, the crossbar architecture has a cell size of 8.75-12.25 F2depending on if the source line is shared between neighboring rows. In another aspect, the invention relates to a circuitry comprising one or more moiré synaptic transistors as disclosed above. In yet another aspect, the invention relates to an electronic device comprising one or more moiré synaptic transistors as disclosed above. In one aspect, the invention relates a crossbar array, comprising: M columns and N rows of moiré synaptic transistors, each of M and N being an integer greater than zero, each moiré synaptic transistor comprising a top gate; a bottom gate; an asymmetric moiré heterostructure disposed between the top gate and the bottom gate; and a source and a drain spatial-apart formed on the asymmetric moiré heterostructure to define a conductance channel in the asymmetric moiré heterostructure therebetween, wherein the top gate and the bottom gate are capacitively coupled with the conductance channel. In one embodiment, the asymmetric moiré heterostructure comprises vertically stacked multilayers of first and second two-dimensional (2D) materials with predetermined stacking Attorney Docket No.: 0116936.300WO2 orders and alignment angles. In one embodiment, two 2D material combinations that form moiré heterostructure can be, but not limited to, (1) graphene and hBN; (2) WS2 and MoS2; (3) WSe2 and MoSe2; or (4) WSe2 and MoS2. In one embodiment, the asymmetric moiré heterostructure comprises stacked bilayer graphene (BLG) sandwiched by top and bottom hexagonal boron nitride (hBN) layers, thereby defining a top interface between the BLG and the top hBN layer, and a bottom interface between the BLG and the bottom hBN layer. In one embodiment, at the top interface, the BLG is closely aligned with the top hBN layer, resulting in a long-range moiré potential that leads to charge localization and enhanced Coulomb interactions, and at the bottom interface, the BLG is purposely misaligned with the bottom hBN layer by the alignment angle in a range of 20-50 degrees, which results in a more uniform and highly mobile charge distribution. In one embodiment, the angle is about 30 degrees. In one embodiment, the top hBN layer and the BLG form a long wavelength moiré superlattice. In one embodiment, the asymmetric moiré heterostructure is configured to have an asymmetric moiré potential landscape that divides the moiré synaptic transistor into localized and itinerant subsystems, and wherein the two subsystems are separated in a vertical z-direction but remain Coulomb-coupled. In one embodiment, the asymmetric moiré potential landscape comprises a long-range moiré potential at the top interface serving as a charge reservoir that localizes charges, which are separated in the z-direction by less than 1 nm from the conducting channel, which serves as an itinerant system for lateral charge transport. In one embodiment, at specific biasing conditions, dynamical interplay between the two subsystems leads to carrier ratcheting that accommodates hysteretic, non-volatile carrier transfers that control the conductance of the moiré synaptic transistor. In one embodiment, when functioning as an electron ratchet, the top gate adds electrons to the channel in the forward scans but does not fully remove them in the backward scans. In one embodiment, gradual increase of the channel conductance is enabled by electron ratchet pulsing. In one embodiment, when functioning as a hole ratchet, the top gate adds holes to the Attorney Docket No.: 0116936.300WO2 channel in the backward scans but does not fully remove them in the forward scans. In one embodiment, gradual decrease of the channel conductance is enabled by hole ratchet pulsing. In one embodiment, the hysteretic carrier ratcheting results in room-temperature tuning of non-volatile conductance states with unique gate-tunable synaptic plasticity. In one embodiment, the gate-tunable synaptic plasticity enables bio-realistic neuromorphic functionalities including tunable synaptic responses, spike-based perceptrons, spatiotemporal-based tempotrons, and input-specific adaptations. In one embodiment, the moiré synaptic transistor is configured such that the top and bottom gates provide differential control over the moiré localization sites and the channel conductance, respectively. In one embodiment, the moiré synaptic transistor is capable of emulating Hebbian learning of biological synapses when the top gate is connected to the pre-neurons and the source is connected to the post-neurons. In one embodiment, the synaptic functionalities are facilitated by the voltage bias (VTG) of the top gate alone. In one embodiment, the asymmetry of the BLG / hBN moiré heterostructure enables that the voltage biases (VTG and VBG) of the top gate and the bottom gate provide distinct tunability. In one embodiment, the voltage biases (VTGand VBG) of the top gate and the bottom gate have preferential control over the conductance channel and the moiré localization sites, respectively. In one embodiment, only in the ratcheting regime does the voltage bias (VTG) of the top gate induce a unidirectional charge injection into the conductance channel. In one embodiment, the voltage bias (VTG) of the top gate hysteretically controls the non- volatile ratcheting effect at the top BLG / hBN interface, whereas the voltage bias (VBG) of the bottom gate reversibly controls the conductance channel in a manner analogous to a conventional BLG transistor. In one embodiment, by exploiting the combined effects of the voltage biases (VTG and VBG) of the top gate and the bottom gate, the occupation of the moiré localization sites and the channel conductance are deterministically programmable, enabling rich and broad tunability of the MST synaptic response. In one embodiment, the contrasting control provided by the voltage biases (VTGand VBG) Attorney Docket No.: 0116936.300WO2 of the top gate and the bottom gate enables the realization of neuromorphic input-specific adaptation. In one embodiment, each moiré synaptic transistor has low power consumption that is equal to or less than 20 pW of power to pass a synaptic spike through the moiré synaptic transistor. In one embodiment, the crossbar array has a cell size of 8.75-12.25 F2depending on if the source line is shared between neighboring rows. In one embodiment, the crossbar array is a biomimetic MST-based Hopfield neural network that associates a prestored pattern with a similar but nonidentical input pattern. These and other aspects of the present invention will become apparent from the following description of the preferred embodiment taken in conjunction with the following drawings, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings illustrate one or more embodiments of the invention and together with the written description, serve to explain the principles of the invention. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like elements of an embodiment. FIG.1 shows non-volatile charge injection in moiré synaptic transistors enabled by an electronically controlled ratcheting mechanism, according to embodiments of the invention. Panel a: Schematic of a dual-gated moiré synaptic transistor. Inset showing that the top hBN and BLG form a long wavelength moiré superlattice. Panel b: Moiré potential at the top interface serves as a charge reservoir that can localize charges, which are separated in the z-direction by less than 1 nm from the conducting channel, which serves as an itinerant system for lateral charge transport. Panel c: Drain current (ID) of device No.1 measured as a function of VTG(each has a 20 nA offset for clarity and y-axis is only for reading the bottommost curves) with VTG always scanning in the forward direction first from 0 V to a finite positive value and then back to 0 V (as illustrated by the inset). The red line represents the forward scan direction, and blue line represents the backward scan direction. Panel d: Drain current (ID) of device No.1 measured as a function of VTG (each has a 20 nA offset for clarity and y-axis is only for reading the bottommost curves) with VTGalways scanning in the backward direction from 0 V to a finite negative Attorney Docket No.: 0116936.300WO2 value and then back to 0 V (as illustrated by the inset). Panel e: Extracted electron density (ne) at the end of each scan in c (the blue dot in the inset, which is always at VTG= 0 V) as a function of VTG scan range. When functioning as an electron ratchet, the top gate adds electrons to the channel in the forward (red) scans but does not fully remove them in the backward (blue) scans. Panel f: Extracted hole density (nh) at the end of each scan in panel d (the blue dot in inset, which is always at VTG= 0 V) as a function of VTGscan range. When functioning as a hole ratchet, the top gate adds holes to the channel in the backward (red) scans but does not fully remove them in the forward (blue) scans. Panel g: Gradual increase of the channel conductance enabled by electron ratchet pulsing. Panel h: Gradual decrease of the channel conductance enabled by hole ratchet pulsing. VD is 0.1 mV for all measurements. FIG.2 shows synaptic responses and applications of moiré synaptic transistors, according to embodiments of the invention. Panel a: Measurements of device No.2 showing the wide range of tunable long-term potentiation (LTP) and long term depression (LTD) plasticity in a moiré synaptic transistor by adjusting the amplitude of 10 ms VTG pulses. Each curve shows alternating potentiation and depression behavior in a long sequence of corresponding pulses indicated in the legend. Panel b: Schematic of a moiré synaptic transistor mimicking a biological synapse. Panel c: Schematic showing the architecture of moiré synaptic transistors being implemented in a crossbar array for large-scale neural network operation. Panels d-f: Demonstration of tempotron- based multi-spike computation with moiré synaptic transistors. Panel d: Illustration of input spatiotemporal patterns to train the tempotron. Panel e: Two output neurons are trained to fire 0 and 1 times in response to input patterns. Panel f: Generalization error of the tempotron as a function of jitter standard deviation ^^^^^^^^applied on input patterns. VD is 0.1 mV for all measurements. FIG.3 shows dual-gate response of moiré synaptic transistors, according to embodiments of the invention. Panel a: Measurements of device No.1 showing that sweeping VBGpredominantly modulates carrier density in the conducting channel without hysteresis. The dashed line highlights the shift of the charge neutrality point as function of VTG (each curve has a 12 nA offset for clarity). The red curve corresponds to the VBGscan in the forward direction, and the blue curve corresponds to the VBG scan in the backward direction. Panel b: Measurements of device No.1 showing that sweeping VTG leads to strong hysteresis between the forward VTG scan (red) and backward VTGscan (blue) for a range of VBGvalues (each curve has a 22 nA offset for Attorney Docket No.: 0116936.300WO2 clarity). The dashed lines mark the transition between the constant conductance regime and ratcheting regime for the forward and backward scans. The voltage range of the constant conductance regime remains the same for both VTG scan directions regardless of the VBG values. Panel c: Measured drain current ID of the moiré synaptic transistor by applying 10 ms VTG pulses with 2.5 V amplitude at various VBGbiases from -2 V to 2 V. Panel d: Measured IDof the moiré synaptic transistor by applying 10 ms VTGpulses with 4 V amplitude at various VBGbiases from - 2 V to 2 V. Panel e: The overall ^ID of c showing that the LTD / LTP threshold point is between VBG = 0 V and 1 V. Panel f: The overall ^ID of d showing that the LTD / LTP threshold point is between VBG = -1 V and 0 V. VD is 0.1 mV for all measurements. FIG.4 shows input-specific adaptation for associative learning based on moiré synaptic transistors, according to embodiments of the invention. Panel a: Input-specific adaptation can be manifested as bidirectional synaptic threshold sliding with a tunable threshold ^^^^^^(m = 1, 2, 3, …), which is different than panel b, Hebbian / anti-Hebbian learning rules, where the LTD / LTP threshold point ^^^^is fixed. As shown in a, input-specific adaptation can be realized by the moiré synaptic transistor by simply tuning the two gate biases as opposed to the more cumbersome frequency tuning in traditional neuromorphic hardware implementations. Panels c-d: Schematics showing associative learning of a moiré synaptic transistor neural network following the learning rules illustrated in a. See Section X for details. Panels e-g: Waveforms of neural network states ‘x1, x2, x3’ being updated under different learning rules. Panel e: Without eye deprivation, moiré synaptic transistors following the learning rule in panel a or panel b enable the neural network to correctly associate the prestored ‘111’ pattern (each digit corresponds to xi, i = 1, 2, 3) with a similar but nonidentical input ‘000’ pattern. Panel f: With eye deprivation and following the learning rule in panel b, the neural network fails to associate the prestored ‘111’ pattern with the input ‘000’ pattern. Panel g: With eye deprivation and following the learning rule in a, input- specific adaptation in moiré synaptic transistors enables the neural network to correctly associate the prestored ‘111’ pattern with the input ‘000’ pattern. FIG.5 shows carrier density extraction, according to embodiments of the invention. Carrier density in panels e-f of FIG.1 is extracted by comparing the current value measured in panels c-d of FIG.1 (top left) to a reference ID – VTG curve (top right), which is then converted to a corresponding carrier density value (bottom right). FIG.6 shows contrasting VBGand VTGtuning of the moiré synaptic transistor, according Attorney Docket No.: 0116936.300WO2 to embodiments of the invention. Panel a: An illustration showing that VBG can reversibly add electrons (remove holes) in the forward scan (red) or remove electrons (add holes) in thebackward scan (blue) in the channel. Panel b: An illustration showing that VTG, as an electronratchet, can add electrons in the channel in a forward scan but cannot take electrons out of thechannel if VTG reverses its scanning direction. Panel c: An illustration showing that VTG, as a holeratchet, can add holes in the channel in the backward scan but cannot take holes out of the channel if VTG reverses its scanning direction. FIG.7 shows channel conductance tuned by the electron ratchet in a series of programmable states, according to embodiments of the invention. Channel conductance measured as a function of VTG and VBG, where VBG always fast scans from -2 V to 2 V and Panel a: VTG slowly scans in the forward direction from -4 V to -2 V and in the backward direction from -2 V to -4 V; Panel b: VTGslowly scans in the forward direction from -4 V to 1.6 V and in the backward direction from 1.6 V to -4 V; Panel c: VTG slowly scans in the forward direction from -4 V to 2 V and in the backward direction from 2 V to -4 V; Panel d: VTG slowly scans in the forward direction from -4 V to 3 V and in the backward direction from 3 V to -4 V; Panel e: VTGslowly scans in the forward direction from -4 V to 4 V and in the backward direction from 4 V to -4 V. The bottom schematics illustrate how the electron ratchet cannot add electrons in the channel when VTG scans in the forward direction in the constant conductance segments, can keep adding electrons in the channel when VTGscans in the forward direction in the ratcheting regime, and cannot remove electrons from the channel when VTG reverse its scan direction. FIG.8 shows channel conductance tuned by the hole ratchet in a series of programmable states, according to embodiments of the invention. Channel conductance measured as a function of VTG and VBG, where VBG always fast scans from -2 V to 2 V and Panel a: VTG slowly scans in the backward direction from 4 V to 2 V and in the forward direction from 2 V to 4 V; Panel b: VTGslowly scans in the backward direction from 4 V to -1.6 V and in the forward direction from -1.6 V to 4 V; Panel c: VTGslowly scans in the backward direction from 4 V to -2 V and in the forward direction from -2 V to 4 V; Panel d: VTG slowly scans in the backward direction from 4 V to -3 V and in the forward direction from -3 V to 4 V; Panel e: VTG slowly scans in the backward direction from 4 V to -4 V and in the forward direction from -4 V to 4 V. The bottom schematics illustrate that the hole ratchet cannot add holes in the channel when VTG scans in backward direction in the constant conductance segments, can keep adding holes in the channel when VTGscans in the backward direction in the ratcheting regime, and cannot remove holes Attorney Docket No.: 0116936.300WO2 from the channel when VTG reverse its scan direction. FIG.9 shows channel conductance tuned by sweeping both VTGand VBG, according to embodiments of the invention. Channel conductance measured as a function of VTG and VBG, where VBG always fast scans from -10 V to 10 V and VTG slowly scans in the forward direction from -20 V to 20 V. All data were measured at 4 K. FIG.10 shows Retention and endurance characterization, according to embodiments of the invention. Panel a: Retention characterization of two representative conductance states in the moiré synaptic transistor for 24 hours. Panel b: Endurance characterization of two representative conductance states for 1000 cycles. FIG.11 shows measurement conditions for retention and endurance characterization, according to embodiments of the invention. Panel a: The measurement condition of retention characterization. Panel b: The measurement condition of endurance characterization. FIG.12 shows retention characterization of multiple memory states, according to embodiments of the invention. FIG.13 shows power and voltage benchmarks for moiré synaptic transistors, according to embodiments of the invention. FIG.14 shows illustration of passing spikes through a moiré synaptic transistor, according to embodiments of the invention. FIG.15 shows top and bottom gate leakage currents of a moiré synaptic transistor, according to embodiments of the invention. Panel a: Drain current (ID), top gate current (ITG), and bottom gate current (IBG) during the VBG sweep. Panel b: Top gate and bottom gate currents from a are plotted in log-scale. FIG.16 shows architecture and footprint of moiré synaptic transistor, according to embodiments of the invention. Panels a-b: The layout of a moiré synaptic transistor crossbar using minimum values of feature widths according to the MOSIS deep submicron lambda rule: metal width 4 λ; metal space 4 λ; gate width 2 λ; contact width 2 λ; metal enclosure contact 1 λ. The source lines are shared between neighboring rows in panel a and panel b giving a footprint of 196 λ2(=12.25 F2where F = 4 λ). Panel c: The footprint decreases to 140 λ2(=8.75 F2) when source lines are shared between neighboring rows. FIG.17 shows multilayer perceptron-based recognition. Panel a: Schematic embedding moiré synaptic transistors in a three-synaptic-layer MLP neural network. Panel b: Flow schematic of the perceptron in the invention. Panel c: MINST handwritten digit recognition Attorney Docket No.: 0116936.300WO2 accuracy of the MST-based MLP as a function of the number of training epochs, taking into account simulated device-to-device and cycle-to-cycle variations. The inset shows typical MINST handwritten digits used in training and recognition. FIG.18 shows tempotron design, according to embodiments of the invention. Flow schematic of the tempotron in the invention. FIG.19 shows crossbar architecture and pulsing schemes for MSTs in the tempotron, according to embodiments of the invention. Panel a: Crossbar array architecture of MSTs used to implement the tempotron. Panels b-c: Input pulses arrive at each afferent and trigger a tunable pulsing scheme that is applied on specific MSTs. Panel b: Input temporal patterns for a tempotron. Panel c: Schematic showing that when one temporal input spike signal arrives at an afferent, VTG and VD pulsing schemes are applied on the specific MST of that afferent. FIG.20 shows flow schematic of input-specific adaptation in a Hopfield neural network enabled by MSTs, according to embodiments of the invention. FIG.21 shows crossbar architecture of the Hopfield neural network, according to embodiments of the invention. Crossbar array of the Hopfield neural network for associative memory implementation with 3-by-3 synaptic units and 3 neuron units. The synaptic units (SU) and neuron units (NU) are shown in FIG.22. FIG.22 shows circuit implementation of the Hopfield neural network for associative memory, according to embodiments of the invention. A biomimetic MST-based Hopfield neural network was simulated that can recall pre-stored pattern ^^prebased on the input pattern ^^in, where each digit is represented by a voltage bias being either 0 or 1 V. The neural network has an additional input by having ^^Dand ^^Bthat correspond to whether or not eye deprivation is occurring. DETAILED DESCRIPTION OF THE INVENTION The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. However, this invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this specification will be thorough and complete and fully convey the invention's scope to those skilled in the art. Like reference numerals refer to like elements throughout. Attorney Docket No.: 0116936.300WO2 The terms used in this specification generally have their ordinary meanings in the art, within the context of the invention, and in the specific context where each term is used. Certain terms used to describe the invention are discussed below, or elsewhere in the specification, to provide additional guidance to the practitioner regarding the description. For convenience, certain terms may be highlighted, for example using italics and / or quotation marks. The use of highlighting has no influence on the scope and meaning of a term; the scope and meaning of a term are the same, in the same context, whether or not it is highlighted. It will be appreciated that same thing can be said in more than one way. Consequently, alternative language and synonyms may be used for any one or more of the terms discussed herein, nor is any special significance to be placed upon whether or not a term is elaborated or discussed herein. Synonyms for certain terms are provided. A recital of one or more synonyms does not exclude the use of other synonyms. The use of examples anywhere in this specification including examples of any terms discussed herein is illustrative only, and in no way limits the scope and meaning of the invention or of any exemplified term. Likewise, the invention is not limited to various embodiments given in this specification. It will be understood that, as used in the description herein and throughout the claims that follow, the meaning of “a”, “an”, and “the” includes plural reference unless the context clearly dictates otherwise. Also, it will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, or section without departing from the invention's teachings. Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element’s relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the Attorney Docket No.: 0116936.300WO2 device in addition to the orientation depicted in the figures. For example, if the device in one of the figures. is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, can, therefore, encompasses both an orientation of “lower” and “upper,” depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. Therefore, the exemplary terms “below” or “beneath” can encompass both an orientation of above and below. It will be further understood that the terms “comprises” and / or “comprising,” or “includes” and / or “including” or “has” and / or “having”, or “carry” and / or “carrying,” or “contain” and / or “containing,” or “involve” and / or “involving, and the like are to be open-ended, i.e., to mean including but not limited to. When used in this specification, they specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this specification, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used in this specification, “around”, “about”, “approximately” or “substantially” shall generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around”, “about”, “approximately” or “substantially” can be inferred if not expressly stated. As used in this specification, the phrase “at least one of A, B, and C” should be construed to mean a logical (A or B or C), using a non-exclusive logical OR. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. The description below is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. The broad teachings of the invention can be implemented in a variety of forms. Therefore, while this invention includes particular examples, the true Attorney Docket No.: 0116936.300WO2 scope of the invention should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. It should be understood that one or more steps within a method may be executed in a different order (or concurrently) without altering the principles of the invention. Moiré quantum materials host exotic electronic phenomena through enhanced internal Coulomb interactions in twisted two-dimensional heterostructures. When combined with the exceptionally high electrostatic control in atomically thin materials, moiré heterostructures have the potential to enable next-generation electronic devices with unprecedented functionality. However, despite extensive exploration, moiré electronic phenomena have thus far been limited to impractically low cryogenic temperatures, thus precluding real-world applications of moiré quantum materials. In view of the foregoing, the invention discloses the experimental realization and room- temperature operation of a low-power (20 pW) moiré synaptic transistor based on an asymmetric bilayer graphene / hexagonal boron nitride moiré heterostructure. The asymmetric moiré potential gives rise to robust electronic ratchet states, which enable hysteretic, non-volatile injection of charge carriers that control the conductance of the device. The asymmetric gating in dual-gated moiré heterostructures realize diverse bio-realistic neuromorphic functionalities such as reconfigurable synaptic responses, spatiotemporal-based tempotrons, and Bienestock-Cooper- Munro input-specific adaptation. In this manner, the moiré synaptic transistor enables efficient compute-in-memory designs and edge hardware accelerators for artificial intelligence and machine learning. Without intent to limit the scope of the invention, exemplary embodiments of the invention are given below. In one embodiment, the moiré synaptic transistor (MST) comprises a top gate, a bottom gate, and an asymmetric moiré heterostructure disposed between the top gate and the bottom gate. In one embodiment, the moiré synaptic transistor further comprises a source and a drain spatial-apart formed on the asymmetric moiré heterostructure to define a conductance channel in the asymmetric moiré heterostructure therebetween, and wherein the top gate and the bottom gate are capacitively coupled with the conductance channel. In one embodiment, the asymmetric moiré heterostructure comprises vertically stacked Attorney Docket No.: 0116936.300WO2 multilayers of first and second two-dimensional (2D) materials with predetermined stacking orders and alignment angles. In one embodiment, two 2D material combinations that form moiré heterostructure can be, but not limited to, (1) graphene and hBN; (2) WS2 and MoS2; (3) WSe2 and MoSe2; or (4) WSe2and MoS2. In one embodiment, the asymmetric moiré heterostructure comprises stacked bilayer graphene (BLG) sandwiched by top and bottom hexagonal boron nitride (hBN) layers, thereby defining a top interface between the BLG and the top hBN layer, and a bottom interface between the BLG and the bottom hBN layer. In one embodiment, the top and bottom hBN layers have a same thickness or different thicknesses in a range of 1-50 nm. In one embodiment, at the top interface, the BLG is closely aligned with the top hBN layer, resulting in a long-range moiré potential that leads to charge localization and enhanced Coulomb interactions, and at the bottom interface, the BLG is purposely misaligned with the bottom hBN layer by the alignment angle in a range of 20-50 degrees, which results in a more uniform and highly mobile charge distribution. In one embodiment, the angle is about 30 degrees. In one embodiment, the top hBN layer and the BLG form a long wavelength moiré superlattice. In one embodiment, the asymmetric moiré heterostructure is configured to have an asymmetric moiré potential landscape that divides the moiré synaptic transistor into localized and itinerant subsystems, and wherein the two subsystems are separated in a vertical z-direction but remain Coulomb-coupled. In one embodiment, the asymmetric moiré potential landscape comprises a long-range moiré potential at the top interface serving as a charge reservoir that localizes charges, which are separated in the z-direction by less than 1 nm from the conducting channel, which serves as an itinerant system for lateral charge transport. In one embodiment, at specific biasing conditions, dynamical interplay between the two subsystems leads to carrier ratcheting that accommodates hysteretic, non-volatile carrier transfers that control the conductance of the moiré synaptic transistor. In one embodiment, when functioning as an electron ratchet, the top gate adds electrons to the channel in the forward scans but does not fully remove them in the backward scans. Attorney Docket No.: 0116936.300WO2 In one embodiment, gradual increase of the channel conductance is enabled by electron ratchet pulsing. In one embodiment, when functioning as a hole ratchet, the top gate adds holes to the channel in the backward scans but does not fully remove them in the forward scans. In one embodiment, gradual decrease of the channel conductance is enabled by hole ratchet pulsing. In one embodiment, the hysteretic carrier ratcheting results in room-temperature tuning of non-volatile conductance states with unique gate-tunable synaptic plasticity. In one embodiment, the gate-tunable synaptic plasticity enables bio-realistic neuromorphic functionalities including tunable synaptic responses, spike-based perceptrons, spatiotemporal-based tempotrons, and input-specific adaptations. In one embodiment, the moiré synaptic transistor is configured such that the top and bottom gates provide differential control over the moiré localization sites and the channel conductance, respectively, which enables bidirectional synaptic threshold sliding that is suitable for implementing input-specific adaptation in neuromorphic hardware. In one embodiment, the moiré synaptic transistor is capable of emulating Hebbian learning of biological synapses when the top gate is connected to the pre-neurons and the source is connected to the post-neurons. In one embodiment, the synaptic functionalities are facilitated by the voltage bias (VTG) of the top gate alone. In one embodiment, the asymmetry of the BLG / hBN moiré heterostructure enables that the voltage biases (VTGand VBG) of the top gate and the bottom gate provide distinct tunability in the dual-gated MST. In one embodiment, the voltage biases (VTG and VBG) of the top gate and the bottom gate have preferential control over the conductance channel and the moiré localization sites, respectively. In one embodiment, only in the ratcheting regime does the voltage bias (VTG) of the top gate induce a unidirectional charge injection into the conductance channel. In one embodiment, the voltage bias (VTG) of the top gate hysteretically controls the non- volatile ratcheting effect at the top BLG / hBN interface, whereas the voltage bias (VBG) of the bottom gate reversibly controls the conductance channel in a manner analogous to a conventional BLG transistor. Attorney Docket No.: 0116936.300WO2 In one embodiment, by exploiting the combined effects of the voltage biases (VTG and VBG) of the top gate and the bottom gate, the occupation of the moiré localization sites and the channel conductance are deterministically programmable, enabling rich and broad tunability of the MST synaptic response. In one embodiment, the contrasting control provided by the voltage biases (VTGand VBG) of the top gate and the bottom gate enables the realization of neuromorphic input-specific adaptation. In one embodiment, the input-specific adaptation is realizable in a biomimetic MST- based Hopfield neural network that associates a prestored pattern with a similar but nonidentical input pattern. In one embodiment, vestibular-ocular reflex and feedforward dentate gyrus-CA3 microcircuits are realizable using the MSTs to efficiently process information from sensory, memory, and motor actions in neuromorphic hardware. In one embodiment, the moiré synaptic transistor has low power consumption that is equal to or less than 20 pW of power to pass a synaptic spike through the moiré synaptic transistor. In one embodiment, the moiré synaptic transistor is compatible with crossbar array architecture for large-scale neural networks including spike-based perceptrons and spatiotemporal-based tempotrons. In one embodiment, the crossbar architecture has a cell size of 8.75-12.25 F2depending on if the source line is shared between neighboring rows. In one embodiment, a circuitry comprises one or more moiré synaptic transistors as disclosed above. In one embodiment, an electronic device comprises one or more moiré synaptic transistors as disclosed above. In one embodiment, a crossbar array comprises M columns and N rows of moiré synaptic transistors, each of M and N being an integer greater than zero, each moiré synaptic transistor comprising a top gate; a bottom gate; an asymmetric moiré heterostructure disposed between the top gate and the bottom gate; and a source and a drain spatial-apart formed on the asymmetric moiré heterostructure to define a conductance channel in the asymmetric moiré heterostructure therebetween, wherein the top gate and the bottom gate are capacitively coupled with the conductance channel. Attorney Docket No.: 0116936.300WO2 In one embodiment, the asymmetric moiré heterostructure comprises vertically stacked multilayers of first and second two-dimensional (2D) materials with predetermined stacking orders and alignment angles. In one embodiment, two 2D material combinations that form moiré heterostructure can be, but not limited to, (1) graphene and hBN; (2) WS2and MoS2; (3) WSe2and MoSe2; or (4) WSe2and MoS2. In one embodiment, the asymmetric moiré heterostructure comprises stacked bilayer graphene (BLG) sandwiched by top and bottom hexagonal boron nitride (hBN) layers, thereby defining a top interface between the BLG and the top hBN layer, and a bottom interface between the BLG and the bottom hBN layer. In one embodiment, at the top interface, the BLG is closely aligned with the top hBN layer, resulting in a long-range moiré potential that leads to charge localization and enhanced Coulomb interactions, and at the bottom interface, the BLG is purposely misaligned with the bottom hBN layer by the alignment angle in a range of 20-50 degrees, which results in a more uniform and highly mobile charge distribution. In one embodiment, the angle is about 30 degrees. In one embodiment, the top hBN layer and the BLG form a long wavelength moiré superlattice. In one embodiment, the asymmetric moiré heterostructure is configured to have an asymmetric moiré potential landscape that divides the moiré synaptic transistor into localized and itinerant subsystems, and wherein the two subsystems are separated in a vertical z-direction but remain Coulomb-coupled. In one embodiment, the asymmetric moiré potential landscape comprises a long-range moiré potential at the top interface serving as a charge reservoir that localizes charges, which are separated in the z-direction by less than 1 nm from the conducting channel, which serves as an itinerant system for lateral charge transport. In one embodiment, at specific biasing conditions, dynamical interplay between the two subsystems leads to carrier ratcheting that accommodates hysteretic, non-volatile carrier transfers that control the conductance of the moiré synaptic transistor. In one embodiment, when functioning as an electron ratchet, the top gate adds electrons to the channel in the forward scans but does not fully remove them in the backward scans. In one embodiment, gradual increase of the channel conductance is enabled by electron Attorney Docket No.: 0116936.300WO2 ratchet pulsing. In one embodiment, when functioning as a hole ratchet, the top gate adds holes to the channel in the backward scans but does not fully remove them in the forward scans. In one embodiment, gradual decrease of the channel conductance is enabled by hole ratchet pulsing. In one embodiment, the hysteretic carrier ratcheting results in room-temperature tuning of non-volatile conductance states with unique gate-tunable synaptic plasticity. In one embodiment, the gate-tunable synaptic plasticity enables bio-realistic neuromorphic functionalities including tunable synaptic responses, spike-based perceptrons, spatiotemporal-based tempotrons, and input-specific adaptations. In one embodiment, the moiré synaptic transistor is configured such that the top and bottom gates provide differential control over the moiré localization sites and the channel conductance, respectively. In one embodiment, the moiré synaptic transistor is capable of emulating Hebbian learning of biological synapses when the top gate is connected to the pre-neurons and the source is connected to the post-neurons. In one embodiment, the synaptic functionalities are facilitated by the voltage bias (VTG) of the top gate alone. In one embodiment, the asymmetry of the BLG / hBN moiré heterostructure enables that the voltage biases (VTG and VBG) of the top gate and the bottom gate provide distinct tunability. In one embodiment, the voltage biases (VTG and VBG) of the top gate and the bottom gate have preferential control over the conductance channel and the moiré localization sites, respectively. In one embodiment, only in the ratcheting regime does the voltage bias (VTG) of the top gate induce a unidirectional charge injection into the conductance channel. In one embodiment, the voltage bias (VTG) of the top gate hysteretically controls the non- volatile ratcheting effect at the top BLG / hBN interface, whereas the voltage bias (VBG) of the bottom gate reversibly controls the conductance channel in a manner analogous to a conventional BLG transistor. In one embodiment, by exploiting the combined effects of the voltage biases (VTG and VBG) of the top gate and the bottom gate, the occupation of the moiré localization sites and the channel conductance are deterministically programmable, enabling rich and broad tunability of Attorney Docket No.: 0116936.300WO2 the MST synaptic response. In one embodiment, the contrasting control provided by the voltage biases (VTGand VBG) of the top gate and the bottom gate enables the realization of neuromorphic input-specific adaptation. In one embodiment, each moiré synaptic transistor has low power consumption that is equal to or less than 20 pW of power to pass a synaptic spike through the moiré synaptic transistor. In one embodiment, the crossbar array has a cell size of 8.75-12.25 F2depending on if the source line is shared between neighboring rows. In one embodiment, the crossbar array is a biomimetic MST-based Hopfield neural network that associates a prestored pattern with a similar but nonidentical input pattern. The invention, among other things, provides the following advantages. Novel bio-realistic synaptic functions. Dual-gated moiré synaptic transistors can perform bio-mimetic functionality such as multi-layer perceptrons and tempotrons. In addition, dual- gated moiré synaptic transistors are a hardware embodiment of the Bienenstock, Cooper, and Munro (BCM) neuronal model in which frequency threshold sliding is replaced with voltage threshold sliding, which is preferred for integration of high-speed, low-power neural network circuits. By taking an example of the Hopfield neural network, we demonstrate an input-specific adaptation that is uniquely enabled by the electrostatic effects in dual-gated moiré synaptic transistors. Overall, the moiré synaptic transistor can perform many novel bio-realistic synaptic functions that are not possible for traditional memristive devices. Non-volatile memory is an intrinsic electronic property of the moiré sites between bilayer graphene and hBN. The ratcheting effect has an electronic origin. In contrast to existing synaptic devices, the key difference is the underlying mechanism of hysteretic ratcheting arising from a new type of ferroelectricity driven by electronic degrees of freedom instead of ion migration and atomic displacement that form the basis of traditional memristors and ferroelectric memories. These conventional devices require specialized growth techniques, annealing, active layers, and / or electroforming processes to intentionally create defective states, filaments, or multiple ferroelectric domains within switching layers. In contrast, the moiré synaptic transistor can be directly fabricated by stacking hBN and bilayer graphene layers with predetermined alignment angles. Consequently, the resulting device characteristics do not suffer from the stochastic behavior of atomic motion in memristors and ferroelectric memories. The electronic origin also Attorney Docket No.: 0116936.300WO2 implies that the ratcheting effect can be controlled electrostatically in a manner that is not possible with two-terminal memristors. Ultralow power consumption. The moiré synaptic transistor consumes only 20 pW of power to pass a synaptic spike through the device, which is many orders of magnitude lower than traditional memristive synaptic devices. To name a few examples, a Cu-Te based CBRAM device typically consumes around 1 W, a MoS2based memristor device typically consumes 0.01 W, and a HfO2 based memristor device typically consumes 0.1 ^W for a synaptic spike. The outstanding power efficiency of moiré synaptic transistors make them promising candidate for realizing neural network hardware in wearable and edge computing settings, where the power source is limited. The moiré synaptic transistor can be implemented into a crossbar architecture to perform complicated computing tasks. The footprint of a moiré synaptic transistor crossbar is comparable to that of a memristor crossbar because the bottom and top gates are in two different layers and the moiré heterostructure includes vertically stacked 2D materials that do not increase the lateral footprint. The footprint of a moiré synaptic transistor crossbar is 8.75-12.25 F2. For comparison, the cell sizes for one-transistor-one-memristor crossbars and SRAM cells are 7F2and 120-150 F2, respectively. The invention may have widespread applications in non-volatile memory, neuromorphic computing, artificial neural networks, in-memory computing, spatio-temporal encoding, analog electronics, and the like. These and other aspects of the invention are further described below. Without intent to limit the scope of the invention, exemplary instruments, apparatus, methods, and their related results according to the embodiments of the invention are given below. Note that titles or subtitles may be used in the examples for convenience of a reader, which in no way should limit the scope of the invention. Moreover, certain theories are proposed and disclosed herein; however, in no way they, whether they are right or wrong, should limit the scope of the invention so long as the invention is practiced according to the invention without regard for any particular theory or scheme of action. EXAMPLE: THE MOIRÉ SYNAPTIC TRANSISTOR: A ROOM-TEMPERATURE QUANTUM DEVICE WITH RECONFIGURABLE NEUROMORPHIC FUNCTIONALITY Attorney Docket No.: 0116936.300WO2 The exploding use of artificial intelligence (AI) and machine learning (ML) has created an urgent demand for alternative computing schemes that can handle vast quantities of data in an energy-efficient manner. Conventional digital computing hardware relies on the von Neumann architecture with distinct memory and information processing blocks, which necessitate frequent data transfer with unfavorable speed and power consumption characteristics, especially in the limit of big data. Neuromorphic computing is an emerging approach to circumvent the von Neumann bottleneck, which takes inspiration from the human brain (e.g., co-location of memory and logic, parallel processing, and hyperconnectivity) to enable low-power hardware accelerators for AI / ML. The major bottleneck in neuromorphic hardware is a fast, stable, and scalable non- volatile memory element that can also emulate the synaptic behavior of biological neural networks. Common candidates such as memristors rely on conductive filament formation and rupture, defect migration, charge trapping, material phase change, and ferroelectricity. The physical limitations of these mechanisms imply that existing memristive devices typically possess one or more drawbacks including limited switching speed and endurance, large device- to-device variations, redundant forming processes, uncontrollable stochasticity, high voltage operation, and a limited number of non-volatile conductance states. In addition, memristive synaptic devices typically do not incorporate the additional functionality that underlies the sophisticated and reconfigurable learning behavior of biological neural networks. Recently, moiré heterostructures based on twisted two-dimensional (2D) nanosheets have emerged as a material platform capable of hosting diverse electronic phenomena such as unconventional superconductivity, orbital magnetism, generalized Wigner crystal states, and interacting moiré excitonic phases. In particular, the ferroelectricity hosted in bilayer graphene (BLG) / hexagonal boron nitride (hBN) moiré heterostructures stands out as a potential candidate for neuromorphic devices. Different from the sliding ferroelectricity found in twisted hBN and transition metal dichalcogenide heterostructures, BLG / hBN moiré ferroelectricity possesses an intrinsically electronic origin resulting from the asymmetric moiré structure. Specifically, the structure includes Bernal-stacked BLG sandwiched by two hBN layers with vastly different angle alignments (panel a of FIG.1). At the top interface, BLG is closely aligned with the top hBN, resulting in a long-range moiré potential that leads to charge localization and enhanced Coulomb interactions. At the bottom interface, BLG is purposely misaligned with the bottom hBN by roughly 30 degrees, which results in a more uniform and highly mobile charge distribution. Hence, the asymmetric moiré potential landscape divides the system into localized Attorney Docket No.: 0116936.300WO2 and itinerant subsystems. These two subsystems are separated in the z-direction but remain Coulomb-coupled (panel b of FIG.1). At specific biasing conditions, the dynamical interplay between the two subsystems leads to the emergence of a ratcheting electronic state that accommodates hysteretic, non-volatile charge transfer. Importantly, the deep moiré potential and strong internal Coulomb interactions allow these electronic properties to be preserved at elevated temperatures, suggesting the possibility of room-temperature device applications. In this example, we disclose the experimental realization of a moiré synaptic transistor (MST) based on the BLG / hBN moiré heterostructure, which presents two main advantages over existing non-volatile memories. First, the intrinsic ratcheting states are realized by stacking hBN and BLG layers with specific stacking orders and alignment angle, which result in ferroelectricity from the electronic degrees of freedom. In contrast, traditional memristors and ferroelectric memories rely on ion migration and atomic displacement, and often require specialized growth techniques, annealing, active layers, and forming processes to intentionally create defective states or multiple ferroelectric domains in switching layers. With their underlying ratcheting mechanism, MSTs possess low power consumption (20 pW) comparable to the state-of-the-art, show high endurance and retention of multiple states, and are compatible with scalable fabrication in crossbar architectures. Second, hysteretic electronic ratcheting results in room-temperature tuning of non-volatile conductance states with unique gate-tunable synaptic plasticity. This reconfigurable synaptic plasticity enables diverse neuromorphic computing applications such as spike-based perceptrons and spatiotemporal-based tempotrons. Furthermore, the unique asymmetry of the dual-gated BLG / hBN moiré heterostructure allows for bio-realistic bidirectional synaptic threshold sliding using voltage as a state variable instead of frequency, which is preferred for hardware integration and is not possible with competing devices without additional circuit elements. These distinctive features imply that MSTs possess clear advantages over existing non-volatile memories for mimicking biological homeostatic mechanisms and input-specific adaptation that can accelerate emerging neural network applications. We first examine the basic characteristics of the MST. In panel c of FIG.1, the drain current (ID) is plotted as a function of the top gate bias (VTG) in a closed loop while varying the VTGrange (^VTG) in the positive direction (the VTGscan trajectory is shown in the inset). The device is prepared to be in the same state at the beginning of each loop (VTGat 0 V). The forward and backward traces overlap when ^VTG is below 1.5 V, but show strong hysteresis when ^VTG Attorney Docket No.: 0116936.300WO2 exceeds 1.5 V. In the latter case, the device reaches distinct conductance states at the end of each loop as ^VTGincreases. Similar behavior is observed when varying ^VTGin the negative direction (panel d of FIG.1). The carrier density is extracted at the end of the scan loop (indicated by the blue dot in the insets in panels c-d of FIG.1) according to the conductance state (FIG.5) and then plotted as a function of ^VTG in panels e-f of FIG.1, respectively. In panel e of FIG.1, the electron density remains unchanged for small ^VTG (< 1.5 V) and linearly increases as ^VTG becomes larger. Similarly, in panel f of FIG.1, the hole density remains unchanged for small ^VTG (|^VTG |< 1.5 V) and linearly increases when |^VTG| becomes larger. The corresponding moiré wavelength is 13.2 nm (see Section II). This unidirectional charge density modulation effect arises from the layer-contrasting electronic states in the asymmetric BLG / hBN moiré heterostructure. In particular, the long-range moiré potential at the top BLG / hBN interface leads to charge localization, whereas the uniform charge distribution at the bottom interface leads to mobile charge transport. In the loop measurements in panel c of FIG.1, no charges are initially occupying the moiré localization sites. Scanning VTGin the positive direction (red lines) adds electrons to the moiré localization sites such that the channel conductance remains constant. When ^VTG < 1.5 V, this process is reversible, meaning that electrons are removed from the moiré localization sites to return the system back to its original state (blue lines). However, this process becomes irreversible when ^VTG> 1.5 V. Once the moiré localization sites are fully filled, increasing VTGcan no longer add electrons to the localized subsystem due to on-site Coulomb repulsion. Instead, these electrons are added to the conductance channel, resulting in a change of conductance (panel e of FIG.1). This process is driven by the formation of new electronic states such that the MST falls into a local energy minimum at each increment, making this process irreversible. Hence, reversing the voltage scan direction anywhere within this regime triggers a hysteretic response, where electrons are removed from the localization sites, leaving the channel conductance unchanged (blue lines). At the end of the voltage loop measurement, the device returns to a different electronic state each time the range of ^VTGis increased (for ^VTG> 1.5 V). The scenario in panels d-f of FIG.1 is the same as panels c and e of FIG.1 except that the process is described in terms of hole injection. This unidirectional electron / hole injection into the conductance channel from VTG resembles a mechanical ratchet that can be electrically controlled. Additional details of this electronic ratcheting effect are shown in FIGS.6-8. Attorney Docket No.: 0116936.300WO2 The electronic ratcheting effect allows continuous tuning of the conductance by applying short VTGpulses. For example, by applying 3 V, 10 ms pulses, VTGacts as an electron ratchet and monotonically increases the conductance of the channel as shown in panel g of FIG.1 (in this measurement, the majority carriers in the channel are initially electrons). Then, by subsequently applying -3 V, 10 ms pulses, VTGacts as a hole ratchet and monotonically decreases the conductance of the channel (panel h of FIG.1). The ratcheting effect is consistently observed among multiple fabricated devices (FIG.9), and device-to-device variability can be further improved by controlling the thickness of the hBN layers and orientation angle in the moiré heterostructure (see Section IV). Retention and endurance characterization of multiple intermediate conductance states indicate the non-volatile nature of the ratcheting mechanism (FIGS.10-12). The power needed to pass one spike through an MST is approximately 20 pW (FIGS.13-15), which compares favorably with state-of-the-art synaptic devices such as memristors, phase change memories, magnetic memories, and charge trap memories. Just as the degree of depolarization of a postsynaptic cell in biological neuronal networks can be increased (also called potentiation) or decreased (also called depression) by pulsed electrical stimulation of the presynaptic cell, the ratcheting effect enables the BLG / hBN moiré heterostructure to show similar synaptic behavior and thus act as a synaptic transistor. For example, the inset of panel a of FIG.2 shows a series of VTG pulses with differing amplitudes that result in a range of synaptic potentiation and depression responses (panel a of FIG.2). Device No.2 behaves qualitatively the same as Device No.1 except that Device No.2 has a thicker hBN layer and thus requires larger gate biases to introduce similar charge carrier concentration into the system (Section VII). Specifically, the long-term potentiation (LTP) and long-term depression (LTD) can be tuned from strong LTP (panel a of FIG.2, blue line) to moderate LTP (panel a of FIG.2, lavender line) and from strong LTD (panel a of FIG.2, orange line) to moderate LTD (panel a of FIG.2, pink line). In this manner, MSTs can emulate the Hebbian learning of biological synapses when the top gate is connected to the pre-neurons and the source is connected to the post-neurons (panel b of FIG.2). As schematically depicted in panel c of FIG.2 and FIG.16, MSTs are also compatible with crossbar array architectures for large-scale neural networks including spike-based perceptrons and spatiotemporal-based tempotrons using existing growth and transfer methods for hBN and BLG, as described in Section VIII. The proposed crossbar architecture in FIG.16 occupies a cell size of 8.75-12.25 F2depending on if the source line is shared between neighboring rows. For comparison, the cell Attorney Docket No.: 0116936.300WO2 sizes for one-transistor-one-memristor (1T1M) crossbars and SRAM cells are 7 F2and 120-150 F2, respectively. A comparable footprint to 1T1M is achieved because the two gates for MSTs are processed in different layers below and above the hBN / BLG heterojunction. Using the MST synaptic response, a multilayer perceptron (MLP) is modeled in FIG.17, resulting in a >85-90% recognition rate of handwritten digits even with device-to-device and cycle-to-cycle variations of 10%. While MLPs encode information through the rates of neuronal action potential firing, tempotrons employ spatiotemporal spike patterns that are used in biologically plausible supervised learning models to supplement the perceptron model. To demonstrate utility for tempotrons, MSTs are modeled as afferents that can integrate input patterns into output signals (panel d of FIG.2 and FIGS.18-19). When the output value exceeds a predetermined threshold, the neural network fires a single spike and resets the output value to zero (see Section IX). By employing the tunable LTP / LTD plasticity of MSTs, two neurons can be trained in the tempotron to fire 0 and 1 times in response to input patterns (panel e of FIG.2). To test the robustness of the tempotron, jitter noise (quantified by ^^pre) was added to the input patterns (panel f of FIG.2, inset). Stability against jitter noise is observed for ^^pre< 5 ms (panel f of FIG. 2), suggesting high noise tolerance for MST-based tempotrons. In addition to the synaptic functionalities facilitated by VTG alone, the asymmetry of the BLG / hBN moiré heterostructure implies that VTGand VBGprovide distinct tunability in dual- gated MSTs. Due to the spatial separation between the two subsystems in the BLG / hBN moiré heterostructure, VBG and VTG have preferential control over the conductance channel and the moiré localization sites, respectively. In particular, only in the ratcheting regime does VTG induce a unidirectional charge injection into the conductance channel. In panel a of FIG.3, the drain current ID is measured as a function of VBG at a range of VTG values between 0 V and 3.2 V. Regardless of the VTG value, the forward scan (red) and backward scan (blue) overlap with each other, indicating that VBGcan add and remove charges from the conductance channel in a reversible manner (panel c of FIG.3). In comparison, panel b of FIG.3 shows the ID versus VTG curves at different VBG values. At each VBG value, significant hysteresis is observed between the forward and backward scans. In the constant conductance segments, VTGmodulates the occupation of the moiré localization sites, leaving the channel conductance unchanged. The voltage range for the constant conductance segments is the same for each scan, which corresponds to the maximum charge density that the moiré localization sites can accommodate. Attorney Docket No.: 0116936.300WO2 In the ratcheting regime, VTG adds electrons / holes to the conductance channel through the electron / hole ratchet mechanism (panels b-c of FIG.6, respectively). In contrast, reversing the VTG voltage scan direction immediately activates the ratchet locking mechanism such that charges are first removed from the moiré localization sites. In summary, VTG hysteretically controls the non-volatile ratcheting effect at the top BLG / hBN interface, whereas VBGreversibly controls the conductance channel in a manner analogous to a conventional BLG transistor. By exploiting the combined effects of VTG and VBG, the occupation of the moiré localization sites and the channel conductance can be deterministically programmed (FIGS.7-8), enabling rich and broad tunability of the MST synaptic response. Experimentally, we initialize the MST to the same state through a closed loop sweep of VBG (from -2 V to 2 V and then back to -2 V) while constantly biasing VTG at -4 V. The drain current ID is then measured after applying 10 ms VTGpulses of amplitude 2.5 V (panel c of FIG.3) or 4 V (panel d of FIG.3) at various VBG biases from -2 V to 2 V. The change in ID (^ID) from panels c-d of FIG.3 is plotted in panels e-f of FIG.3, respectively, showing how the threshold where LTD and LTP switch (noted as ^^t) is modified by VTG. In the case when VTGis 2.5 V (panel e of FIG.3), ^^tfalls between 0 V and 1 V in VBG, which indicates that the device is LTD favored. On the other hand, in the case when VTG is 4 V (panel f of FIG.3), ^^tlies between -1 V and 0 V in VBG, which indicates the device is LTP-favored. The contrasting control provided by VTGand VBGin MSTs enables the realization of neuromorphic input-specific adaptation. In the Bienestock-Cooper-Munro (BCM) model, input- specific adaptation is described using bidirectional synaptic threshold sliding (panel a of FIG.4) and is applicable to biological neurons in the visual cortex under eye deprivation conditions. From a neuromorphic computing perspective (Section X), input-specific adaptation allows neural networks to actively adapt to overall activity, maintain system stability, and mimic higher-order correlations in the brain in addition to supplementing Hebbian / anti-Hebbian learning rules (panel b of FIG.4, synaptic threshold is fixed). Both the original biological model and recent neuromorphic hardware demonstrations rely on the frequency variation of postsynaptic stimulation (noted as c in panel a of FIG.4) to trigger input-specific adaptation. However, the use of stimulation frequency as an input variable in neuromorphic hardware is challenging, slow, and inefficient. In contrast, MSTs achieve bidirectional synaptic threshold sliding using only VTGand VBG, thus overcoming these limitations. Attorney Docket No.: 0116936.300WO2 We demonstrate MST-based input-specific adaptation using an associative memory model where eye deprivation is considered. In a stable environment, associative memory allows the recall of a brain-stored pattern after seeing a similar but nonidentical pattern. In a changing environment, such as when eye deprivation occurs (e.g., poor lighting conditions), the adversarial effect is compensated by input-specific adaptation in the neural system to ensure that associative memory functions correctly. Specifically, we modeled a biomimetic MST-based Hopfield neural network that associates a prestored pattern ^^pre(‘111’) with a similar but nonidentical input pattern ^^in(‘000’ in our demonstration) (see Section X and FIGS.20-22). Initially, we limited the MSTs to only follow Hebbian / anti-Hebbian learning rules with ^^tbeing fixed (panel b of FIG.4). In a stable environment case without eye deprivation (panel c of FIG. 4), the neural network recalled ^^pre(panel e of FIG.4). However, when eye deprivation occurred (panel d of FIG.4), the neural network failed to recall ^^preand became stuck at a local minimum (panel f of FIG.4). Next, we allowed the MSTs to possess tunable synaptic threshold sliding^^tm (^^ = 1, 2, 3, ... ) (FIG. 4a). In this case, even in the presence of eye deprivation (panel d ofFIG.4), the neural network correctly recalled ^^pre(panel g of FIG.4). In particular, the onset of eye deprivation triggered the input-specific adaptation of the MSTs and enabled weight- adjustment of the devices in the training process to mitigate adversarial effects. Since this functionality can be realized simply by controlling biases to the gate terminals, MSTs provide an efficient and scalable solution for implementing bio-realistic neuromodulation computational models in a compact form compared to traditional two-terminal memristors. For example, in addition to input-specific adaptation, vestibular-ocular reflex and feedforward dentate gyrus-CA3 microcircuits can be realized using MSTs to efficiently process information from sensory, memory, and motor actions in neuromorphic hardware. Neurosynaptic cores based on MST crossbars have the potential to be scaled up by native tiling in a 3D fashion in a manner similar to the architecture of the IBM TrueNorth chip to better address sensory-based problems. The unique functionality of MSTs further offers a means of tuning the synchronization level of moiré devices in a crossbar to address the sparse nature of spiking neural networks in large-scale computing chips such as the Intel Loihi Chip (Section XI). In conclusion, we have harnessed BLG / hBN moiré heterostructures to realize room- temperature MSTs. The electronic ratcheting characteristics of these MSTs provide tunable synaptic responses that are suitable for neuromorphic spike-based perceptrons and Attorney Docket No.: 0116936.300WO2 spatiotemporal-based tempotrons. Moreover, the spatial asymmetry of the BLG / hBN moiré heterostructure implies that the top and bottom gates in dual-gated MSTs provide differential control over the moiré localization sites and the channel conductance, respectively, which enables bidirectional synaptic threshold sliding that is suitable for implementing input-specific adaptation in neuromorphic hardware. While demonstrated here with BLG / hBN moiré heterostructures, the evolving family of moiré heterostructures based on other twisted 2D nanosheets are likely to yield additional non-volatile synaptic characteristics with utility for neuromorphic computing. When coupled with recent advances in large-area, single-crystal 2D material growth techniques and wafer-scale aligned transfer methods, MSTs have the potential for scaling in crossbar architectures that can implement complex neuromodulation and bio- mimicking functionalities. Method Device Fabrication: When fabricating moiré synaptic transistors (MSTs), graphene and hBN flakes are first exfoliated onto SiO2 / Si substrates. Bilayer graphene (BLG) is then identified using Raman spectroscopy. The bottom hBN, BLG, and top hBN flakes are subsequently stacked together and transferred onto pre-patterned metal bottom gates through a standard dry transfer technique using a polydimethylsiloxane / poly(bisphenol A carbonate) stamp. The remaining top contacts are fabricated by first defining the contact area with electron-beam lithography, then exposing graphene with etching of the top hBN within those areas, and finally forming contacts by evaporating chromium / palladium / gold on top of the now exposed graphene. Electrical Measurements: All room-temperature electrical measurements were carried out in a vacuum probe station at a pressure of ~5×10-5Torr using a LakeShore CRX 4K probe station. All pulse measurements were carried out with pulse measurement units in a Keithley 4200A-SCS Parameter Analyzer using home-built LabVIEW®programs. In panel f of FIG.1, the conductance of the device is measured after each VTGpulse as shown in the legend. Thus, VTG alternates between -3 V and 0 V during the write and the read pulses for 10 ms each. The read voltage (VD = 10 mV) was continuously applied during the write and read process. Only one value of read current was obtained during each reading. Each potentiating (depressing) section of the zig-zag pattern in panel a of FIG.2 is one LTP (LTD) curve similar to the curves being shown in panel g of FIG.1 (panel h of FIG.1). Attorney Docket No.: 0116936.300WO2 Section I. Extraction of Charge Density FIG. 5 shows carrier density extraction. Carrier density in panels e-f of FIG. 1 isextracted by comparing the current value measured in panels c-d of FIG.1 (top left) to a reference ID – VTG curve (top right), which is then converted to a corresponding carrier density value (bottom right). Section II. Moiré Wavelength and Moiré Site Filling by VTG We can infer the angle alignment between the graphene and hBN and the moiré wavelength by analyzing our charge transport measurements. In panels e-f of FIG.1, we show that within |ΔVTG | < 1.5 V, the system behaves reversibly as we ramp VTG back and forth. In this regime, the top gate is solely modifying the doping level of the moiré localization sites. When |ΔVTG| > 1.5 V, we start to observe a change in the density after we sweep VTGto a finite value and back to zero, which indicates that the moiré localization sites can be filled with |ΔVTG| = 1.5V (total change of VTG by 3V), corresponding to a charge density of 2.6 × 1012cm-2. If we assume two electrons per moiré unit cell, then the corresponding moiré wavelength is 13.2 nm (~0.34 degrees rotational misalignment between the graphene and hBN). Section III. Ratcheting Mechanism Contrasting VBGand VTGfunctions in tuning the MST conductance. FIG.6 shows the contrasting VBG and VTG tuning of the moiré synaptic transistor. a, An illustration showing that VBG can reversibly add electrons (remove holes) in the forward scan (red) or remove electrons (add holes) in the backward scan (blue) in the channel. b, An illustration showing that VTG, as an electron ratchet, can add electrons in the channel in a forward scan but cannot take electrons out of the channel if VTG reverses its scanning direction. c, An illustration showing that VTG, as a hole ratchet, can add holes in the channel in the backward scan but cannot take holes out of the channel if VTGreverses its scanning direction. Electron ratchet enables the tuning of MSTs into a series of programmable conductance states. FIG.7 shows the channel conductance tuned by the electron ratchet in a series of programmable states. The channel conductance is measured as a function of VTGand VBG, where VBG always fast scans from -2 V to 2 V and panel a, VTG slowly scans in the forward direction from -4 V to -2 V and in the backward direction from -2 V to -4 V; panel b, VTG slowly scans in the forward direction from -4 V to 1.6 V and in the backward direction from 1.6 V to -4 Attorney Docket No.: 0116936.300WO2 V; panel c, VTG slowly scans in the forward direction from -4 V to 2 V and in the backward direction from 2 V to -4 V; panel d, VTGslowly scans in the forward direction from -4 V to 3 V and in the backward direction from 3 V to -4 V; panel e, VTG slowly scans in the forward direction from -4 V to 4 V and in the backward direction from 4 V to -4 V. The bottom schematics illustrate how the electron ratchet cannot add electrons in the channel when VTGscans in the forward direction in the constant conductance segments, can keep adding electrons in the channel when VTG scans in the forward direction in the ratcheting regime, and cannot remove electrons from the channel when VTG reverse its scan direction. Hole ratchet enables the tuning of MSTs into a series of programmable conductance states. FIG.8 shows the channel conductance tuned by the hole ratchet in a series of programmable states. The channel conductance is measured as a function of VTG and VBG, where VBGalways fast scans from -2 V to 2 V and panel a, VTGslowly scans in the backward direction from 4 V to 2 V and in the forward direction from 2 V to 4 V; panel b, VTG slowly scans in the backward direction from 4 V to -1.6 V and in the forward direction from -1.6 V to 4 V; panel c, VTGslowly scans in the backward direction from 4 V to -2 V and in the forward direction from -2 V to 4 V; panel d, VTGslowly scans in the backward direction from 4 V to -3 V and in the forward direction from -3 V to 4 V; panel e, VTG slowly scans in the backward direction from 4 V to -4 V and in the forward direction from -4 V to 4 V. The bottom schematics illustrate that the hole ratchet cannot add holes in the channel when VTGscans in a backward direction in the constant conductance segments, can keep adding holes in the channel when VTG scans in the backward direction in the ratcheting regime, and cannot remove holes from the channel when VTGreverse its scan direction. Section IV. Device-to-Device Variation To show that the synaptic functionality can be achieved with minimal device-to-device variation, four additional devices similar to device No.1 in the main text were fabricated and characterized (D1 to D4 as shown in FIG.9). D1 to D4 show similar charge transport characteristics that are consistent with the behavior of device No.1 in the main text. This device- to-device homogeneity can be further enhanced by minimizing variations in hBN thickness and utilizing robot-assisted uniform angle alignment during the fabrication of moiré synaptic transistors. FIG.9 shows the channel conductance tuned by sweeping both VTGand VBG. The channel Attorney Docket No.: 0116936.300WO2 conductance is measured as a function of VTG and VBG, where VBG always fast scans from -10 V to 10 V and VTGslowly scans in the forward direction from -20 V to 20 V. All data were measured at 4 K. Section V. Retention and Endurance Characterization The measurement protocol for retention measurements in panel a of FIG.10 is provided in panel a of FIG.11. We set the device conductance to a high conductance state (red symbols) by applying VTG pulses of -25 V for 10 ms (VBG = 0 V, VD = 0.1 mV). Then, we read and record the current every 10 min at VTG= 0 V, VBG= 0 V, and VD= 0.1 mV. Next, we set the device conductance to a low conductance state (blue symbols) by applying VTG pulses of 25 V for 10 ms (VBG = 0 V, VD = 0.1 mV). Then, we read and record the current every 10 min at VTG = 0 V, VBG = 0 V, and VD= 0.1 mV. The measurement condition of endurance in panel b of FIG.10 is illustrated in panel b of FIG.11. We varied the conductance of the device between a high conductance state (red symbols) and a low conductance state (blue symbols) by VTGpulses. Here, VTGalternates between 25 V (write), 0 V (read), -25 V (write), and 0 V (read) pulses for 10 ms each. The read voltage (VD = 0.1 mV) was continuously applied during the write and read processes. For access stability of multiple states, we programmed the device conductance to five different conductance states by applying different numbers of VTGpulses of 4 V for 10 ms (VBG= 0 V, VD = 0.1 mV). Then, we read and record the drain current every 10 min using the measurement conditions shown in FIG.12. FIG.10 shows retention and endurance characterization. Panel a, Retention characterization of two representative conductance states in the moiré synaptic transistor for 24 hours. Panel b, Endurance characterization of two representative conductance states for 1000 cycles. FIG.11 shows measurement conditions for retention and endurance characterization. Panel a, The measurement condition of retention characterization. Panel b, The measurement condition of endurance characterization. FIG.12 shows retention characterization of multiple memory states. Section VI. Power and Voltage Benchmarks for Moiré Synaptic Transistors Referring to FIG.13, we benchmark the power consumption of moiré synaptic transistors Attorney Docket No.: 0116936.300WO2 in comparison to state-of-the-art synaptic devices governed by other mechanisms. The energy cost is calculated by multiplying the power by the pulse duration. Below, we show how we estimate the energy and power required to pass one spike through a moiré synaptic transistor shown in FIG.13. In the moiré synaptic transistor, 10 ms pulses are applied during training and synaptic operation (FIG.14). Under this measurement condition and during each pulse period, energy costs are composed of two parts: from channel current and from gate leakage current. For the channel current, the power is 6 pW (the drain voltage is 0.1 mV, and the maximum current is around 60 nA) and the energy cost is 60 femtojoule / pulse: ^^DS = ^^^^ = 0.1^^^^ × 60^^^^ = 6 ^^^^.For the gate leakage current, the power is 15 pW for a single pulse (maximum VTG= 4 V and VBG = 2 V, the top or bottom gate leakage current is around 5 pA, i.e., the noise floor of Keithley 4200 semiconductor parameter analyzer, as shown in FIG.15). ∫ ^^ ^ 0^^^^^^^^4^^ ∗ 5^^^^ ∗ 10^^^^= ^^Thus, the total power transistor is 21 pW. FIG.14 is an a transistor. FIG.15 shows top and bottom gate leakage currents of a moiré synaptic transistor. Panel a, Drain current (ID), top gate current (ITG), and bottom gate current (IBG) during the VBG sweep. Panel b, Top gate and bottom gate currents from panel a are plotted in log-scale. Section VII. Comparison between the Two MSTs The two different devices (device No.1 and No.2) in the main text (FIGS.1-3) both show the electronic ratchet effect with some variations in the current amplitude and hysteresis window that occur in the anomalous screening regime where the top gate is ineffective. These variations can be attributed to charge localization at the top interface between the BLG and hBN. Thus, the device-to-device variation primarily results from two factors: hBN thickness, and alignment angle between hBN and graphene. Device No.2 has thicker hBN, so it takes a larger Attorney Docket No.: 0116936.300WO2 gate voltage to induce similar charge carriers into the system. Likewise, alignment between the BLG and top hBN was done manually using an optical microscope, which leads to some variation from device to device. By minimizing hBN thickness variations and employing robotic control of alignment, device-to-device homogeneity can be improved. Section VIII. Crossbar Architecture and Scalability of Moiré Synaptic Transistors FIG.16 shows architecture and footprint of moiré synaptic transistor. The layout of a moiré synaptic transistor crossbar using minimum values of feature widths according to the MOSIS deep submicron lambda rule: metal width 4 λ; metal space 4 λ; gate width 2 λ; contact width 2 λ; metal enclosure contact 1 λ. The source lines are shared between neighboring rows in (a) and (b) giving a footprint of 196 λ2(=12.25 F2where F = 4 λ). (c) The footprint decreases to 140 λ2(=8.75 F2) when source lines are shared between neighboring rows. The proposed cell size is 8.75-12.25 F2without sharing source electrodes between neighboring rows. For comparison, the cell sizes for one-transistor-one-memristor crossbars and SRAM cells are 7F2and 120-150 F2, respectively. In our design, the footprint of a moiré synaptic transistor crossbar is comparable to that of a memristor crossbar because the bottom and top gates are in two different layers and the moiré heterostructure includes vertically stacked 2D materials that do not increase the lateral footprint. Scaling moiré synaptic transistors to wafer-scale would require large-area single-crystal bilayer graphene (BLG) and hBN that have been grown by many groups. For BLG, Ruoff et al. have reported large-area Bernal-stacked single crystalline BLG synthesized on Cu. Similarly, Liu et al. have reported synthesis of BLG with nearly 100% film coverage on 10-by-30 cm2Cu substrates with an average domain size of 30-50 ^m. Beyond direct growth techniques, the formation of single crystalline BLG (2 cm diameter) via aligned transfer of two CVD-grown single crystalline graphene monolayers was reported by Lee et al. Likewise, direct growth of large-area single-crystal hBN monolayers and multilayers has been reported by several groups. In particular, Liu et al. reported the growth of a 100 cm2single- crystal hBN monolayer on Cu by CVD. In addition, Li et al. reported the growth of a 2-inch single-crystal hBN monolayer on Cu. In yet another example, Shin et al. reported growth of a 2- by-5 cm2single-crystal hBN trilayer on Ni. In general, there is a promising path forward for both large-area BLG and hBN from a materials standpoint. By combining these growth methods with established wafer-scale aligned transfer methods, uniform crossbar arrays of moiré synaptic Attorney Docket No.: 0116936.300WO2 transistors can be produced in a scalable manner. Section IX. Models of Perceptron and Tempotron Perceptron model: The MST can be tuned continuously to achieve different and stable levels of conductance. This property can be applied in perceptron-based classifications. A perceptron is a fundamental building block of artificial neural networks and is a type of linear binary classifier. Connecting multiple layers of perceptrons together in a feedforward manner forms a multi-layer perceptron (MLP). MLPs typically consist of three types of layers: input layer, hidden layers, and output layer (panel a of FIG.17). The connections between nodes of all three layers are synaptic weights. The goal of the perceptron is to recursively update and find a set of weights (wi) that correctly assigns inputs (xi) to a target class. Mathematical discussions and memristive-device-based applications of the perceptron model can be found in Refs.

[0069] -

[0071] . Here we simulated a multilayer perceptron with one hidden layer (panel a of FIG.17). The flow diagram is shown in panel b of FIG.17. The dataset is from MNIST handwritten digits (Ref.

[0072] ) (panel c of FIG.17). The neural network is implemented as a crossbar array architecture of MSTs. The training images are coded as input vectors (xi) that are sent to the neural network as input VTG pulses, which are applied at the rows of the crossbar array. At each cross point, the top gate of an MST is connected to the input row (connecting to the presynaptic neuron), and the source is connected to the output column (connecting to the postsynaptic neuron). The accessible conductance of each MST is extracted from one period of the potentiation / depression curve, as shown in panel a of FIG.2 (pink). After each epoch run of the perceptron, the conductance of each MST in the neural network is updated using backpropagation with gradient descent. FIG.17 shows multilayer perceptron-based recognition. Panel a, Schematic embedding moiré synaptic transistors in a three-synaptic-layer MLP neural network. Panel b, Flow schematic of the perceptron in this work. Panel c, MINST handwritten digit recognition accuracy of the MST-based MLP as a function of the number of training epochs, taking into account simulated device-to-device and cycle-to-cycle variations. The inset shows typical MINST handwritten digits used in training and recognition. Tempotron model: The conductance of MSTs can be changed to a different value with a tunable rate by adopting VTG pulsing schemes (panels g-h of FIG.1, and panel a of FIG.2). This property is used to realize the learning function in a tempotron. A tempotron is another type of Attorney Docket No.: 0116936.300WO2 building block of an artificial neural network specially designed for temporal spike pattern recognition and classification. Unlike a perceptron where the input spikes do not contain temporal information, the input of a tempotron is a sequence of binary spike events representing the occurrence or absence of events at different time steps. The connection between the input nodes and the output node is synaptic weight. Every sequence of input patterns gets multiplied by its specific weight and then is added to the output. The goal of a tempotron is to adjust the weights so that a continuous integrate-and-fire neuron can learn to fire a target number of times by decoding information embedded in spatiotemporal spike patterns. Mathematical discussions of the tempotron model can be found in Refs.

[0073] -

[0074] . The flow diagram of a tempotron in our work is shown in FIG.18. The neural network can be implemented as a crossbar array architecture of MSTs (panel a of FIG.19). The temporal input signals are continuously sent to each cross point of the neural network (i.e., afferent). When one temporal input spike signal arrives at an afferent, VTG and VD pulses are applied on the specific MST by adopting a pulsing scheme as shown in panels b-c of FIG.19. Using different VTG pulsing schemes (panels g-h of FIG.1, and panel a of FIG.2), the MST can achieve a wide range of tunable long-term potentiation (LTP) and long-term depression (LTD) from strong LTP (blue) to moderate LTP (lavender) and from strong LTD (orange) to moderate LTD (pink). When the output of the column reaches the firing threshold, the neural network fires one output spike. Then the output is reset to zero by shunting all incoming input signals that arrive after the output spike. At end of each run of the tempotron, the contributions from each afferent are evaluated. Then we update the VTG pulsing scheme to implement tunable LTP / LTD learning behaviors to each afferent so the conductance of MSTs in each afferent can be updated differently in the next run of the tempotron. If the neural network fires when it should not fire, then all afferents get LTD next time. If the neural network does not fire when it should have fired, then all afferents get LTP next time. Similar to Ref.

[0075] , in our tempotron, the neuron membrane potential dynamics, ^^(^^), is: ^^(^^) = ∑^^ ^^ ^^=1 ^^^^ ∑^^^^^^^^(^^ − ^^^^),(1)where ^^ denotes ^^-th ^^ ^^ ^^ input spike of the ^^-th afferent.^^(^^ − ^^^^ ^^) is the postsynaptic potential contributed by each incoming input spike: Attorney Docket No.: 0116936.300WO2 ^^ (2) where ^^^^and ^^^^denote time constants of the membrane and synaptic potential, and ^^0is a normalization factor. The tempotron learning is realized by updating ^^^^with the gradient descent method: ^^ − ^^^^ ^^(3) where ^^ denotes the time calculation of ∆^^^^and whether the final FC(number of firing times) is erroneous, we adjust the VTG pulsing scheme for each afferent to implement tunable LTP / LTD learning behaviors so that the conductance of an MST can address the ∆^^^^in each afferent accordingly. Each MST is either strongly or mildly potentiated or depressed when input spikes arrive in the next run of the tempotron. FIG.19 is crossbar architecture and pulsing schemes for MSTs in the tempotron. Panel a, Crossbar array architecture of MSTs used to implement the tempotron. Panels b-c, Input pulses arrive at each afferent and trigger a tunable pulsing scheme that is applied on specific MSTs.Panel b, Input temporal patterns for a tempotron. Panel c, Schematic showing that when onetemporal input spike signal arrives at an afferent, VTG and VD pulsing schemes are applied on the specific MST of that afferent. Section X. Models of Associative Memory with Input-specific Adaptation Hopfield neural network model of associative memory considering eye deprivation effect: MSTs possess a bidirectional synaptic threshold sliding property (panels c-f of FIG.3) due to the contrasting control provided by VTGand VBG. This property can be used to realize input-specific adaptation in a Hopfield neural network (HNN). In this work, associative memory HNN seeks to maintain the stability of the neural system when eye deprivation is considered. Discussions on associative memory HNN using the Hebbian rule can be found in Ref.

[0076] . From a neuromorphic computing perspective, input-specific adaptation allows neural networks to actively adapt to overall activity, maintain system stability, and mimic higher-order correlations in the brain in addition to supplementing Hebbian / anti-Hebbian learning rules. Below we demonstrate input-specific adaptation enabled by MSTs in associative memory HNN. FIG.20 shows flow schematic of input-specific adaptation in a Hopfield neural network enabled by MSTs. Attorney Docket No.: 0116936.300WO2 In our work, a pattern is represented by a state vector ^^ = (^^1, ^^2, ^^3), where ^^i = 0 V or1 V. The target state that we want the associative memory to be able to recall is (1, 1, 1). The flow diagram of the HNN in our work is shown in FIG.20. Mathematically, the synaptic weight matrix representing the conductance of MSTs in the neural network is: ^^11^^12^^13(4) A background weight matrix not (noted as ^^BB) is: ^^^^^^11^^^^^^12^^^^^^13^^^^^^11^^^^^^12^^^^^^13), (5) The threshold vector is: ^^ = (^^1,^^2,^^3), (6)If the input state vector is ^^(^^), the output state vector is updated by the following update rule: ^^(^^ + 1) = sign[^^(^^) ∙ (^^S − ^^B) − ^^], (7)where the sign function is defined as: sign(^^) = {1, ^^^^ ^^ > 00, ^^^^ ^^ < 0(8) FIG.21 shows crossbar architecture of the Hopfield neural network. Crossbar array of the Hopfield neural network for associative memory implementation with 3-by-3 synaptic units and 3 neuron units. The circuit implementation of the Hopfield neural network with the synaptic units (SU) and neuron units (NU) for associative memory is shown in FIG.22. A biomimetic MST-based Hopfield neural network was simulated that can recall pre-stored pattern ^^prebased on the input pattern ^^in, where each digit is represented by a voltage bias being either 0 or 1 V. The neural network has an additional input by having ^^Dand ^^Bthat correspond to whether or not eye deprivation is occurring. The circuit for implementing this 3 × 3 HNN with MSTs is shown in FIGS. 21-22. Thetarget pattern is stored in the HNN, which is achieved by pre-tuning the resistances of MSTs tohave the desired weight matrix ^^^^ − ^^^^. Based on experimental results, we set the range ofresistances available for MST to vary between 1.5 k^ and 2.5 k^. To store the associative memory state (1, 1, 1) in the neural network, we assign the resistance values in FIG.15 to be: Attorney Docket No.: 0116936.300WO2^^B = 1 MΩ, ^^D = 33 Ω; ^^S = 5 Ω for MST1,1, MST2,2, MST3,3; ^^S = 50 Ω for other MSTs,^^L = 1 kΩ; and resistance of each MST as:4 3.8 4^^MST = ( 3.8 4 3.3 ) kΩ. (9)4 3.3 4Thus, the weight matrix is: ^^11^^12^^13 0 1.3 1.23^^S = (^^21^^22^^23 ) = (1.3 0 1.5), (10) ^^31^^32^^33 1.23 1.5 0 The bright background matrix (no eye deprivation) is: ^^^^^^11^^^^^^12^^^^^^13 0 0 0The dark ^^^^^^11^^^^^^12^^^^^^1310 3 3^^ The threshold ^^ = (^^ ,^^ ,^^ ) =1 12 3100(−1, −1, −1), (13)Initially, in the follow Hebbian / anti-Hebbian learning rules with ^^tbeing fixed (panel b of FIG.4). In a stable environment case without eye deprivation (panel c of FIG.4), the neural network updates the output state by: ^^(^^ + 1) = sign[^^(^^) ∙ (^^S − ^^BB) − ^^] = sign[^^(^^) ∙ ^^S − ^^], (14)and the neural network recalls ^^pre = (1,1,1) (panel e of FIG. 4). However, when eyedeprivation occurred (panel d of FIG.4), the neural network updates the output state by: ^^(^^ + 1) = sign[^^(^^) ∙ (^^S − ^^DB) − ^^]. (15)Because we limited the MSTs to only follow Hebbian / anti-Hebbian learning rules with ^^tbeing fixed (panel b of FIG.4), the neural network failed to recall ^^preand became stuck at a local minimum (panel f of FIG.4). Next, we allowed the MSTs to possess tunable synaptic threshold sliding ^^tm (^^ =1, 2, 3, ... ) (panel a of FIG. 4). In this case, in the presence of eye deprivation (panel d of FIG.4), the neural network still updates the output state by Equation 15. However, because of the synaptic threshold sliding property, the MSTs in the neural network get potentiated regardless of Attorney Docket No.: 0116936.300WO2 whether the input is 0 V or 1 V, and thus ^^Schanges accordingly in every iteration and compensates for the effect of ^^DB. As shown in panel g of FIG.4, the neural network correctly recalled ^^preafter several iterations when the effect of ^^DBis mostly compensated. Therefore, the input-specific adaptation of the MSTs enables weight-adjustment of the devices in the training process to mitigate adversarial effects. Section XI. Potential Computational Applications Emphasizing Neuromodulation in Neuroscience by Moiré Synaptic Transistors The multi-terminal moiré synaptic devices could realize new computational models in neuroscience in a compact form compared to traditional two-terminal memristors. The following models can potentially be implemented with moiré synaptic transistor-based neural networks: (1) Neuromodulators achieve the vestibular-ocular reflex (VOR) through modulation of synaptic plasticity and adjustment of VOR gain and sensitivity. By applying the VOR effect, moiré synaptic transistor neural networks can efficiently process sensory inputs and generate motor outputs. (2) Neuromodulators like acetylcholine are also major players in hippocampal theta rhythm. The theta oscillation plays an important role in mammalian spatial navigation and memory. A recent computational study showed that by implementing theta oscillation by neuromodulation, a neural network can accelerate learning and viably solve the credit assignment problems in reinforcement learning without resorting to slow bootstrapping or maintaining implausible long memory traces. (3) A neuroscience study showed that integration of the actions of neuromodulators in the feedforward dentate gyrus-CA3 microcircuit in the hippocampus can lead to episodic memories by performing pattern separation and pattern completion. This episodic memory is a type of long-term memory for recent or past specific events, situations, and experiences. It has been used to improve the efficiency of deep reinforcement learning by capturing information from the memory and experience of past training. Here we suggest a possible implementation to realize the third model. We can build a moiré synaptic transistor crossbar for the purposes of mimicking a network of CA3 pyramidal cells. The top gates and bottom gates mimic the complex neuro-modulatory inputs from the projections of axons and mossy fibers of dentate gyrus granule cells to CA3 pyramidal cells. For Attorney Docket No.: 0116936.300WO2 memory encoding mode, the distribution of moiré synaptic transistors is tuned by both gates to be more excitable and less input specific, which mimics the CA3 network being more suitable for the pattern separation process. For memory retrieval mode, the distribution of moiré synaptic transistors is tuned by both gates to be less excitable and more input specific, which mimics the CA3 network being more suitable for the pattern completion process. With the realization of pattern separation and pattern completion, a moiré synaptic transistor crossbar can support novelty detection or episodic memory retrieval as needed for deep reinforcement learning algorithms. The foregoing description of the exemplary embodiments of the invention has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described to explain the principles of the invention and their practical application to enable others skilled in the art to utilize the invention and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the invention pertains without departing from its spirit and scope. Accordingly, the scope of the invention is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein. Some references, which may include patents, patent applications, and various publications, are cited and discussed in the description of this invention. The citation and / or discussion of such references is provided merely to clarify the description of the invention and is not an admission that any such reference is “prior art” to the invention described herein. All references cited and discussed in this specification are incorporated herein by reference in their entireties and to the same extent as if each reference was individually incorporated by reference. LIST OF REFERENCES[1]. Cao, Y. et al. Unconventional superconductivity in magic-angle graphene superlattices.Nature 556, 43-50 (2018).[2]. Cao, Y. et al. Correlated insulator behaviour at half-filling in magic-angle graphenesuperlattices. Nature 556, 80-84 (2018).[3]. Zheng, Z. et al. Unconventional ferroelectricity in moiré heterostructures. Nature 588,71-76 (2020).[4]. Andrei, E. Y. et al. The marvels of moiré materials. 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Claims

1. Attorney Docket No.: 0116936.300WO2 CLAIMS What is claimed is:

1. A moiré synaptic transistor (MST), comprising:a top gate, a bottom gate, and an asymmetric moiré heterostructure disposed between the top gate and the bottom gate.

2. The moiré synaptic transistor of claim 1, further comprising a source and a drain spatial-apart formed on the asymmetric moiré heterostructure to define a conductance channel in the asymmetric moiré heterostructure therebetween, and wherein the top gate and the bottom gate are capacitively coupled with the conductance channel.

3. The moiré synaptic transistor of claim 2, wherein the asymmetric moiré heterostructurecomprises vertically stacked multilayers of first and second two-dimensional (2D) materials with predetermined stacking orders and alignment angles.

4. The moiré synaptic transistor of claim 3, wherein, first and second 2D materialcombinations that form the asymmetric moiré heterostructure comprise: graphene and hBN; WS2 and MoS2; WSe2 and MoSe2; or WSe2and MoS2.

5. The moiré synaptic transistor of claim 4, wherein the asymmetric moiré heterostructurecomprises stacked bilayer graphene (BLG) sandwiched by top and bottom hexagonal boron nitride (hBN) layers, thereby defining a top interface between the BLG and the top hBN layer, and a bottom interface between the BLG and the bottom hBN layer.

6. The moiré synaptic transistor of claim 5, wherein the top and bottom hBN layers have asame thickness or different thicknesses in a range of 1-50 nm. Attorney Docket No.: 0116936.300WO27. The moiré synaptic transistor of claim 5, wherein at the top interface, the BLG is closelyaligned with the top hBN layer, resulting in a long-range moiré potential that leads to charge localization and enhanced Coulomb interactions, and at the bottom interface, the BLG is purposely misaligned with the bottom hBN layer by the alignment angle in a range of 20-50 degrees, which results in a more uniform and highly mobile charge distribution.

8. The moiré synaptic transistor of claim 7, wherein the angle is about 30 degrees.

9. The moiré synaptic transistor of claim 7, wherein the top hBN layer and the BLG form along wavelength moiré superlattice.

10. The moiré synaptic transistor of claim 7, wherein the asymmetric moiré heterostructure isconfigured to have an asymmetric moiré potential landscape that divides the moiré synaptic transistor into localized and itinerant subsystems, and wherein the two subsystems are separated in a vertical z-direction but remain Coulomb-coupled.

11. The moiré synaptic transistor of claim 10, wherein the asymmetric moiré potentiallandscape comprises a long-range moiré potential at the top interface serving as a charge reservoir that localizes charges, which are separated in the z-direction by less than 1 nm from the conducting channel, which serves as an itinerant system for lateral charge transport.

12. The moiré synaptic transistor of claim 10, wherein at specific biasing conditions,dynamical interplay between the two subsystems leads to carrier ratcheting that accommodates hysteretic, non-volatile carrier transfers that control the conductance of the moiré synaptic transistor.

13. The moiré synaptic transistor of claim 12, wherein when functioning as an electronratchet, the top gate adds electrons to the channel in the forward scans but does not fully remove them in the backward scans. Attorney Docket No.: 0116936.300WO214. The moiré synaptic transistor of claim 13, wherein gradual increase of the channelconductance is enabled by electron ratchet pulsing.

15. The moiré synaptic transistor of claim 12, wherein when functioning as a hole ratchet, thetop gate adds holes to the channel in the backward scans but does not fully remove them in the forward scans.

16. The moiré synaptic transistor of claim 15, wherein gradual decrease of the channelconductance is enabled by hole ratchet pulsing.

17. The moiré synaptic transistor of claim 12, wherein the hysteretic carrier ratcheting resultsin room-temperature tuning of non-volatile conductance states with unique gate-tunable synaptic plasticity.

18. The moiré synaptic transistor of claim 17, wherein the gate-tunable synaptic plasticityenables bio-realistic neuromorphic functionalities including tunable synaptic responses, spike-based perceptrons, spatiotemporal-based tempotrons, and input-specific adaptations.

19. The moiré synaptic transistor of claim 12, wherein the moiré synaptic transistor isconfigured such that the top and bottom gates provide differential control over the moiré localization sites and the channel conductance, respectively, which enables bidirectional synaptic threshold sliding that is suitable for implementing input-specific adaptation in neuromorphic hardware.

20. The moiré synaptic transistor of claim 19, wherein the moiré synaptic transistor iscapable of emulating Hebbian learning of biological synapses when the top gate is connected to the pre-neurons and the source is connected to the post-neurons.

21. The moiré synaptic transistor of claim 19, wherein the synaptic functionalities are Attorney Docket No.: 0116936.300WO2 facilitated by the voltage bias (VTG) of the top gate alone.

22. The moiré synaptic transistor of claim 21, wherein the asymmetry of the BLG / hBN moiréheterostructure enables that the voltage biases (VTG and VBG) of the top gate and the bottom gate provide distinct tunability in the dual-gated MST.

23. The moiré synaptic transistor of claim 22, wherein the voltage biases (VTG and VBG) ofthe top gate and the bottom gate have preferential control over the conductance channel and the moiré localization sites, respectively.

24. The moiré synaptic transistor of claim 23, wherein only in the ratcheting regime does thevoltage bias (VTG) of the top gate induce a unidirectional charge injection into the conductance channel.

25. The moiré synaptic transistor of claim 23, wherein the voltage bias (VTG) of the top gatehysteretically controls the non-volatile ratcheting effect at the top BLG / hBN interface, whereas the voltage bias (VBG) of the bottom gate reversibly controls the conductance channel in a manner analogous to a conventional BLG transistor.

26. The moiré synaptic transistor of claim 23, wherein by exploiting the combined effects ofthe voltage biases (VTGand VBG) of the top gate and the bottom gate, the occupation of the moiré localization sites and the channel conductance are deterministically programmable, enabling rich and broad tunability of the MST synaptic response.

27. The moiré synaptic transistor of claim 23, wherein the contrasting control provided by thevoltage biases (VTG and VBG) of the top gate and the bottom gate enables the realization of neuromorphic input-specific adaptation.

28. The moiré synaptic transistor of claim 27, wherein the input-specific adaptation isrealizable in a biomimetic MST-based Hopfield neural network that associates a prestored pattern with a similar but nonidentical input pattern. Attorney Docket No.: 0116936.300WO229. The moiré synaptic transistor of claim 5, wherein vestibular-ocular reflex andfeedforward dentate gyrus-CA3 microcircuits are realizable using the MSTs to efficiently process information from sensory, memory, and motor actions in neuromorphic hardware.

30. The moiré synaptic transistor of claim 5, wherein the moiré synaptic transistor has lowpower consumption that is equal to or less than 20 pW of power to pass a synaptic spike through the moiré synaptic transistor.

31. The moiré synaptic transistor of claim 5, wherein the moiré synaptic transistor iscompatible with crossbar array architecture for large-scale neural networks including spike-based perceptrons and spatiotemporal-based tempotrons.

32. The moiré synaptic transistor of claim 31, wherein the crossbar architecture has a cellsize of 8.75-12.25 F2depending on if the source line is shared between neighboring rows.

33. A circuitry, comprising one or more moiré synaptic transistors according to any one ofclaims 1-32.

34. An electronic device, comprising one or more moiré synaptic transistors according to anyone of claims 1-32.

35. A crossbar array, comprising: M columns and N rows of moiré synaptic transistors, eachof M and N being an integer greater than zero, each moiré synaptic transistor comprising: a top gate; a bottom gate; an asymmetric moiré heterostructure disposed between the top gate and the bottom gate; and a source and a drain spatial-apart formed on the asymmetric moiré heterostructure to define a conductance channel in the asymmetric moiré heterostructure therebetween, wherein the top gate and the bottom gate are capacitively coupled with the conductance channel. Attorney Docket No.: 0116936.300WO236. The crossbar array of claim 35, wherein the asymmetric moiré heterostructure comprisesvertically stacked multilayers of first and second two-dimensional (2D) materials with predetermined stacking orders and alignment angles.

37. The crossbar array of claim 36, wherein, first and second 2D material combinations thatform the asymmetric moiré heterostructure comprise: graphene and hBN; WS2and MoS2; WSe2 and MoSe2; or WSe2 and MoS2.

38. The crossbar array of claim 37, wherein the asymmetric moiré heterostructure comprisesstacked bilayer graphene (BLG) sandwiched by top and bottom hexagonal boron nitride (hBN) layers, thereby defining a top interface between the BLG and the top hBN layer, and a bottom interface between the BLG and the bottom hBN layer.

39. The crossbar array of claim 38, wherein at the top interface, the BLG is closely alignedwith the top hBN layer, resulting in a long-range moiré potential that leads to charge localization and enhanced Coulomb interactions, and at the bottom interface, the BLG is purposely misaligned with the bottom hBN layer by the alignment angle in a range of 20- 50 degrees, which results in a more uniform and highly mobile charge distribution.

40. The crossbar array of claim 39, wherein the angle is about 30 degrees.

41. The crossbar array of claim 39, wherein the top hBN layer and the BLG form a longwavelength moiré superlattice.

42. The crossbar array of claim 39, wherein the asymmetric moiré heterostructure isconfigured to have an asymmetric moiré potential landscape that divides the moiré synaptic transistor into localized and itinerant subsystems, and wherein the two Attorney Docket No.: 0116936.300WO2 subsystems are separated in a vertical z-direction but remain Coulomb-coupled.

43. The crossbar array of claim 42, wherein the asymmetric moiré potential landscapecomprises a long-range moiré potential at the top interface serving as a charge reservoir that localizes charges, which are separated in the z-direction by less than 1 nm from the conducting channel, which serves as an itinerant system for lateral charge transport.

44. The crossbar array of claim 42, wherein at specific biasing conditions, dynamicalinterplay between the two subsystems leads to carrier ratcheting that accommodates hysteretic, non-volatile carrier transfers that control the conductance of the moiré synaptic transistor.

45. The crossbar array of claim 44, wherein when functioning as an electron ratchet, the topgate adds electrons to the channel in the forward scans but does not fully remove them in the backward scans.

46. The crossbar array of claim 45, wherein gradual increase of the channel conductance isenabled by electron ratchet pulsing.

47. The crossbar array of claim 44, wherein when functioning as a hole ratchet, the top gateadds holes to the channel in the backward scans but does not fully remove them in the forward scans.

48. The crossbar array of claim 47, wherein gradual decrease of the channel conductance isenabled by hole ratchet pulsing.

49. The crossbar array of claim 44, wherein the hysteretic carrier ratcheting results in room-temperature tuning of non-volatile conductance states with unique gate-tunable synaptic plasticity.

50. The crossbar array of claim 49, wherein the gate-tunable synaptic plasticity enables bio- Attorney Docket No.: 0116936.300WO2 realistic neuromorphic functionalities including tunable synaptic responses, spike-based perceptrons, spatiotemporal-based tempotrons, and input-specific adaptations.

51. The crossbar array of claim 44, wherein the moiré synaptic transistor is configured suchthat the top and bottom gates provide differential control over the moiré localization sites and the channel conductance, respectively.

52. The crossbar array of claim 51, wherein the moiré synaptic transistor is capable ofemulating Hebbian learning of biological synapses when the top gate is connected to the pre-neurons and the source is connected to the post-neurons.

53. The crossbar array of claim 51, wherein the synaptic functionalities are facilitated by thevoltage bias (VTG) of the top gate alone.

54. The crossbar array of claim 53, wherein the asymmetry of the BLG / hBN moiréheterostructure enables that the voltage biases (VTG and VBG) of the top gate and the bottom gate provide distinct tunability.

55. The crossbar array of claim 54, wherein the voltage biases (VTG and VBG) of the top gateand the bottom gate have preferential control over the conductance channel and the moiré localization sites, respectively.

56. The crossbar array of claim 55, wherein only in the ratcheting regime does the voltagebias (VTG) of the top gate induce a unidirectional charge injection into the conductance channel.

57. The crossbar array of claim 55, wherein the voltage bias (VTG) of the top gatehysteretically controls the non-volatile ratcheting effect at the top BLG / hBN interface, whereas the voltage bias (VBG) of the bottom gate reversibly controls the conductance channel in a manner analogous to a conventional BLG transistor. Attorney Docket No.: 0116936.300WO258. The crossbar array of claim 55, wherein by exploiting the combined effects of the voltagebiases (VTGand VBG) of the top gate and the bottom gate, the occupation of the moiré localization sites and the channel conductance are deterministically programmable, enabling rich and broad tunability of the MST synaptic response.

59. The crossbar array of claim 55, wherein the contrasting control provided by the voltagebiases (VTG and VBG) of the top gate and the bottom gate enables the realization of neuromorphic input-specific adaptation.

60. The crossbar array of claim 38, wherein each moiré synaptic transistor has low powerconsumption that is equal to or less than 20 pW of power to pass a synaptic spike through the moiré synaptic transistor.

61. The crossbar array of claim 36, wherein the crossbar array has a cell size of 8.75-12.25 F2depending on if the source line is shared between neighboring rows.

62. The crossbar array of claim 36, wherein the crossbar array is a biomimetic MST-basedHopfield neural network that associates a prestored pattern with a similar but nonidentical input pattern.

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