Display panel and display apparatus

Abstract

The present disclosure relates to the technical field of display. Provided are a display panel and a display apparatus. The display panel comprises a pixel driving circuit, wherein the pixel driving circuit comprises a driving transistor, and the driving transistor outputs a driving current on the basis of a voltage difference between a gate electrode and a source electrode of the driving transistor. The display panel further comprises a base substrate, a first active portion, a source electrode portion and a gate electrode portion, wherein the first active portion comprises a first active sub-portion and a second active sub-portion, which are connected to each other, the first active sub-portion is used for forming a channel region of the driving transistor, and the second active sub-portion is a semiconductor structure; the source electrode portion is a conductor structure, the source electrode portion and the second active sub-portion form Schottky contact, and the source electrode portion is used for forming the source electrode of the driving transistor; an orthographic projection of the gate electrode portion on the base substrate covers an orthographic projection of the first active sub-portion on the base substrate, and the gate electrode portion is used for forming the gate electrode of the driving transistor; and in a direction in which the base substrate and the first active portion are stacked, at least part of the source electrode portion and at least part of the gate electrode portion are respectively located at two sides of the second active sub-portion, and the orthographic projections of the source electrode portion and the gate electrode portion, which are located at the two sides of the second active sub-portion, on the base substrate at least partially overlap with each other. The display quality of the display panel can thus be improved. (FIG. 1)

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The pixel drive circuit includes a drive transistor that outputs a drive current based on the gate-source voltage difference of the drive transistor. In related art, the drive transistor is generally a low-temperature polysilicon transistor. However, on the one hand, low-temperature polysilicon transistors produce a significant warping effect at small channel lengths, resulting in poor display uniformity on the display panel; on the other hand, low-temperature polysilicon transistors have a large saturation voltage, which increases the power consumption of the display panel; and on the other hand, low-temperature polysilicon transistors have poor output characteristic uniformity when displaying low grayscale.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a display panel is provided, the display panel including a pixel driving circuit, the pixel driving circuit including a driving transistor, the driving transistor outputting a driving current according to a gate-source voltage difference thereof, and the display panel further including:

[0006] substrate;

[0007] a first active portion, the first active portion including a first sub-active portion and a second sub-active portion connected to each other, the first sub-active portion being used to form a channel region of the driving transistor, and the second sub-active portion being a semiconductor structure;

[0008] a source portion, the source portion being a conductor structure, the source portion and the second sub-active portion forming a Schottky contact, and the source portion being used to form a source of the driving transistor;

[0009] a gate portion, an orthographic projection of the gate portion on the base substrate covering an orthographic projection of the first sub-active portion on the base substrate, the gate portion being used to form a gate of the driving transistor;

[0010] In which, in the stacking direction of the base substrate and the first active portion, at least part of the source portion and at least part of the gate portion are respectively located on both sides of the second sub-active portion, and the orthographic projections of the source portion and the gate portion located on both sides of the second sub-active portion on the base substrate at least partially overlap.

[0011] In an exemplary embodiment of the present disclosure, the conduction band bottom of the second sub-active portion is smaller than a work function of a contact portion between the source portion and the second sub-active portion.

[0012] In an exemplary embodiment of the present disclosure, a difference between a work function of a contact portion between the source portion and the second sub-active portion and a conduction band bottom of the second sub-active portion is greater than or equal to 0.3 eV.

[0013] In an exemplary embodiment of the present disclosure, the orthographic projections of the source portion and the gate portion on both sides of the second sub-active portion on the base substrate and the orthographic projection of the second sub-active portion on the base substrate have a common overlapping area.

[0014] In an exemplary embodiment of the present disclosure, the source portion includes a first source portion and a second source portion;

[0015] The first source portion and the second sub-active portion are connected through a via hole, and the first source portion conformally covers at least a portion of a side wall and at least a portion of a bottom wall of the via hole;

[0016] The second source portion is located on a side of the first source portion away from the second sub-active portion, and the second source portion is at least partially filled in the via hole.

[0017] In an exemplary embodiment of the present disclosure, the first source electrode portion includes one or more of silver oxide, platinum, titanium oxide, and molybdenum oxide.

[0018] In an exemplary embodiment of the present disclosure, the source portion is located on a side of the first active portion facing away from the base substrate, and the gate portion is located between the first active portion and the base substrate.

[0019] In an exemplary embodiment of the present disclosure, the gate portion is located on a side of the first active portion facing away from the base substrate;

[0020] The source portion includes a third source portion and a fourth source portion, the third source portion is in Schottky contact with the second sub-active portion, and the third source portion is at least partially located between the second sub-active portion and the base substrate, and the fourth source portion is connected to the third source portion through a via;

[0021] An orthographic projection of the third source portion on the base substrate and an orthographic projection of the gate portion on the base substrate at least partially overlap.

[0022] In an exemplary embodiment of the present disclosure, the driving transistor is an N-type transistor, the source of the driving transistor is the output end of the driving current, and the pixel driving circuit further includes a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the source of the driving transistor;

[0023] At least a portion of the structure of the gate portion is reused as a first electrode of the capacitor, and at least a portion of the structure of the source portion is reused as a second electrode of the capacitor.

[0024] In an exemplary embodiment of the present disclosure, the first active portion further includes a third sub-active portion, and the first sub-active portion is connected between the second sub-active portion and the third sub-active portion;

[0025] The display panel further includes:

[0026] The drain portion is a conductor structure, the drain portion and the third sub-active portion form a Schottky contact, and the drain portion is used to form the drain of the driving transistor.

[0027] In an exemplary embodiment of the present disclosure, the width-to-length ratio of the channel region of the driving transistor is 2 / 2-2 / 10.

[0028] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0029] a gate layer, located on one side of the base substrate, the gate layer including the gate portion;

[0030] an active layer, located on a side of the gate layer facing away from the base substrate, the active layer including the first active portion;

[0031] a Schottky contact layer, the Schottky contact layer including a first source portion, wherein the first source portion and the second sub-source portion form a Schottky contact;

[0032] a first source-drain layer, located on a side of the Schottky contact layer facing away from the substrate, the first source-drain layer including a second source portion, the second source portion being electrically connected to the first source portion;

[0033] The first source portion and the second source portion constitute the source portion.

[0034] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0035] a dielectric layer located between the active layer and the Schottky contact layer, wherein a via is formed in the dielectric layer, and the via exposes at least a portion of the second sub-active portion outside the dielectric layer;

[0036] The first source portion conformally covers at least a portion of the sidewalls and at least a portion of the bottom wall of the via hole, and the second source portion at least partially fills the via hole.

[0037] In an exemplary embodiment of the present disclosure, the first active portion further includes a third sub-active portion, and the first sub-active portion is connected between the second sub-active portion and the third sub-active portion;

[0038] The Schottky contact layer includes a first drain portion, and the first drain portion and the third sub-source portion form a Schottky contact;

[0039] The first source-drain layer further includes a second drain portion, the second drain portion is electrically connected to the first drain portion, and the first drain portion and the second drain portion constitute a drain of the driving transistor.

[0040] In an exemplary embodiment of the present disclosure, the length direction of the channel region of the driving transistor is a first direction;

[0041] The gate portion includes a first gate portion, the second source portion includes a first conductive portion, the orthographic projection of the first gate portion on the base substrate is located on one side of the orthographic projection of the first sub-active portion on the base substrate in the second direction, and the orthographic projection of the second source portion on the base substrate is located on one side of the orthographic projection of the first sub-active portion on the base substrate in the second direction;

[0042] An orthographic projection of the first gate portion on the base substrate and an orthographic projection of the first conductive portion on the base substrate at least partially overlap, and the first direction and the second direction intersect.

[0043] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes: a fourth transistor, wherein a first electrode of the fourth transistor is connected to the initial signal line, a second electrode is connected to the source of the driving transistor, and a gate is connected to the reset signal line;

[0044] The gate layer further includes the reset signal line, and the orthographic projection of the reset signal line on the base substrate extends along a first direction;

[0045] In the second direction, the orthographic projection of the first gate portion and the orthographic projection of the second source portion on the base substrate are located between the orthographic projection of the reset signal line and the orthographic projection of the first sub-active portion on the base substrate.

[0046] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes: a switching transistor;

[0047] The gate layer further includes a gate line, an orthographic projection of the gate line on the base substrate extending along a first direction, and a partial structure of the gate line being used to form a gate of the switching transistor;

[0048] The gate line includes sub-gate lines that are spaced and extended in the first direction, and the first source and drain layer further includes a connecting line, an orthographic projection of the connecting line on the base substrate extending in the first direction, and the connecting line connects multiple sub-gate lines in the same gate line through vias;

[0049] The square resistance of the gate layer is greater than the square resistance of the first source and drain layer.

[0050] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes:

[0051] a second transistor, a first electrode of which is connected to the data line, a second electrode of which is connected to the gate of the driving transistor, and a gate of which is connected to the second gate line;

[0052] a third transistor, a first electrode of which is connected to the reference voltage line, a second electrode of which is connected to the gate of the driving transistor, and a gate of which is connected to the first gate line;

[0053] a fourth transistor, having a first electrode connected to the initial signal line, a second electrode connected to the source of the driving transistor, and a gate connected to the reset signal line;

[0054] a fifth transistor, having a first electrode connected to the power line, a second electrode connected to the drain of the driving transistor, and a gate connected to the enable signal line;

[0055] The first gate line, the second gate line, the reset signal line, and the enable signal line are located in the gate layer, a portion of the first gate line is used to form the gate of the third transistor, a portion of the second gate line is used to form the gate of the second transistor, a portion of the reset signal line is used to form the gate of the fourth transistor, and a portion of the enable signal line is used to form the gate of the fifth transistor;

[0056] The orthographic projections of the first gate line, the second gate line, the reset signal line, and the enable signal line on the base substrate extend along a first direction;

[0057] In the same pixel driving circuit, the orthographic projection of the enable signal line on the base substrate, the orthographic projection of the reset signal line on the base substrate, the orthographic projection of the gate portion on the base substrate, the orthographic projection of the second gate line on the base substrate, and the orthographic projection of the first gate line on the base substrate are distributed in sequence in the second direction, and the first direction and the second direction intersect.

[0058] In an exemplary embodiment of the present disclosure, according to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0059] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0061] FIG1 is a schematic structural diagram of a driving transistor in an exemplary embodiment of a display panel disclosed herein;

[0062] FIG2 is a diagram showing the working principle of a driving transistor in a display panel of the present disclosure;

[0063] FIG3 is a schematic structural diagram of a driving transistor in another exemplary embodiment of a display panel disclosed herein;

[0064] FIG4 is a schematic structural diagram of a driving transistor in another exemplary embodiment of a display panel disclosed herein;

[0065] FIG5 is a schematic structural diagram of a pixel driving circuit in an exemplary embodiment of a display panel disclosed herein;

[0066] FIG6 is a timing diagram of each node in a driving method of the pixel driving circuit shown in FIG5 ;

[0067] FIG7 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0068] FIG8 is a structural layout diagram of the gate layer in the display panel shown in FIG7 ;

[0069] FIG9 is a structural diagram of the active layer in the display panel shown in FIG7 ;

[0070] FIG10 is a structural diagram of the Schottky contact layer in the display panel shown in FIG7 ;

[0071] FIG11 is a structural layout diagram of the first source and drain layer in the display panel shown in FIG7 ;

[0072] FIG12 is a structural layout diagram of the second source and drain layer in the display panel shown in FIG7 ;

[0073] FIG13 is a structural layout diagram of the gate layer and active layer in the display panel shown in FIG7 ;

[0074] FIG14 is a structural layout diagram of the gate layer, active layer, and Schottky contact layer in the display panel shown in FIG7 ;

[0075] FIG15 is a structural layout diagram of the gate layer, active layer, Schottky contact layer, and first source and drain layer in the display panel shown in FIG7 ;

[0076] FIG16 is a structural layout diagram of the gate layer, active layer, Schottky contact layer, first source and drain layer, and second source and drain layer in the display panel shown in FIG7 ;

[0077] FIG17 is a partial cross-sectional view of the display panel shown in FIG7 taken along dotted line AA. DETAILED DESCRIPTION

[0078] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0079] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "comprising" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0080] In the related art, the driving transistor operates in the saturation region, and the source-drain voltage difference of the driving transistor is equal to the sum of the saturation voltage of the driving transistor and the compensation voltage. The saturation voltage of the driving transistor is the minimum drain-source voltage at which the driving transistor enters the saturation region, and the compensation voltage is used to compensate for the voltage drop of the signal line in the display panel. In the related art, the saturation voltage of the driving transistor is relatively high, and accordingly, the compensation voltage is also relatively high. The driving transistor operates at a relatively high source-drain voltage difference, which increases the power consumption of the display panel. In addition, in the related art, the warping effect of the driving transistor is relatively obvious, which affects the uniformity of the display of the display panel.

[0081] Based on this, this exemplary embodiment first provides a display panel. The display panel includes a pixel driving circuit, which includes a driving transistor. The driving transistor outputs a driving current based on its gate-source voltage difference. FIG1 is a schematic diagram of the structure of the driving transistor in an exemplary embodiment of the display panel disclosed herein. The display panel also includes a base substrate 91, a first active portion 51, a source portion 6, and a gate portion 11. The first active portion 51 includes a first sub-active portion 511 and a second sub-active portion 512 connected to each other, the first sub-active portion 511 is used to form a channel region of the driving transistor, and the second sub-active portion 512 is a semiconductor structure; the source portion 6 is a conductor structure, the source portion 6 and the second sub-active portion 512 form a Schottky contact, and the source portion 6 is used to form the source of the driving transistor; the orthographic projection of the gate portion 11 on the base substrate 91 covers the orthographic projection of the first sub-active portion 511 on the base substrate, and the gate portion 11 is used to form the gate of the driving transistor T1; wherein, in the stacking direction of the base substrate 91 and the first active portion 51, at least part of the source portion 6 and at least part of the gate portion 11 are respectively located on both sides of the second sub-active portion 512, and the orthographic projections of the source portion 6 and the gate portion 11 located on both sides of the second sub-active portion 512 on the base substrate at least partially overlap.

[0082] In this exemplary embodiment, a Schottky contact is formed between the source portion 6 and the second sub-active portion 512 of the driver transistor, forming a potential barrier between the source portion 6 and the second sub-active portion 512. The gate-source voltage difference of the driver transistor can adjust the potential barrier between the source portion 6 and the second sub-active portion 512, thereby adjusting the output current of the driver transistor. Meanwhile, as shown in FIG2 , which is a diagram of the operating principle of the driver transistor in the display panel of the present disclosure, this exemplary embodiment utilizes the source portion 6 and the gate portion 11 located on both sides of the second sub-active portion 512 to form an electric field at the position of the second sub-active portion 512. This electric field can form a depletion layer 5121 and an accumulation layer 5122 in the second sub-active portion 512. The depletion layer 5121 can form an auxiliary current channel between the source and drain of the driver transistor, thereby adjusting the output characteristics of the driver transistor. In this exemplary embodiment, the driving transistor is set as a source-gated transistor (SGT) through the above structure. The source-gated transistor has a smaller saturation voltage, a very small warping effect, and a wider saturation voltage range. In addition, the source-gated transistor has a more stable output characteristic when outputting a small current, so that the driving transistor can reduce the power consumption of the display panel and also improve the uniformity of the display panel.

[0083] In the present exemplary embodiment, the conduction band bottom of the second sub-active portion 512 is smaller than the work function of the contact portion between the source portion 6 and the second sub-active portion 512. The difference between the work function of the contact portion between the source portion 6 and the second sub-active portion 512 and the conduction band bottom of the second sub-active portion 512 is greater than or equal to 0.3 eV. For example, the difference between the work function of the contact portion between the source portion 6 and the second sub-active portion 512 and the conduction band bottom of the second sub-active portion 512 may be equal to 0.3 eV, 0.4 eV, 0.5 eV, 0.6 eV, 0.7 eV, 0.8 eV, 0.9 eV, 1 eV, 2 eV, 3 eV, 4 eV, 5 eV, etc.

[0084] In this exemplary embodiment, as shown in FIG1 , the orthographic projections of the source portion 6 and gate portion 11 on either side of the second sub-active portion 512 on the substrate 91 and the orthographic projection of the second sub-active portion 512 on the substrate have a common overlapping region. In other words, the three orthographic projections have a common overlapping region. This arrangement allows the second sub-active portion 512 to be located between the parallel plate capacitor structure formed by the source portion 6 and the gate portion 11, thereby facilitating the formation of a depletion layer and an accumulation layer on the second sub-active portion 512.

[0085] It should be understood that in other exemplary embodiments, the orthographic projection of the second sub-active portion 512 on the base substrate may also be located outside the overlapping region of the orthographic projections of the source portion 6 and the gate portion 11 on the base substrate 91. That is, the second sub-active portion 512 is located outside the parallel plate capacitor structure formed by the source portion 6 and the gate portion 11. Furthermore, in other exemplary embodiments, the driving transistor may also be a source-gated transistor having other structures.

[0086] In this exemplary embodiment, as shown in FIG1 , the source portion 6 may include a first source portion 61 and a second source portion 62 . The first source portion 61 and the second sub-active portion 512 are connected via a via, with the first source portion 61 conformally covering at least a portion of the sidewalls and at least a portion of the bottom wall of the via. The second source portion 62 is located on the side of the first source portion 61 facing away from the second sub-active portion 512 , and at least partially fills the via, wherein the bottom wall of the via is formed by the second sub-active portion 512 . The first source portion 61 is generally made of a precious metal material; for example, the first source portion 61 may include one or more of silver oxide, platinum, titanium oxide, and molybdenum oxide. In this exemplary embodiment, the first source portion 61 conformally covers the sidewalls and bottom wall of the via, thereby reducing the volume of the first source portion 61. The second source portion 62 is in ohmic contact with the first source portion 61. The second source portion 62 can be made of a low-cost metal. For example, the second source portion 62 can be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum / titanium alloy or a stack, or can be a conductive layer such as a titanium / aluminum / titanium stack.

[0087] In this exemplary embodiment, the first active portion 51 may be indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium gallium tin oxide (IGTO), or the like.

[0088] 1 , the source portion 6 is located on a side of the first active portion 51 away from the substrate 91 , and the gate portion 11 is located between the first active portion 51 and the substrate 91 . That is, the driving transistor has a bottom-gate structure.

[0089] In this exemplary embodiment, as shown in FIG. 1 , the display panel may further include a first insulating layer 92 and a dielectric layer 93 . The first insulating layer 92 is located between the gate portion 11 and the first active portion 51 , and the dielectric layer 93 is located between the first active portion 51 and the source portion 6 .

[0090] In this exemplary embodiment, as shown in FIG1 , the first active portion 51 may further include a third sub-active portion 513 , wherein the first sub-active portion 511 is connected between the second sub-active portion 512 and the third sub-active portion 513 . The display panel further includes a drain portion 7 , which is a conductive structure. The drain portion 7 forms a Schottky contact with the third sub-active portion 513 and is used to form the drain of the driving transistor. As shown in FIG1 , the drain portion 7 may include a first drain portion 71 and a second drain portion 72 . The first drain portion 71 and the third sub-active portion 513 are connected via a via. The first drain portion 71 conformally covers at least a portion of the sidewalls and at least a portion of the bottom wall of the via. The second drain portion 72 is located on a side of the first drain portion 71 facing away from the third sub-active portion 513 and at least partially fills the via. The first drain portion 71 may include one or more of silver oxide, platinum, titanium oxide, or molybdenum oxide. The second drain portion 72 is in ohmic contact with the first drain portion 71 . The second drain portion 72 can be made of one of molybdenum, aluminum, copper, titanium, niobium, or an alloy, or a molybdenum / titanium alloy or a stack, or a conductive layer such as a titanium / aluminum / titanium stack.

[0091] In this exemplary embodiment, a method for manufacturing a display panel may include: forming a gate portion 11 on a base substrate 91 through a patterning process; forming a first insulating layer 92 on the gate portion 11; forming a first active portion 51 on the first insulating layer 92 through a patterning process; forming a dielectric layer 93 on the first active portion 51; forming at least two vias on the dielectric layer 93 to expose at least a portion of the second sub-active portion 512 and at least a portion of the third sub-active portion 513, respectively; the first source portion 61 and the first drain portion 71 may be deposited in the vias respectively through a sputtering process; finally, the second source portion 62 and the second drain portion 72 may be arranged on the first source portion 61 and the first drain portion, respectively.

[0092] It should be understood that in other exemplary embodiments, the first source portion 61 may be arranged in other ways. For example, FIG. 3 is a schematic diagram of the structure of a driving transistor in another exemplary embodiment of the display panel of the present disclosure. The first source portion 61 and the first drain portion 71 may be located between the dielectric layer 93 and the first active portion 51.

[0093] In other exemplary embodiments, the driver transistor may also have a top-gate structure. FIG4 shows a schematic diagram of the structure of a driver transistor in another exemplary embodiment of the display panel disclosed herein. The gate portion 11 may be located on the side of the first active portion 51 facing away from the substrate 91. The source portion 6 may include a third source portion 63 and a fourth source portion 64. The third source portion 63 forms a Schottky contact with the second sub-active portion 512. The third source portion 63 is at least partially located between the second sub-active portion 512 and the substrate 91. The fourth source portion 64 is connected to the third source portion 63 via a via. The orthographic projection of the third source portion 63 on the substrate at least partially overlaps with the orthographic projection of the gate portion 11 on the substrate.

[0094] As shown in Figure 4, the drain portion 7 may also include a third drain portion 73 and a fourth drain portion 74. The third drain portion 73 and the third sub-active portion 513 are in Schottky contact. The third drain portion 73 is at least partially located between the third sub-active portion 513 and the base substrate 91. The fourth drain portion 74 is connected to the third drain portion 73 through a via.

[0095] In this exemplary embodiment, the driving transistor can be an N-type transistor, the source of the driving transistor is the output terminal of the driving current, and the pixel driving circuit also includes a capacitor, the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode of the capacitor is connected to the source of the driving transistor; the capacitor is used to maintain its gate-source voltage difference when the driving transistor outputs current to its source, thereby maintaining its output current unchanged. In the source-gated transistor provided in this exemplary embodiment, at least part of the structure of the gate portion 11 can be reused as the first electrode of the capacitor, and at least part of the structure of the source portion 6 can be reused as the second electrode of the capacitor. This display panel can save the space for setting up the capacitor, thereby improving the integration of the display panel.

[0096] In this exemplary embodiment, the source-gated transistor has a low saturation voltage, minimal warping effect, and a wide saturation voltage range. The source-gated transistor can have a relatively small channel length while ensuring desired output characteristics. In this exemplary embodiment, the width-to-length ratio of the driver transistor channel region can be 2 / 2-2 / 10. For example, the width-to-length ratio of the driver transistor channel region can be 2 / 2, 2 / 3, 2 / 4, 2 / 5, 2 / 6, 2 / 7, 2 / 8, 2 / 9, 2 / 10, etc.

[0097] Figure 5 shows a schematic diagram of a pixel driving circuit in an exemplary embodiment of a display panel disclosed herein. The pixel driving circuit includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a capacitor C. The first electrode of the second transistor T2 is connected to the data line Data, and the second electrode is connected to the gate of the driving transistor T1, which is also connected to the second gate line G2. The first electrode of the third transistor T3 is connected to the reference voltage line Vref, and the second electrode is connected to the gate of the driving transistor T1, which is also connected to the first gate line G1. The first electrode of the fourth transistor T4 is connected to the initial signal line Vinit, the second electrode is connected to the source of the driving transistor T1, and the gate is connected to the reset signal line Re. The first electrode of the fifth transistor T5 is connected to the power line VDD, the second electrode is connected to the drain of the driving transistor T1, and the gate is connected to the enable signal line EM. The driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all N-type transistors. The first electrode of the capacitor C is connected to the gate of the driving transistor, and the second electrode of the capacitor C is connected to the source of the driving transistor. The pixel driving circuit is used to drive a light emitting unit OLED, wherein a first electrode of the light emitting unit OLED is connected to a source of a driving transistor, and a second electrode of the light emitting unit OLED is connected to a common electrode VSS.

[0098] Figure 6 shows a timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 5. Re is a timing diagram of the reset signal line, G1 is a timing diagram of the first gate line, G2 is a timing diagram of the second gate line, and EM is a timing diagram of the enable signal line.

[0099] The driving method of the pixel driving circuit includes: an initialization phase t1, a threshold compensation phase t2, a data writing phase t3, and a light-emitting phase t4. In the initialization phase t1: the reset signal line Re1 and the first gate line G1 output a high-level signal, the third transistor T3 and the fourth transistor T4 are turned on, the initial signal line Vinit inputs an initial signal to the source of the driving transistor T1, and the reference voltage line Vref inputs a reference voltage to the gate of the driving transistor T1. In the threshold compensation phase t2: the first gate line G1 and the enable signal line EM output a high-level signal, the third transistor T3 is continuously turned on, the reference voltage line Vref continuously inputs a reference voltage Vf to the gate of the driving transistor T1, and the source voltage of the driving transistor T1 becomes Vf-Vth, where Vth is the threshold voltage of the driving transistor. In the data writing phase t3: the second gate line G2 outputs a high-level signal, the second transistor T2 is turned on, and the data line Data writes a data signal Vda to the gate of the driving transistor. In the light-emitting stage t4: the enable signal line EM outputs a high-level signal, the fifth transistor T5 is turned on, and the driving transistor T1 outputs a driving current, wherein the driving current I = (μWCox / 2L)(Vgs-Vth) 2=(μWCox / 2L)(Vda-(Vf-Vth)-Vth) 2 , where μ is carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driver transistor channel; L is the length of the driver transistor channel; Vgs is the gate-source voltage difference of the driver transistor; and Vth is the threshold voltage of the driver transistor. This pixel driver circuit can avoid the influence of the driver transistor threshold on its output current.

[0100] In this exemplary embodiment, the display panel may include a gate layer, an active layer, a Schottky contact layer, a first source and drain layer, a second source and drain layer, and an electrode layer stacked in sequence, with an insulating layer disposed between the layers. As shown in Figures 7-16, Figure 7 is a structural layout diagram of an exemplary embodiment of a display panel of the present disclosure, Figure 8 is a structural layout diagram of a gate layer in the display panel shown in Figure 7, Figure 9 is a structural layout diagram of an active layer in the display panel shown in Figure 7, Figure 10 is a structural layout diagram of a Schottky contact layer in the display panel shown in Figure 7, Figure 11 is a structural layout diagram of a first source / drain layer in the display panel shown in Figure 7, Figure 12 is a structural layout diagram of a second source / drain layer in the display panel shown in Figure 7, Figure 13 is a structural layout diagram of a gate layer and an active layer in the display panel shown in Figure 7, Figure 14 is a structural layout diagram of a gate layer, an active layer, and a Schottky contact layer in the display panel shown in Figure 7, Figure 15 is a structural layout diagram of a gate layer, an active layer, a Schottky contact layer, and a first source / drain layer in the display panel shown in Figure 7, and Figure 16 is a structural layout diagram of a gate layer, an active layer, a Schottky contact layer, a first source / drain layer, and a second source / drain layer in the display panel shown in Figure 7. The display panel includes a plurality of pixel driving circuits arranged in an array along a first direction X and a second direction Y.

[0101] As shown in Figures 7, 8, and 13, the gate layer may include a gate portion 11, a first gate line G1, a reset signal line Re, a first gate line Ga1, a second gate line G2, and an enable signal line EM. The orthographic projections of the reset signal line Re, the first gate line G1, the second gate line G2, and the enable signal line EM on the substrate all extend along the first direction X. The gate portion 11 is used to form the gate of the driving transistor T1, a portion of the first gate line G1 is used to form the gate of the third transistor T3, a portion of the second gate line G2 is used to form the gate line of the second transistor T2, a portion of the reset signal line Re is used to form the gate of the fourth transistor, and a portion of the enable signal line EM is used to form the gate of the fifth transistor. The second gate line G2 may include a plurality of second sub-gate lines G21 extending along the first direction X and spaced apart, and the reset signal line Re may include a plurality of sub-reset signal lines Re1 extending along the first direction X and spaced apart.

[0102] As shown in Figures 7, 9, and 13, the active layer may include a first active portion 51, a second active portion 52, a third active portion 53, a fourth active portion 54, and a fifth active portion 55. The first active portion 51 includes a first sub-active portion 511, a second sub-active portion 512, and a third sub-active portion 513 connected to both ends of the first sub-active portion 511. The first sub-active portion 511 is used to form the channel region of the driving transistor T1, the second active portion 52 is used to form the channel region of the second transistor T2, the third active portion 53 is used to form the channel region of the third transistor T3, the fourth active portion 54 is used to form the channel region of the fourth transistor T4, and the fifth active portion 55 is used to form the channel region of the fifth transistor T5. In addition, the active layer may further include a sixth active portion 56, a seventh active portion 57, an eighth active portion 58, a ninth active portion 59, a tenth active portion 510, a fourteenth active portion 514, and a fifteenth active portion 515.

[0103] As shown in Figures 7, 10, and 14, the Schottky contact layer includes a first source portion 61 and a first drain portion 71. The first source portion 61 can be connected to the second sub-active portion 512 through a via, and the first source portion 61 can be conformally covered on the bottom wall and side walls of the via; the first drain portion 71 can be connected to the third sub-active portion 513 through a via, and the first drain portion 71 can be conformally covered on the bottom wall and side walls of the via.

[0104] As shown in Figures 7, 11, and 15, the first source-drain layer includes a power line 2VDD, an initial signal line Vinit, a reset connection line 2Re, a second source portion 62, a second drain portion 72, a third bridge portion 23, a fourth bridge portion 24, a second gate connection line 2G2, and a reference voltage line Vref. The orthographic projections of the power line 2VDD, the initial signal line Vinit, the reset connection line 2Re, the reference voltage line Vref, and the second gate connection line 2G2 on the substrate extend along a first direction X. The power line 2VDD is connected to the eighth active portion 58 through a via, thereby connecting to the first electrode of the fifth transistor T5; the initial signal line Vinit is connected to the tenth active portion 510 through a via, thereby connecting to the first electrode of the fourth transistor T4; and the reference voltage line Vref is connected to the fourteenth active portion 514 through a via, thereby connecting to the first electrode of the third transistor T3. The reset connection line 2Re is connected to multiple sub-reset signal lines Re1 in the same reset signal line Re through a via; the second gate connection line 2G2 is connected to multiple second sub-gate lines G21 in the same second gate line G2 through a via. In this exemplary embodiment, the square resistance of the first source and drain layer is less than the square resistance of the gate layer. This setting can reduce the voltage difference of the gates of multiple fourth transistors T4 connected to the same reset signal line Re, and reduce the voltage difference of the gates of multiple second transistors connected to the same second gate line G2, thereby improving the uniformity of the display panel. It should be understood that in other exemplary embodiments, other gate lines may also include sub-gate lines that are spaced and extended along the first direction. Accordingly, the first source and drain layer may include a connection line, the orthographic projection of the connection line on the substrate extends in the first direction, and the connection line connects multiple sub-gate lines in the same gate line through a via. Among them, the gate line is a signal line extending along the first direction and used to form the transistor gate. For example, the first gate line and the enable signal line are both gate lines. The second source portion 62 overlies the first source portion 61, and is partially located within the via hole where the first source portion 61 is located. The second drain portion 72 overlies the first drain portion 71, and is partially located within the via hole where the first drain portion 71 is located. The third bridge portion 23 connects to the sixth active portion 56 and the gate portion 11 through via holes, respectively, to connect the second electrode of the second transistor T2 and the gate of the driving transistor T1. The fourth bridge portion 24 connects to the seventh active portion 57 through a via hole, to connect the first electrode of the second transistor T2.

[0105] As shown in Figures 7, 8, and 11, the longitudinal direction of the channel region of the driving transistor is the first direction X; the gate portion 11 includes a first gate portion 111, and the second source portion 62 includes a first conductive portion 621. The orthographic projection of the first gate portion 111 on the substrate is located on one side of the orthographic projection of the first sub-active portion 511 on the substrate in the second direction Y, and the orthographic projection of the second source portion 62 on the substrate is located on one side of the orthographic projection of the first sub-active portion 511 on the substrate in the second direction Y; the orthographic projection of the first gate portion 111 on the substrate and the orthographic projection of the first conductive portion 621 on the substrate at least partially overlap, the first gate portion 111 can be used to form a first electrode of a capacitor, and the first conductive portion 621 can be used to form a second electrode of a capacitor.

[0106] As shown in Figures 7, 12, and 16, the second source-drain layer includes: a data line Data, a power connection line 3VDD, and a fifth bridge portion 35. The data line Data is connected to the fourth bridge portion 24 through a via to connect to the first electrode of the second transistor. The power connection line 3VDD is connected to the intersecting power line 2VDD through a via. The power connection line 3VDD and the power line 2VDD form a grid structure. The power lines in this grid structure have low resistance, thereby improving the display uniformity of the display panel. The fifth bridge portion 35 can be connected to the second source portion 62 through a via.

[0107] As shown in FIG7 , the electrode layer may include a plurality of electrode portions, which may include an electrode portion R, an electrode portion G (not shown), and an electrode portion B. The electrode portions may be connected to the fifth bridge portion 35 through vias to connect to the source of the driving transistor.

[0108] It should be noted that, as shown in Figures 7, 14, 15, and 16, the black squares drawn on the side of the Schottky contact layer facing away from the substrate represent vias connecting the Schottky contact layer to other layers facing the substrate; the black squares drawn on the side of the first source / drain layer facing away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black squares drawn on the side of the second source / drain layer facing away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate. The black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. Different vias represented by black squares in different positions can penetrate different insulating layers.

[0109] FIG17 is a partial cross-sectional view of the display panel shown in FIG7 taken along dashed line AA. The display panel includes a base substrate 91, a gate layer, a first insulating layer 92, an active layer, a dielectric layer 93, a Schottky contact layer, a first source / drain layer, a passivation layer 94, a planarization layer 95, and an electrode layer, which are stacked in sequence. The first insulating layer 92 can be a single-layer or multi-layer structure and can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The dielectric layer 93 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or silicon-glass bonding (SOG). The passivation layer 94 can be a silicon oxide layer. The base substrate 91 can include a glass substrate, a barrier layer, and a polyimide layer, which can be stacked in sequence. The barrier layer can be an inorganic material. The gate layer can be made of one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The first source and drain layer and the second source and drain layer may include metal materials, for example, one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum / titanium alloy or a stack, or a conductive layer such as a titanium / aluminum / titanium stack.

[0110] It should be noted that the proportions of the drawings in this disclosure can be used as a reference in actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to limit different structural names, and they do not have a specific order of meaning. The same structural layer can be formed by the same composition process. In this exemplary embodiment, the orthographic projection of a certain structure on the base substrate extends in a certain direction, which can be understood as the orthographic projection of the structure on the base substrate extending in a straight line or bending along that direction.

[0111] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0112] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0113] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0114] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor, and the driving transistor outputs a driving current according to a gate-source voltage difference thereof. The display panel further includes: substrate; a first active portion, the first active portion including a first sub-active portion and a second sub-active portion connected to each other, the first sub-active portion being used to form a channel region of the driving transistor, and the second sub-active portion being a semiconductor structure; a source portion, the source portion being a conductor structure, the source portion and the second sub-active portion forming a Schottky contact, and the source portion being used to form a source of the driving transistor; a gate portion, an orthographic projection of the gate portion on the base substrate covering an orthographic projection of the first sub-active portion on the base substrate, the gate portion being used to form a gate of the driving transistor; In which, in the stacking direction of the base substrate and the first active portion, at least part of the source portion and at least part of the gate portion are respectively located on both sides of the second sub-active portion, and the orthographic projections of the source portion and the gate portion located on both sides of the second sub-active portion on the base substrate at least partially overlap.

2. The display panel according to claim 1, wherein A conduction band bottom of the second sub-active portion is smaller than a work function of a contact portion between the source portion and the second sub-active portion.

3. The display panel according to claim 2, wherein: A difference between a work function of a contact portion between the source portion and the second sub-active portion and a conduction band bottom of the second sub-active portion is greater than or equal to 0.3 eV.

4. The display panel according to claim 1, wherein: The orthographic projections of the source portion and the gate portion located on both sides of the second sub-active portion on the base substrate and the orthographic projection of the second sub-active portion on the base substrate have a common overlapping area.

5. The display panel according to claim 1, wherein: The source portion includes a first source portion and a second source portion; The first source portion and the second sub-active portion are connected through a via hole, and the first source portion conformally covers at least a portion of a side wall and at least a portion of a bottom wall of the via hole; The second source portion is located on a side of the first source portion away from the second sub-active portion, The second source portion is at least partially filled in the via hole. The display panel according to claim 5 , wherein: The first source portion includes one or more of silver oxide, platinum, titanium oxide, and molybdenum oxide.

7. The display panel according to claim 1, wherein: The source portion is located on a side of the first active portion facing away from the base substrate, and the gate portion is located between the first active portion and the base substrate.

8. The display panel according to claim 1, wherein: The gate portion is located on a side of the first active portion facing away from the base substrate; The source portion includes a third source portion and a fourth source portion, the third source portion is in Schottky contact with the second sub-active portion, and the third source portion is at least partially located between the second sub-active portion and the base substrate, and the fourth source portion is connected to the third source portion through a via; An orthographic projection of the third source portion on the base substrate and an orthographic projection of the gate portion on the base substrate at least partially overlap.

9. The display panel according to claim 1, wherein: The driving transistor is an N-type transistor, the source of the driving transistor is the output end of the driving current, the pixel driving circuit further includes a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the source of the driving transistor; At least a portion of the structure of the gate portion is reused as a first electrode of the capacitor, and at least a portion of the structure of the source portion is reused as a second electrode of the capacitor.

10. The display panel according to claim 5, wherein: The first active portion further includes a third sub-active portion, wherein the first sub-active portion is connected between the second sub-active portion and the third sub-active portion; The display panel further includes: The drain portion is a conductor structure, the drain portion and the third sub-active portion form a Schottky contact, and the drain portion is used to form the drain of the driving transistor.

11. The display panel according to claim 1, wherein: The width-to-length ratio of the channel region of the driving transistor is 2 / 2-2 / 10.

12. The display panel according to claim 1, wherein: The display panel further includes: a gate layer, located on one side of the base substrate, the gate layer including the gate portion; An active layer is located on the side of the gate layer away from the substrate, and the active layer includes the first active portion; a Schottky contact layer, the Schottky contact layer including a first source portion, wherein the first source portion and the second sub-source portion form a Schottky contact; a first source-drain layer, located on a side of the Schottky contact layer facing away from the substrate, the first source-drain layer including a second source portion, the second source portion being electrically connected to the first source portion; The first source portion and the second source portion constitute the source portion.

13. The display panel according to claim 12, wherein: The display panel further includes: a dielectric layer located between the active layer and the Schottky contact layer, wherein a via is formed in the dielectric layer, and the via exposes at least a portion of the second sub-active portion outside the dielectric layer; The first source portion conformally covers at least a portion of the sidewalls and at least a portion of the bottom wall of the via hole, and the second source portion at least partially fills the via hole.

14. The display panel according to claim 12, wherein: The first active portion further includes a third sub-active portion, wherein the first sub-active portion is connected between the second sub-active portion and the third sub-active portion; The Schottky contact layer includes a first drain portion, and the first drain portion and the third sub-source portion form a Schottky contact; The first source-drain layer further includes a second drain portion, the second drain portion is electrically connected to the first drain portion, and the first drain portion and the second drain portion constitute a drain of the driving transistor.

15. The display panel according to claim 12, wherein: The length direction of the channel region of the driving transistor is a first direction; The gate portion includes a first gate portion, the second source portion includes a first conductive portion, the orthographic projection of the first gate portion on the base substrate is located on one side of the orthographic projection of the first sub-active portion on the base substrate in the second direction, and the orthographic projection of the second source portion on the base substrate is located on one side of the orthographic projection of the first sub-active portion on the base substrate in the second direction; An orthographic projection of the first gate portion on the base substrate and an orthographic projection of the first conductive portion on the base substrate at least partially overlap, and the first direction and the second direction intersect.

16. The display panel according to claim 15, wherein: The pixel driving circuit further includes: a fourth transistor, wherein a first electrode of the fourth transistor is connected to the initial signal line, a second electrode is connected to the source of the driving transistor, and a gate is connected to the reset signal line; The gate layer further includes the reset signal line, and the orthographic projection of the reset signal line on the base substrate extends along a first direction; In the second direction, the orthographic projection of the first gate portion and the orthographic projection of the second source portion on the base substrate are located between the orthographic projection of the reset signal line and the orthographic projection of the first sub-active portion on the base substrate.

17. The display panel according to claim 12, wherein: The pixel driving circuit further includes: a switching transistor; The gate layer further includes a gate line, an orthographic projection of the gate line on the base substrate extending along a first direction, and a partial structure of the gate line being used to form a gate of the switching transistor; The gate line includes sub-gate lines that are spaced and extended in the first direction, the first source and drain layer further includes a connecting line, an orthographic projection of the connecting line on the substrate extends in the first direction, and the connecting line connects multiple sub-gate lines in the same gate line through vias; The square resistance of the gate layer is greater than the square resistance of the first source and drain layer.

18. The display panel according to claim 12, wherein: The pixel driving circuit further includes: a second transistor, a first electrode of which is connected to the data line, a second electrode of which is connected to the gate of the driving transistor, and a gate of which is connected to the second gate line; a third transistor, a first electrode of which is connected to the reference voltage line, a second electrode of which is connected to the gate of the driving transistor, and a gate of which is connected to the first gate line; a fourth transistor, having a first electrode connected to the initial signal line, a second electrode connected to the source of the driving transistor, and a gate connected to the reset signal line; a fifth transistor, having a first electrode connected to the power line, a second electrode connected to the drain of the driving transistor, and a gate connected to the enable signal line; The first gate line, the second gate line, the reset signal line, and the enable signal line are located in the gate layer, a portion of the first gate line is used to form the gate of the third transistor, a portion of the second gate line is used to form the gate of the second transistor, a portion of the reset signal line is used to form the gate of the fourth transistor, and a portion of the enable signal line is used to form the gate of the fifth transistor; The first gate line, the second gate line, the reset signal line, and the enable signal line are arranged on the substrate The orthographic projection on extends along the first direction; In the same pixel driving circuit, the orthographic projection of the enable signal line on the base substrate, the orthographic projection of the reset signal line on the base substrate, the orthographic projection of the gate portion on the base substrate, the orthographic projection of the second gate line on the base substrate, and the orthographic projection of the first gate line on the base substrate are distributed in sequence in the second direction, and the first direction and the second direction intersect.

19. A display device, wherein: The display device comprises the display panel according to any one of claims 1 to 18.

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