Non-isolated resonant gate driving circuit

Abstract

The present invention provides a non-isolated resonant gate driving circuit, comprising a PMOS driving network, an NMOS clamping circuit, and an inductor, wherein the PMOS driving network and the NMOS clamping circuit are connected in parallel to two ends of the inductor; input signals of the PMOS driving network are provided by a function generator rear-connected driving chip; the input signals are processed by the PMOS driving network, the NMOS clamping circuit, and the inductor and then driving signals are outputted from an output port vgsr1 and an output port vgsr2; the NMOS clamping circuit is used for controlling state change of the output port vgsr1 and the output port vgsr2; the inductor forms LC resonance with a gate capacitor Cgsr1 and a gate capacitor Cgsr2 in the NMOS clamping circuit, respectively, so as to recover energy in a turn-off process of the driving circuit and use the recovered energy for a turn-on process of the driving circuit. According to the present invention, a small number of devices are used, thereby saving the cost and space and facilitating miniaturization and integration. In addition, in the present invention, control signals are simple, the complexity of the control signals is reduced, and the system stability is improved.

Description

A non-isolated resonant gate drive circuit Technical Field

[0001] The present invention belongs to the technical field of power tube driving, and in particular relates to a non-isolated resonant gate driving circuit. Background Art

[0002] Increasing the frequency of switching power supplies allows for the use of smaller inductors and capacitors in circuits, reducing the size of the power supply system and lowering production costs. However, high-frequency switching increases the proportion of power transistor switching losses in the overall system power loss, leading to increased total losses. Reducing power transistor drive losses has become a key issue in reducing losses and increasing power density in high-frequency switching power supplies.

[0003] The energy of traditional gate drive circuits is dissipated in the resistance of the charge and discharge paths. A resonant gate drive circuit is a highly efficient drive circuit with energy recovery capabilities. Among existing power tube resonant gate drive technologies, a dual-channel resonant gate drive circuit uses four switching tubes and an inductor connected across the midpoint of the bridge arm. This circuit can output two symmetrical drive signals and recover most of the energy, but requires four signals to control the switching tubes, making control signal matching difficult and reducing the stability of the output drive signal. A transformer-based magnetically isolated resonant gate drive technology adds a transformer to the drive circuit. The output drive signal can simultaneously drive both the upper and lower tubes of the half-bridge, achieving a floating ground function for the drive signal. However, the use of a transformer increases the circuit complexity and footprint.

[0004] Summary of the Invention

[0005] The purpose of the present invention is to solve the technical problems of the above-mentioned driving technology, such as low energy recovery rate, large number of control signals, difficulty in signal matching, large occupied area, and disadvantageous for miniaturization, and to provide a non-isolated resonant gate drive circuit;

[0006] To achieve the above objectives, the present invention adopts the following technical solutions: a non-isolated resonant gate drive circuit, comprising: a PMOS drive network, an NMOS clamping circuit, and an inductor, wherein the PMOS drive network and the NMOS clamping circuit are connected in parallel at both ends of the inductor;

[0007] The input signal of the PMOS drive network is provided by a function generator connected to a drive chip, and the input signal is processed by the PMOS drive network, the NMOS clamp circuit and the inductor and then output from the output port v gsr1 and output port v gsr2 Output drive signal, the NMOS clamp circuit is used to control the output port v gsr1 and output port v gsr2The state of the inductor changes, and the gate capacitance C in the NMOS clamp circuit gsr1 and gate capacitance C gsr2 An LC resonance is formed to recover energy during the turn-off process of the driving circuit and use it in the turn-on process of the driving circuit.

[0008] Furthermore, the PMOS drive network includes: a first PMOS transistor and a second PMOS transistor, wherein the sources of the first PMOS transistor and the second PMOS transistor are both connected to a power supply Vcc, the gate of the first PMOS transistor is connected to a PWM1 output port of a driver chip connected to a function generator, the drain of the first PMOS transistor is connected to one end of an inductor, the gate of the second PMOS transistor is connected to a PWM2 output port of the driver chip connected to the function generator, and the drain of the second PMOS transistor is connected to the other end of the inductor.

[0009] Furthermore, the NMOS clamp circuit includes: a first NMOS transistor, a second NMOS transistor, a gate capacitor C gsr1 and gate capacitance C gsr2 The gate of the first NMOS tube and the drain of the second NMOS tube, the other end of the inductor, the output port v gsr2 , the drain and gate capacitance C of the second PMOS gsr2 The drain of the first NMOS tube is connected to the gate of the second NMOS tube, one end of the inductor, and the output port v gsr1 , the drain of the first PMOS tube and the gate capacitance C gsr1 One end of the first NMOS tube is connected to the source and gate capacitor C gsr1 The other end is connected to GND, the gate of the second NMOS tube is connected to one end of the inductor and the output port v gsr1 , the drain of the first PMOS tube and the gate capacitance C gsr1 Connect the drain of the second NMOS tube to the other end of the inductor and the output port v gsr2 , the drain and gate capacitance C of the second PMOS gsr2 The source of the second NMOS tube is connected to the gate capacitor C gsr2 The other end is connected to GND, the gate capacitor C gsr1 One end of the inductor and the output port v gsr1 and the drain of the first PMOS tube, the gate capacitor C gsr2 One end of the inductor and the other end of the output port v gsr2 and the drain of the second PMOS.

[0010] Furthermore, the output port v gsr1Connect one end of the inductor and the drain of the first PMOS tube, the output port v gsr2 The other end of the inductor is connected to the drain of the second PMOS tube. Beneficial effects:

[0011] 1. The present invention has a small number of components. The entire non-isolated resonant gate drive circuit is composed of two PMOS tubes, two NMOS tubes and an inductor. The magnetic component only requires an inductor and no transformer, which saves cost and space and is conducive to miniaturization and integration.

[0012] 2. The control signal of the present invention is simple. A function generator connected to a driver chip provides two square waves with a phase difference of 180 degrees and the same frequency and duty cycle to control the two PMOS driver tubes. The gates of the two NMOS tubes do not need external signal control, which simplifies the complexity of the control signal and improves system stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG1 is a circuit diagram of the present invention.

[0014] FIG2 is a module diagram of a control signal of the present invention.

[0015] FIG3 is a circuit diagram of an LLC DC transformer applicable to the present invention.

[0016] FIG4 is a key waveform timing diagram of the circuit of the present invention.

[0017] FIG5 is a simulation diagram of key waveforms of the circuit of the present invention.

[0018] FIG6 shows the current loops of the circuit of the present invention in different modes.

[0019] In the figure: 1. PMOS driver network; 2. NMOS clamp circuit. DETAILED DESCRIPTION

[0020] The present invention will be further explained below with reference to the accompanying drawings.

[0021] As shown in Figure 1, the present invention provides a non-isolated resonant gate drive circuit including a PMOS drive network 1, an NMOS clamping circuit 2 and an inductor L. The function generator is connected to a drive chip to generate PWM1 and PWM2 input signals. The PWM1 input signal controls the first PMOS transistor Q1, and the PWM2 input signal controls the first PMOS transistor Q2. The phase difference between the PWM1 and PWM2 input signals is 180 degrees, and the frequency and duty cycle can be adjusted according to the driven circuit. The NMOS clamping circuit 2 makes the port v of the output drive signal gsr1 and v gsr2 The voltage output range is 0-Vcc, and the NMOS clamp circuit also participates in the resonance process, so that the output port v gsr1and v gsr2 The state of the inductor L changes; the inductor L plays the role of energy transfer in the resonance and excitation process in the non-isolated resonant gate drive circuit, and the inductor L is respectively connected to the gate capacitance C in the NMOS clamp circuit 2 gsr1 and gate capacitance C gsr2 An LC resonance is formed to recover energy during the turn-off process of the driving circuit and use it in the turn-on process of the driving circuit.

[0022] As shown in Figure 2, this is the control signal input module of the present invention. The function generator provides square wave signals PWM1 and PWM2 with adjustable frequency and duty cycle. The two input signals are provided to the input port of the non-isolated resonant gate drive circuit through the driver chip: the gate of the first PMOS tube Q1 is v g_Q1 And the gate of the second PMOS tube Q2 g_Q2 .

[0023] As shown in Figure 3, this is an LLC DC transformer applicable to the present invention. The output signal of the present invention can provide gate drive signals for the low-voltage side switch tube and the secondary synchronous rectifier tube of the primary full bridge of the LLC DC transformer. gsr1 and v gsr2 and the gate signal v in Figure 3 gs2 、v gs4 or v gsr1 、v gsr2 Correspondingly, the switching tubes S2 and S4 on and off of the primary side full-bridge low-voltage side and the secondary side tubes SR1 and SR2 are controlled to realize the rectification function. The switching tubes S1, S2, S3 and S4 form a full-bridge topology structure. r1 , L r2 is the leakage inductance of the transformer, L m1 , L m2 is the transformer's magnetizing inductance, C r is the resonant capacitance, S R1 、S R2 is the secondary synchronous rectifier tube, C o is the output capacitor, R L For load.

[0024] As shown in Figure 4, this is the key waveform timing diagram of the circuit in Figure 1, including control signals, output voltage signals, and key currents. The first line is the gate control signal of the first PMOS transistor Q1, the second line is the gate control signal of the second PMOS transistor Q2, and the third line is the output port v gsr1 and v gsr2 The output drive signal, i1 in the fourth row is the current flowing through the first PMOS tube Q1, i2 in the fourth row is the current flowing through the first PMOS tube Q2, and i3 in the fifth row is the current flowing through the first NMOS tube Q3 and the gate capacitor C gsr1The current i4 in the fifth row is the current flowing through the second NMOS tube Q4 and the gate capacitor C gsr2 The current of the sixth row is i L is the current flowing through the inductor 3 , wherein the direction of the current is the positive current as marked in FIG1 .

[0025] FIG5 is a simulation waveform diagram of the circuit in FIG1 and the control signal in FIG4 on SIMetrix software. The simulation waveform is identical to the waveform timing diagram analyzed in FIG4 , further verifying the feasibility of the circuit of the present invention.

[0026] As shown in Figure 6, this is the current loop diagram at different time stages corresponding to Figure 4. The following will combine Figure 4 and Figure 6 to analyze the input port v of the non-isolated resonant gate drive circuit. g_Q1 、v g_Q2 Eight different circuit modes generated by signal changes.

[0027] During t0-t1, the gate capacitance C gsr2 The initial voltage on the capacitor is Vcc, and the capacitor C gsr1 The initial voltage is zero, the first NMOS tube Q3 is turned on, the other three MOS tubes are turned off, and the gate capacitance C gsr2 It resonates with the inductor L and the gate capacitance C gsr2 The inductor L is discharged in a resonant manner, and the output port v gsr2 The voltage at the gate decreases and the current in the resonant inductor increases. Energy is transferred from the gate capacitance to the inductor until the gate capacitance C gsr2 Fully discharged.

[0028] During t1-t2, the gate capacitance C gsr1 and C gsr2 The initial voltage on the gate is zero, the second NMOS tube Q4 is turned on, and the other three MOS tubes are turned off. gsr1 It resonates with the inductor L, and the inductor L discharges in a resonant manner. The gate capacitance C gsr1 Charging in a resonant manner, the output port v gsr1 The voltage at the gate increases and the current in the resonant inductor decreases. Energy is transferred from the inductor L to the gate capacitor C. gsr1 until the gate capacitance C gsr1 The upper voltage rises to Vcc.

[0029] During the period t2-t3, the first PMOS transistor Q1 and the second NMOS transistor Q4 are turned on, and the gate capacitor C gsr1 The upper voltage is kept at Vcc, and the gate capacitance Cgsr2 is kept at zero voltage, so that the output port v gsr1 Keep high level, output port v gsr2Keep it low. The energy on the inductor L is recovered by the power supply Vcc, and the current flows to the power supply until the current decreases to zero.

[0030] During the period t3-t4, the switching state of the MOS tube and the output port voltage are the same as those during the period t2-t3, and the current direction is opposite. The power supply Vcc charges the inductor, and the current flowing through the inductor increases until the first PMOS tube Q1 is turned off.

[0031] During t4-t5, the gate capacitance C gsr1 The initial voltage on the capacitor is Vcc, and the capacitor C gsr2 The initial voltage is zero, the second NMOS tube Q4 is turned on, the other three MOS tubes are turned off, and the gate capacitance C gsr1 It resonates with the inductor L and the gate capacitance C gsr1 The inductor L is discharged in a resonant manner, and the output port v gsr1 The voltage at the gate decreases and the current in the resonant inductor increases. The energy is transferred from the gate capacitance C gsr1 Transferred to the inductor L until the gate capacitance C gsr1 Fully discharged.

[0032] During t5-t6, the gate capacitance C gsr1 and C gsr2 The initial voltage on the gate is zero, the first NMOS tube Q3 is turned on, the other three MOS tubes are turned off, and the gate capacitance C gsr2 It resonates with the inductor L, and the inductor L discharges in a resonant manner. The gate capacitance C gsr2 Charging in a resonant manner, the output port v gsr2 The voltage at the gate increases and the current in the resonant inductor decreases. Energy is transferred from the inductor L to the gate capacitor C. gsr2 until the gate capacitance C gsr2 The upper voltage rises to Vcc.

[0033] During t6-t7, the second PMOS transistor Q2 and the first NMOS transistor Q3 are turned on, and the gate capacitor C gsr2 The upper voltage is kept at Vcc, and the gate capacitance C gsr1 Keep zero voltage, so that the output port v gsr2 Keep high level, output port v gsr1 Keep it low. The energy on the inductor L is recovered by the power supply Vcc, and the current flows to the power supply until the current decreases to zero.

[0034] During the period t7-t8, the switching state of the MOS tube and the output port voltage are the same as those during the period t6-t7, and the current direction is opposite. The power supply Vcc charges the inductor, and the current flowing through the inductor increases until the second PMOS tube Q2 is turned off.

[0035] In summary, the present invention connects the gate capacitor C gsr1 and gate capacitance C gsr2 The LC resonance is formed, energy recovery is achieved, and driving loss is greatly reduced. The output driving signal provided can be used to drive the primary low-voltage side switching tube and the secondary synchronous rectifier tube of the LLC DC transformer.

[0036] Furthermore, the present invention has a small number of components. The entire non-isolated resonant gate drive circuit is composed of two PMOS tubes, two NMOS tubes and an inductor. The magnetic component only requires an inductor and no transformer, which saves cost and space and is conducive to miniaturization and integration. At the same time, the present invention has a simple control signal. A function generator connected to a driver chip provides two square waves with a frequency of 180 degrees phase difference and the same duty cycle to control the two PMOS driver tubes. The gates of the two NMOS tubes do not need to be provided with external signal control, which simplifies the complexity of the control signal and improves system stability.

[0037] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A non-isolated resonant gate drive circuit, characterized in that: include: A PMOS driving network, an NMOS clamping circuit and an inductor, wherein the PMOS driving network and the NMOS clamping circuit are connected in parallel at both ends of the inductor; Wherein: the input signal of the PMOS driving network is provided by a function generator connected to a driving chip, and the input signal is processed by the PMOS driving network, the NMOS clamping circuit and the inductor and then output from the output port v gsr1 and output port v gsr2 Output drive signal, the NMOS clamp circuit is used to control the output port v gsr1 and output port v gsr2 The state of the inductor changes, and the gate capacitance C in the NMOS clamp circuit gsr1 and gate capacitance C gsr2 An LC resonance is formed to recover energy during a turn-off process of the driving circuit for use in a turn-on process of the driving circuit.

2. The non-isolated resonant gate drive circuit according to claim 1, characterized in that: The PMOS driving network includes: a first PMOS tube and a second PMOS tube, wherein the sources of the first PMOS tube and the second PMOS tube are both connected to a power supply Vcc, the gate of the first PMOS tube is connected to a PWM1 output port of a driving chip connected to a function generator, the drain of the first PMOS tube is connected to one end of an inductor, the gate of the second PMOS tube is connected to a PWM2 output port of the driving chip connected to the function generator, and the drain of the second PMOS tube is connected to the other end of the inductor.

3. The non-isolated resonant gate drive circuit according to claim 1, characterized in that: The NMOS clamp circuit includes: a first NMOS tube, a second NMOS tube, a gate capacitor C gsr1 and gate capacitance C gsr2 The gate of the first NMOS tube and the drain of the second NMOS tube, the other end of the inductor, and the output port v gsr2 , the drain and gate capacitance C of the second PMOS gsr2 The drain of the first NMOS tube is connected to the gate of the second NMOS tube, one end of the inductor, and the output port v gsr1 , the drain and gate capacitance C of the first PMOS tube gsr1 The source of the first NMOS tube is connected to the gate capacitor C gsr1 The other end is connected to GND, the gate of the second NMOS tube is connected to one end of the inductor and the output port v gsr1 , the drain and gate capacitance C of the first PMOS tube gsr1 The drain of the second NMOS tube is connected to the other end of the inductor and the output port v gsr2 , the drain and gate capacitance C of the second PMOS gsr2 The source of the second NMOS tube is connected to the gate capacitor C gsr2 The other end is connected to GND, the gate capacitor C gsr1 One end of the inductor and the output port v gsr1 and the drain of the first PMOS tube, the gate capacitor C gsr2 One end of the inductor and the other end of the inductor, the output port v gsr2 and the drain connection of the second PMOS.

4. The non-isolated resonant gate drive circuit according to claim 1, characterized in that: The output port v gsr1 Connected to one end of the inductor and the drain of the first PMOS tube, the output port v gsr2 The other end of the inductor is connected to the drain of the second PMOS tube.

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