Circuit board of graphics processing unit, and server system

Abstract

The present application provides a circuit board of a graphics processing unit, on which a first connector, a second connector, a third connector and a fourth connector, a first switching chip and a second switching chip, and a first slot set comprising M+P slots and a second slot set comprising N slots are deployed, wherein N is equal to M+P. The first switching chip is connected to the first connector, the third connector, and M slots of the first slot set, the second switching chip is connected to the fourth connector and N slots of the second slot set, and the second connector is connected to P slots of the first slot set; the first connector is connected to a central processing unit; the second connector is connected to the third connector; the third connector is connected to the second connector or the fourth connector. The present application solves the problem of complex switching operation for connection topological structures of a plurality of graphics processing units on a server, and achieves the effect of reducing the complexity of switching operation for the connection topological structures of the plurality of graphics processing units on the server.

Description

Graphics processor circuit board and server system

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 1, 2023, with application number 202311634161.1 and application name “Circuit board and server system for graphics processor”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The embodiments of the present application relate to the field of computers, and more specifically, to a circuit board of a graphics processor and a server system. Background Art

[0004] In recent years, GPUs (Graphics Processing Units) have been widely used in computer games, film and television special effects, scientific computing, machine learning and other fields due to their highly parallel computing capabilities. For servers, due to considerations of algorithm efficiency, multiple GPUs are required to meet complex computing needs. In different application scenarios, multiple GPUs need to adopt different machine topologies. Therefore, the switching of GPU connection topologies on servers is very frequent. At present, the GPUs on servers are connected by complex cables. When switching between different topologies, the cables need to be reconnected. The entire operation process involves multiple cables with different cable lengths, requiring cable switching for different models. The operation plan is relatively complicated, and the complex connection operation is also prone to damage to the cables and the GPU board interface.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a circuit board for a graphics processor and a server system to at least solve the problem in the related art that changing the machine topology requires complex operations and is prone to damage to cables and interfaces.

[0007] According to one embodiment of the present application, a circuit board for a graphics processor is provided, on which a connector group, a switching chipset and a device slot group are deployed, the connector group including: a first connector, a second connector, a third connector and a fourth connector, the switching chipset including: a first switching chip and a second switching chip, the device slot group including: a first slot set and a second slot set, the first slot set including M+P device slots, the second slot set including N device slots, where N is equal to M+P; the first switching chip is connected to the first connector, the third connector and the M device slots in the first slot set respectively through circuit board routing, the second switching chip is connected to the fourth connector and the N device slots in the second slot set respectively through circuit board routing, and the second connector is connected to the P device slots in the first slot set through circuit board routing; the first connector is configured to connect to a central processing unit; the second connector is configured to connect to the third connector; the third connector is configured to connect to the second connector, or, the fourth connector; the fourth connector is configured to connect to the third connector, or, the central processing unit; the device slot group is configured to connect to a graphics processor.

[0008] Optionally, the second connector, the third connector and the fourth connector are all board-to-board connectors, the second connector, the third connector and the fourth connector are arranged in a straight line and in the same direction, and the spacing between the second connector and the third connector and the spacing between the third connector and the fourth connector are both target spacings.

[0009] Optionally, the connectors in the connector group are connected through a connector circuit board, wherein a fifth connector and a sixth connector are deployed on the same side of the connector circuit board, the fifth connector and the sixth connector are connected through circuit board routing, the fifth connector and the sixth connector are both board-to-board connectors, and the spacing between the fifth connector and the sixth connector is the target spacing.

[0010] Optionally, the connector circuit board is configured to slide on the circuit board of the graphics processor, and switching between the connection between the third connector and the second connector and the connection between the third connector and the fourth connector is achieved by sliding.

[0011] Optionally, the connector circuit board is configured to achieve connection between the third connector and the second connector, and between the third connector and the fourth connector by plugging and unplugging.

[0012] Optionally, the connectors in the connector group are connected via a connecting cable comprising two connectors, wherein a first connector of the connecting cable is connected to the third connector, and a second connector of the connecting cable is configured to be connected to the second connector or the fourth connector.

[0013] Optionally, the connection structure between the second connector and the third connector is used to form a balanced topology structure, or a common topology structure, of the graphics processor.

[0014] Optionally, the second connector is connected to the third connector, and the first connector and the fourth connector are respectively connected to different central processing units to form a balanced topology structure.

[0015] Optionally, the second connector is connected to the third connector, and the first connector and the fourth connector are connected to the same central processor to form a common topology structure.

[0016] Optionally, the connection structure between the third connector and the fourth connector is used to form a series topology structure of the graphics processor.

[0017] Optionally, the third connector is connected to the fourth connector, and the first connector is connected to the central processor to form a series topology structure.

[0018] Optionally, M is equal to N-1, and P is equal to 1.

[0019] Optionally, N is equal to 5.

[0020] According to another embodiment of the present application, a server system is provided, comprising: a central processing unit group, a circuit board of a graphics processing unit, and the graphics processing unit group, wherein the circuit board of the graphics processing unit is connected between the central processing unit group and the graphics processing unit group.

[0021] A graphics processor circuit board is provided with a connector group, a switching chipset, and a device slot group. The connector group includes a first connector, a second connector, a third connector, and a fourth connector. The switching chipset includes a first switching chip and a second switching chip. The device slot group includes a first slot set and a second slot set. The first slot set includes M+P device slots, and the second slot set includes N device slots, where N equals M+P.

[0022] The first switching chip is connected to the first connector, the third connector, and the M device slots in the first slot set through circuit board traces, respectively; the second switching chip is connected to the fourth connector and the N device slots in the second slot set through circuit board traces, respectively; and the second connector is connected to the P device slots in the first slot set through circuit board traces;

[0023] The first connector is configured to connect to a central processing unit in a central processing unit group; the second connector is configured to connect to a third connector; the third connector is configured to connect to the second connector or the fourth connector; the fourth connector is configured to connect to the third connector or the central processing unit in the central processing unit group;

[0024] A device slot group is configured to connect graphics processors in a graphics processor group.

[0025] Optionally, the second connector is connected to the third connector, the first connector is connected to the first central processor in the central processor group, and the fourth connector is connected to the second central processor in the central processor group to form a balanced topology structure of the graphics processor group.

[0026] Optionally, the second connector is connected to the third connector, and the first connector and the fourth connector are both connected to the third central processor in the central processor group to form a common topology structure of the graphics processor group.

[0027] Optionally, the third connector is connected to the fourth connector, and the first connector is connected to the fourth central processor in the central processor group to form a series topology structure of the graphics processor group.

[0028] Optionally, the server system further includes: a connector circuit board, wherein:

[0029] The second connector, the third connector, and the fourth connector are all board-to-board connectors. The second connector, the third connector, and the fourth connector are arranged in a straight line and in the same direction. The spacing between the second connector and the third connector and the spacing between the third connector and the fourth connector are both target spacings.

[0030] The connectors in the connector group are connected through a connector circuit board, wherein the fifth connector and the sixth connector are deployed on the same side of the connector circuit board, the fifth connector and the sixth connector are connected through circuit board routing, the fifth connector and the sixth connector are both board-to-board connectors, and the spacing between the fifth connector and the sixth connector is the target spacing.

[0031] Optionally, the connector circuit board is configured to slide on the circuit board of the graphics processor, and switching between the connection between the third connector and the second connector and the connection between the third connector and the fourth connector is achieved by sliding.

[0032] Optionally, the connector circuit board is configured to achieve connection between the third connector and the second connector, and between the third connector and the fourth connector by plugging and unplugging.

[0033] According to the present application, a circuit board for connecting a graphics processor and a central processing unit is provided. A connector group, a switching chipset, and a device slot are deployed on the circuit board. The connector group includes a first connector, a second connector, a third connector, and a fourth connector. The switching chipset includes a first switching chip and a second switching chip. The device slot group includes a first slot set and a second slot set. Some components on the circuit board are connected by circuit board traces. The first switching chip is connected to the first connector, the third connector, and M device slots in the first slot set respectively through circuit board traces. The second switching chip is connected to the fourth connector and N device slots in the second slot set respectively through circuit board traces. The second connector is connected to P device slots in the first slot set through circuit board traces. Furthermore, the first connector is configured for connecting to the central processing unit, the second connector is configured for connecting to the third connector, the third connector is configured for connecting to the second connector or the fourth connector, and the fourth connector is configured for connecting to the third connector or the central processing unit. This simplifies the structure of the circuit board of the graphics processor while meeting the connection topology requirements of the graphics processor. This can solve the problem of high complexity in switching the connection topology of multiple graphics processors on a server, thereby reducing the complexity of switching the connection topology of multiple graphics processors on the server. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a schematic diagram of a circuit board of a graphics processor according to an embodiment of the present application;

[0035] FIG2 is a schematic diagram of a bridge according to an embodiment of the present application;

[0036] FIG3 is a schematic diagram of an optional balanced topology structure according to an embodiment of the present application;

[0037] FIG4 is a schematic diagram of an optional common topology structure according to an embodiment of the present application;

[0038] FIG5 is a schematic diagram of an optional series topology structure according to an embodiment of the present application;

[0039] FIG6 is a schematic diagram of an optional server system according to an embodiment of the present application;

[0040] FIG7 is a detailed diagram of an optional circuit board according to the present application. DETAILED DESCRIPTION

[0041] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0042] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0043] In an embodiment of the present application, a circuit board for a graphics processor is provided. FIG1 is a schematic diagram of a circuit board for a graphics processor according to an embodiment of the present application. As shown in FIG1 , a connector group, a switching chipset, and a device slot group are deployed on the circuit board. The connector group includes: a first connector, a second connector, a third connector, and a fourth connector. The switching chipset includes: a first switching chip and a second switching chip. The device slot group includes: a first slot set and a second slot set. The first slot set includes M+P device slots, and the second slot set includes N device slots, where N equals M+P.

[0044] The first switching chip is connected to the first connector, the third connector, and the M device slots in the first slot set through circuit board traces, respectively; the second switching chip is connected to the fourth connector and the N device slots in the second slot set through circuit board traces, respectively; and the second connector is connected to the P device slots in the first slot set through circuit board traces;

[0045] The first connector is configured to connect to a central processing unit; the second connector is configured to connect to a third connector; the third connector is configured to connect to the second connector or the fourth connector; the fourth connector is configured to connect to the third connector or the central processing unit;

[0046] A device slot group configured to connect to a graphics processor.

[0047] Through the above design, a circuit board for connecting a graphics processor and a central processing unit is provided. A connector group, a switching chipset, and device slots are deployed on the circuit board. The connector group includes a first connector, a second connector, a third connector, and a fourth connector. The switching chipset includes a first switching chip and a second switching chip. The device slot group includes a first slot set and a second slot set. Some components on the circuit board are connected via circuit board traces. The first switching chip is connected to the first connector, the third connector, and M device slots in the first slot set respectively via circuit board traces. The second switching chip is connected to the fourth connector and N device slots in the second slot set respectively via circuit board traces. The second connector is connected to P device slots in the first slot set via circuit board traces. Furthermore, the first connector is configured for connection to the central processing unit, the second connector is configured for connection to the third connector, the third connector is configured for connection to the second connector or the fourth connector, and the fourth connector is configured for connection to the third connector or the central processing unit. This simplifies the structure of the circuit board of the graphics processor while meeting the connection topology requirements of the graphics processor. This solves the problem of high complexity in switching the connection topologies of multiple graphics processors on a server, thereby reducing the complexity of switching the connection topologies of multiple graphics processors on a server.

[0048] Optionally, in an embodiment of the present application, the port on the connector group side of the circuit board is configured to connect to a central processing unit, the port on the device slot group side of the circuit board is configured to connect to a graphics processor, and the device slot group includes multiple device slots for connecting to graphics processors, thereby realizing the connection between the central processing unit and multiple graphics processors.

[0049] Optionally, in an embodiment of the present application, in order to implement different connection topologies of the graphics processor, the connection relationship between the second connector, the third connector, and the fourth connector may be changed to implement different connection topology requirements of the graphics processor.

[0050] Optionally, in an embodiment of the present application, the second connector, the third connector and the fourth connector can be arranged in sequence in a straight line on the circuit board, and the second connector, the third connector and the fourth connector can be connected by cables or by connecting devices. For example, the second connector, the third connector and the fourth connector can adopt connectors with external connection interfaces (such as board-to-board connectors). In this case, the connecting device can be a connecting device with two connection interfaces, and the connection interface on the connecting device is configured to be connected to the external connection interface on the connector. For example, the connecting device can be a connecting cable including two connecting heads, the first connecting head of the connecting cable is connected to the third connector, and the second connecting head on the connecting cable is configured to be connected to the second connector or the fourth connector. By switching the connection relationship between the second connecting head and the second connector or the fourth connector, And switch the connection topology of the graphics processor; the connector can also be a connection board including two connection heads, in this case the second connector, the third connector and the fourth connector are arranged in a straight line, and the spacing between the second connector, the third connector and the fourth connector is equal, the spacing between the two connection joints on the connection board is equal to the spacing between the third connector and the second connector or the spacing between the third connector and the connector. In use, the connection topology of the graphics processor can be changed by changing the connection relationship between the connection board and the second connector, the third connector and the fourth connector, or the connection board can be configured to be slidable on the circuit board, and the connection topology of the graphics processor can be changed by sliding the connection board between the second connector, the third connector and the fourth connector, thereby changing the connection relationship between the connection board and the second connector, the third connector and the fourth connector.

[0051] Optionally, in an embodiment of the present application, the above-mentioned graphics processing circuit board supports a GPU board with 8 × 16 GPUs and 2 × 16 network cards, and supports three topologies: balance, cascade, and common. The above-mentioned switching chip is two 96 lane PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) switch (96-channel PCIe switch) chips.

[0052] As an optional embodiment, the second connector, the third connector and the fourth connector are all board-to-board connectors, the second connector, the third connector and the fourth connector are arranged in a straight line and in the same direction, and the spacing between the second connector and the third connector and the spacing between the third connector and the fourth connector are both target spacings.

[0053] Optionally, in the embodiment of the present application, the board-to-board connector may be a vertical connector or a right angle connector.

[0054] Optionally, in the embodiment of the present application, the board-to-board connector may be an MCIO (Mini Cool Edge IO) connector or a gen-z connector.

[0055] Optionally, in an embodiment of the present application, the third connector is spaced equidistant from the second connector and the fourth connector, and their orientations are consistent, so that the specifications of the connectors used to connect the third connector and the second connector, and to connect the third connector and the fourth connector are unified. Therefore, the same connector can be configured to connect different connectors under different graphics processor topologies, thereby meeting the topological requirements of different graphics connectors and simplifying the operating structure of the graphics processor circuit board.

[0056] As an optional embodiment, the connectors in the connector group are connected through a connector circuit board, wherein the fifth connector and the sixth connector are deployed on the same side of the connector circuit board, the fifth connector and the sixth connector are connected through circuit board routing, the fifth connector and the sixth connector are both board-to-board connectors, and the spacing between the fifth connector and the sixth connector is the target spacing.

[0057] Optionally, in an embodiment of the present application, the connector circuit board can realize the connection between the third connector and the second connector, and the third connector and the fourth connector by plugging and unplugging, or the connecting circuit board can also be set to slide on the circuit board of the graphics processor, and when in use, the connection between the third connector and the second connector can be switched to the connection between the third connector and the fourth connector by sliding. This solution does not limit this.

[0058] Optionally, in an embodiment of the present application, FIG2 is a schematic diagram of a bridge according to an embodiment of the present application. As shown in FIG2 , the fifth connector and the sixth connector are two board-to-board connectors, which are soldered on a PCB and connected via a ×16 PCIe signal. The spacing between the fifth connector and the sixth connector is equal to the spacing between the second connector and the third connector. For data transmission (Transmit, TX) and reception (Receive, RX) on the bridge PCB, a design (reversal) can be made in which the direction of data transmission can be changed by changing the connection method to facilitate GPU board wiring.

[0059] Optionally, in an embodiment of the present application, the bridge includes but is not limited to a bridge that can use a 4C connector (SFF-TA-1002 (an edge connector system)), and this solution does not limit this.

[0060] According to the above content, a fifth connector and a sixth connector are provided on the connecting circuit board, and the spacing between the fifth connector and the sixth connector is the target spacing, and the fifth connector and the sixth connector are both board-to-board connectors, so that the connection between the second connector and the third connector can be achieved through the connecting circuit board by plugging and unplugging, and the connection between the third connector and the fourth connector can be achieved through the connecting circuit board, thereby realizing the change of the topology structure of the image processor by plugging and unplugging the same connecting circuit board on different connectors.

[0061] As an optional embodiment, the connection structure between the second connector and the third connector is used to form a balanced topology structure, or a common topology structure, of the graphics processor.

[0062] Optionally, in an embodiment of the present application, both the balanced topology and the ordinary topology structures are connected through the second connector and the third connector. The difference is that in the balanced topology structure, the first connector and the fourth connector are respectively connected to different central processing units, while in the ordinary topology structure, the first connector and the fourth connector are connected to the same central processing unit.

[0063] Through the above content, by connecting the second connector and the fourth connector, the functions of the balanced topology structure and the normal topology structure can be realized, so that in actual use, the number of external connections for these two topologies can be effectively simplified, thereby simplifying the change operation content of the two topologies.

[0064] As an optional embodiment, the second connector is connected to the third connector, and the first connector and the fourth connector are respectively connected to different central processing units to form a balanced topology structure.

[0065] Optionally, in an embodiment of the present application, the connection method between the first connector and the central processing unit can be a cable connection, and the connection method between the fourth connector and the central processing unit can be a cable connection. Connecting wires can be configured at the ports of the first connector and the fourth connector on the circuit board, and the function of a balanced topology structure can be achieved by connecting the other end of the connecting wire to the corresponding processor.

[0066] FIG3 is a schematic diagram of an optional balanced topology structure according to an embodiment of the present application. As shown in FIG3 , two PCIe switch chips on a circuit board constitute a switching chipset, PCIe switch0 (first switching chip) and PCIe switch1 (second switching chip), four connectors constitute a connector group, C0 connector (first connector), C1 (second connector), C2 (third connector), and C3 connector (fourth connector), and 10 × 16 PCIe slots constitute a device slot group. The PCIe switch chip should support at least 96 lanes of PCIe signals, with C1, C2, and C3 arranged in a straight line and oriented in the same direction. The spacing between C1 and C2 is equal to the spacing between C2 and C3. The 10 × 16 PCIe slots are sequentially designated as Slot 0 to Slot 9. PCIe switch 0 is connected to slots 0 through 3 via ×16 PCIe signals; PCIe switch 0 is connected to slots C0 and C2 via ×16 PCIe signals; PCIe switch 1 is connected to slots 6 through 9 via ×16 PCIe signals; PCIe switch 1 is connected to slot C3 via ×16 PCIe signals; and C1 is connected to slot 4 via ×16 PCIe signals. In a balanced topology, the C0 connector (first connector) on the GPU board is connected to CPU0 via a cable, and the C3 connector (fourth connector) is connected to CPU1 via a cable. The two connectors (fifth and sixth connectors) on the bridge (connector board) correspond to the C1 (second connector) and C2 (third connector) connectors on the GPU board, respectively. In an embodiment of the present application, the connector circuit board includes two board-to-board connectors, which are matched with C0 to C3 of the aforementioned GPU board and can be connected to each other; the two board-to-board connectors are soldered on a PCB (Printed Circuit Board) and are connected through a ×16 PCIe signal; the spacing between the two board-to-board connectors is equal to the spacing between C1 and C2 on the aforementioned GPU board; optionally, TX and RX on the bridge PCB can be reversible to facilitate GPU board wiring.

[0067] As an optional embodiment, the second connector is connected to the third connector, and the first connector and the fourth connector are connected to the same central processor to form a common topology structure.

[0068] FIG4 is a schematic diagram of an optional common topology structure according to an embodiment of the present application. As shown in FIG4 , two PCIe switch chips on a circuit board constitute a switching chipset, PCIe switch0 (first switching chip) and PCIe switch1 (second switching chip). Four connectors constitute a connector group, namely, connector C0 (first connector), C1 (second connector), C2 (third connector), and C3 (fourth connector). Ten × 16 PCIe slots constitute a device slot group. The PCIe switch chip should support at least 96 lanes of PCIe signals. C1, C2, and C3 are arranged in a straight line and face the same direction. The spacing between C1 and C2 is equal to the spacing between C2 and C3. The ten × 16 PCIe slots are sequentially designated as Slot 0 to Slot 9. PCIe switch 0 connects to slots 0 through 3 via ×16 PCIe signaling; PCIe switch 0 connects to slots C0 and C2 via ×16 PCIe signaling; PCIe switch 1 connects to slots 6 through 9 via ×16 PCIe signaling; PCIe switch 1 connects to slot C3 via ×16 PCIe signaling; and C1 connects to slot 4 via ×16 PCIe signaling. In a cascade topology, the C0 connector on the GPU board is connected to CPU0 via a cable, while the C3 connector is not connected to a cable. The two connectors on the bridge correspond to the C2 and C3 connectors on the GPU board, respectively. In an embodiment of the present application, the connector circuit board includes two board-to-board connectors, which are matched with C0 to C3 of the aforementioned GPU board and can be connected to each other; the two board-to-board connectors are soldered on a PCB and connected to each other through a ×16 PCIe signal; the spacing between the two board-to-board connectors is equal to the spacing between C1 and C2 on the aforementioned GPU board; optionally, TX and RX on the bridge PCB can be reversible to facilitate GPU board wiring.

[0069] As an optional embodiment, the connection structure between the third connector and the fourth connector is used to form a series topology structure of the graphics processor.

[0070] As an optional embodiment, the third connector is connected to the fourth connector, and the first connector is connected to the central processor to form a series topology structure.

[0071] FIG5 is a schematic diagram of an optional serial topology structure according to an embodiment of the present application. As shown in FIG5 , two PCIe switch chips on a circuit board constitute a switching chipset, PCIe switch0 (first switching chip) and PCIe switch1 (second switching chip), four connectors constitute a connector group, C0 connector (first connector), C1 (second connector), C2 (third connector), and C3 connector (fourth connector), and 10 × 16 PCIe slots constitute a device slot group. The PCIe switch chip should support at least 96 lanes of PCIe signals, with C1, C2, and C3 arranged in a straight line and oriented in the same direction. The spacing between C1 and C2 is equal to the spacing between C2 and C3. The 10 × 16 PCIe slots are sequentially designated as Slot 0 to Slot 9. PCIe switch 0 is connected to slots 0 through 3 via ×16 PCIe signaling; PCIe switch 0 is connected to slots C0 and C2 via ×16 PCIe signaling; PCIe switch 1 is connected to slots 6 through 9 via ×16 PCIe signaling; PCIe switch 1 is connected to slot C3 via ×16 PCIe signaling; and C1 is connected to slot 4 via ×16 PCIe signaling. In a common topology, the C0 connector on the GPU board is connected to CPU0 via a cable, and the C3 connector is connected to CPU0 via a cable. The two connectors on the bridge correspond to the C1 and C2 connectors on the GPU board, respectively. In an embodiment of the present application, the connector circuit board includes two board-to-board connectors, which are matched with C0 to C3 of the aforementioned GPU board and can be connected to each other; the two board-to-board connectors are soldered on a PCB and connected to each other through a ×16 PCIe signal; the spacing between the two board-to-board connectors is equal to the spacing between C1 and C2 on the aforementioned GPU board; optionally, TX and RX on the bridge PCB can be reversible to facilitate GPU board wiring.

[0072] As an optional embodiment, M is equal to N-1, and P is equal to 1.

[0073] As an optional embodiment, N is equal to 5.

[0074] In an exemplary embodiment of the present application, a server system is provided, comprising: a central processing unit group, a circuit board of a graphics processing unit, and a graphics processing unit group, wherein the circuit board of the graphics processing unit is connected between the central processing unit group and the graphics processing unit group.

[0075] A graphics processor circuit board is provided with a connector group, a switching chipset, and a device slot group. The connector group includes a first connector, a second connector, a third connector, and a fourth connector. The switching chipset includes a first switching chip and a second switching chip. The device slot group includes a first slot set and a second slot set. The first slot set includes M+P device slots, and the second slot set includes N device slots, where N equals M+P.

[0076] The first switching chip is connected to the first connector, the third connector, and the M device slots in the first slot set through circuit board traces, respectively; the second switching chip is connected to the fourth connector and the N device slots in the second slot set through circuit board traces, respectively; and the second connector is connected to the P device slots in the first slot set through circuit board traces;

[0077] The first connector is configured to connect to a central processing unit in a central processing unit group; the second connector is configured to connect to a third connector; the third connector is configured to connect to the second connector or the fourth connector; the fourth connector is configured to connect to the third connector or the central processing unit in the central processing unit group;

[0078] A device slot group is configured to connect graphics processors in a graphics processor group.

[0079] Through the above design, a circuit board for connecting a graphics processor and a central processing unit is provided. A connector group, a switching chipset, and device slots are deployed on the circuit board. The connector group includes a first connector, a second connector, a third connector, and a fourth connector. The switching chipset includes a first switching chip and a second switching chip. The device slot group includes a first slot set and a second slot set. Some components on the circuit board are connected via circuit board traces. The first switching chip is connected to the first connector, the third connector, and M device slots in the first slot set respectively via circuit board traces. The second switching chip is connected to the fourth connector and N device slots in the second slot set respectively via circuit board traces. The second connector is connected to P device slots in the first slot set via circuit board traces. Furthermore, the first connector is configured for connection to the central processing unit, the second connector is configured for connection to the third connector, the third connector is configured for connection to the second connector or the fourth connector, and the fourth connector is configured for connection to the third connector or the central processing unit. This simplifies the structure of the circuit board of the graphics processor while meeting the connection topology requirements of the graphics processor. This solves the problem of high complexity in switching the connection topologies of multiple graphics processors on a server, thereby reducing the complexity of switching the connection topologies of multiple graphics processors on a server.

[0080] Figure 6 is a schematic diagram of an optional server system according to an embodiment of the present application. As shown in Figure 6, the server system includes: a central processing unit group, a circuit board of a graphics processing unit and a graphics processing unit group, wherein the circuit board of the graphics processing unit is connected between the central processing unit group and the graphics processing unit group, and a connector group, a switching chipset and a device slot group are deployed on the circuit board of the graphics processing unit, wherein the connector group includes: a first connector, a second connector, a third connector and a fourth connector, the switching chipset includes: a first switching chip and a second switching chip, and the device slot group includes: a first slot set and a second slot set, the first slot set includes M+P device slots, and the second slot set includes N device slots, where N is equal to M+P; A switching chip is connected to a first connector, a third connector, and M device slots in a first slot set through circuit board traces, a second switching chip is connected to a fourth connector and N device slots in a second slot set through circuit board traces, and a second connector is connected to P device slots in the first slot set through circuit board traces; the first connector is configured to connect to a central processing unit in a central processing unit group; the second connector is configured to connect to a third connector; the third connector is configured to connect to the second connector or the fourth connector; the fourth connector is configured to connect to the third connector or the central processing unit in the central processing unit group; and the device slot group is configured to connect to a graphics processor in a graphics processing unit group.

[0081] Optionally, in an embodiment of the present application, the port on the connector group side of the circuit board is configured to connect to a central processing unit, the port on the device slot group side of the circuit board is configured to connect to a graphics processor, and the device slot group includes multiple device slots for connecting to graphics processors, thereby realizing the connection between the central processing unit and multiple graphics processors.

[0082] Optionally, in an embodiment of the present application, in order to implement different connection topologies of the graphics processor, the connection relationship between the second connector, the third connector, and the fourth connector may be changed to implement different connection topology requirements of the graphics processor.

[0083] Optionally, in an embodiment of the present application, the second connector, the third connector and the fourth connector can be arranged in sequence in a straight line on the circuit board, and the second connector, the third connector and the fourth connector can be connected by cables or by connecting devices. For example, the second connector, the third connector and the fourth connector can adopt connectors with external connection interfaces (such as board-to-board connectors). In this case, the connecting device can be a connecting device with two connection interfaces, and the connection interface on the connecting device is configured to be connected to the external connection interface on the connector. For example, the connecting device can be a connecting cable including two connecting heads, the first connecting head of the connecting cable is connected to the third connector, and the second connecting head on the connecting cable is configured to be connected to the second connector or the fourth connector. By cutting the connection relationship between the second connecting head and the second connector or the fourth connector, And switch the connection topology of the graphics processor; the connector can also be a connection board including two connection heads, in this case the second connector, the third connector and the fourth connector are arranged in a straight line, and the spacing between the second connector, the third connector and the fourth connector is equal, the spacing between the two connection joints on the connection board is equal to the spacing between the third connector and the second connector or the spacing between the third connector and the connector. In use, the connection topology of the graphics processor can be changed by changing the connection relationship between the connection board and the second connector, the third connector and the fourth connector, or the connection board can be configured to be slidable on the circuit board, and the connection topology of the graphics processor can be changed by sliding the connection board between the second connector, the third connector and the fourth connector, thereby changing the connection relationship between the connection board and the second connector, the third connector and the fourth connector.

[0084] Optionally, in an embodiment of the present application, the graphics processing circuit board supports a GPU board with 8 ×16 GPUs and 2 ×16 network cards, and supports three topologies: balance, cascade, and common. The switching chip is two 96-lane PCIe switch chips.

[0085] As an optional embodiment, the second connector is connected to the third connector, the first connector is connected to the first CPU in the CPU group, and the fourth connector is connected to the second CPU in the CPU group to form a balanced topology of the graphics processor group.

[0086] Optionally, in an embodiment of the present application, when designed as a balance topology (balanced topology structure), the C0 (first connector) connector on the GPU board is connected to CPU0 through a cable, the C3 (fourth connector) connector is connected to CPU1 through a cable, and the two connectors on the bridge correspond to the C1 (second connector) and C2 (third connector) connectors of the GPU board respectively.

[0087] As an optional embodiment, the second connector is connected to the third connector, and the first connector and the fourth connector are both connected to the third central processor in the central processor group to form a common topology structure of the graphics processor group.

[0088] Optionally, in an embodiment of the present application, when designed as a cascade topology (normal topology), the C0 connector (first connector) on the GPU board is connected to CPU0 through a cable, the C3 connector (fourth connector) is not plugged with a cable, and the two connectors on the bridge correspond to the GPU board C2 (third connector) and C3 (fourth connector) connectors respectively.

[0089] As an optional embodiment, the third connector is connected to the fourth connector, and the first connector is connected to the fourth central processor in the central processor group to form a series topology structure of the graphics processor group.

[0090] Optionally, in an embodiment of the present application, when designed as a common topology (serial topology), the C0 connector (first connector) on the GPU board is connected to CPU0 through a cable, the C3 connector (fourth connector) is connected to CPU0 through a cable, and the two connectors on the bridge correspond to the GPU board C1 (second connector) and C2 (third connector) connectors respectively.

[0091] As an optional embodiment, the server system further includes: a connector circuit board, wherein:

[0092] The second connector, the third connector, and the fourth connector are all board-to-board connectors. The second connector, the third connector, and the fourth connector are arranged in a straight line and in the same direction. The spacing between the second connector and the third connector and the spacing between the third connector and the fourth connector are both target spacings.

[0093] The connectors in the connector group are connected through a connector circuit board, wherein the fifth connector and the sixth connector are deployed on the same side of the connector circuit board, the fifth connector and the sixth connector are connected through circuit board routing, the fifth connector and the sixth connector are both board-to-board connectors, and the spacing between the fifth connector and the sixth connector is the target spacing.

[0094] Optionally, in an embodiment of the present application, the connector circuit board can realize the connection between the third connector and the second connector, and the third connector and the fourth connector by plugging and unplugging, or the connecting circuit board can also be set to slide on the circuit board of the graphics processor, and when in use, the connection between the third connector and the second connector can be switched to the connection between the third connector and the fourth connector by sliding. This solution does not limit this.

[0095] Optionally, in the embodiment of the present application, the bridge includes but is not limited to a bridge that can use a 4C connector (SFF-TA-1002), and this solution does not limit this.

[0096] Figure 7 is a detailed diagram of an optional circuit board according to the present application. As shown in Figure 7, the embodiment of the present application designs a GPU board that supports 8 ×16 GPUs and 2 ×16 network cards, and supports three topology forms of balance, cascade, and common. In the design scheme, the GPU board is designed with two 96-lane PCIe switch chips, which are respectively recorded as PCIe switch 0 (first switching chip) and PCIe switch 1 (second switching chip); in the design scheme, the GPU board is designed with four board-to-board connectors that support ×16 PCIe signals, which are respectively recorded as C0 (first connector) to C3; among them, C1 (second connector), C2 (third connector), and C3 (fourth connector) are arranged in the same direction and in a straight line, with C2 in the middle and C1 and C3 on both sides; optionally, the board-to-board connector can be vertical or right angle; optionally, the board-to-board connector can be an MCIO connector or a gen-z connector; in the design scheme, the GPU board is designed with 10 ×16 PCIe slots, which are respectively recorded as Slot 0 to Slot 9; Optionally, the slot where the GPU is installed reserves space for a double-width AIC (Add-In Card, a product form of a solid-state drive); PCIe switch 0 is connected to slots 0 to Slot 3 via a ×16 PCIe signal; PCIe switch 0 is connected to slots C0 and C2 via a ×16 PCIe signal; PCIe switch 1 is connected to slots Slot 6 to Slot 9 via a ×16 PCIe signal; PCIe switch 1 is connected to slot C3 via a ×16 PCIe signal; and C1 is connected to slot 4 via a ×16 PCIe signal. This example also includes a bridge design consisting of two board-to-board connectors. These board-to-board connectors mate with C0 through C3 on the GPU board, allowing for interconnection. The two board-to-board connectors are soldered to a single PCB and connected via ×16 PCIe signals. The spacing between the two board-to-board connectors equals the spacing between C1 and C2 on the GPU board. Optionally, the TX and RX ports on the bridge PCB can be reversible to facilitate GPU board wiring. A 4C connector (SFF-TA-1002) is used for the bridge.When the design is a balance topology, the C0 connector on the GPU board is connected to CPU0 through a cable, the C3 connector is connected to CPU1 through a cable, and the two connectors on the bridge correspond to the C1 and C2 connectors on the GPU board respectively. When the design is a cascade topology, the C0 connector on the GPU board is connected to CPU0 through a cable, the C3 connector is not plugged with a cable, and the two connectors on the bridge correspond to the C2 and C3 connectors on the GPU board respectively. When the design is a common topology, the C0 connector on the GPU board is connected to CPU0 through a cable, the C3 connector is connected to CPU0 through a cable, and the two connectors on the bridge correspond to the C1 and C2 connectors on the GPU board respectively.

[0097] Through the above embodiment, 1) the number of connectors is reduced and the original ×8 connector is changed to a ×16 connector, thereby reducing the number of cables; 2) the design is simplified by adopting a board-to-board connector design; 3)

[0098] The newly added bridge design increases connection reliability and reduces the number of steps when changing topologies. The board-to-board connectors are designed side by side, and the bridge with matching connectors effectively simplifies the board design and can easily support switching between different topologies.

[0099] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A circuit board for a graphics processor, characterized in that: The circuit board is equipped with a connector group, a switching chipset group and a device slot group, wherein: The connector group includes: a first connector, a second connector, a third connector and a fourth connector, the switching chip group includes: a first switching chip and a second switching chip, the device slot group includes: a first slot set and a second slot set, the first slot set includes M+P device slots, the second slot set includes N device slots, N is equal to M+P; The first switching chip is respectively connected to the first connector, the third connector, and the M device slots in the first slot set through circuit board wiring, the second switching chip is respectively connected to the fourth connector and the N device slots in the second slot set through circuit board wiring, and the second connector is connected to the P device slots in the first slot set through circuit board wiring; The first connector is configured to connect to a central processing unit; the second connector is configured to connect to the third connector; the third connector is configured to connect to the second connector, or the fourth connector; the fourth connector is configured to connect to the third connector, or the central processing unit; The device slot group is configured to connect a graphics processor.

2. The circuit board according to claim 1, characterized in that: The second connector, the third connector and the fourth connector are all board-to-board connectors, the second connector, the third connector and the fourth connector are arranged in a straight line and in the same direction, and the spacing between the second connector and the third connector and the spacing between the third connector and the fourth connector are both target spacings.

3. The circuit board according to claim 2, characterized in that: The connectors in the connector group are connected through a connector circuit board, wherein a fifth connector and a sixth connector are deployed on the same side of the connector circuit board, the fifth connector and the sixth connector are connected through circuit board routing, the fifth connector and the sixth connector are both board-to-board connectors, and the spacing between the fifth connector and the sixth connector is the target spacing.

4. The circuit board according to claim 3, characterized in that: The connector circuit board is configured to slide on the circuit board of the graphics processor, and the switching of the connection between the third connector and the second connector and the connection between the third connector and the fourth connector is achieved by sliding.

5. The circuit board according to claim 3, characterized in that: The connector circuit board is configured to achieve connection between the third connector and the second connector, and between the third connector and the fourth connector by plugging and unplugging.

6. The circuit board according to claim 2, characterized in that: The connectors in the connector group are connected via a connecting cable including two connecting heads, wherein the first connecting head of the connecting cable is connected to the third connector, and the second connecting head of the connecting cable is configured to be connected to the second connector or the fourth connector.

7. The circuit board according to claim 1, characterized in that: The connection structure between the second connector and the third connector is used to form a balanced topology structure or a common topology structure of the graphics processor.

8. The circuit board according to claim 7, characterized in that: The second connector is connected to the third connector, and the first connector and the fourth connector are respectively connected to different central processors to form the balanced topology structure.

9. The circuit board according to claim 7, characterized in that: The second connector is connected to the third connector, and the first connector and the fourth connector are connected to the same central processor to form the common topology.

10. The circuit board according to claim 1, characterized in that: The connection structure between the third connector and the fourth connector is used to form a series topology structure of the graphics processor.

11. The circuit board according to claim 10, characterized in that: The third connector is connected to the fourth connector, and the first connector is connected to the central processor to form the series topology structure.

12. The circuit board according to claim 1, characterized in that: M equals N-1, and P equals 1.

13. The circuit board according to claim 12, characterized in that: N is equal to 5.

14. A server system, characterized in that: include: A central processing unit group, a circuit board of a graphics processing unit and a graphics processing unit group, wherein the circuit board of the graphics processing unit is connected between the central processing unit group and the graphics processing unit group, A connector group, a switching chipset and a device slot group are deployed on the circuit board of the graphics processor, wherein the connector group includes: a first connector, a second connector, a third connector and a fourth connector, the switching chipset includes: a first switching chip and a second switching chip, and the device slot group includes: a first slot set and a second slot set, the first slot set includes M+P device slots, and the second slot set includes N device slots, where N is equal to M+P; The first switching chip is respectively connected to the first connector, the third connector, and the M device slots in the first slot set through circuit board wiring, the second switching chip is respectively connected to the fourth connector and the N device slots in the second slot set through circuit board wiring, and the second connector is connected to the P device slots in the first slot set through circuit board wiring; The first connector is configured to connect to a central processor in the central processor group; the second connector is configured to connect to the third connector; the third connector is configured to connect to the second connector, or the fourth connector; the fourth connector is configured to connect to the third connector, or the central processor in the central processor group; The device slot group is configured to connect the graphics processors in the graphics processor group.

15. The server system according to claim 14, characterized in that: The second connector is connected to the third connector, the first connector is connected to the first central processor in the central processor group, and the fourth connector is connected to the second central processor in the central processor group to form a balanced topology structure of the graphics processor group.

16. The server system according to claim 14, characterized in that: The second connector is connected to the third connector, and the first connector and the fourth connector are both connected to the third central processor in the central processor group to form a common topology structure of the graphics processor group.

17. The server system according to claim 14, characterized in that: The third connector is connected to the fourth connector, and the first connector is connected to the fourth central processor in the central processor group to form a series topology structure of the graphics processor group.

18. The server system according to claim 14, characterized in that: The server system further includes: a connector circuit board, wherein: The second connector, the third connector and the fourth connector are all board-to-board connectors, the second connector, the third connector and the fourth connector are arranged in a straight line and in the same direction, and the spacing between the second connector and the third connector and the spacing between the third connector and the fourth connector are both target spacings; The connectors in the connector group are connected through the connector circuit board, wherein a fifth connector and a sixth connector are deployed on the same side of the connector circuit board, the fifth connector and the sixth connector are connected through circuit board routing, the fifth connector and the sixth connector are both board-to-board connectors, and the spacing between the fifth connector and the sixth connector is the target spacing.

19. The server system according to claim 18, characterized in that: The connector circuit board is configured to slide on the circuit board of the graphics processor, and the switching of the connection between the third connector and the second connector and the connection between the third connector and the fourth connector is achieved by sliding.

20. The server system according to claim 18, characterized in that: The connector circuit board is configured to achieve connection between the third connector and the second connector, and between the third connector and the fourth connector by plugging and unplugging.

Images