Chip, chip-on-carrier, transmitter, and related device

Abstract

A chip, a chip-on-carrier, a transmitter, and a related device. The chip comprises a conductive substrate (100), an insulating layer (200), a quantum well (300), a first capacitor pad (400), a distributed feedback laser (DFB) pad (500) and an electrical absorption modulator (EAM) pad (600), wherein the insulating layer (200) and the quantum well (300) are grown on the conductive substrate (100), the DFB pad (500) and the EAM pad (600) are grown on the insulating layer (200) and the quantum well (300), the first capacitor pad (400) is grown on the insulating layer (200), and the first capacitor pad (400) is used for forming a first capacitor with the conductive substrate (100). In this way, a capacitor is built in an EML chip, such that the modulation effect of a high-frequency signal on a DFB region can be effectively mitigated while a COC structure and process are simplified, thereby realizing differential driving having a lower RIN.

Description

A chip, chip on carrier, transmitter and related equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on November 27, 2023, with application number 202311607683.2 and invention name “A chip, chip on carrier, transmitter and related equipment”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of communication technology, and in particular to a chip, a chip-on-carrier, a transmitter, and related equipment. Background Art

[0003] Electro-absorption modulated laser (EML) is widely used in the field of optical communications due to its low cost, high bandwidth, and good linearity.

[0004] An EML chip typically consists of two parts: a distributed feedback laser (DFB) region, used to generate laser light at a specific wavelength, and an electrical absorption modulator (EAM) region. Currently, these two parts of mainstream EML chips use a common cathode chip architecture and a butt-joint method for optical coupling.

[0005] The chip periphery of this structure is usually driven in a single-ended manner. At the same time, such chips can also achieve differential drive through a chip-on-carrier (COC) design. When implementing differential drive, an external capacitor C must be added to the periphery of the EML chip to eliminate the modulation of the distributed feedback laser (DFB) area by the signal on the differential signal connection line. Otherwise, the laser relative intensity noise (RIN) will be severely degraded.

[0006] However, the above solution places high demands on the external capacitor C. Ordinary external capacitors are difficult to ensure that the RIN of the EML chip is at a good level. At the same time, this solution also places high demands on the volume of the capacitor C. Large-sized external capacitors also affect the bandwidth of the entire COC, making the overall complexity of the COC higher.

[0007] Summary of the Invention

[0008] The present invention provides a chip that integrates capacitors, simplifying the COC structure and process while also effectively eliminating the modulation effect of high-frequency signals on the DFB region, achieving differential drive with lower RIN noise. The present invention also provides a corresponding chip-on-carrier, transmitter, optical component, optical module, optical line terminal, optical network unit, and communication equipment.

[0009] The first aspect of the present application provides a chip, which includes a conductive substrate, an insulating layer, a quantum well, a first capacitor electrode, a distributed feedback laser DFB electrode and an electro-absorption modulator EAM electrode, wherein the insulating layer and the quantum well are grown on the conductive substrate, the insulating layer and the quantum well jointly cover the conductive substrate, and the insulating layer covers the side surfaces of the quantum well. The DFB electrode and the EAM electrode are grown on the insulating layer and the quantum well, and the DFB electrode and the EAM electrode cover the top surface of the quantum well. The first capacitor electrode is grown on the insulating layer, the first capacitor electrode is electrically connected to the DFB electrode, and the first capacitor electrode is used to form a first capacitor with the conductive substrate. The DFB electrode, the EAM electrode and the first capacitor electrode respectively cover different and non-adjacent portions of the insulating layer.

[0010] In this application, the chip is an electro-absorption modulated laser (EML) chip, and a conductive substrate serves as the base of the entire chip, and its specific material may be indium phosphide (InP), etc. The insulating layer and the quantum well are grown on the surface of the conductive substrate.

[0011] In this application, the insulating layer is non-conductive and needs to cover the sides of the quantum well. This means the quantum well can be the same height as the insulating layer, or it can be higher than the insulating layer, with the insulating layer covering the sides of the raised portion of the quantum well. The quantum well can be divided into two parts, one covered by the DFB electrode and the other covered by the EAM electrode.

[0012] In this application, a quantum well is a thin layer structure, typically made of a thin semiconductor dielectric. The quantum well in the DFB region is used to generate laser light. The DFB electrode and EAM electrode serve as the P-pole, while the shared conductive substrate serves as the N-pole. The DFB electrode, EAM electrode, quantum well, and insulating layer are all inherent structures of the EML chip.

[0013] In this application, the integrated capacitor (first capacitor electrode) of the EML chip can be implemented through an EML chip epitaxial growth process, such as molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD). The electrodes at the two ends of the capacitor are the surface capacitor electrode and the conductive substrate, respectively. The capacitance of the first capacitor can be increased by reducing the thickness of the thin film material between the two electrodes or selecting a material with a larger dielectric constant, thereby achieving better control of the RIN of the EML chip.

[0014] In this application, the growth positions of the DFB electrode, EAM electrode and first capacitor electrode are arbitrary, but the DFB electrode, EAM electrode and first capacitor electrode are not coupled to each other or in direct contact, that is, they exist independently on the insulating layer or quantum well.

[0015] In the first aspect, the chip includes a conductive substrate, an insulating layer, a quantum well, a first capacitor electrode, a distributed feedback laser DFB electrode and an electro-absorption modulator EAM electrode, wherein the first capacitor electrode is used to form a first capacitor with the conductive substrate, thereby integrating the capacitor into the EML chip. While simplifying the COC structure and process, it can also better eliminate the modulation effect of high-frequency signals on the DFB area, thereby achieving differential drive with lower RIN noise.

[0016] In a possible implementation of the first aspect, the chip further includes a semiconductor optical amplifier (SOA) electrode and a second capacitor electrode, the SOA electrode being grown on the insulating layer and the quantum well, the SOA electrode covering the top surface of the quantum well. The second capacitor electrode is grown on the insulating layer, the second capacitor electrode is electrically connected to the SOA electrode, and the second capacitor electrode is used to form a second capacitor with the conductive substrate. The DFB electrode, the EAM electrode, the SOA electrode, the first capacitor electrode, and the second capacitor electrode respectively cover different and non-adjacent portions of the insulating layer.

[0017] In this possible implementation, by coupling a semiconductor optical amplifier, the applicable scenarios of the chip can be expanded and the feasibility of the solution can be improved.

[0018] In a possible implementation manner of the first aspect, the conductive substrate includes a metallized portion, and the first capacitor electrode is used to form a first capacitor with the metallized portion.

[0019] In this possible implementation, the size or material of the metallized portion in the conductive substrate can be adjusted or set according to user needs, thereby more conveniently controlling the capacitance of the first capacitor.

[0020] In a possible implementation manner of the first aspect, the material of the insulating layer is silicon dioxide or titanium dioxide.

[0021] In this possible implementation, silicon dioxide or titanium dioxide is used as the dielectric material, which has a relatively large dielectric constant and can further increase the capacitance value of the first capacitor.

[0022] In a possible implementation manner of the first aspect, the chip further includes a first connecting line, and the DFB electrode and the first capacitor electrode are electrically connected inside the chip through the first connecting line.

[0023] In this possible implementation, the DFB electrode and the first capacitor electrode are connected on-chip, which is beneficial to miniaturization of the entire chip.

[0024] In a possible implementation manner of the first aspect, the chip further includes a second connecting line, and the SOA electrode and the second capacitor electrode are electrically connected inside the chip through the second connecting line.

[0025] In this possible implementation, the SOA electrode and the second capacitor electrode are also connected on-chip, which is beneficial to the miniaturization of the entire chip.

[0026] The second aspect of the present application provides a chip on a carrier, which includes a chip and a differential signal transmission line, the differential signal transmission line is used to provide a drive signal to the chip, and the chip includes a conductive substrate, an insulating layer, a quantum well, a first capacitor electrode, a distributed feedback laser DFB electrode and an electro-absorption modulator EAM electrode, wherein the insulating layer and the quantum well are grown on the conductive substrate, the insulating layer and the quantum well jointly cover the conductive substrate, and the insulating layer covers the side of the quantum well. The DFB electrode and the EAM electrode are grown on the insulating layer and the quantum well, and the DFB electrode and the EAM electrode cover the top surface of the quantum well. The first capacitor electrode is grown on the insulating layer, and the first capacitor electrode is used to form a first capacitor with the conductive substrate. The DFB electrode, the EAM electrode and the first capacitor electrode respectively cover different and non-adjacent parts on the insulating layer.

[0027] In the second aspect, the chip of the above-mentioned first aspect or any possible implementation method of the first aspect can be used in a carrier-on-chip, with minor changes to the overall structure of the original carrier-on-chip, which can avoid the high requirements for capacitance and improve the feasibility of the solution.

[0028] In a possible implementation manner of the second aspect, the chip on the carrier further includes a first conductive block and a first magnetic bead, and the first conductive block is connected to the first capacitor electrode through the first magnetic bead.

[0029] In this possible implementation, the first magnetic bead is directly connected to the EML chip. Compared with the original chip-on-carrier solution, the connection length between the two is shortened, which is conducive to improving the overall bandwidth of the chip-on-carrier.

[0030] In a possible implementation of the second aspect, the chip further includes a semiconductor optical amplifier (SOA) electrode and a second capacitor electrode. The SOA electrode is grown on the insulating layer and the quantum well, and covers the top surface of the quantum well. The second capacitor electrode is grown on the insulating layer, electrically connected to the SOA electrode, and configured to form a second capacitor with the conductive substrate. The DFB electrode, the EAM electrode, the SOA electrode, the first capacitor electrode, and the second capacitor electrode each cover different and non-adjacent portions of the insulating layer.

[0031] In a possible implementation manner of the second aspect, the chip on the carrier further includes a second conductive block and a second magnetic bead, and the second conductive block is connected to the second capacitor electrode through the second magnetic bead.

[0032] In this possible implementation, the second magnetic bead is directly connected to the SOA, which shortens the connection length between the two and is conducive to the miniaturization of the chip on the carrier.

[0033] In a possible implementation manner of the second aspect, the conductive substrate includes a metallized portion, and the first capacitor electrode is used to form a first capacitor with the metallized portion.

[0034] In a possible implementation manner of the second aspect, the material of the insulating layer is silicon dioxide or titanium dioxide.

[0035] In a possible implementation manner of the second aspect, the chip further includes a first connecting line, and the DFB electrode and the first capacitor electrode are electrically connected inside the chip through the first connecting line.

[0036] In a possible implementation manner of the second aspect, the chip on the carrier further includes a third connecting line, and the DFB electrode and the first capacitor electrode are electrically connected outside the chip through the third connecting line.

[0037] In this possible implementation, the DFB electrode and the first capacitor electrode can be connected off-chip, which improves the feasibility of the solution.

[0038] In a possible implementation manner of the second aspect, the chip further includes a second connecting line, and the SOA electrode and the second capacitor electrode are electrically connected inside the chip through the second connecting line.

[0039] In a possible implementation manner of the second aspect, the chip on the carrier further includes a fourth connecting line, and the SOA electrode and the second capacitor electrode are electrically connected outside the chip through the fourth connecting line.

[0040] In this possible implementation, the SOA electrode and the second capacitor electrode may also be connected off-chip, thereby improving the feasibility of the solution.

[0041] In a possible implementation manner of the second aspect, the chip on the carrier further includes a detection unit, and the detection unit is used to determine the luminescence condition of the chip.

[0042] In this possible implementation, the chip-on-carrier does not require an external capacitor on the EML chip, thus avoiding the backlight blocking of the EML chip by the external capacitor in the original chip-on-carrier solution, making it easier to implement backlight detection.

[0043] A third aspect of the present application provides a transmitter, which includes a transmission signal source and a chip on a carrier as described in the second aspect or any possible implementation of the second aspect. The transmission signal source is used to provide a driving signal to the chip through a differential signal transmission line.

[0044] The fourth aspect of the present application provides an optical component, which includes a chip such as the first aspect or any possible implementation of the first aspect, a chip on a carrier such as the second aspect or any possible implementation of the second aspect, or a transmitter such as the third aspect.

[0045] In a fifth aspect, the present application provides an optical module, which includes a chip as in the first aspect or any possible implementation of the first aspect, or a chip on a carrier as in the second aspect or any possible implementation of the second aspect, or a transmitter as in the third aspect.

[0046] In a sixth aspect, the present application provides an optical line terminal, which includes a chip according to the first aspect or any possible implementation of the first aspect, or a chip on a carrier according to the second aspect or any possible implementation of the second aspect, or a transmitter according to the third aspect.

[0047] In a seventh aspect, the present application provides an optical network unit, which includes a chip as described in the first aspect or any possible implementation of the first aspect, or a chip on a carrier as described in the second aspect or any possible implementation of the second aspect, or a transmitter as described in the third aspect.

[0048] In an eighth aspect, the present application provides a communication device, which includes a chip as in the first aspect or any possible implementation of the first aspect, or a chip on a carrier as in the second aspect or any possible implementation of the second aspect, or a transmitter as in the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG1 is a schematic diagram of the architecture of a passive optical network;

[0050] FIG2 is a schematic diagram of the architecture of an electro-absorption modulated laser (EML) transmitter;

[0051] FIG3 is a schematic cross-sectional view of a chip provided in an embodiment of the present application;

[0052] FIG4 is a schematic top view of a chip provided in an embodiment of the present application;

[0053] FIG5 is a schematic diagram of another embodiment of a chip provided in an embodiment of the present application;

[0054] FIG6 is a schematic diagram of another embodiment of a chip provided in an embodiment of the present application;

[0055] FIG7 is a schematic diagram of another embodiment of a chip provided in an embodiment of the present application;

[0056] FIG8A is a schematic diagram of an embodiment of a chip-on-carrier provided in an embodiment of the present application;

[0057] FIG8B is a schematic diagram of an embodiment of a transmitter provided in an embodiment of the present application;

[0058] FIG9 is a schematic diagram of another embodiment of a transmitter provided in an embodiment of the present application;

[0059] FIG10 is a schematic diagram of an embodiment of a passive optical network provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] The following describes embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described are merely a portion of the embodiments of the present application, and not all of them. Those skilled in the art will appreciate that, as technology advances and new scenarios emerge, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0061] The terms "first," "second," and the like in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0062] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0063] In addition, numerous specific details are provided in the detailed description below to better illustrate the present application. Those skilled in the art will appreciate that the present application can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present application.

[0064] The following examples illustrate the application scenarios involved in the embodiments of the present application.

[0065] In the field of optical communications, both Ethernet and passive optical networks (PONs) need to realize the mutual conversion between electrical signals and optical signals. For example, PON is a point-to-multipoint passive optical network, which is a combination of network elements in an optical access network based on an optical distribution network (ODN), and the optical distribution network does not contain any electronic devices or electronic power supplies. Among them, ODN is entirely composed of passive components such as optical splitters. A PON includes an optical line terminal (OLT) installed in a central control station and multiple optical network units (ONUs) installed in user locations, and implements a specific set of physical medium-related layers, transmission convergence layers and management protocols.

[0066] As shown in Figure 1, the optical line terminal (OLT) is connected to two optical network units (ONUs) via an optical distribution network (ODN). The ODN refers to the entire passive optical network (PON) between the OLT port and each ONU port. It should be understood that in other networking scenarios, a single OLT can connect to a larger number of ONUs. The OLT and the ODN must be interconnected via optical modules. These modules convert electrical signals from the OLT into optical signals, which are then transmitted to the ONUs via the ODN. Furthermore, the optical modules convert optical signals transmitted from the ONUs via the ODN into electrical signals, which are then transmitted to the OLT.

[0067] Specifically, the optical module or the optical component in the optical module includes a transmitter, which is used to convert electrical signals into optical signals. Electro-absorption modulated laser (EML) is widely used in transmitters due to its low cost, high bandwidth, and good linearity.

[0068] As shown in Figure 2, an EML transmitter typically includes a transmission signal source, a driver, and EML optical components. The transmission signal source is typically a digital-to-analog converter (DAC), and the EML optical components are the EML chip and components coupled to it. To further reduce module power consumption, the driver is integrated with the transmission signal source to directly drive the EML optical components. This eliminates the need for an external driver chip, resulting in lower costs. Furthermore, the integrated solution often helps reduce overall transmitter power consumption.

[0069] There are usually two ways to directly drive EML: single-ended drive and differential drive:

[0070] Single-ended drive: The transmitting signal source outputs a single-ended signal, and the EML optical device is driven by the single-ended signal. Since the transmitting signal source outputs a single-ended signal, the signal quality is somewhat degraded compared to the differential signal. At the same time, the use of a single-ended signal to drive the EML optical device has high requirements for the single-ended signal output amplitude and it is difficult to achieve a high extinction ratio (ER). Therefore, it is difficult to use in application scenarios with high ER requirements.

[0071] Differential drive: The transmitting signal source outputs differential signals, and the EML optical device is driven by differential signals. This solution outputs differential signals with relatively good signal quality. At the same time, differential drive of EML optical devices has relatively low requirements for signal output amplitude, which can achieve lower power consumption.

[0072] As optical communication speeds increase, single-ended direct drive solutions are no longer sufficient due to limitations in DAC output capabilities, leading to the widespread adoption of differential drive solutions. Currently, EML chips can utilize complex differential EML chips or traditional single-ended drive chip architectures. In the chip packaging, differential drive is implemented through a chip-on-carrier (COC) design, known as a COC differential drive solution. However, the introduction of modulation signals in differential signal lines increases the relative intensity noise (RIN) of the EML chip. Therefore, capacitors must be added to the EML's distributed feedback laser (DFB) region to eliminate modulation of the DFB region by high-frequency signals on the differential signal lines.

[0073] However, in the above solution, in order to ensure a low RIN of the EML chip, the requirements for the external capacitor C are relatively high. Not only is the capacitor required to be small in size, but it is also required to have a large capacitance, low equivalent series inductance (ESL) and equivalent series resistance (ESR).

[0074] However, in practice, it is difficult to achieve larger capacitance and smaller size in COC through thin-film capacitor technology, resulting in a serious degradation of the relative intensity noise of the EML chip in the differential drive structure in response to the modulated signal. Based on this, an embodiment of the present application provides a chip that integrates capacitors in the chip. While simplifying the COC structure and process, it can also better eliminate the modulation effect of high-frequency signals on the DFB area, achieving differential drive with lower RIN. The embodiment of the present application also provides corresponding carrier chips, transmitters, optical components, optical modules, optical line terminals, optical network units, and communication equipment. The following are detailed descriptions.

[0075] The chip, chip-on-carrier, and transmitter provided in the embodiments of the present application are described below in conjunction with the above application scenarios.

[0076] As shown in Figures 3 and 4, an embodiment of the present application provides a chip, which includes a conductive substrate 100, an insulating layer 200, a quantum well 300, a first capacitor electrode 400, a distributed feedback laser (DFB) electrode (pad) 500 and an electro-absorption modulator (EAM) electrode 600.

[0077] The insulating layer 200 and the quantum well 300 are grown on the conductive substrate 100, the DFB electrode 500 and the EAM electrode 600 (the EAM electrode 600 in FIG3 is blocked by the DFB electrode 500, so the EAM electrode 600 is shown in FIG4) are grown on the insulating layer 200 and the quantum well 300, and the first capacitor electrode 400 is grown on the insulating layer 200. The first capacitor electrode 400 is used to form a first capacitor C with the conductive substrate 100.

[0078] Specifically, the chip is an electro-absorption modulated laser (EML) chip. A conductive substrate 100 serves as the base of the entire chip. The conductive substrate 100 is conductive and may be made of, for example, indium phosphide (InP). An insulating layer 200 and a quantum well 300 are grown on the conductive substrate 100. This means that the insulating layer 200 and the quantum well 300 together cover the entire surface of the conductive substrate 100. For example, the quantum well 300 may be grown in the middle of the conductive substrate 100, while the rest of the surface of the conductive substrate 100 is covered by the insulating layer 200.

[0079] The insulating layer 200 is non-conductive and needs to cover the sides of the quantum well 300. That is, the quantum well 300 can be the same height as the insulating layer 200, or the quantum well 300 can be taller than the insulating layer 200, with the insulating layer 200 covering the sides of the raised portion of the quantum well 300. The quantum well 300 can be divided into two parts, one covered by the DFB electrode 500 and the other covered by the EAM electrode 600. The quantum well 300 is used to generate laser light. The quantum well 300 is typically made of a thin layer of semiconductor dielectric, for example, by sandwiching a material (such as gallium arsenide) between two layers of a material with a wider band gap (such as aluminum arsenide) in a semiconductor. It can be prepared using molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD).

[0080] Furthermore, the DFB electrode 500 and the EAM electrode 600 are grown on the insulating layer 200 and the quantum well 300, that is, the DFB electrode 500 covers the quantum well 300 and the insulating layer 200, and the EAM electrode 600 also covers the quantum well 300 and the insulating layer 200. Specifically, the DFB electrode 500 and the EAM electrode 600 both cover the top surface of the quantum well 300. Thus, the side surfaces of the quantum well 300 are covered by the insulating layer 200, the bottom surface is covered by the conductive substrate 100, and the top surface is covered by the DFB electrode 500 and the EAM electrode 600.

[0081] The DFB electrode 500 and the EAM electrode 600 serve as the P-pole, and the common conductive substrate 100 serves as the N-pole. The DFB electrode 500, the EAM electrode 600, the quantum well 300, and the insulating layer 200 are all inherent structures of the EML chip and will not be described in detail in this embodiment.

[0082] In the embodiment of the present application, the first capacitor electrode 400 is grown on the insulating layer 200 and is used to form a first capacitor C with the conductive substrate 100. The DFB electrode 500, the EAM electrode 600, and the first capacitor electrode 400 respectively cover different and non-adjacent portions of the insulating layer 200. That is, the growth positions of the DFB electrode 500, the EAM electrode 600, and the first capacitor electrode 400 are arbitrary, but the DFB electrode 500, the EAM electrode 600, and the first capacitor electrode 400 are not coupled to each other or in direct contact, that is, they are all independently present on the insulating layer 200 or the quantum well 300. Exemplarily, the quantum well 300 is located in the center of the entire chip, the DFB electrode 500 and the EAM electrode 600 are grown on the insulating layer 200 to the right of the quantum well 300, and on the quantum well 300, the first capacitor electrode 400 is grown on the insulating layer 200 to the left of the quantum well 300, and the first capacitor electrode 400 does not contact the DFB electrode 500.

[0083] It should be understood that the DFB electrode 500 and the EAM electrode 600 can also be grown on the insulating layer 200 on the left side of the quantum well 300, and the first capacitor electrode 400 can be grown on the insulating layer 200 on the right side of the quantum well 300. The embodiment of the present application does not limit the layout position of each component on the chip, but only needs to ensure that the DFB electrode 500 and other components can realize their own functions.

[0084] The formula for a parallel plate capacitor is:

[0085] Wherein, A is the area of ​​the parallel plate capacitor, i.e., the area of ​​the first capacitor electrode 400 ; d is the distance between the two parallel plates, i.e., the distance between the first capacitor electrode 400 and the conductive substrate 100 ; ε is the dielectric constant of the medium between the parallel plates, i.e., the dielectric constant of the insulating layer 200 .

[0086] A smaller d can be achieved through epitaxial growth processes of the EML chip, such as MBE and MOCVD, or by using dielectric materials with a large dielectric constant, such as silicon dioxide or titanium dioxide as the material of the insulating layer 200, the capacitance value of the first capacitor C can be increased, thereby better controlling the relative intensity noise of the EML chip.

[0087] Optionally, as shown in FIG5 , the conductive substrate 100 includes a metallized portion 101, and the first capacitor electrode 400 is configured to form a first capacitor C with the metallized portion 101. Specifically, the metallized portion 101 in the conductive substrate 100 is parallel to the first capacitor electrode 400, and the metallized portion 101 and the first capacitor electrode 400 form two parallel plates, thus forming the first capacitor C. The size or material of the metallized portion 101 in the conductive substrate 100 can be adjusted or configured according to user needs, thereby more conveniently controlling the capacitance of the first capacitor C.

[0088] Optionally, as shown in Figure 6, the chip also includes a semiconductor optical amplifier (SOA) electrode 700 and a second capacitor electrode 800, the SOA electrode 700 is grown on the insulating layer 200 and the quantum well 300, and the second capacitor electrode 800 is grown on the insulating layer 200, and the second capacitor electrode 800 is used to form a second capacitor with the conductive substrate 100.

[0089] At this time, the SOA electrode 700 covers the top surface of the quantum well 300. The quantum well 300 can be divided into three parts: one part is covered by the DFB electrode 500, one part is covered by the EAM electrode 600, and another part is covered by the SOA electrode 700. The second capacitor electrode 800 is electrically connected to the SOA electrode 700, and the DFB electrode 500, EAM electrode 600, SOA electrode 700, first capacitor electrode 400, and second capacitor electrode 800 respectively cover different and non-adjacent portions of the insulating layer 200. In other words, the DFB electrode 500, EAM electrode 600, first capacitor electrode 400, SOA electrode 700, and second capacitor electrode 800 are not coupled to each other or in direct contact.

[0090] Specifically, the chip is an EML-SOA chip at this time, which also includes an SOA electrode 700 and a second capacitor electrode 800. The arrangement of the SOA electrode 700 and the second capacitor electrode 800 can refer to the DFB electrode 500 and the first capacitor electrode 400, that is, the SOA700 electrode is grown on the insulating layer 200 on the right side of the quantum well 300, and on the quantum well 300, and the second capacitor electrode 800 is grown on the insulating layer 200 on the left side of the quantum well 300, and the second capacitor electrode 800 does not contact the SOA electrode 700.

[0091] It should be understood that the SOA electrode 700 can also be replaced by other optical amplifier electrodes, such as erbium-doped fiber amplifier (EDFA) electrodes. The embodiment of the present application does not limit the elements that can be stacked on the EML chip.

[0092] Optionally, as shown in FIG7 , the chip further includes a first connecting line and a second connecting line, wherein the DFB electrode 500 is electrically connected to the first capacitor electrode 400 within the chip via the first connecting line, and the SOA electrode 700 is electrically connected to the second capacitor electrode 800 within the chip via the second connecting line. That is, the first capacitor electrode 400 and the DFB electrode 500 are connected on-chip, and the second capacitor electrode 700 and the SOA electrode 800 are connected on-chip. This avoids the need for the DFB electrode 500 to be connected to the first capacitor electrode 400 off-chip, and also avoids the need for the SOA electrode 700 to be connected to the second capacitor electrode 800 off-chip. It should be understood that the off-chip approach is more complicated and is not conducive to the miniaturization of the entire EML chip.

[0093] It should be understood that the first connecting line and the second connecting line do not need to be used at the same time, and whether to use the first connecting line and / or the second connecting line can be selected according to actual needs.

[0094] As shown in Figure 8A, an embodiment of the present application also provides a chip on carrier (COC). As shown in Figure 8B, the COC can be used in a transmitter. The transmitter includes a transmission signal source and a chip on carrier (COC). The COC includes a chip and a differential signal transmission line. The differential signal transmission line is used to provide a driving signal to the chip. The transmission signal source is used to provide a driving signal to the chip through the differential signal transmission line. The chip includes a conductive substrate, an insulating layer, a quantum well, a first capacitor electrode, a distributed feedback laser DFB electrode and an electro-absorption modulator EAM electrode.

[0095] The insulating layer and quantum well are grown on a conductive substrate, and the insulating layer and quantum well jointly cover the conductive substrate, with the insulating layer covering the sides of the quantum well. The DFB electrode and EAM electrode are grown on the insulating layer and quantum well. A first capacitor electrode is grown on the insulating layer, electrically connected to the DFB electrode, and configured to form a first capacitor with the conductive substrate. The DFB electrode, EAM electrode, and first capacitor electrode each cover different, non-adjacent portions of the insulating layer.

[0096] Specifically, the chip in the transmitter is the chip described in Figures 3 to 7, and its specific implementation method can refer to the corresponding description above. For example, in the chip, the conductive substrate includes a metallized part, the first capacitor electrode is used to form a first capacitor with the metallized part, and the material of the insulating layer is silicon dioxide or titanium dioxide. The embodiments of this application will not be repeated.

[0097] Exemplarily, the transmitting signal source includes a printed circuit board (PCB), and the digital to analog converter (DAC) on the PCB outputs a differential signal. The PCB also includes two radio frequency differential signal lines (RF- and RF+), which serve as transmission lines of the transmitting signal source and transmit the differential signals of P and N respectively. The COC also includes two differential signal transmission lines (AC- and AC+). AC- and RF- are connected through off-chip connecting lines, and AC+ and RF+ are also connected through off-chip means. In addition, two connecting lines are used between the PCB and the COC to be grounded (GND), and AC- and AC+ are connected to the chip, so that the transmitting signal source provides a driving signal to the chip, that is, differential driving is realized.

[0098] Furthermore, the PCB also includes two electrodes, B and C, and the COC also includes two electrodes, A and D. Electrodes B and C on the PCB are connected to RF- and RF+, respectively, via magnetic beads. The EML chip also includes a first connecting wire, electrically connecting the DFB electrode and the first capacitor electrode within the chip via the first connecting wire.

[0099] The COC also includes a first conductive block and a first magnetic bead. Electrode D is specifically a conductive block, namely the first conductive block. The first capacitor electrode on the EML chip is connected to electrode D via the first magnetic bead. The power supply to the DFB electrode can be controlled by the current between electrodes A and B. The first magnetic bead is placed directly on the first capacitor electrode of the EML chip, that is, the first magnetic bead is directly connected to the EML chip. Compared with the existing chip-on-carrier solution, the connection length between the two is shortened, which helps to improve the overall bandwidth of the chip-on-carrier.

[0100] For the EAM electrode, the COC also includes a second capacitor (capacitor 2). The EAM electrode is connected to AC+ and the second capacitor through off-chip connecting wires. The bias voltage of the EAM electrode is achieved by controlling the voltage difference between the corresponding electrodes B and C.

[0101] Optionally, the DFB electrode and the first capacitor electrode may not be connected on the chip. In this case, the COC also includes a third connecting line, and the DFB electrode and the first capacitor electrode are electrically connected outside the chip through the third connecting line, that is, the DFB electrode and the first capacitor electrode are connected outside the chip, such as by external bonding (third connecting line). At this time, the power supply control method of the DFB electrode remains unchanged.

[0102] Optionally, as shown in Figure 9, the chip in the transmitter also includes a semiconductor optical amplifier (SOA) electrode and a second capacitor electrode, wherein the SOA electrode is grown on the insulating layer and the quantum well, and the SOA electrode covers the top surface of the quantum well. The second capacitor electrode is grown on the insulating layer, electrically connected to the SOA electrode, and is used to form a second capacitor with the conductive substrate. The DFB electrode, the EAM electrode, the SOA electrode, the first capacitor electrode, and the second capacitor electrode respectively cover different and non-adjacent portions on the insulating layer. The chip at this time can also refer to the EML-SOA chip as shown in Figure 6, and the embodiments of the present application will not be repeated here.

[0103] For example, the transmitter can refer to the transmitter shown in Figure 8B, except that the EML-SOA chip further includes a second connecting line, and the SOA electrode and the second capacitor electrode are electrically connected within the chip via the second connecting line, and the COC further includes a second conductive block (electrode E) and a second magnetic bead, and the second conductive block is connected to the second capacitor electrode via the second magnetic bead. The power supply to the SOA electrode can be controlled by the current between electrode E and electrode B.

[0104] Optionally, the SOA electrode and the second capacitor electrode may not be connected on the chip. In this case, the COC also includes a fourth connecting line, and the SOA electrode and the second capacitor electrode are electrically connected outside the chip through the fourth connecting line, that is, the SOA electrode and the second capacitor electrode are connected outside the chip, such as by external bonding (fourth connecting line). At this time, the power supply control method of the SOA electrode remains unchanged.

[0105] Optionally, in the transmitter shown in FIG8B or FIG9 , the COC further includes a detection unit for determining the chip's luminescence status. The detection unit may specifically be a monitor photodiode (mPD). Because the first capacitor electrode is coupled to the EML chip, the backlight output of the EML chip is no longer blocked by the external capacitor in a conventional transmitter, thereby enabling the detection unit to better implement backlight detection.

[0106] It should be understood that the chip-on-carrier provided in the embodiments of the present application is not limited to application in transmitters. Various possible implementations of the chip-on-carrier can be implemented separately on the COC, and are not limited to implementation in transmitters.

[0107] In summary, the above embodiments show that the chip, chip-on-carrier, or transmitter provided in the embodiments of the present application can bring about the following four beneficial effects, including but not limited to:

[0108] (1) Using a differential drive scheme to avoid the output amplitude requirements of the digital-to-analog converter required by the single-ended drive scheme;

[0109] (2) By building the capacitors on the chip, it is easier to realize large capacitance through the epitaxial process, avoiding the high requirements for capacitors in the COC differential drive scheme, thereby better controlling the relative intensity noise of the EML chip.

[0110] (3) The COC differential drive scheme is modified slightly, avoiding the complex structure of the differential EML chip, reducing the complexity of chip production, and avoiding the impact of large external capacitors on the overall bandwidth of the COC;

[0111] (4) The transmitter does not need an external capacitor on the EML chip, which avoids the backlight blocking of the EML chip in the COC differential drive solution and makes it easier to implement backlight detection.

[0112] The above introduces the chip, chip carrier and transmitter provided in the embodiments of the present application. The following introduces the related devices provided in the embodiments of the present application in conjunction with the accompanying drawings.

[0113] As shown in Figure 10, an embodiment of the present application provides a passive optical network, which is a 50G PON, and can also be the passive optical network shown in Figure 1. The passive optical network includes an optical line terminal 900, an optical network unit 1000, and an optical distribution network 1100, where the optical line terminal 900 and the optical network unit 1000 can also be understood as communication equipment.

[0114] The optical line terminal 900 includes an optical module 901, which includes an optical component 902. The optical network unit 1000 also includes an optical module 1001, which includes an optical component 1002. The optical component 902 and / or the optical component 1002 include the chip, chip-on-carrier, or transmitter provided in the embodiments of the present application, or the chip, chip-on-carrier, or transmitter provided in the embodiments of the present application are directly integrated into the optical module 901 and / or the optical module 1001. In this case, the optical module 901 and / or the optical module 1001 can adopt a package form such as QSFP28, QSFP-DD, or SFP.

[0115] Taking the optical line terminal 900 as an example, the optical module 901 may also include devices such as a wavelength division multiplexing (WDM) module. The chip, chip on a carrier, or transmitter provided in the embodiment of the present application can be connected to devices such as WDM as a photoelectric conversion unit, but the embodiment of the present application does not limit the specific internal structure and devices of the optical module 901. The chip, chip on a carrier, or transmitter in the optical module 901 can be connected to other devices, or other connection methods can be used.

[0116] In the optical line terminal 900 provided in the embodiment of the present application, the optical line terminal 900 may further include devices such as a medium access control (MAC) chip and a line card. The optical module 901 may be connected to the MAC chip through the line card, but the embodiment of the present application does not limit the specific internal structure and devices of the optical line terminal 900. The optical module 901 in the optical line terminal 900 may be connected to other devices or adopt other connection methods.

[0117] In addition, the chip, chip-on-carrier, and transmitter provided in the embodiments of the present application can also be used in optical modules or optical components in Ethernet networks such as 100G, 200G, or 400G, or in communication equipment or electronic equipment that requires EML chips.

[0118] Those skilled in the art will appreciate that the structural units of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of this application.

[0119] In the several embodiments provided in this application, it should be understood that the disclosed structure can be implemented in other ways. For example, the embodiments described above are merely schematic. For example, the division of the structure can be divided in other ways in actual implementation, such as multiple units or components can be combined or integrated into another structure, or some features can be ignored. Some or all of the structures can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, structures or units, which can be electrical, mechanical or other forms.

[0120] In addition, the various structures in the embodiments of the present application may be integrated into one structure, or each structure may exist physically separately, or two or more structures may be integrated into one structure.

[0121] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip, characterized in that: It includes a conductive substrate, an insulating layer, a quantum well, a first capacitor electrode, a distributed feedback laser DFB electrode and an electro-absorption modulator EAM electrode, wherein: The insulating layer and the quantum well are grown on the conductive substrate, the insulating layer and the quantum well jointly cover the conductive substrate, and the insulating layer covers the side surface of the quantum well; The DFB electrode and the EAM electrode are grown on the insulating layer and the quantum well, and the DFB electrode and the EAM electrode cover the top surface of the quantum well; The first capacitor electrode is grown on the insulating layer, the first capacitor electrode is electrically connected to the DFB electrode, and the first capacitor electrode is used to form a first capacitor with the conductive substrate; The DFB electrode, the EAM electrode and the first capacitor electrode respectively cover different and non-adjacent portions of the insulating layer.

2. The chip according to claim 1, characterized in that: The chip further comprises a semiconductor optical amplifier SOA electrode and a second capacitor electrode, wherein the SOA electrode is grown on the insulating layer and the quantum well, and the SOA electrode covers the top surface of the quantum well; The second capacitor electrode is grown on the insulating layer, the second capacitor electrode is electrically connected to the SOA electrode, and the second capacitor electrode is used to form a second capacitor with the conductive substrate; The DFB electrode, the EAM electrode, the SOA electrode, the first capacitor electrode, and the second capacitor electrode respectively cover different and non-adjacent portions on the insulating layer.

3. The chip according to claim 1 or 2, characterized in that: The conductive substrate includes a metallization portion, and the first capacitor electrode is used to form the first capacitor with the metallization portion.

4. The chip according to any one of claims 1 to 3, characterized in that: The material of the insulating layer is silicon dioxide or titanium dioxide.

5. The chip according to any one of claims 1 to 4, characterized in that: The chip further includes a first connection line, and the DFB electrode and the first capacitor electrode are electrically connected inside the chip through the first connection line.

6. The chip according to any one of claims 2 to 5, characterized in that: The chip further includes a second connecting line, and the SOA electrode and the second capacitor electrode are electrically connected inside the chip through the second connecting line.

7. A chip on a carrier, characterized in that: The invention comprises a chip and a differential signal transmission line, wherein the differential signal transmission line is used to provide a driving signal to the chip, and the chip comprises a conductive substrate, an insulating layer, a quantum well, a first capacitor electrode, a distributed feedback laser DFB electrode and an electro-absorption modulator EAM electrode, wherein: The insulating layer and the quantum well are grown on the conductive substrate, the insulating layer and the quantum well jointly cover the conductive substrate, and the insulating layer covers the side surface of the quantum well; The DFB electrode and the EAM electrode are grown on the insulating layer and the quantum well, and the DFB electrode and the EAM electrode cover the top surface of the quantum well; The first capacitor electrode is grown on the insulating layer, the first capacitor electrode is electrically connected to the DFB electrode, and the first capacitor electrode is used to form a first capacitor with the conductive substrate; The DFB electrode, the EAM electrode and the first capacitor electrode respectively cover different and non-adjacent portions of the insulating layer.

8. The chip on carrier according to claim 7, characterized in that: The chip on carrier further includes a first magnetic bead and a first conductive block, and the first conductive block is connected to the first capacitor electrode through the first magnetic bead.

9. The chip on carrier according to claim 7 or 8, characterized in that: The chip further comprises a semiconductor optical amplifier SOA electrode and a second capacitor electrode, wherein the SOA electrode is grown on the insulating layer and the quantum well, and the SOA electrode covers the top surface of the quantum well; The second capacitor electrode is grown on the insulating layer, the second capacitor electrode is electrically connected to the SOA electrode, and the second capacitor electrode is used to form a second capacitor with the conductive substrate; The DFB electrode, the EAM electrode, the SOA electrode, the first capacitor electrode, and the second capacitor electrode respectively cover different and non-adjacent portions on the insulating layer.

10. The chip on carrier according to claim 9, characterized in that: The chip on the carrier further includes a second conductive block and a second magnetic bead, and the second conductive block is connected to the second capacitor electrode through the second magnetic bead.

11. The chip on carrier according to any one of claims 7 to 10, characterized in that: The conductive substrate includes a metallization portion, and the first capacitor electrode is used to form the first capacitor with the metallization portion.

12. The chip on carrier according to any one of claims 7 to 11, characterized in that: The material of the insulating layer is silicon dioxide or titanium dioxide.

13. The chip on carrier according to any one of claims 7 to 12, characterized in that: The chip further includes a first connection line, and the DFB electrode and the first capacitor electrode are electrically connected inside the chip through the first connection line.

14. The chip on carrier according to any one of claims 7 to 12, characterized in that: The chip on carrier further includes a third connection line, and the DFB electrode and the first capacitor electrode are electrically connected outside the chip through the third connection line.

15. The chip on carrier according to any one of claims 7 to 14, characterized in that: The chip further includes a second connecting line, and the SOA electrode and the second capacitor electrode are electrically connected inside the chip through the second connecting line.

16. The chip on carrier according to any one of claims 7 to 14, characterized in that: The chip on carrier further includes a fourth connecting line, and the SOA electrode and the second capacitor electrode are electrically connected outside the chip through the fourth connecting line.

17. The chip on carrier according to any one of claims 7 to 16, characterized in that: The chip on the carrier further comprises a detection unit, and the detection unit is used to determine the luminescence condition of the chip.

18. A transmitter, characterized in that: The transmitter comprises a transmission signal source and a chip on a carrier as claimed in any one of claims 7 to 17, wherein the transmission signal source is used to provide a driving signal to the chip through a differential signal transmission line.

19. An optical component, characterized in that: The optical component comprises a chip according to any one of claims 1 to 6, a chip on a carrier according to any one of claims 7 to 17, or a transmitter according to claim 18.

20. An optical module, characterized in that: The optical module comprises a chip according to any one of claims 1 to 6, a chip on a carrier according to any one of claims 7 to 17, or a transmitter according to claim 18.

21. An optical line terminal, characterized in that: The optical line terminal comprises a chip according to any one of claims 1 to 6, a chip on a carrier according to any one of claims 7 to 17, or a transmitter according to claim 18.

22. An optical network unit, characterized in that: The optical network unit comprises a chip according to any one of claims 1 to 6, a chip on a carrier according to any one of claims 7 to 17, or a transmitter according to claim 18.

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