Power amplifier, radio frequency module and electronic device

Abstract

Embodiments of the present application provide a power amplifier, a radio frequency module and an electronic device. The power amplifier comprises a signal input end, a signal output end, and a plurality of transistor cores connected in parallel; the transistor cores each comprise an electrode finger extending in a first direction, and the electrode finger comprises a gate finger, a source finger and a drain finger; in a second direction, the signal input end and the signal output end are respectively located on two sides of the plurality of transistor cores, wherein the second direction is perpendicular to the first direction. According to the present application, the extension direction of the electrode fingers is configured to be perpendicular to a signal input / output direction, so that under a limited layout area, the performance of the electrode fingers can be optimized to the maximum extent and the requirement of high power can be met, and a flexible possibility is created for circuit architecture design.

Description

Power amplifier, radio frequency module and electronic equipment

[0001] This invention claims priority to the Chinese patent application filed with the State Intellectual Property Office on November 30, 2023, with application number 202311636607.4 and application name “A power amplifier, radio frequency module and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a power amplifier, a radio frequency module and an electronic device. Background Art

[0003] Power amplifiers are widely used in radio frequency wireless communications. The mainstream power amplifiers used in the current communications industry include LDMOS (Laterally Diffused Metal Oxide Semiconductor) processes, high-voltage (28V / 48V) GaN (gallium nitride) processes, and GaAs (gallium arsenide) processes. GaAs processes include HBT (heterojunction bipolar transistor) and pHEMT (pseudomorphic high electron mobility transistor) processes. LDMOS and high-voltage GaN processes are predominant in base station applications, while GaAs HBT processes are predominant in terminal applications. Research is also underway on new low-voltage GaN processes for terminal applications.

[0004] With the development of technology, the power requirements of products are getting higher and higher. Under such high power requirements, the layout structure of traditional power amplifiers will occupy a large space and cannot meet the design space requirements.

[0005] Summary of the Invention

[0006] In view of this, the present application provides a power amplifier, a radio frequency module and an electronic device to solve the problem in the prior art that the layout structure of a traditional power amplifier occupies a large space under high power requirements.

[0007] In a first aspect, an embodiment of the present application provides a power amplifier comprising a signal input terminal, a signal output terminal and a plurality of tube cores connected in parallel; the tube core comprises electrode fingers extending along a first direction, the electrode fingers comprising gate fingers, source fingers and drain fingers; in a second direction, the signal input terminal and the signal output terminal are respectively located on both sides of the plurality of tube cores, and the second direction is perpendicular to the first direction.

[0008] In the power amplifier provided by the embodiment of the present application, the extension direction of the electrode fingers is perpendicular to the signal input / output direction. The total gate width can be increased by connecting the tube cores in parallel in the second direction of the signal input / output, or by connecting the tube cores in parallel in the first direction of the electrode fingers. The space in the second direction can be fully utilized, and the length occupied in the first direction can be reduced. Compared with the traditional device layout method, there is no need to reduce the occupation of the first direction by sacrificing the optimal electrical performance of the electrode fingers. The power amplifier provided by the embodiment of the present application can be applied to high-voltage GaN-based devices and can also be applied to low-voltage GaN-based devices. It can maximize the optimization of the electrode finger performance and meet the high-power requirements within a limited layout area, and creates flexible possibilities for circuit architecture design.

[0009] The power amplifier includes a gate lead connected to a signal input terminal and a drain lead connected to a signal output terminal, a gate finger connected to the gate lead, and a drain finger connected to the drain lead. A plurality of dies arranged along a second direction form a die row. The dies in a die row share a drain lead and a gate lead, thereby achieving parallel connection of the dies.

[0010] In some embodiments, a row of die is positioned between adjacent drain leads and gate leads. Using the row of die to separate the drain and gate leads can prevent the drain lead signal from coupling with the gate lead signal, which could cause the power amplifier to malfunction, thereby ensuring normal operation of the power device.

[0011] In some embodiments, the power amplifier includes at least one structural group, which includes two adjacent tube core rows in a first direction; the two tube core rows in the structural group share a gate lead or a drain lead, thereby realizing flexible wiring of the gate lead and the drain lead.

[0012] In some embodiments, the number of dies in the two die rows within a structure group is equal. This arrangement allows for efficient utilization of space in the second direction, avoiding wasted space. It also allows for a regular arrangement of the multiple dies within the power amplifier, resulting in a more regular arrangement of the electrode fingers, which facilitates etching uniformity.

[0013] In some embodiments, a power amplifier includes n structure groups connected in parallel, where the n structure groups are arranged along a first direction, where n is a positive integer and n ≥ 2. During device layout design, after a certain number of dies are arranged in a die row, the total gate width can be increased by increasing the number of structure groups to meet power requirements and balance the space occupied by the overall device in the first and second directions.

[0014] In some embodiments, in a row of tube cores, adjacent tube cores share a drain finger and / or a source finger, the first end of the gate lead is connected to the signal input terminal and the second end is connected to the gate finger, the first end of the drain lead is connected to the drain finger and the second end is connected to the signal output terminal; the first ends of at least two gate leads electrically connected to two adjacent structural groups are electrically connected, and the second ends of at least two drain leads electrically connected to two adjacent structural groups are electrically connected. When the number of tube cores in the tube core row is fixed, the design of the embodiment of the present application can reduce the length occupied by the tube core row in the second direction, saving the layout space of the power amplifier. In addition, when it is necessary to further save space in the first direction y, the number of tube cores in the tube core row can be appropriately increased to meet high power requirements.

[0015] In some embodiments, in at least one die row, two groups of electrode fingers of at least two dies are staggered in the second direction. This arrangement can disperse heat dissipation in the device, reduce local hot spots, and increase overall system performance reliability in applications.

[0016] In some embodiments, at least one die row includes a first die, a second die, and a third die, the second die being located between the first die and the third die, the first die and the second die being adjacent, and the third die and the second die being separated by m dies, where m is an integer and m ≥ 0; the two sets of electrode fingers of the first die and the second die are staggered in the second direction, the two sets of electrode fingers of the second die and the third die are staggered in the second direction, and the electrode fingers of the first die and the electrode fingers of the third die are offset in the same direction relative to the electrode fingers of the second die. Such an arrangement not only disperses the heat dissipation distribution in the device, but also minimizes the width of the die row in the first direction, meeting the layout space requirements of high-power devices. Furthermore, it minimizes the current phase difference between different die, ensuring device performance.

[0017] In some embodiments, a power amplifier includes a microstrip line, the microstrip line including a first microstrip line and a second microstrip line; at least one die row includes a fourth die and a fifth die, and two sets of electrode fingers of the fourth die and the fifth die are staggered in a second direction; along the first direction, the distance between the electrode fingers of the fourth die and the drain lead is greater than the distance between the electrode fingers of the fifth die and the drain lead; the drain fingers of the fourth die are electrically connected to the drain lead via the first microstrip line, and the gate fingers of the fifth die are electrically connected to the gate lead via the second microstrip line. Providing the first and second microstrip lines can reduce the phase difference between the output signals of the fourth and fifth die, ensuring that the phases remain consistent as much as possible, thereby improving the synthesis effect of the output signals of the parallel die and enhancing device performance.

[0018] In some embodiments, the electrode fingers of at least two of the multiple dies have unequal lengths. This arrangement can compensate for differences in signal transmission paths between the different dies, thereby balancing phase differences in output signals from the different dies, ultimately achieving an optimal output current synthesis state, thereby improving the overall electrical performance of the device.

[0019] In some embodiments, the plurality of dies include a sixth die and a seventh die, the electrode fingers of the sixth die are longer than the electrode fingers of the seventh die, the power amplifier includes a microstrip line, the microstrip line includes a third microstrip line electrically connected to the gate fingers of the seventh die, and / or the microstrip line includes a fourth microstrip line electrically connected to the drain fingers of the seventh die. The microstrip line can balance the phase difference of the output signals of the seventh and sixth dies, so that the final current synthesis reaches an optimal output state, thereby improving the overall electrical performance of the device.

[0020] On the second aspect, based on the same inventive concept, an embodiment of the present application also provides a radio frequency module, including the power amplifier provided by any embodiment of the present application.

[0021] On the third aspect, based on the same inventive concept, an embodiment of the present application also provides an electronic device, including the radio frequency module provided by any embodiment of the present application.

[0022] The power amplifier, radio frequency module and electronic device provided by the embodiments of the present application have the following beneficial effects: the extension direction of the electrode finger is set to be perpendicular to the signal input / output direction, and the tube cores can be connected in parallel in the second direction of signal input / output to increase the total gate width, or the tube cores can be connected in parallel in the first direction of the electrode finger extension to increase the total gate width. It is possible to make full use of the space in the second direction and reduce the length occupied in the first direction. Compared with the traditional device layout method, there is no need to reduce the occupation of the first direction by sacrificing the optimal electrical performance of the electrode finger. The power amplifier provided by the embodiment of the present application can maximize the optimization of the electrode finger performance and meet the high power requirements within a limited layout area, and creates flexible possibilities for circuit architecture design. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] FIG1 is a diagram of a stacked structure of a GaN device in the prior art;

[0025] FIG2 is a diagram showing a stacked structure of a GaAs HBT device in the prior art;

[0026] FIG3 is a diagram of a stacked structure of a GaN device provided in an embodiment of the present application;

[0027] FIG4 is a schematic diagram of the structure of a power amplifier in the prior art;

[0028] FIG5 is a schematic diagram of a power amplifier provided in an embodiment of the present application;

[0029] FIG6 is a schematic diagram of another power amplifier provided in an embodiment of the present application;

[0030] FIG7 is a schematic diagram of another power amplifier provided in an embodiment of the present application;

[0031] FIG8 is a schematic diagram comparing a power amplifier provided by an embodiment of the present application with a conventional power amplifier;

[0032] FIG9 is a schematic diagram of another power amplifier provided in an embodiment of the present application;

[0033] FIG10 is a schematic diagram of another power amplifier provided in an embodiment of the present application;

[0034] FIG11 is a schematic diagram of another power amplifier provided in an embodiment of the present application;

[0035] FIG12 is a schematic diagram of another power amplifier provided in an embodiment of the present application;

[0036] FIG13 is a schematic diagram of another power amplifier provided in an embodiment of the present application;

[0037] FIG14 is a schematic diagram of another power amplifier provided in an embodiment of the present application;

[0038] FIG15 is a schematic diagram of another power amplifier provided in an embodiment of the present application;

[0039] FIG16 is a schematic diagram of another power amplifier provided in an embodiment of the present application;

[0040] FIG17 is a schematic diagram of a circuit architecture provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0042] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0043] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0044] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0045] Figure 1 shows a stacked structure of a GaN device in the prior art. The GaN device in Figure 1 is a high-voltage GaN device. As shown in Figure 1, the high-voltage GaN device includes an AlN (aluminum nitride) transition layer 012, an AlGaN (aluminum gallium nitride) buffer layer 013, a GaN channel layer 014, an AlGaN barrier layer 015, as well as a gate 016, a source 017, and a drain 018, stacked on a SiC / Si (silicon carbide / silicon) substrate 011. Due to the piezoelectric effect, a two-dimensional electron gas (2DEG) forms in the GaN channel layer 014 along the interface between the GaN channel layer 014 and the AlGaN barrier layer 015, generating electrical conduction. The 2DEG serves as a conductive channel between the source 017 and the drain 018. As can be seen from FIG1 , the high-voltage GaN device is further provided with a gate field plate 0161 connected to the gate 016 and a source field plate 0171 connected to the source 017 . The field plate is an important component of the high-voltage GaN device and its function is to control the charge distribution and the electric field distribution.

[0046] Figure 2 shows the stacked structure of a GaAs HBT device in the prior art. As shown in Figure 2, the GaAs HBT device includes an n+GaAs subcollector region 022, an nGaAs collector region 023, a p+GaAs base region 024, an nInGaP (indium gallium phosphide) layer 025, an n+GaAs layer 026, as well as a base 027, an emitter 028, and a collector 029, stacked on a GaAs substrate 021. The GaAs HBT device is a longitudinal current device.

[0047] At present, high-voltage GaN devices are mainly used in base station scenarios, such as high-voltage (28v / 48v) GaN process devices, while GaAs HBT devices are mainly used in terminal scenarios. However, GaAs HBT devices have the disadvantage of thermal reliability in terminal scenarios. The embodiment of the present application provides a low-voltage GaN power amplifier device to be applied to terminal scenarios. Terminal products can be, for example, portable electronic devices such as mobile phones, tablets, smart wearable products (such as watches). The operating voltage (i.e., drain voltage) of the low-voltage GaN power amplifier device provided in the embodiment of the present application is Vo, Vo≤15V. In some embodiments, Vo≤12V. Optionally, Vo≥3V.

[0048] FIG3 is a diagram of a stacked structure of a GaN device provided in an embodiment of the present application. The GaN device in FIG3 is a low-voltage GaN device. As shown in FIG3 , the low-voltage GaN device sequentially includes a SiC / Si substrate 031, an AlN transition layer 032, an AlGaN buffer layer 033, a GaN channel layer 034, an AlGaN barrier layer 035, a gate 036, a source 037, and a drain 038. Optionally, the low-voltage GaN device further includes a nucleation layer, which is located between the SiC / Si substrate 031 and the AlN transition layer 032. The nucleation layer has a lattice structure and / or a thermal expansion coefficient, and the nucleation layer is suitable for bridging the lattice dislocation and / or thermal expansion coefficient mismatch between the substrate layer and the upper layer. Optionally, the low-voltage GaN device further includes an AlN insertion layer, which is located between the GaN channel layer 034 and the AlGaN barrier layer 035. Optionally, the low-voltage GaN device further includes a GaN cap layer, which is located on the side of the AlGaN barrier layer 035 away from the GaN channel layer 034. The low-voltage GaN device utilizes the piezoelectric effect to form a two-dimensional electron gas in the GaN channel layer 034 to conduct electricity. The low-voltage GaN device provided in the embodiment of the present application can be manufactured using the following process: first, a SiC / Si substrate is provided, which has high resistance properties, a square resistance of >5kohm.cm, and a thickness of 50μm to 300μm; then, an AlN / AlGaN multilayer structure is grown on the substrate to form a nucleation layer, a transition layer, and a buffer layer, with a total thickness of approximately 300nm to 2μm; then, a GaN channel layer and an AlN insertion layer are grown, with a total thickness of approximately 100nm to 500nm; then, a barrier layer and a cap layer are grown, with a total thickness of approximately 5 to 30nm; and finally, a gate, source, and drain are fabricated. The manufacturing processes for the gate, source, and drain include, but are not limited to, evaporation, electroplating, sputtering, and the like. The gate, source and drain electrodes are made of metals including one or more combinations of elements such as Ti (titanium), Al, Ni (nickel), Au (gold), and Pt (platinum).

[0049] Comparing Figures 2 and 3, it can be seen that low-voltage GaN devices and GaAs HBT devices have completely different physical structures. Figures 1 and 3 also show that the structures of low-voltage GaN devices and high-voltage GaN devices differ to some extent. For example, low-voltage GaN devices do not require a field plate structure. Furthermore, the spacing between the source and drain in low-voltage GaN devices, Lds, is ≤3μm, and the barrier layer thickness is approximately 5nm to 20nm. In contrast, the spacing between the source and drain in high-voltage GaN devices, Lds, is ≥5μm, and the barrier layer thickness is approximately 25nm to 35nm. In other words, low-voltage GaN devices are generally smaller than high-voltage GaN devices. Despite the size difference, the electrode layout of low-voltage GaN power amplifier devices can be designed based on the traditional high-voltage GaN power amplifier devices.

[0050] Figure 4 is a schematic diagram of the structure of a power amplifier in the prior art, showing a top view. As shown in Figure 4, a conventional power amplifier structure includes multiple dies 03 connected in parallel. Die 03 includes gate fingers 031, source fingers 032, and drain fingers 033. Gate fingers 031, source fingers 032, and drain fingers 033 all extend along a first direction a. Multiple dies 03 are arranged in a second direction b and connected in parallel, with the first direction a and the second direction b being perpendicular to each other. Die 03 is the basic unit of a power amplifier, and connecting dies 03 in parallel achieves a higher combined current or power. Arrows in Figure 4 illustrate signal flow: signals are input from the left and output from the right, meaning the power amplifier's signal flow is left-in, right-out. In other words, the signal input / output direction is the first direction a. The extension direction of each electrode finger in Figure 4 is parallel to the signal input / output direction.

[0051] When designing a power amplifier, the total gate width is equivalent to power: that is, the larger the total gate width, the higher the power. In a power amplifier, the width of a gate finger is the gate length, while the length of a gate finger is the gate width. In Figure 4, the gate width is the length of a gate finger 031 in the first direction a, and the total gate width is the product of the number of gate fingers 031 and the length of the gate finger 031. However, the traditional device layout shown in Figure 4 presents the following problems in high-power applications: When the length of a single gate finger 031 is fixed, more dies 03 must be connected in parallel in the second direction b to meet the high power requirement. This results in the device occupying a large length in the second direction b (i.e., perpendicular to the signal input / output direction), making it difficult to layout the power amplifier when the module system is space-constrained. When the number of dies 03 connected in parallel is fixed, increasing the length of a single gate finger 031 can meet the total gate width requirement. However, since longer gate fingers 031 increase losses, increasing the length of the gate finger 031 may miss the optimal finger length for optimal electrical performance, resulting in significant power loss. It can be seen that traditional device layout methods cannot simultaneously meet the layout space and optimal electrode finger length requirements under high power demands. Especially when considering the production of low-voltage GaN power amplifier devices for end products, the requirements for miniaturization of the power amplifier devices will also be relatively high.

[0052] In order to solve the problems existing in the layout of traditional power amplifiers in high-power applications, an embodiment of the present application provides a solution, which sets the extension direction of the electrode fingers to be perpendicular to the signal transmission direction, rationally utilizes the layout space in two directions, and can maximize the performance of the electrode fingers under limited layout area conditions, and can meet the layout space requirements and the optimal finger length requirements in high-power applications.

[0053] FIG5 is a schematic diagram of a power amplifier provided by an embodiment of the present application. As shown in FIG5 , the power amplifier includes a signal input terminal 10, a signal output terminal 20, and a plurality of dies 30 connected in parallel. The dies 30 include a set of electrode fingers 40 extending along a first direction y, wherein the electrode fingers 40 include gate fingers 41, source fingers 42, and drain fingers 43. A plurality of dies 30 arranged along a second direction x form a die row 30H, where the second direction x is perpendicular to the first direction y. The term "perpendicular" as used herein refers to being substantially perpendicular to each other. For example, if the angle between the first direction y and the second direction x falls within the range of [95°, 105°], the two directions are considered perpendicular to each other. The width of the gate finger 41 is smaller than that of the source finger 42 and the drain finger 43. In FIG5 , the gate finger 41 is illustrated only as a thin black line.

[0054] In the second direction x, the signal input terminal 10 and the signal output terminal 20 are located on both sides of the plurality of dies 30. FIG5 shows that the signal in the power amplifier is input from the left and output from the right, that is, the signal input / output direction is the second direction x.

[0055] Figure 5 is a top view schematic diagram of the power amplifier. As shown in Figure 5, "electrode fingers extending along the first direction y" means that the length direction of the electrode fingers 40 is the first direction y, and the width direction of the corresponding electrode fingers 40 is the second direction x; "in the second direction x, the signal input terminal 10 and the signal output terminal 20 are respectively located on both sides of the multiple tube cores 30" means that the signal input terminal 10 and the signal output terminal 20 are respectively arranged on both sides of the multiple tube cores 30 in the second direction x; in some embodiments, the virtual line between the signal input terminal 10 and the signal output terminal 20 forms a non-zero angle with the second direction x; in another embodiment, the virtual line between the signal input terminal 10 and the signal output terminal 20 is in the second direction x; "multiple tube cores 30 arranged along the second direction x" means that the tube cores 30 are arranged at intervals in the second direction x, specifically, the width direction of the electrode fingers 40 in the tube core 30 is the second direction x, or it can be said that the width direction of the tube core 30 is the second direction x.

[0056] As shown in FIG5 , the power amplifier further includes a gate lead 51 and a drain lead 52. The gate fingers 41 are connected to the signal input terminal 20 via the gate lead 51, and the drain fingers 43 are connected to the signal output terminal 20 via the drain lead 52. A signal input from the signal input terminal 10 enters the gate fingers 41 of the multiple parallel dies 30 via the gate lead 51. The signals output by the drain fingers 43 of the multiple dies 30 are then combined via the drain lead 52 and output from the signal output terminal 20.

[0057] In the power amplifier provided by the embodiment of the present application, the extension direction of the electrode finger 40 is perpendicular to the signal input / output direction. The total gate width can be increased by connecting the tube core 30 in parallel in the second direction x of the signal input / output, or by connecting the tube core 30 in parallel in the first direction y where the electrode finger 40 extends. With such an arrangement, the space in the second direction x can be fully utilized, and the length occupied in the first direction y (i.e., the direction perpendicular to the signal input / output direction) can be reduced. Compared with the traditional device layout method, there is no need to reduce the occupation of the first direction y by sacrificing the optimal electrical performance of the electrode finger 40. The embodiment of the present application can maximize the optimization of the electrode finger performance and meet the high power requirements within a limited layout area, and creates flexible possibilities for circuit architecture design.

[0058] In some embodiments, as shown in FIG5 , multiple dies 30 in a die row 30H share a drain lead 52 and a gate lead 51. That is, multiple drain fingers 43 in the same die row 30H are connected to the same drain lead 52, and multiple gate fingers 41 are connected to the same gate lead 51, thereby achieving parallel connection of multiple dies 30.

[0059] Optionally, both the gate lead 51 and the drain lead 52 extend along the second direction x. The line shapes of the gate lead 51 and the drain lead 52 are not limited to straight lines; they may also be broken lines or curves. Arranging the extension direction of the drain lead 52 and the gate lead 51 to intersect the extension direction of the electrode fingers 40 facilitates the connection between the gate fingers 41 and the gate lead 51, and also facilitates the connection between the drain fingers 43 and the drain lead 52, thereby reducing the lead winding length and saving space.

[0060] In some embodiments, as shown in FIG5 , a die row 30H is located between adjacent drain leads 52 and gate leads 51. In other words, a die row 30H is spaced between adjacent drain leads 52 and gate leads 51. Separating the drain leads 52 and gate leads 51 prevents the signal from the drain lead 52 from coupling with the signal from the gate lead 51, which could cause the power amplifier to malfunction, thereby ensuring normal operation of the power device.

[0061] As shown in FIG5 , adjacent die 30 in a die row 30H share drain fingers 43 or source fingers 42. When the number of die 30 in a die row 30H is fixed, the design of the present embodiment can reduce the length of the die row 30H in the second direction x, saving layout space for the power amplifier. Furthermore, when further space savings in the first direction y are required, the number of die 30 in the die row 30H can be appropriately increased to meet high power requirements.

[0062] In some embodiments, a power amplifier includes a structural group, each of which includes two die rows 30H. Since the signal input / output direction is the second direction x, it is easy to arrange leads so that the die rows 30H in the structural group are connected in parallel. That is, multiple die 30 in the structural group are connected in parallel. As shown in Figure 5, a structural group 60 includes two adjacent die rows 30H in a first direction y. The two die rows 30H in the structural group 60 share a gate lead 51. In the first direction y, two drain leads 52 are located on either side of the structural group 60. In this embodiment, the signal is input through the gate lead 51 located between the two die rows 30H, and the output signal is then synthesized and output from the upper and lower sides of the structural group 60.

[0063] In other embodiments, two rows of die within a structure group share a drain lead. Figure 6 is a schematic diagram of another power amplifier provided by an embodiment of the present application. As shown in Figure 6, a structure group 60 includes two adjacent rows of die 30H in a first direction y. The two rows of die 30H within structure group 60 share a drain lead 52. In the first direction y, two gate leads 51 are located on either side of structure group 60. In this embodiment, signals are input via the gate leads 51 located at the top and bottom sides of structure group 60, and the output signal is then synthesized between the two rows of die 30H and output.

[0064] As shown in FIG5 or FIG6 , the two die rows 30H within the structure group 60 have an equal number of dies 30. This arrangement effectively utilizes the space in the second direction x, avoiding wasted space. It also ensures a regular arrangement of the multiple dies 30 within the power amplifier, resulting in a more regular arrangement of the electrode fingers 40, which facilitates etching uniformity.

[0065] In some embodiments, the power amplifier includes n structure groups 60 connected in parallel, and the n structure groups 60 are arranged along the first direction y, where n is a positive integer and n≥2. Taking n=4 as an example, FIG7 is a schematic diagram of another power amplifier provided in an embodiment of the present application. As shown in FIG7 , the power amplifier includes four structure groups 60 connected in parallel, and each structure group 60 includes two tube core rows 30H. The tube core row 30H includes four tube cores 30 connected in parallel, and each structure group 60 includes eight tube cores 30, and the power amplifier includes a total of 32 tube cores 30. When designing the layout of the device, after setting a certain number of tube cores 30 in the tube core row 30H, the total gate width can be increased by increasing the number of structure groups 60 to meet the power requirements and balance the space occupied by the overall device in the first direction y and the second direction x.

[0066] As can be seen in Figure 7 , the first end of the gate lead 51 is connected to the signal input terminal 10, and the second end is connected to the gate finger 41. The first end of the drain lead 52 is connected to the drain finger 43, and the second end is connected to the signal output terminal 20. The first ends of at least two gate leads 51 electrically connected to two adjacent structural groups 60 are electrically connected, and the second ends of at least two drain leads 52 electrically connected to two adjacent structural groups 60 are electrically connected, thus achieving parallel connection of the two adjacent structural groups 60. Figure 7 illustrates that two rows of dies 30H in a structural group 60 share a gate lead 51. That is, one gate lead 51 and two drain leads 52 are required for each structural group 60. The first ends of the two gate leads 51 corresponding to the two adjacent structural groups 60 are electrically connected. Figure 7 also illustrates that two adjacent structural groups 60 share a drain lead 52 and two drain leads 52 used by each of them. That is, the second ends of the two drain leads 52 electrically connected to the two adjacent structural groups 60 are electrically connected. In other embodiments, two adjacent structural groups 60 may not share a drain lead 52 , and each structural group 60 may be provided with two drain leads 52 , which are electrically connected to the second ends of the four drain leads 52 electrically connected to the two adjacent structural groups 60 .

[0067] FIG8 is a schematic diagram comparing a power amplifier provided in an embodiment of the present application with a traditional power amplifier. FIG8 A is a schematic diagram of a power amplifier layout provided in an embodiment of the present application, and FIG8 B is a schematic diagram of a traditional power amplifier layout. Taking each structure group 60 including 8 tube cores 30 as an example, the length of the gate finger 41 is 125μm, that is, the gate width of a single finger is 125μm, and the total gate width is 4mm. Both FIG8 and FIG8 include 4 structure groups 60. In FIG8, the gate lead 51 and the drain lead 52 extend along the second direction x, and in FIG8, the gate lead 51 and the drain lead 52 extend along the first direction y. Other process conditions (such as gate length, source and drain spacing, etc.) of FIG8 and FIG8 are the same. The arrows in FIG8 indicate the transmission direction of the signal, and it can be understood that the signal is input from the left and output from the right. In the traditional power amplifier layout, the extension direction of the electrode finger is parallel to the signal input / output direction, while the extension direction of the electrode finger 40 designed in the embodiment of the present application is perpendicular to the signal input / output direction. Comparing Figure A and Figure B, it can be seen that, when the total gate width is the same, the design of the embodiment of the present application appropriately utilizes the space in the second direction x and can reduce the space occupied by the device in the first direction y.

[0068] Figure 8A illustrates a single die row with four dies 30 as an example. To meet the total gate width requirement, more dies 30 can be connected in parallel within the die row. Figure 9 is a schematic diagram of another power amplifier according to an embodiment of the present application. As shown in Figure 9, a die row 30H includes eight dies 30, with two structure groups 60 arranged along the first direction y. When other process conditions, such as the length of the electrode fingers 50 and the spacing between the source and drain fingers 42, 43, are the same as those in Figure 8A, Figure 9 also meets the total gate width design requirements. Compared to the design in Figure 8A, the embodiment in Figure 9 can further save 50% of space in the first direction y. The design in Figure 9 enables a more compact device layout, appropriately increasing the space occupied by the device in the second direction x, and reducing the number of structure groups 60 connected in parallel in the first direction y, thereby further reducing the space occupied by the device in the first direction y.

[0069] In some embodiments, two groups of electrode fingers 40 of at least two dies 30 in at least one die row 30H are staggered in the second direction x, wherein the two dies 30 with the staggered electrode fingers 40 may be adjacent or non-adjacent.

[0070] Figure 10 is a schematic diagram of another power amplifier provided by an embodiment of the present application. As shown in Figure 10 , at least one die row 30H includes a first die 31 and a second die 32. In a second direction x, the electrode fingers 40 of the first die 31 and the electrode fingers 40 of the second die 32 are staggered. That is, the electrode fingers 40 of the first die 31 and the electrode fingers 40 of the second die 32 are not aligned in the second direction x. This arrangement can disperse heat dissipation within the device, reduce local hot spots, and improve the overall performance and reliability of the system in applications.

[0071] The gate fingers 41, source fingers 42, and drain fingers 43 in the electrode fingers 40 are substantially equal in length. The two sets of electrode fingers 40 in two adjacent die 20 are staggered in the second direction x. The staggered length of the two sets of electrode fingers 40 along the first direction y is L, which is no greater than half the length of the electrode finger 40. This prevents a single die row 30H from being too long in the first direction y, which would affect the space occupied by the device in the first direction y. It also prevents excessive signal phase differences between adjacent die 30s, which would affect the output signal synthesis effect.

[0072] Figure 10 illustrates a structure group 60 in which two rows of dies 30H share a gate lead 51. In other embodiments, Figure 11 is a schematic diagram of another power amplifier provided by an embodiment of the present application. As shown in Figure 11, two rows of dies 30H in a structure group 60 share a drain lead 52, and two groups of electrode fingers 40 of at least two dies 30 in at least one row of dies 30H are staggered in the second direction x.

[0073] As shown in FIG10 , at least one die row 30H includes a first die 31, a second die 32, and a third die 33. The second die 32 is located between the first die 31 and the third die 33. The first die 31 and the second die 32 are adjacent to each other, and there is m dies between the third die 33 and the second die 32, where m is an integer and m ≥ 0; FIG10 illustrates the arrangement with m = 0. The two sets of electrode fingers 40 of the first die 31 and the second die 32 are offset in a second direction x. The two sets of electrode fingers 40 of the second die 32 and the third die 33 are offset in the same direction relative to the electrode fingers 40 of the second die 32. In other words, the two sets of electrode fingers 40 of the first die 31 and the third die 33 are offset relative to the electrode fingers 40 of the second die 32, away from the drain lead 52 to which these three dies 30 are connected. In other words, the electrode fingers 40 of the second die 32 are offset relative to the two groups of electrode fingers 40 of the first die 31 and the third die 33 in a direction away from the gate lead 52 to which the three dies 30 are connected.

[0074] As can be seen in the top view of the layout in Figure 10, the electrode fingers 40 of the second die 32 are offset upward relative to the two sets of electrode fingers 40 of the first die 31 and the third die 33. Considering that if the electrode fingers 40 of the second die 32 are offset upward relative to the electrode fingers 40 of the first die 31, and the electrode fingers 40 of the third die 33 are offset upward relative to the electrode fingers 40 of the second die 32, not only will the width of the die row 30H containing these three dies 30 increase in the first direction y, affecting the overall size of the device, but it will also cause the phase difference of the current signals in these three dies 30 to increase, affecting device performance. However, the design of the embodiment of the present application not only disperses the heat dissipation distribution in the device, but also minimizes the width of the die row 30H in the first direction y, meeting the layout space requirements of high-power devices. Furthermore, it minimizes the current phase difference between different dies 30, ensuring device performance.

[0075] In some embodiments, as shown in FIG10 , the two sets of electrode fingers 40 of any two adjacent die 30 in a die row 30H are staggered in the second direction x, and the electrode fingers 40 of the odd-numbered die 30 are offset in the same direction relative to the electrode fingers 40 of the even-numbered die 30. This arrangement can further disperse heat dissipation in the device and improve device performance and reliability.

[0076] In other embodiments, FIG12 is a schematic diagram of another power amplifier provided by an embodiment of the present application. As shown in FIG12 , in a die row 30H, there are two sets of electrode fingers 40 for two adjacent die 30 that are staggered in the second direction x, and there are also two sets of electrode fingers 40 for two adjacent die 30 that are aligned in the second direction x. The number of die 30 that are aligned continuously is two or more.

[0077] The two adjacent and aligned dies 30 illustrated in FIG12 do not share common electrode fingers. In other embodiments, in a die row 30H, two sets of electrode fingers 40 of two adjacent dies 30 may be staggered in the second direction x, or two sets of electrode fingers 40 of two adjacent dies 30 may be aligned in the second direction x, wherein the two adjacent and aligned dies 30 do not share common source fingers 42 or common drain fingers 43. This is not illustrated in the figures here.

[0078] In other embodiments, the two groups of electrode fingers 40 of at least two dies 30 in at least one die row 30H are staggered in the second direction x, and a microstrip line is provided in the power amplifier to balance the signal phase differences between different dies 30. FIG13 is a schematic diagram of another power amplifier provided by an embodiment of the present application. As shown in FIG13 , the power amplifier includes a microstrip line 70. The microstrip line 70 is a transmission line that has low signal loss during transmission. The microstrip line 70 includes a first microstrip line 71 and a second microstrip line 72. The two sets of electrode fingers 40 of the fourth die 34 and the fifth die 35 are staggered in the second direction x. Along the first direction y, the distance between the electrode fingers 40 of the fourth die 34 and the drain lead 52 is greater than the distance between the electrode fingers 40 of the fifth die 35 and the drain lead 52. The drain fingers 43 of the fourth die 34 are electrically connected to the drain lead 52 via the first microstrip line 71, and the gate fingers 41 of the fifth die 35 are electrically connected to the gate lead 51 via the second microstrip line 72. Because the distance between the electrode fingers 40 of the fourth die 34 and the drain lead 52 is greater, the transmission distance of the signal output by the fourth die 34 to the drain lead 52 is relatively long. Therefore, the provision of the first microstrip line 71 between the drain fingers 43 of the fourth die 34 and the drain lead 52 can reduce the loss of the output signal of the fourth die 34. Because the electrode fingers 40 of the fifth die 35 are relatively far from the gate lead 51, the transmission distance of the input signal transmitted from the gate lead 51 to the fifth die 35 is relatively long. Therefore, providing a second microstrip line 72 between the gate fingers 41 of the fifth die 35 and the gate lead 51 can reduce the loss of the input signal provided to the fifth die 35. In this embodiment, providing the first microstrip line 71 and the second microstrip line 72 can reduce the phase difference between the output signals of the fourth die 34 and the fifth die 35, so that the phases are kept consistent as much as possible, thereby improving the synthesis effect of the output signals of the parallel die 30 and improving device performance.

[0079] In the embodiment of FIG10 , to illustrate the staggered arrangement of the tube cores 30, the three sequentially arranged tube cores are named first tube core 31, second tube core 32, and third tube core 33. In FIG13 , to illustrate the arrangement of the microstrip line 70, the tube cores are named fourth tube core 34 and fifth tube core 35. When the embodiment of FIG10 is applied to the arrangement of the microstrip line 70 in the embodiment of FIG13 , it can be understood that in FIG10 , the first tube core 31 and the third tube core 33 are equivalent to the fourth tube core 34, and the second tube core 32 is equivalent to the fifth tube core 35. A first microstrip line 71 can be correspondingly arranged for the first tube core 31 and the third tube core 33, and a second microstrip line 72 can be arranged for the second tube core 32.

[0080] In some embodiments, the electrode fingers 40 of at least two die 30 in a power amplifier have unequal lengths. Dies 30 with unequal electrode fingers 40 can be located in the same die row 30H or in different die rows 30H. Figure 14 is a schematic diagram of another power amplifier according to an embodiment of the present application. As shown in Figure 14, the multiple die 30 include a sixth die 36 and a seventh die 37. The electrode fingers 40 of the sixth die 36 are longer than those of the seventh die 37. Figure 13 illustrates the signal input terminal 10 and the signal output terminal 20. It can be seen that the die 30 in the first die row 30H, counting from the top, are relatively far from both the signal input terminal 10 and the signal output terminal 20. The seventh die 37 is located in the first die row 30H, while the sixth die 36 is relatively close to both the signal input terminal 10 and the signal output terminal 20. It can be understood that the signal transmission path through the seventh die 37 is longer than the signal transmission path through the sixth die 36. By setting the length difference between the electrode finger 40 of the sixth tube core 36 and the electrode finger 40 of the seventh tube core 37, the difference in signal transmission paths between the two can be compensated, and then the phase difference of the output signals of the two can be balanced, so that the final current synthesis reaches the optimal output state, thereby improving the overall electrical performance of the device.

[0081] FIG14 illustrates a situation where the tube cores 30 with electrode fingers 40 of different lengths are located in different tube core rows 30H. In other embodiments, tube cores 30 with electrode fingers 40 of different lengths are provided in the same tube core row 30H. FIG15 is a schematic diagram of another power amplifier provided in an embodiment of the present application, taking the two groups of electrode fingers 40 of two adjacent tube cores 30 in the tube core row 30H as an example in which they are staggered in the second direction x. As shown in FIG15 , the tube core row 30H includes four tube cores 30, and the lengths of the electrode fingers 40 of the four tube cores 30 from left to right are L1, L2, L3 and L4 respectively. For example, L1 = L4, L2 = L3, and L1 ≠ L2; for another example, L1 = L2, L3 = L4, and L3 ≠ L2. In practice, the length of the electrode finger 40 can be set according to the specific position of the tube core 30. By optimizing the length of the electrode finger 40 in each tube core 30, the current synthesis output by multiple tube cores 30 can reach the optimal output state, thereby improving the overall electrical performance of the device.

[0082] In the embodiment of Figure 15, the two groups of electrode fingers 40 of two adjacent tube cores 30 in the tube core row 30H are staggered in the second direction x, and the tube core row 30H includes tube cores 30 with electrode fingers 40 of different lengths. On the basis of being able to disperse the heat consumption in the structural group, the length of the electrode fingers 40 in the tube core 30 is also optimized, which can enable the current synthesis output by multiple tube cores 30 to achieve the optimal output state.

[0083] In other embodiments, FIG16 is a schematic diagram of another power amplifier provided by an embodiment of the present application. As shown in FIG16 , the length of the electrode fingers 40 of the sixth die 36 is greater than the length of the electrode fingers 40 of the seventh die 37. The microstrip line 70 includes a third microstrip line 73 electrically connected to the gate fingers 41 of the seventh die 37; and / or the microstrip line 70 includes a fourth microstrip line 74 electrically connected to the drain fingers 43 of the seventh die 37. In this embodiment, the microstrip line 70 is connected to the seventh die 37. The microstrip line 70 can be used to balance the phase difference between the output signals of the seventh die 37 and the sixth die 36, so that the final current synthesis reaches the optimal output state, thereby improving the overall electrical performance of the device.

[0084] In some embodiments, FIG17 is a schematic diagram of a circuit architecture provided by an embodiment of the present application. As shown in FIG17 , the circuit includes a first power amplifier 100 and a second power amplifier 200. The signal flow is indicated by arrows in FIG17 . The signal output end of the first power amplifier 100 is connected to the functional circuit 300, and the output end of the functional circuit 300 is connected to the signal output end of the second power amplifier 200. That is, the signal output by the first power amplifier 100 is provided to the functional circuit 300, and the signal output by the functional circuit 300 and the signal output by the second power amplifier 200 are integrated and output. The design of the embodiment of the present application can reduce the space occupied by the first power amplifier 100 and the second power amplifier 200, and arrange high-power power amplifier devices in a limited layout space. It is possible to realize other high-efficiency power amplifier architectures in the module system.

[0085] The above embodiment does not show the source lead connected to the source finger 42 in the die 30. Optionally, the source lead is grounded. In conjunction with FIG3 , the source 037 (i.e., the source finger 42) is connected to the source lead through a via extending through the substrate 031 below.

[0086] Based on the same inventive concept, embodiments of the present application further provide a radio frequency module, comprising a power amplifier provided in any embodiment of the present application. The structure of the power amplifier has been described in the above embodiments and will not be repeated here. The radio frequency module provided in embodiments of the present application may, for example, be a radio frequency front-end module.

[0087] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, comprising the radio frequency module provided in any embodiment of the present application. The electronic device may be, for example, a mobile phone, a television, a tablet computer, an e-reader, an in-vehicle display, or other terminal product.

[0088] In this specification, reference can be made to the same or similar parts between the various embodiments. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

Claims

1. A power amplifier, characterized in that: It includes a signal input terminal, a signal output terminal and a plurality of dies connected in parallel; The tube core includes electrode fingers extending along a first direction, and the electrode fingers include gate fingers, source fingers and drain fingers; in a second direction, the signal input end and the signal output end are respectively located on both sides of the plurality of tube cores, and the second direction is perpendicular to the first direction.

2. The power amplifier according to claim 1, characterized in that: The power amplifier comprises a gate lead connected to the signal input terminal and a drain lead connected to the signal output terminal, the gate finger is connected to the gate lead, and the drain finger is connected to the drain lead; The plurality of tube cores arranged along the second direction form a tube core row, and the plurality of tube cores in one tube core row share one drain lead and one gate lead.

3. The power amplifier according to claim 2, characterized in that: The row of dies is located between adjacent drain leads and gate leads.

4. The power amplifier according to claim 3, characterized in that: The power amplifier comprises at least one structure group, the structure group comprising two rows of dies adjacent to each other in the first direction; Two tube core rows in the structure group share one gate lead or one drain lead.

5. The power amplifier according to claim 4, characterized in that: The numbers of the tube cores in the two tube core rows in the structure group are equal.

6. The power amplifier according to claim 4, characterized in that: The power amplifier comprises n structure groups connected in parallel, the n structure groups are arranged along the first direction, n is a positive integer, and n≥2; The first end of the gate lead is connected to the signal input end, and the second end is connected to the gate finger. The first end of the drain lead is connected to the drain finger, and the second end is connected to the signal output end. The first ends of at least two gate leads electrically connected to two adjacent structure groups are electrically connected, and the second ends of at least two drain leads electrically connected to two adjacent structure groups are electrically connected.

7. The power amplifier according to claim 2, characterized in that: In the die row, adjacent dies share the drain fingers and / or the source fingers.

8. The power amplifier according to claim 2, characterized in that: In at least one of the tube die rows: two groups of the electrode fingers of at least two of the tube dies are staggered in the second direction.

9. The power amplifier according to claim 8, characterized in that: At least one of the tube die rows includes a first tube die, a second tube die and a third tube die, the second tube die is located between the first tube die and the third tube die, the first tube die and the second tube die are adjacent, and there are m tube die between the third tube die and the second tube die, where m is an integer and m≥0; The two groups of electrode fingers of the first tube core and the second tube core are staggered in the second direction, the two groups of electrode fingers of the second tube core and the third tube core are staggered in the second direction, and the electrode fingers of the first tube core and the electrode fingers of the third tube core are offset and staggered in the same direction relative to the electrode fingers of the second tube core.

10. The power amplifier according to claim 8, characterized in that: The power amplifier includes a microstrip line, and the microstrip line includes a first microstrip line and a second microstrip line; At least one of the tube core rows includes a fourth tube core and a fifth tube core, and two groups of the electrode fingers of the fourth tube core and the fifth tube core are staggered in the second direction; Along the first direction, the distance between the electrode finger of the fourth tube core and the drain lead is greater than the distance between the electrode finger of the fifth tube core and the drain lead; The drain fingers of the fourth tube core are electrically connected to the drain lead through the first microstrip line, and the gate fingers of the fifth tube core are electrically connected to the gate lead through the second microstrip line.

11. The power amplifier according to claim 2, characterized in that: The lengths of the electrode fingers of at least two of the plurality of tube dies are unequal.

12. The power amplifier according to claim 11, characterized in that: The plurality of tube dies include a sixth tube die and a seventh tube die, and the length of the electrode finger strip of the sixth tube die is greater than the length of the electrode finger strip of the seventh tube die; The power amplifier includes a microstrip line; The microstrip line includes a third microstrip line, and the third microstrip line is electrically connected to the gate finger of the seventh tube core; And / or, the microstrip line includes a fourth microstrip line, and the fourth microstrip line is electrically connected to the drain finger of the seventh tube core.

13. The power amplifier according to claim 1, characterized in that: The material of the power amplifier includes gallium nitride.

14. The power amplifier according to claim 1, characterized in that: The operating voltage of the power amplifier is Vo, Vo≤15V.

15. A radio frequency module, characterized in that: A power amplifier comprising the power amplifier according to any one of claims 1 to 14.

16. An electronic device, characterized in that: Including the radio frequency module described in claim 15.

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