Level converter

Abstract

The present invention is applicable to the technical field of electronics, and provides a level converter. Compared with the prior art, the level converter provided by the present invention comprises a low-voltage inverter chain, a conversion capacitor unit, a conversion protection diode unit and a conversion cross-coupling pair. The conversion capacitor unit comprises a first capacitor and a second capacitor. A first end of the first capacitor receives a second differential logic signal, and a first end of the second capacitor receives a first differential logic signal. A second end of the first capacitor and a second end of the second capacitor are respectively connected to input ends of the conversion protection diode unit. Input ends of the conversion capacitor unit comprises a first capacitor input end and a second capacitor input end. The first end of the first capacitor serves as the first capacitor input end, and the first end of the second capacitor serves as the second capacitor input end. According to the level converter of the present invention, the overall structure is simpler, power consumption is effectively reduced, and a conversion dead zone is avoided.

Description

A level converter Technical Field

[0001] The present invention is applicable to the field of electronic technology, and in particular relates to a level converter. Background Art

[0002] With the development of technology, the application and demand of level converters are increasing. As a voltage conversion device, the core function of a level converter is to achieve smooth conversion between different logic levels.

[0003] In chip design, the MOS tubes in some process design kits (PDKs) have insufficient withstand voltage, but their supply voltage is high, often exceeding the withstand voltage of the tube. For example, in a low dropout regulator (LDO), the gate of the power tube needs to be pulled up by a conductive PMOS tube when not in operation to cut off the power tube. The gate voltage of this PMOS tube must be low, but if it is used at 0 voltage, it will exceed the withstand voltage of the tube, causing damage to the tube and the entire chip to malfunction.

[0004] Therefore, a new level converter is urgently needed to convert the logic signal of the low voltage domain into the logic signal of the high voltage domain so as to realize the enabling function of the above-mentioned LDO.

[0005] Summary of the Invention

[0006] The present invention provides a level converter, which aims to solve the problem that the gate voltage of a MOS tube is unstable, which easily causes the MOS tube to be damaged and causes the chip to fail to work.

[0007] The level converter includes: a signal input terminal, a low-voltage inverter chain, a conversion capacitor unit, a conversion protection diode unit, a conversion cross-coupling pair, and a signal output terminal; the input terminal of the low-voltage inverter chain receives a control signal output from the signal input terminal, and converts the control signal into a first differential logic signal and a second differential logic signal and outputs the signals; the input terminal of the conversion capacitor unit is connected to the output terminal of the low-voltage inverter chain; the input terminal of the conversion protection diode unit is connected to the output terminal of the conversion capacitor unit; the input terminal of the conversion cross-coupling pair is connected to the output terminal of the conversion protection diode unit, and the output terminal of the conversion cross-coupling pair is connected to the signal output terminal;

[0008] The low-voltage inverter chain includes a first inverter and a second inverter connected in sequence, wherein the first output terminal of the first inverter is used to receive the control signal, the second input terminal of the first inverter is used to connect to a first inverting power supply voltage, the third input terminal of the first inverter is grounded, and the output terminal of the first inverter is used to output the first differential logic signal; the first output terminal of the second inverter is used to receive the first differential logic signal, the second input terminal of the second inverter is used to connect to the first inverting power supply voltage, the third input terminal of the second inverter is grounded, and the output terminal of the second inverter is used to output the second differential logic signal.

[0009] Preferably, the conversion capacitor unit includes a first capacitor and a second capacitor, the first end of the first capacitor serves as the first input end of the conversion capacitor unit to receive the second differential logic signal, and the first end of the second capacitor serves as the second input end of the conversion capacitor unit to receive the first differential logic signal.

[0010] Preferably, the conversion protection diode unit includes a first MOS transistor and a second MOS transistor; the second end of the first capacitor serves as the first output end of the conversion capacitor unit, and the second end of the second capacitor serves as the second output end of the conversion capacitor unit;

[0011] The gate of the first MOS transistor is connected to the second end of the first capacitor as the first input end of the conversion protection diode unit, the gate of the first MOS transistor is connected to the drain of the first MOS transistor, and the gate of the first MOS transistor is connected to the first input end of the conversion cross-coupling pair as the first output end of the conversion protection diode unit, and the source of the first MOS transistor is connected to the second input end of the conversion cross-coupling pair as the second output end of the conversion protection diode unit;

[0012] The gate of the second MOS transistor is connected to the second end of the second capacitor as the second input end of the conversion protection diode unit, the gate of the second MOS transistor is connected to the drain of the second MOS transistor, and the gate of the second MOS transistor is connected to the third input end of the conversion cross-coupling pair as the second output end of the conversion protection diode unit, and the source of the second MOS transistor is connected to the fourth input end of the conversion cross-coupling pair as the fourth output end of the conversion protection diode unit.

[0013] Preferably, the conversion cross-coupling pair includes a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor;

[0014] The gate of the third MOS transistor is connected to the drain of the fourth MOS transistor and the drain of the sixth MOS transistor respectively, and the gate of the third MOS transistor serves as the fourth input terminal of the conversion cross-coupling pair;

[0015] The gate of the fourth MOS transistor is connected to the drain of the third MOS transistor and the drain of the fifth MOS transistor respectively, and the gate of the fourth MOS transistor serves as the second input end of the conversion cross-coupling pair;

[0016] The source of the third MOS transistor and the source of the fourth MOS transistor are respectively used to connect to the first power supply voltage;

[0017] The gate of the fifth MOS transistor serves as the third input terminal of the conversion cross-coupling pair, the gate of the sixth MOS transistor serves as the first input terminal of the conversion cross-coupling pair, and the source of the fifth MOS transistor and the source of the sixth MOS transistor are respectively used to connect to the second power supply voltage.

[0018] Preferably, the first power supply voltage is VDD / 2, and the second power supply voltage is VDD.

[0019] Preferably, a first output end of the conversion cross-coupling pair is provided between the drain of the fourth MOS transistor and the drain of the sixth MOS transistor, and a second output end of the conversion cross-coupling pair is provided between the drain of the third MOS transistor and the drain of the fifth MOS transistor. The first output end of the conversion cross-coupling pair and the second output end of the conversion cross-coupling pair are respectively connected to the signal output end; the first output end of the conversion cross-coupling pair outputs a first output differential logic signal, and the second output end of the conversion cross-coupling pair outputs a second output differential logic signal.

[0020] Preferably, the voltage domain of the first output differential logic signal and the second output differential logic signal are both VDD / 2 to VDD.

[0021] Preferably, the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor and the sixth MOS transistor are PMOS transistors or NMOS transistors.

[0022] Compared with the prior art, the level converter proposed in the present invention includes a low-voltage inverter chain, a conversion capacitor unit, a conversion protection diode unit, and a conversion cross-coupling pair. The input end of the low-voltage inverter chain receives a control signal and converts the control signal into a first differential logic signal and a second differential logic signal for output; the input end of the conversion capacitor unit is connected to the output end of the low-voltage inverter chain; the input end of the conversion protection diode unit is connected to the output end of the conversion capacitor unit; the input end of the conversion cross-coupling pair is connected to the output end of the conversion protection diode unit; the conversion capacitor unit includes a first capacitor and a second capacitor, the first end of the first capacitor receives the second differential logic signal, the first end of the second capacitor receives the first differential logic signal, the second end of the first capacitor and the second end of the second capacitor are respectively connected to the input end of the conversion protection diode unit, the input end of the conversion capacitor unit includes a first capacitor input end and a second capacitor input end, the first end of the first capacitor serves as the first capacitor input end, and the first end of the second capacitor serves as the second capacitor input end. Compared with the low-voltage domain to high-voltage domain level converter in the prior art, the present invention has a simpler overall structure, effectively reduces power consumption, and avoids conversion dead zone. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made with reference to the following drawings. In the accompanying drawings:

[0024] FIG1 is a schematic diagram of a module of a level conversion device provided by an embodiment of the present invention;

[0025] FIG2 is a schematic diagram of the structure of a level converter provided by an embodiment of the present invention;

[0026] FIG3 is a timing diagram of control signal switching of a level converter provided by an embodiment of the present invention.

[0027] In the figure, 100, level converter, 10, signal input terminal, 1, low voltage inverter chain, 2, conversion capacitor unit, 3, conversion protection diode unit, 4, conversion cross-coupling pair, 20, signal output terminal. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0029] 1 to 3 , the present invention provides a level converter 100 , which includes:

[0030] A signal input terminal 10, a low-voltage inverter chain 1, a conversion capacitor unit 2, a conversion protection diode unit 3, a conversion cross-coupling pair 4, and a signal output terminal 20; the input terminal of the low-voltage inverter chain 1 receives a control signal EN, converts the control signal EN into a first differential logic signal ENB and a second differential logic signal ENA for output; the input terminal of the conversion capacitor unit 2 is connected to the output terminal of the low-voltage inverter chain 1; the input terminal of the conversion protection diode unit 3 is connected to the output terminal of the conversion capacitor unit 2; the input terminal of the conversion cross-coupling pair 4 is connected to the output terminal of the conversion protection diode unit 3, and the output terminal of the conversion cross-coupling pair 4 is connected to the signal output terminal 20;

[0031] The low-voltage inverter chain 1 includes a first inverter INV1 and a second inverter INV2 connected in sequence. The first output of the first inverter INV1 is used to receive the control signal EN, the second input of the first inverter INV1 is used to connect to a first inverting power supply voltage, the third input of the first inverter INV1 is grounded, and the output of the first inverter INV1 is used to output the first differential logic signal ENB. The first output of the second inverter INV2 is used to receive the first differential logic signal ENB, the second input of the second inverter INV2 is used to connect to the first inverting power supply voltage, the third input of the second inverter INV2 is grounded, and the output of the second inverter INV2 is used to output the second differential logic signal ENA. Specifically, the first inverting power supply voltage is VDD / 2, the control signal EN of the low-voltage inverter chain 1 has a voltage range of 0 to VDD / 2, and the output voltage ranges of the first differential logic signal ENB and the second differential logic signal ENA are 0 to VDD / 2.

[0032] In an embodiment of the present invention, the conversion capacitor unit 2 includes a first capacitor C1 and a second capacitor C2, the first end of the first capacitor C1 serves as the first input end of the conversion capacitor unit 2 to receive the second differential logic signal ENA, and the first end of the second capacitor C2 serves as the second input end of the conversion capacitor unit 2 to receive the first differential logic signal ENB.

[0033] Specifically, the present invention utilizes the characteristic that the voltage across capacitors cannot change suddenly. When the first differential logic signal ENB and the second differential logic signal ENA vary within the voltage range of 0 to VDD / 2, the voltage at the second ends of the first capacitor C1 and the capacitor C2 will vary between VDD / 2 and VDD, causing the cross-coupling pair 4 to switch the output signal. To prevent excessive voltage changes at the second ends of the first capacitor C1 and the second capacitor C2 due to leakage, the capacitance of the first capacitor C1 and the second capacitor C2 must be large.

[0034] In the embodiment of the present invention, the conversion protection diode unit 3 includes a first MOS transistor M1 and a second MOS transistor M2; the second end of the first capacitor C1 serves as the first output end of the conversion capacitor unit 2, and the second end of the second capacitor C2 serves as the second output end of the conversion capacitor unit 2.

[0035] The gate of the first MOS transistor M1 is connected to the second end of the first capacitor C1 as the first input end of the conversion protection diode unit 3, the gate of the first MOS transistor M1 is connected to the drain of the first MOS transistor M1, and the gate of the first MOS transistor M1 is connected to the first input end of the conversion cross-coupling pair 4 as the first output end of the conversion protection diode unit 3, and the source of the first MOS transistor M1 is connected to the second input end of the conversion cross-coupling pair 4 as the second output end of the conversion protection diode unit 3;

[0036] The gate of the second MOS transistor M2 is connected to the second end of the second capacitor C2 as the second input end of the conversion protection diode unit 3, the gate of the second MOS transistor M2 is connected to the drain of the second MOS transistor M2, and the gate of the second MOS transistor M2 is connected to the third input end of the conversion cross-coupling pair 4 as the second output end of the conversion protection diode unit 3, and the source of the second MOS transistor M2 is connected to the fourth input end of the conversion cross-coupling pair 4 as the fourth output end of the conversion protection diode unit 3.

[0037] In the embodiment of the present invention, the conversion cross-coupling pair 4 includes a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5 and a sixth MOS transistor M6;

[0038] The gate of the third MOS transistor M3 is connected to the drain of the fourth MOS transistor M4 and the drain of the sixth MOS transistor M6 respectively, and the gate of the third MOS transistor M3 serves as the fourth input terminal of the conversion cross-coupling pair 4;

[0039] The gate of the fourth MOS transistor M4 is connected to the drain of the third MOS transistor M3 and the drain of the fifth MOS transistor M5 respectively, and the gate of the fourth MOS transistor M4 serves as the second input end of the conversion cross-coupling pair 4;

[0040] The source of the third MOS transistor M3 and the source of the fourth MOS transistor M4 are respectively used to connect to the first power supply voltage;

[0041] The gate of the fifth MOS transistor M5 serves as the third input terminal of the conversion cross-coupling pair 4, the gate of the sixth MOS transistor M6 serves as the first input terminal of the conversion cross-coupling pair 4, and the source of the fifth MOS transistor M5 and the source of the sixth MOS transistor M6 are respectively used to connect to the second power supply voltage.

[0042] In an embodiment of the present invention, the voltage of the first power supply voltage is VDD / 2, and the voltage of the second power supply voltage is VDD.

[0043] In the embodiment of the present invention, a first output terminal of the conversion cross-coupling pair 4 is provided between the drain of the fourth MOS transistor M4 and the drain of the sixth MOS transistor M6, and a second output terminal of the conversion cross-coupling pair 4 is provided between the drain of the third MOS transistor M3 and the drain of the fifth MOS transistor M5. The first output terminal and the second output terminal of the conversion cross-coupling pair 4 are respectively connected to the signal output terminal 20. The first output terminal of the conversion cross-coupling pair 4 outputs a first output differential logic signal ENB_H, and the second output terminal of the conversion cross-coupling pair 4 outputs a second output differential logic signal ENA_H.

[0044] In an embodiment of the present invention, a voltage range of the first output differential logic signal ENB_H and the second output differential logic signal ENA_H is VDD / 2 to VDD.

[0045] Specifically, when the level shifter 100 is in a steady state, for example, when the voltage of the control signal EN is VDD / 2, the voltage of the second differential logic signal ENA is VDD / 2, and the voltage of the first differential logic signal ENB is 0, to ensure that the level shifter 100 can successfully perform a level shift when the control signal EN changes from high to low, the voltage at the second end of the first capacitor C1 should be close to VDD, and the voltage at the second end of the second capacitor C2 should be close to VDD / 2. Because no current flows through the first MOS transistor M1 and the second MOS transistor M2 when the level shifter 100 is in a steady state, the gate voltage of the first MOS transistor M1 and the gate-source voltage of the second MOS transistor M2 are very small. At this time, the source voltage of the first MOS transistor M1 is VDD, and the source voltage of the second MOS transistor M2 is VDD / 2.

[0046] When the control signal EN changes from VDD / 2 to 0, the voltage at the second end of the second capacitor C2 changes from VDD / 2 to VDD, the voltage at the second end of the first capacitor C1 and the source of the first MOS transistor M1 change from VDD to VDD / 2, the gates of the third MOS transistor M3 and the fifth MOS transistor M5 change simultaneously, forming push-pull amplification, and the second output differential logic signal ENA_H switches rapidly. The second end of the second capacitor C2 and the source of the second MOS transistor M2 change from VDD / 2 to VDD, the gates of the fourth MOS transistor M4 and the sixth MOS transistor M6 also change simultaneously, and the first output differential logic signal ENB_H also switches rapidly, avoiding a conversion dead zone.

[0047] In the embodiment of the present invention, the first MOS transistor M1 , the second MOS transistor M2 , the third MOS transistor M3 , the fourth MOS transistor M4 , the fifth MOS transistor M5 , and the sixth MOS transistor M6 are PMOS transistors or NMOS transistors.

[0048] In the embodiment of the present invention, the structure of the conversion cross-coupling pair 4 can be changed according to specific circumstances, as long as it can complete its function.

[0049] In the embodiment of the present invention, the number of inverters INV in the low-voltage inverter chain 1 may be changed according to specific circumstances, as long as differential signals can be provided.

[0050] FIG3 is a timing diagram of the switching of the control signal EN. As shown in FIG3 , when the voltage of the control signal EN changes from 0 to VDD / 2 at time T1, the voltage at the second end (A in the figure) of the first capacitor C1 changes from VDD / 2 to VDD, causing the sixth MOS transistor M6 to turn off and the fourth MOS transistor M4 to turn on, and the voltage of the first output differential logic signal ENB_H to change from VDD to VDD / 2; the voltage at the second end (B in the figure) of the second capacitor C2 changes from VDD to VDD / 2, causing the third MOS transistor M3 to turn off and the fifth MOS transistor M5 to turn on, and the voltage of the second output differential logic signal ENA_H to change from VDD / 2 to VDD;

[0051] Compared with the prior art, the level converter proposed in the present invention includes a low-voltage inverter chain, a conversion capacitor unit, a conversion protection diode unit, and a conversion cross-coupling pair. The input end of the low-voltage inverter chain receives a control signal and converts the control signal into a first differential logic signal and a second differential logic signal for output; the input end of the conversion capacitor unit is connected to the output end of the low-voltage inverter chain; the input end of the conversion protection diode unit is connected to the output end of the conversion capacitor unit; the input end of the conversion cross-coupling pair is connected to the output end of the conversion protection diode unit; the conversion capacitor unit includes a first capacitor and a second capacitor, the first end of the first capacitor receives the second differential logic signal, the first end of the second capacitor receives the first differential logic signal, the second end of the first capacitor and the second end of the second capacitor are respectively connected to the input end of the conversion protection diode unit, the input end of the conversion capacitor unit includes a first capacitor input end and a second capacitor input end, the first end of the first capacitor serves as the first capacitor input end, and the first end of the second capacitor serves as the second capacitor input end. Compared with the low-voltage domain to high-voltage domain level converter in the prior art, the present invention has a simpler overall structure, effectively reduces power consumption, and avoids conversion dead zone.

[0052] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0053] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only a preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A level converter, characterized in that: include: A signal input terminal, a low-voltage inverter chain, a conversion capacitor unit, a conversion protection diode unit, a conversion cross-coupling pair, and a signal output terminal; the input terminal of the low-voltage inverter chain receives the control signal output by the signal input terminal, and converts the control signal into a first differential logic signal and a second differential logic signal and outputs them; the input terminal of the conversion capacitor unit is connected to the output terminal of the low-voltage inverter chain; the input terminal of the conversion protection diode unit is connected to the output terminal of the conversion capacitor unit; the input terminal of the conversion cross-coupling pair is connected to the output terminal of the conversion protection diode unit, and the output terminal of the conversion cross-coupling pair is connected to the signal output terminal; The low voltage inverter chain comprises a first inverter and a second inverter connected in sequence, wherein the first output terminal of the first inverter is used to receive the control signal, the second input terminal of the first inverter is used to connect to a first inverting power supply voltage, the third input terminal of the first inverter is grounded, and the output terminal of the first inverter is used to output the first differential logic signal; The first output terminal of the second inverter is used to receive the first differential logic signal, the second input terminal of the second inverter is used to connect to the first inverting power supply voltage, the third input terminal of the second inverter is grounded, and the output terminal of the second inverter is used to output the second differential logic signal.

2. The level converter according to claim 1, wherein: The conversion capacitor unit includes a first capacitor and a second capacitor. The first end of the first capacitor serves as the first input end of the conversion capacitor unit to receive the second differential logic signal. The first end of the second capacitor serves as the second input end of the conversion capacitor unit to receive the first differential logic signal.

3. The level converter according to claim 2, wherein: The conversion protection diode unit includes a first MOS tube and a second MOS tube; the second end of the first capacitor serves as the first output end of the conversion capacitor unit, and the second end of the second capacitor serves as the second output end of the conversion capacitor unit; The gate of the first MOS transistor is connected to the second end of the first capacitor as the first input end of the conversion protection diode unit, and the gate of the first MOS transistor is connected to the drain of the first MOS transistor. The gate of the first MOS transistor is connected as the first output end of the conversion protection diode unit to the first input end of the conversion cross-coupling pair, and the source of the first MOS transistor is connected as the second output end of the conversion protection diode unit to the second input end of the conversion cross-coupling pair; The gate of the second MOS transistor is connected to the second end of the second capacitor as the second input end of the conversion protection diode unit, the gate of the second MOS transistor is connected to the drain of the second MOS transistor and the gate of the second MOS transistor is connected to the third input end of the conversion cross-coupling pair as the second output end of the conversion protection diode unit, and the source of the second MOS transistor is connected to the fourth input end of the conversion cross-coupling pair as the fourth output end of the conversion protection diode unit.

4. The level converter according to claim 3, wherein: The conversion cross-coupling pair includes a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor; The gate of the third MOS tube is connected to the drain of the fourth MOS tube and the drain of the sixth MOS tube respectively, and the gate of the third MOS tube serves as the fourth input terminal of the conversion cross-coupling pair; The gate of the fourth MOS tube is connected to the drain of the third MOS tube and the drain of the fifth MOS tube respectively, and the gate of the fourth MOS tube serves as the second input end of the conversion cross-coupling pair; The source of the third MOS tube and the source of the fourth MOS tube are respectively used to connect to the first power supply voltage; The gate of the fifth MOS transistor serves as the third input terminal of the conversion cross-coupling pair, the gate of the sixth MOS transistor serves as the first input terminal of the conversion cross-coupling pair, and the source of the fifth MOS transistor and the source of the sixth MOS transistor are respectively used to connect to the second power supply voltage.

5. The level converter according to claim 4, wherein: The voltage of the first power supply voltage is VDD / 2, and the voltage of the second power supply voltage is VDD.

6. The level converter according to claim 5, wherein: A first output end of the conversion cross-coupling pair is provided between the drain of the fourth MOS tube and the drain of the sixth MOS tube, a second output end of the conversion cross-coupling pair is provided between the drain of the third MOS tube and the drain of the fifth MOS tube, the first output end of the conversion cross-coupling pair and the second output end of the conversion cross-coupling pair are respectively connected to the signal output end; the first output end of the conversion cross-coupling pair outputs a first output differential logic signal, and the second output end of the conversion cross-coupling pair outputs a second output differential logic signal.

7. The level converter according to claim 6, wherein: The voltage domains of the first output differential logic signal and the second output differential logic signal are both VDD / 2 to VDD.

8. The level converter according to claim 4, wherein: The first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube and the sixth MOS tube are PMOS tubes or NMOS tubes.

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