Network card device and data transmission system

Abstract

The present application relates to the field of data processing, and disclosed are a network card device and a data transmission system, which are used for solving the problem whereby data transmission occupies the access bandwidth of a host memory. The network card device comprises a storage module; a descriptor queue address register; a calculation high-speed link hard core module, which is used for transmitting data sent by a host to a first data storage area, transmitting a descriptor sent by the host to a first descriptor storage area, and transmitting a trigger instruction sent by the host to a network data processing module; and the network data processing module, which is used for acquiring a base address from the descriptor queue address register when receiving the trigger instruction, reading a target descriptor in the first descriptor storage area based on the base address and the trigger instruction, reading target data corresponding to the target descriptor in the first data storage area, and outputting the target data to a network. The present application can reserve the access bandwidth of a host memory for other functions running on the host to use, so that the overall operation efficiency of the host is improved.

Description

Network card device and data transmission system

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on November 29, 2023, with application number 202311616379.4 and application name “A network card device and data transmission system”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of data processing, and in particular to a network card device and a data transmission system. Background Art

[0004] As a device that requires high-speed data processing, a network interface card (NIC) is typically connected to the host CPU (Central Processing Unit) via the PCIe (Peripheral Component Interconnect Express) bus. During data transmission through the NIC, the host CPU first writes the data to host memory. The data is then read from the host memory to the NIC via the PCIe link, and then sent to the network. This means that each data transfer involves two accesses to host memory, consuming host memory access bandwidth. Furthermore, host memory is shared by multiple CPU cores. Excessive memory bandwidth usage by one processor core or device can affect the performance of other cores.

[0005] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. Summary of the Invention

[0006] The purpose of this application is to provide a network card device and a data transmission system, which can reserve the access bandwidth of the host memory for other functions running on the host, thereby improving the overall operating efficiency of the host.

[0007] To solve the above technical problems, the present application provides a network card device, including:

[0008] A storage module, the storage module including a first descriptor storage area and a first data storage area;

[0009] A descriptor queue address register, configured to store a base address of a first descriptor storage area;

[0010] A computing high-speed link hard core module, configured to receive data and descriptors sent by the host through a computing high-speed link memory protocol, receive a trigger instruction sent by the host through a computing high-speed link enumeration configuration protocol, and transmit the data sent by the host to the first data storage area, transmit the descriptor sent by the host to the first descriptor storage area, and transmit the trigger instruction sent by the host to the network data processing module;

[0011] The network data processing module is used to obtain a base address from the descriptor queue address register when a trigger instruction is received, read the target descriptor in the first descriptor storage area based on the base address and the trigger instruction, read the target data corresponding to the target descriptor in the first data storage area, and output the target data to the network.

[0012] In some exemplary embodiments, the network card device further includes:

[0013] a direct memory access module, configured to read a target descriptor from the first descriptor storage area according to the received read address, read target data corresponding to the target descriptor from the first data storage area, and send the target data to the network data processing module;

[0014] The network data processing module is specifically used to obtain the base address from the descriptor queue address register when a trigger instruction is received, and calculate the read address of the target descriptor based on the base address and the trigger instruction, send the read address to the direct memory access module, obtain the target data sent by the direct memory access module, and output it to the network.

[0015] In some exemplary embodiments, the process of obtaining target data sent by the direct memory access module and outputting it to the network includes:

[0016] Get the target data sent by the direct memory access module;

[0017] When the target data meets the output conditions, the target data is output to the network.

[0018] In some exemplary embodiments, the output condition is that the actual length of the target data is consistent with the target length in the target descriptor.

[0019] In some exemplary embodiments, the trigger instruction includes a descriptor number;

[0020] When a trigger instruction is received, a base address is obtained from the descriptor queue address register, and a process of reading a target descriptor in the first descriptor storage area based on the base address and the trigger instruction includes:

[0021] When a trigger instruction is received, the descriptor number in the trigger instruction is parsed, a target address is calculated based on the descriptor number and the base address, and the target descriptor in the first descriptor storage area is read according to the target address.

[0022] In some exemplary embodiments, the base address includes a first flag bit, and the host memory of the host includes a second descriptor storage area and a second data storage area;

[0023] The network data processing module is further configured to determine a target descriptor storage area and a target data storage area according to the first flag bit; the target descriptor storage area is the first descriptor storage area or the second descriptor storage area, and the target data storage area is the first data storage area or the second data storage area;

[0024] When a trigger instruction is received, a base address is obtained from the descriptor queue address register, a target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction, and target data corresponding to the target descriptor in the first data storage area is read. The process includes:

[0025] When a trigger instruction is received, the base address is obtained from the descriptor queue address register, and when the target descriptor storage area and the target data storage area are determined to be the first descriptor storage area and the first data storage area based on the first flag bit in the base address, the target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction, and the target data corresponding to the target descriptor is read in the first data storage area.

[0026] In some exemplary embodiments, the network data processing module is also used to obtain a base address from a descriptor queue address register when a trigger instruction is received, and when the target descriptor storage area and the target data storage area are determined to be the second descriptor storage area and the second data storage area based on the first flag bit in the base address, read the target descriptor in the second descriptor storage area based on the base address and the trigger instruction, and read the target data corresponding to the target descriptor in the second data storage area.

[0027] In some exemplary embodiments, the process of determining the target descriptor storage area and the target data storage area according to the first flag bit includes:

[0028] When the first flag bit is a first preset value, determining the target descriptor storage area to be the first descriptor storage area, and determining the target data storage area to be the first data storage area;

[0029] When the first flag bit is the second preset value, the target descriptor storage area is determined to be the second descriptor storage area, and the target data storage area is determined to be the second data storage area.

[0030] In some exemplary embodiments, the base address includes a first flag bit, the descriptor includes a second flag bit, and the host memory of the host includes a second descriptor storage area and a second data storage area;

[0031] The network data processing module is further configured to determine a target descriptor storage area and a target data storage area according to the first flag bit and the second flag bit; the target descriptor storage area is the first descriptor storage area or the second descriptor storage area, and the target data storage area is the first data storage area or the second data storage area;

[0032] When a trigger instruction is received, a base address is obtained from the descriptor queue address register, a target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction, and target data corresponding to the target descriptor in the first data storage area is read. The process includes:

[0033] When a trigger instruction is received, the base address is obtained from the descriptor queue address register. When the target descriptor storage area is determined to be the first descriptor storage area based on the first flag bit in the base address, the target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction. When the target data storage area is determined to be the first data storage area based on the second flag bit in the target descriptor, the target data corresponding to the target descriptor is read in the first data storage area.

[0034] In some exemplary embodiments, the network data processing module is also used to obtain a base address from a descriptor queue address register when a trigger instruction is received; when the target descriptor storage area is determined to be the second descriptor storage area based on the first flag bit in the base address, read the target descriptor in the second descriptor storage area based on the base address and the trigger instruction; when the target data storage area is determined to be the first data storage area based on the second flag bit in the target descriptor, read the target data corresponding to the target descriptor in the first data storage area.

[0035] In some exemplary embodiments, the network data processing module is also used to obtain a base address from a descriptor queue address register when a trigger instruction is received; when the target descriptor storage area is determined to be the second descriptor storage area based on the first flag bit in the base address, read the target descriptor in the second descriptor storage area based on the base address and the trigger instruction; when the target data storage area is determined to be the second data storage area based on the second flag bit in the target descriptor, read the target data corresponding to the target descriptor in the second data storage area.

[0036] In some exemplary embodiments, the network data processing module is also used to obtain a base address from a descriptor queue address register when a trigger instruction is received, determine that the target descriptor storage area is the first descriptor storage area based on the first flag bit in the base address, read the target descriptor in the first descriptor storage area based on the base address and the trigger instruction, determine that the target data storage area is the second data storage area based on the second flag bit in the target descriptor, and read the target data corresponding to the target descriptor in the second data storage area.

[0037] In some exemplary embodiments, the process of determining the target descriptor storage area and the target data storage area according to the first flag bit and the second flag bit includes:

[0038] When the first flag bit is a first preset value, determining that the target descriptor storage area is the first descriptor storage area;

[0039] When the first flag bit is a second preset value, determining that the target descriptor storage area is a second descriptor storage area;

[0040] When the second flag bit is a third preset value, determining that the target data storage area is the first data storage area;

[0041] When the second flag bit is a fourth preset value, it is determined that the target data storage area is the second data storage area.

[0042] In some exemplary embodiments, the first preset value and the third preset value are the same, and the second preset value and the fourth preset value are the same.

[0043] In some exemplary embodiments, the descriptor includes a data address and a data length, and the data address of the descriptor in the first descriptor storage area is a physical address inside the storage module calculated based on the global physical address.

[0044] In some exemplary embodiments, the memory module is a double data rate synchronous dynamic random access memory.

[0045] In some exemplary embodiments, the network card device further includes:

[0046] A memory mapping configuration module is used to store the number of transceiver queues and the number of interrupts supported by the network data processing module;

[0047] The high-speed link hard core module is used to transmit the number of transceiver queues and the number of interrupts to the host, so that the host can divide the first data storage area and the first descriptor storage area in the storage module according to the number of received queues and the number of interrupts.

[0048] In some exemplary embodiments, the network card device further includes:

[0049] Mode enable register, used to store function trigger value;

[0050] The high-speed link calculation hard core module is also used to transfer the function trigger value sent by the host to the mode enable register;

[0051] When the function trigger value is the fifth preset value, the network data processing module is disabled, and when the function trigger value is the sixth preset value, the network data processing module is enabled.

[0052] To solve the above technical problems, the present application also provides a data transmission system, comprising:

[0053] Host, used to send data, send descriptors, and send trigger instructions;

[0054] At least one network card device as described above.

[0055] In some exemplary embodiments, the host is further configured to initialize the network card device when the network card device is connected to the host.

[0056] The present application also provides a network card device, including: a storage module, the storage module includes a first descriptor storage area and a first data storage area; a descriptor queue address register, used to store the base address of the first descriptor storage area; a computing high-speed link hard core module, used to receive data and descriptors sent by the host through the computing high-speed link memory protocol, receive trigger instructions sent by the host through the computing high-speed link enumeration configuration protocol, and transfer the data sent by the host to the first data storage area, transfer the descriptor sent by the host to the first descriptor storage area, and transfer the trigger instruction sent by the host to the network data processing module; the network data processing module is used to obtain the base address from the descriptor queue address register when receiving the trigger instruction, read the target descriptor in the first descriptor storage area based on the base address and the trigger instruction, read the target data corresponding to the target descriptor in the first data storage area, and output the target data to the network.

[0057] In actual applications, by using the network card device of the present application, the host can directly write the data and the descriptors corresponding to the data into the local storage module of the network card device through the calculation of the high-speed link hard core module. The network data processing module directly accesses the local storage module, reads the descriptors and data and sends them to the network without accessing the host memory, thereby leaving the access bandwidth of the host memory for other functions running on the host, thereby improving the overall operating efficiency of the host.

[0058] The present application also provides a data transmission system having the same beneficial effects as the above-mentioned network card device. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0060] FIG1 is a schematic structural diagram of a network card device provided by the present application;

[0061] FIG2 is a schematic structural diagram of another network card device provided by the present application;

[0062] FIG3 is a schematic diagram of the structure of another network card device provided by the present application;

[0063] FIG4 is a schematic diagram of the structure of another network card device provided by the present application;

[0064] FIG5 is a schematic structural diagram of a data transmission system provided in this application. DETAILED DESCRIPTION

[0065] The core of this application is to provide a network card device and a data transmission system, which can reserve the access bandwidth of the host memory for other functions running on the host, thereby improving the overall operating efficiency of the host.

[0066] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0067] In the present application, each module and each unit is a device component with specific functions formed by at least one processor, circuit, component, or a combination thereof.

[0068] In the first aspect, referring to FIG1 and FIG2 , the network card device includes:

[0069] Storage module 1, storage module 1 includes a first descriptor storage area and a first data storage area;

[0070] Descriptor queue address register 2, used to store the base address of the first descriptor storage area;

[0071] The computing high-speed link hard core module 3 is configured to receive data and descriptors sent by the host through the computing high-speed link memory protocol, receive a trigger instruction sent by the host through the computing high-speed link enumeration configuration protocol, transfer the data sent by the host to the first data storage area, transfer the descriptor sent by the host to the first descriptor storage area, and transfer the trigger instruction sent by the host to the network data processing module 4;

[0072] The network data processing module 4 is used to obtain the base address from the descriptor queue address register 2 when a trigger instruction is received, read the target descriptor in the first descriptor storage area based on the base address and the trigger instruction, read the target data corresponding to the target descriptor in the first data storage area, and output the target data to the network.

[0073] It can be understood that the Compute Express Link (CXL) protocol-supported hard-core module in the network card device is connected to the host via the PCIe bus. The host can communicate with the Compute Express Link module of the network card device through CXL.io and CXL.mem. The CXL.io protocol is an enumeration configuration protocol, primarily used for device discovery and enumeration, error reporting, etc. The CXL.mem protocol enables the host to access device memory as if it were its own local memory. In the CXL.mem protocol, the host CPU acts as the master device, sending requests, while the device acts as the slave device to reply. Requests are categorized as requests with data or without data, and responses are categorized as responses with data or without data.

[0074] Before data is transmitted through the network card device, this embodiment further includes allocating a segment of memory with a continuous physical address in the storage module 1 of the network card device as a first descriptor storage area through the network card driver on the host, which is used to store the descriptor queue, and writing the base address of this segment of memory into the descriptor queue address register 2 of the network card device by calculating the high-speed link hard core module 3. The descriptor queue includes at least one descriptor. For the same network card device, the data format of each descriptor is the same. For different network card devices, the data format of the descriptor can be the same or different. The descriptor includes at least two pieces of information, namely, the address of the data storage area where the data to be sent is located and the length of the data.

[0075] When transmitting data through the network card, the host's network card driver will first apply for a first data storage area with a continuous physical address in the storage module 1 of the network card device, and write the data to be sent into the first data storage area through the calculation of the high-speed link hard core module 3. Then the host's network card driver will select a descriptor, generally starting from the first descriptor in sequence, and generate a trigger instruction based on the selected descriptor, and send it to the network data processing module 4 in the network device through the calculation of the high-speed link hard core module 3. After receiving the trigger instruction, the network data processing module 4 calculates the address of the descriptor selected by the host in the first descriptor storage area according to the trigger instruction and the base address stored in the descriptor queue address register 2, and then reads the target descriptor from the first descriptor storage area based on the address, and reads the corresponding target data from the first data storage area according to the data address and data length corresponding to the target descriptor, and transmits the target data to the network. In this embodiment, the high-speed link hard core module 3 calculates the descriptor queue and the data to be output and writes them into the local memory of the network card device in advance, so that the network data processing module 4 can directly access the local storage memory without accessing the host memory. On the one hand, this improves the data transmission efficiency, and on the other hand, it can leave the access bandwidth of the host memory for other functions running on the host, thereby improving the overall operation efficiency of the host.

[0076] 3 , which is a schematic diagram of the structure of another network card device provided by the present application, the network card device further includes:

[0077] External interface module;

[0078] A memory-mapped configuration module that stores CXL-supported DVSEC (Designated Vendor-Specific Extended Capability) and CDAT (Coherent Device Attribute Table) tables.

[0079] Memory mapping I / O, which is part of the PCI (Peripheral Component Interconnect, a computer bus standard) specification, places I / O devices in memory space instead of I / O space.

[0080] The memory-mapped input / output module connects the command interface, which is used to configure and manage the device and present partition information and event logs to the software, to the HDM (Host-managed Device Memory) decoder. The HDM decoder determines the mapping between the host physical address (HPA) and the device physical address (DPA), and writes the corresponding data sent by the host to the corresponding address in the storage module 1.

[0081] MAC (Media Access Control) has one end connected to the network data processing module 4 and another end connected to a network cable, so as to output the target data output by the network data processing module 4 to the network through the network cable.

[0082] It can be understood that the PCIe-supported computing high-speed link hard core module 3 used in this embodiment can be shared by the network data transmission function and the extended memory function of the network card device, thereby saving the logic resources of the FPGA (Field Programmable Gate Array) used to build the network card device.

[0083] It can be seen that in this embodiment, the host can directly write the data and the descriptors corresponding to the data into the local storage module 1 of the network card device by calculating the high-speed link hard core module 3, and the network data processing module 4 directly accesses the local storage module 1, reads the descriptors and data and sends them to the network without accessing the host memory, thereby leaving the access bandwidth of the host memory for other functions running on the host, thereby improving the overall operating efficiency of the host.

[0084] As some embodiments of the present application, please refer to FIG3 , the network card device further includes:

[0085] a direct memory access module 5 for reading a target descriptor from the first descriptor storage area according to the received read address, reading target data corresponding to the target descriptor from the first data storage area, and sending the target data to the network data processing module 4;

[0086] The network data processing module 4 is specifically used to obtain the base address from the descriptor queue address register 2 when a trigger instruction is received, and calculate the read address of the target descriptor based on the base address and the trigger instruction, and send the read address to the direct memory access module 5, and obtain the target data sent by the direct memory access module 5 and output it to the network.

[0087] As some embodiments of the present application, the process of obtaining target data sent by the direct memory access module 5 and outputting it to the network includes:

[0088] Obtain target data sent by direct memory access module 5;

[0089] When the target data meets the output conditions, the target data is output to the network.

[0090] As some embodiments of the present application, the output condition is that the actual length of the target data is consistent with the target length in the target descriptor.

[0091] In this embodiment, the network card device also includes a direct memory access module 5. After the network data processing module 4 determines the read address of the target descriptor, it can send the read address to the direct memory access module 5. The direct memory access module 5 then performs data migration in the local memory, moving the target data corresponding to the target descriptor to the network data processing module 4. When the network data processing module 4 determines that the length of the target data sent by the direct memory access module 5 is consistent with the data length of the target descriptor, it sends the target data to the network. Having the direct memory access module 5 perform the data migration task allows the network data processing module 4 to handle other tasks, thereby improving the operating efficiency of the network card device.

[0092] As some embodiments of the present application, the trigger instruction includes a descriptor number;

[0093] When a trigger instruction is received, a base address is obtained from the descriptor queue address register 2, and a process of reading a target descriptor in the first descriptor storage area based on the base address and the trigger instruction includes:

[0094] When a trigger instruction is received, the descriptor number in the trigger instruction is parsed, a target address is calculated based on the descriptor number and the base address, and the target descriptor in the first descriptor storage area is read according to the target address.

[0095] In this embodiment, the descriptor number is used to determine the descriptor to be processed currently selected by the host. Assuming that the Nth descriptor in the descriptor queue is selected, the descriptor number is N. After the network data processing module 4 receives the descriptor number, it calculates the address of the Nth descriptor, that is, the target address, based on the base address of the descriptor queue plus N multiplied by the length of each descriptor.

[0096] 4 , as some embodiments of the present application, the base address includes a first flag bit, and the host memory of the host includes a second descriptor storage area and a second data storage area;

[0097] The network data processing module 4 is also used to determine the target descriptor storage area and the target data storage area according to the first flag bit, so as to read the target descriptor from the target descriptor storage area and read the target data corresponding to the target descriptor from the target data storage area; the target descriptor storage area is the first descriptor storage area or the second descriptor storage area, and the target data storage area is the first data storage area or the second data storage area.

[0098] As some embodiments of the present application, when a trigger instruction is received, a base address is obtained from the descriptor queue address register 2, a target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction, and a process of reading target data corresponding to the target descriptor in the first data storage area includes:

[0099] When a trigger instruction is received, the base address is obtained from the descriptor queue address register 2. When the target descriptor storage area and the target data storage area are determined to be the first descriptor storage area and the first data storage area based on the first flag bit in the base address, the target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction, and the target data corresponding to the target descriptor is read in the first data storage area.

[0100] As some embodiments of the present application, the network data processing module 4 is also used to obtain a base address from the descriptor queue address register 2 when a trigger instruction is received, and when the target descriptor storage area and the target data storage area are determined to be the second descriptor storage area and the second data storage area based on the first flag bit in the base address, read the target descriptor in the second descriptor storage area based on the base address and the trigger instruction, and read the target data corresponding to the target descriptor in the second data storage area.

[0101] As some embodiments of the present application, a process of determining a target descriptor storage area and a target data storage area according to the first flag bit includes:

[0102] When the first flag bit is a first preset value, determining the target descriptor storage area to be the first descriptor storage area, and determining the target data storage area to be the first data storage area;

[0103] When the first flag bit is the second preset value, the target descriptor storage area is determined to be the second descriptor storage area, and the target data storage area is determined to be the second data storage area.

[0104] In order to prevent the network card device from reading descriptors and data to be transmitted in the host memory through the PCIe bus, a first flag is set in the base address in this embodiment. According to the value of the first flag, it can be determined whether the descriptor queue is stored in the host memory or the local memory of the network card device. If the value of the first flag is a first preset value, the descriptor queue and the data to be transmitted are both in the local memory of the network card device. If the value of the first flag is a second preset value, the descriptor queue and the data to be transmitted are both in the host memory of the network card device.

[0105] It can be understood that the descriptor queue and the data to be transmitted are both stored in the host memory of the network card device, and the network data processing module 4 moves the data from the host memory through the direct memory access module 5. The moving process is described above and will not be repeated here.

[0106] 4 , as some embodiments of the present application, the base address includes a first flag bit, the descriptor includes a second flag bit, and the host memory of the host includes a second descriptor storage area and a second data storage area;

[0107] The network data processing module 4 is further configured to determine a target descriptor storage area and a target data storage area according to the first flag bit and the second flag bit, so as to read the target descriptor from the target descriptor storage area and read the target data corresponding to the target descriptor from the target data storage area; the target descriptor storage area is the first descriptor storage area or the second descriptor storage area, and the target data storage area is the first data storage area or the second data storage area;

[0108] As some embodiments of the present application, when a trigger instruction is received, a base address is obtained from the descriptor queue address register 2, a target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction, and a process of reading target data corresponding to the target descriptor in the first data storage area includes:

[0109] When a trigger instruction is received, the base address is obtained from the descriptor queue address register 2. When the target descriptor storage area is determined to be the first descriptor storage area based on the first flag bit in the base address, the target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction. When the target data storage area is determined to be the first data storage area based on the second flag bit in the target descriptor, the target data corresponding to the target descriptor is read in the first data storage area.

[0110] As some embodiments of the present application, the network data processing module 4 is also used to obtain a base address from the descriptor queue address register 2 when a trigger instruction is received, and when the target descriptor storage area is determined to be the second descriptor storage area based on the first flag bit in the base address, read the target descriptor in the second descriptor storage area based on the base address and the trigger instruction, and when the target data storage area is determined to be the first data storage area based on the second flag bit in the target descriptor, read the target data corresponding to the target descriptor in the first data storage area.

[0111] As some embodiments of the present application, the network data processing module 4 is also used to obtain a base address from the descriptor queue address register 2 when a trigger instruction is received, and when the target descriptor storage area is determined to be the second descriptor storage area based on the first flag bit in the base address, read the target descriptor in the second descriptor storage area based on the base address and the trigger instruction, and when the target data storage area is determined to be the second data storage area based on the second flag bit in the target descriptor, read the target data corresponding to the target descriptor in the second data storage area.

[0112] As some embodiments of the present application, the network data processing module 4 is also used to obtain a base address from the descriptor queue address register 2 when a trigger instruction is received, and when the target descriptor storage area is determined to be the first descriptor storage area based on the first flag bit in the base address, read the target descriptor in the first descriptor storage area based on the base address and the trigger instruction, determine the target data storage area to be the second data storage area based on the second flag bit in the target descriptor, and read the target data corresponding to the target descriptor in the second data storage area.

[0113] As some embodiments of the present application, a process of determining a target descriptor storage area and a target data storage area according to a first flag bit and a second flag bit includes:

[0114] When the first flag bit is a first preset value, determining that the target descriptor storage area is the first descriptor storage area;

[0115] When the first flag bit is a second preset value, determining that the target descriptor storage area is a second descriptor storage area;

[0116] When the second flag bit is a third preset value, determining that the target data storage area is the first data storage area;

[0117] When the second flag bit is a fourth preset value, it is determined that the target data storage area is the second data storage area.

[0118] As some embodiments of the present application, the first preset value is the same as the third preset value, and the second preset value is the same as the fourth preset value.

[0119] In this embodiment, in addition to setting the first flag bit in the base address, a second flag bit is also set in the descriptor. According to the values ​​of the first flag bit and the second flag bit, it can be determined whether the descriptor queue and the data to be transmitted are stored in the local memory and / or the host memory. Assuming that the first flag bit in the base address is the first preset value and the second flag bit in the descriptor is the third preset value, the target descriptor and the data to be transmitted are read from the local memory. Assuming that the first flag bit in the base address is the second preset value and the second flag bit in the descriptor is the fourth preset value, the target descriptor and the data to be transmitted are read from the host memory through the direct memory access module 5. Assuming that the first flag bit in the base address is the first preset value and the second flag bit in the descriptor is the third preset value, the target descriptor is read in the local memory and the data to be transmitted is read from the host memory through the direct memory access module 5. Assuming that the first flag bit in the base address is the second preset value and the second flag bit in the descriptor is the third preset value, the target descriptor is read from the host memory through the direct memory access module 5 and the data to be transmitted is read from the local memory.

[0120] As some embodiments of the present application, the descriptor includes a data address and a data length, and the data address of the descriptor in the first descriptor storage area is a physical address inside the storage module 1 calculated based on the global physical address.

[0121] When the network card driver fills the address of the data cache into the descriptor queue, it needs to fill in the physical address inside the device calculated from the global physical address so that the network data processing module 4 in the device can access the local memory device.

[0122] As some embodiments of the present application, the storage module 1 is a double data rate synchronous dynamic random access memory.

[0123] As some embodiments of the present application, the network card device further includes:

[0124] A memory mapping configuration module, used to store the number of transceiver queues and the number of interrupts supported by the network data processing module 4;

[0125] The high-speed link calculation hard core module 3 is used to transmit the number of transceiver queues and the number of interrupts to the host, so that the host can divide the first data storage area and the first descriptor storage area in the storage module 1 according to the number of received queues and the number of interrupts.

[0126] As some embodiments of the present application, the network card device further includes:

[0127] Mode enable register, used to store function trigger value;

[0128] The high-speed link calculation hard core module 3 is further configured to transmit the storage function trigger value sent by the host to the mode enable register;

[0129] When the function trigger value is the fifth preset value, the network data processing module 4 is disabled; and when the function trigger value is the sixth preset value, the network data processing module 4 is enabled.

[0130] It is understood that the network card device in this embodiment can simultaneously implement the extended memory function and the network data transmission function, or can independently implement the extended memory function or independently implement the network data transmission function. By setting a mode enable register in the network card device, the host can enable or disable different functions of the network card device by writing different values ​​to the mode enable register. For the host's operating system, if the network card device is used as CXL extended memory, only the existing CXL driver module is loaded without loading any network card driver. If it is used as a normal network card, it is necessary not to load the relevant CXL driver (or to set the device to be invalid after loading the driver) and only load the network card driver.

[0131] In summary, the present application supports devices with both CXL extended memory and network card functions, that is, one of the functions can be used separately by software configuration, or they can be used simultaneously, which improves the utilization rate of the device and reduces the cost of purchasing the device. When the network card device of the present application uses the network card function to send and receive network data, the allocated descriptor list and data cache are located in the device's own DDR (Double Data Rate) processor (added to the operating system as CXL extended memory), avoiding frequent access to the host memory, freeing up the host memory bandwidth for use by other processor cores, and improving the overall operating efficiency of the system.

[0132] In the second aspect, please refer to FIG5 , which is a schematic diagram of the structure of a data transmission system provided by this application, including:

[0133] Host 31, used to send data, send descriptors, and send trigger instructions;

[0134] At least one network card device 32 as described above.

[0135] As some embodiments of the present application, the host 31 is further configured to initialize the network card device 32 when the network card device 32 is connected to itself.

[0136] Among them, the host 31 includes a computing high-speed link port, a memory controller and a processor core. When the computing high-speed link hard-core module of the network card device 32 is normally connected to the computing high-speed link port of the host 31 through the PCIe bus that supports the CXL protocol, an initialization operation is performed on the Linux operating system of the host 31, including creating a new NUMA (Non Uniform Memory Access) node, and setting the CXL extended memory and the network card (as a PCIe device) to this NUMA node. In the data sending process, when the operating system network protocol stack applies for memory (to store data) for the network card, it will automatically allocate physical memory belonging to the same NUMA node for it. According to the design of this application, it is CXL extended memory (located on the same device as the network card). When writing the network card driver, whether it is applying for memory for the descriptor or applying for cache for the received data, it is necessary to ensure that the applied physical memory and the network card belong to the same NUMA node. To prevent the NIC from reading descriptors and data caches from host 31 memory through the PCIe bus as in conventional solutions, a flag bit negotiated in advance by the software and hardware needs to be set in each descriptor. The software sets the hardware read bit to ensure that the NIC hardware directly accesses the memory processor (DDR) inside the device. When obtaining the NIC configuration (such as the number of queues), the NIC driver no longer reads the configuration from the ordinary PCIe configuration space, but instead reads it from the CXL.io configuration space. When filling in the data cache address in the descriptor, the NIC driver needs to fill in the device's internal physical address calculated from the global physical address, so that the network processing logic in the device can access the device memory.

[0137] For scenarios where the network driver is not Linux (an operating system kernel) but DPDK (Data Plane Development Kit, a software library and driver set) network implementation, the initialization operation includes reserving huge pages in the system to ensure that they belong to the same NUMA node as the device. That is, when the application requests huge pages in the future, it uses the memory extended by the CXL device. When DPDK is started, it is set in the parameters to use huge pages when requesting memory and descriptors. When writing the DPDK driver, support the second item. When writing the DPDK driver and filling in the data cache address in the descriptor, it is necessary to fill in the physical address inside the device calculated from the global physical address so that the network processing logic in the device can access the device memory.

[0138] The network card device 32 includes:

[0139] A storage module, the storage module including a first descriptor storage area and a first data storage area;

[0140] A descriptor queue address register, configured to store a base address of a first descriptor storage area;

[0141] A high-speed link computing hard core module is configured to transmit data sent by the host 31 to the first data storage area, transmit descriptors sent by the host 31 to the first descriptor storage area, and transmit trigger instructions sent by the host 31 to the network data processing module;

[0142] The network data processing module is used to obtain a base address from the descriptor queue address register when a trigger instruction is received, read the target descriptor in the first descriptor storage area based on the base address and the trigger instruction, read the target data corresponding to the target descriptor in the first data storage area, and output the target data to the network.

[0143] As some embodiments of the present application, the network card device 32 further includes:

[0144] a direct memory access module, configured to read a target descriptor from the first descriptor storage area according to the received read address, read target data corresponding to the target descriptor from the first data storage area, and send the target data to the network data processing module;

[0145] The network data processing module is specifically used to obtain the base address from the descriptor queue address register when a trigger instruction is received, and calculate the read address of the target descriptor based on the base address and the trigger instruction, send the read address to the direct memory access module, obtain the target data sent by the direct memory access module, and output it to the network.

[0146] As some embodiments of the present application, the process of obtaining target data sent by the direct memory access module and outputting it to the network includes:

[0147] Get the target data sent by the direct memory access module;

[0148] When the target data meets the output conditions, the target data is output to the network.

[0149] As some embodiments of the present application, the output condition is that the actual length of the target data is consistent with the target length in the target descriptor.

[0150] As some embodiments of the present application, the trigger instruction includes a descriptor number;

[0151] When a trigger instruction is received, a base address is obtained from the descriptor queue address register, and a process of reading a target descriptor in the first descriptor storage area based on the base address and the trigger instruction includes:

[0152] When a trigger instruction is received, the descriptor number in the trigger instruction is parsed, a target address is calculated based on the descriptor number and the base address, and the target descriptor in the first descriptor storage area is read according to the target address.

[0153] As some embodiments of the present application, the base address includes a first flag bit, and the host 31 memory of the host 31 includes a second descriptor storage area and a second data storage area;

[0154] The network data processing module is further configured to determine a target descriptor storage area and a target data storage area according to the first flag bit; the target descriptor storage area is the first descriptor storage area or the second descriptor storage area, and the target data storage area is the first data storage area or the second data storage area;

[0155] When a trigger instruction is received, a base address is obtained from the descriptor queue address register, a target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction, and target data corresponding to the target descriptor in the first data storage area is read. The process includes:

[0156] When a trigger instruction is received, the base address is obtained from the descriptor queue address register, and when the target descriptor storage area and the target data storage area are determined to be the first descriptor storage area and the first data storage area based on the first flag bit in the base address, the target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction, and the target data corresponding to the target descriptor is read in the first data storage area.

[0157] As some embodiments of the present application, the network data processing module is also used to obtain a base address from a descriptor queue address register when a trigger instruction is received, and when the target descriptor storage area and the target data storage area are determined to be the second descriptor storage area and the second data storage area based on the first flag bit in the base address, read the target descriptor in the second descriptor storage area based on the base address and the trigger instruction, and read the target data corresponding to the target descriptor in the second data storage area.

[0158] As some embodiments of the present application, a process of determining a target descriptor storage area and a target data storage area according to the first flag bit includes:

[0159] When the first flag bit is a first preset value, determining the target descriptor storage area to be the first descriptor storage area, and determining the target data storage area to be the first data storage area;

[0160] When the first flag bit is the second preset value, the target descriptor storage area is determined to be the second descriptor storage area, and the target data storage area is determined to be the second data storage area.

[0161] As some embodiments of the present application, the base address includes a first flag bit, the trigger instruction includes a descriptor number, the descriptor number includes a second flag bit, and the host 31 memory of the host 31 includes a second descriptor storage area and a second data storage area;

[0162] The network data processing module is further configured to determine a target descriptor storage area and a target data storage area according to the first flag bit and the second flag bit; the target descriptor storage area is the first descriptor storage area or the second descriptor storage area, and the target data storage area is the first data storage area or the second data storage area;

[0163] When a trigger instruction is received, a base address is obtained from the descriptor queue address register, a target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction, and target data corresponding to the target descriptor in the first data storage area is read. The process includes:

[0164] When a trigger instruction is received, the base address is obtained from the descriptor queue address register. When the target descriptor storage area is determined to be the first descriptor storage area based on the first flag bit in the base address, the target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction. When the target data storage area is determined to be the first data storage area based on the second flag bit in the target descriptor, the target data corresponding to the target descriptor is read in the first data storage area.

[0165] As some embodiments of the present application, the network data processing module is also used to obtain a base address from a descriptor queue address register when a trigger instruction is received, and when the target descriptor storage area is determined to be the second descriptor storage area based on the first flag bit in the base address, read the target descriptor in the second descriptor storage area based on the base address and the trigger instruction, and when the target data storage area is determined to be the first data storage area based on the second flag bit in the target descriptor, read the target data corresponding to the target descriptor in the first data storage area.

[0166] As some embodiments of the present application, the network data processing module is also used to obtain a base address from a descriptor queue address register when a trigger instruction is received, and when the target descriptor storage area is determined to be the second descriptor storage area based on the first flag bit in the base address, read the target descriptor in the second descriptor storage area based on the base address and the trigger instruction, and when the target data storage area is determined to be the second data storage area based on the second flag bit in the target descriptor, read the target data corresponding to the target descriptor in the second data storage area.

[0167] As some embodiments of the present application, the network data processing module is also used to obtain a base address from a descriptor queue address register when a trigger instruction is received, determine that the target descriptor storage area is the first descriptor storage area based on the first flag bit in the base address, read the target descriptor in the first descriptor storage area based on the base address and the trigger instruction, determine that the target data storage area is the second data storage area based on the second flag bit in the target descriptor, and read the target data corresponding to the target descriptor in the second data storage area.

[0168] As some embodiments of the present application, a process of determining a target descriptor storage area and a target data storage area according to a first flag bit and a second flag bit includes:

[0169] When the first flag bit is a first preset value, determining that the target descriptor storage area is the first descriptor storage area;

[0170] When the first flag bit is a second preset value, determining that the target descriptor storage area is a second descriptor storage area;

[0171] When the second flag bit is a third preset value, determining that the target data storage area is the first data storage area;

[0172] When the second flag bit is a fourth preset value, it is determined that the target data storage area is the second data storage area.

[0173] As some embodiments of the present application, the first preset value is the same as the third preset value, and the second preset value is the same as the fourth preset value.

[0174] As some embodiments of the present application, the descriptor includes a data address and a data length, and the data address of the descriptor in the first descriptor storage area is a physical address inside the storage module calculated based on the global physical address.

[0175] As some embodiments of the present application, the storage module is a double data rate synchronous dynamic random access memory.

[0176] As some embodiments of the present application, the network card device 32 further includes:

[0177] A memory mapping configuration module is used to store the number of transceiver queues and the number of interrupts supported by the network data processing module;

[0178] The high-speed link calculation hard core module is used to transmit the number of transceiver queues and the number of interrupts to the host 31, so that the host 31 divides the first data storage area and the first descriptor storage area in the storage module according to the number of received queues and the number of interrupts.

[0179] As some embodiments of the present application, the network card device 32 further includes:

[0180] Mode enable register, used to store function trigger value;

[0181] The computing high-speed link hard core module is further configured to transmit the storage function trigger value sent by the host 31 to the mode enable register;

[0182] When the function trigger value is the fifth preset value, the network data processing module is disabled, and when the function trigger value is the sixth preset value, the network data processing module is enabled.

[0183] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0184] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A network card device, characterized in that: include: A storage module, the storage module comprising a first descriptor storage area and a first data storage area; a descriptor queue address register configured to store a base address of the first descriptor storage area; A computing high-speed link hard core module is configured to receive data and descriptors sent by a host through a computing high-speed link memory protocol, receive a trigger instruction sent by the host through a computing high-speed link enumeration configuration protocol, and transmit the data sent by the host to the first data storage area, transmit the descriptor sent by the host to the first descriptor storage area, and transmit the trigger instruction sent by the host to the network data processing module; The network data processing module is configured to obtain the base address from the descriptor queue address register when receiving the trigger instruction, read the target descriptor in the first descriptor storage area based on the base address and the trigger instruction, read the target data corresponding to the target descriptor in the first data storage area, and output the target data to the network.

2. The network card device according to claim 1, characterized in that: The network card device also includes: a direct memory access module, configured to read a target descriptor in the first descriptor storage area according to a received read address, read target data corresponding to the target descriptor in the first data storage area, and send the target data to the network data processing module; The network data processing module is specifically configured to obtain the base address from the descriptor queue address register when receiving the trigger instruction, calculate the read address of the target descriptor based on the base address and the trigger instruction, send the read address to the direct memory access module, obtain the target data sent by the direct memory access module, and output it to the network.

3. The network card device according to claim 2, characterized in that: The process of obtaining the target data sent by the direct memory access module and outputting it to the network includes: Acquire the target data sent by the direct memory access module; When the target data meets the output condition, the target data is output to the network.

4. The network card device according to claim 3, characterized in that: The output condition is that the actual length of the target data is consistent with the target length in the target descriptor.

5. The network card device according to claim 1, characterized in that: The trigger instruction includes a descriptor number; When the trigger instruction is received, the base address is obtained from the descriptor queue address register, and the process of reading the target descriptor in the first descriptor storage area based on the base address and the trigger instruction includes: When the trigger instruction is received, the descriptor number in the trigger instruction is parsed, a target address is calculated based on the descriptor number and the base address, and a target descriptor in the first descriptor storage area is read according to the target address.

6. The network card device according to claim 1, characterized in that: The base address includes a first flag bit, and the host memory of the host includes a second descriptor storage area and a second data storage area; The network data processing module is further configured to determine a target descriptor storage area and a target data storage area according to the first flag bit, so as to read a target descriptor from the target descriptor storage area and read target data corresponding to the target descriptor from the target data storage area; The target descriptor storage area is the first descriptor storage area or the second descriptor storage area, and the target data storage area is the first data storage area or the second data storage area.

7. The network card device according to claim 6, characterized in that: The process of, when receiving the trigger instruction, obtaining the base address from the descriptor queue address register, reading the target descriptor in the first descriptor storage area based on the base address and the trigger instruction, and reading the target data corresponding to the target descriptor in the first data storage area includes: When the trigger instruction is received, the base address is obtained from the descriptor queue address register, and when the target descriptor storage area and the target data storage area are determined to be the first descriptor storage area and the first data storage area based on the first flag bit in the base address, the target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction, and the target data corresponding to the target descriptor is read in the first data storage area.

8. The network card device according to claim 6, characterized in that: The network data processing module is also configured to, upon receiving the trigger instruction, obtain the base address from the descriptor queue address register, and upon determining based on the first flag bit in the base address that the target descriptor storage area and the target data storage area are the second descriptor storage area and the second data storage area, read the target descriptor in the second descriptor storage area based on the base address and the trigger instruction, and read the target data corresponding to the target descriptor in the second data storage area.

9. The network card device according to claim 6, characterized in that: The process of determining the target descriptor storage area and the target data storage area according to the first flag bit includes: When the first flag bit is a first preset value, determining the target descriptor storage area to be the first descriptor storage area, and determining the target data storage area to be the first data storage area; When the first flag bit is a second preset value, the target descriptor storage area is determined to be the second descriptor storage area, and the target data storage area is determined to be the second data storage area.

10. The network card device according to claim 1, characterized in that: The base address includes a first flag bit, the descriptor includes a second flag bit, and the host memory of the host includes a second descriptor storage area and a second data storage area; The network data processing module is further configured to determine a target descriptor storage area and a target data storage area according to the first flag bit and the second flag bit, so as to read a target descriptor from the target descriptor storage area and read target data corresponding to the target descriptor from the target data storage area; The target descriptor storage area is the first descriptor storage area or the second descriptor storage area, and the target data storage area is the first data storage area or the second data storage area.

11. The network card device according to claim 10, characterized in that: The process of, when receiving the trigger instruction, obtaining the base address from the descriptor queue address register, reading the target descriptor in the first descriptor storage area based on the base address and the trigger instruction, and reading the target data corresponding to the target descriptor in the first data storage area includes: When the trigger instruction is received, the base address is obtained from the descriptor queue address register; when the target descriptor storage area is determined to be the first descriptor storage area based on the first flag bit in the base address, the target descriptor in the first descriptor storage area is read based on the base address and the trigger instruction; when the target data storage area is determined to be the first data storage area based on the second flag bit in the target descriptor, the target data corresponding to the target descriptor is read in the first data storage area.

12. The network card device according to claim 10, characterized in that: The network data processing module is also configured to, upon receiving the trigger instruction, obtain the base address from the descriptor queue address register, upon determining that the target descriptor storage area is the second descriptor storage area based on the first flag bit in the base address, read the target descriptor in the second descriptor storage area based on the base address and the trigger instruction, and upon determining that the target data storage area is the first data storage area based on the second flag bit in the target descriptor, read the target data corresponding to the target descriptor in the first data storage area.

13. The network card device according to claim 10, characterized in that: The network data processing module is also configured to, upon receiving the trigger instruction, obtain the base address from the descriptor queue address register; upon determining that the target descriptor storage area is the second descriptor storage area based on the first flag bit in the base address, read the target descriptor in the second descriptor storage area based on the base address and the trigger instruction; and upon determining that the target data storage area is the second data storage area based on the second flag bit in the target descriptor, read the target data corresponding to the target descriptor in the second data storage area.

14. The network card device according to claim 10, characterized in that: The network data processing module is also configured to, upon receiving the trigger instruction, obtain the base address from the descriptor queue address register, determine that the target descriptor storage area is the first descriptor storage area based on the first flag bit in the base address, read the target descriptor in the first descriptor storage area based on the base address and the trigger instruction, determine that the target data storage area is the second data storage area based on the second flag bit in the target descriptor, and read the target data corresponding to the target descriptor in the second data storage area.

15. The network card device according to claim 10, characterized in that: The process of determining the target descriptor storage area and the target data storage area according to the first flag bit and the second flag bit includes: When the first flag bit is a first preset value, determining that the target descriptor storage area is the first descriptor storage area; When the first flag bit is a second preset value, determining that the target descriptor storage area is the second descriptor storage area; When the second flag bit is a third preset value, determining that the target data storage area is the first data storage area; When the second flag bit is a fourth preset value, it is determined that the target data storage area is the second data storage area.

16. The network card device according to claim 1, characterized in that: The descriptor includes a data address and a data length, and the data address of the descriptor in the first descriptor storage area is a physical address inside the storage module calculated based on a global physical address.

17. The network card device according to claim 1, characterized in that: The network card device also includes: A memory mapping configuration module, configured to store the number of transceiver queues and the number of interrupts supported by the network data processing module; The computing high-speed link hard core module is configured to transmit the number of the transceiver queues and the number of the interrupts to the host so that the host divides the first data storage area and the first descriptor storage area in the storage module according to the number of the received queues and the number of the interrupts.

18. The network card device according to any one of claims 1 to 17, characterized in that: The network card device also includes: A mode enable register configured to store a function trigger value; The computing high-speed link hard core module is also configured to transmit the function trigger value sent by the host to the mode enable register; When the function trigger value is the fifth preset value, the network data processing module is not enabled, and when the function trigger value is the sixth preset value, the network data processing module is enabled.

19. A data transmission system, characterized in that: include: The host is configured to send data, send descriptors, and send trigger commands; At least one network card device as claimed in any one of claims 1-18.

20. The data transmission system according to claim 19, characterized in that: The host is further configured to perform an initialization operation on the network card device when the network card device is connected to the host.

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