Drive circuit, and memory device and operation method therefor

Abstract

The present disclosure provides a drive circuit, and a memory device and an operation method therefor. The drive circuit comprises a first control circuit, a current-limiting circuit and a second control circuit, which are coupled, wherein the first control circuit is configured to transmit, when turned on, a current-limiting operation signal on a current-limiting operation signal line to the current-limiting circuit; the current-limiting circuit is configured to apply, under the control of the current-limiting operation signal, a first operation signal to a load signal line connected to an output end of the drive circuit; and the second control circuit is configured to control, when turned on, the current-limiting circuit to stop applying the first operation signal to the load signal line on the basis of a feedback signal from the load signal line. The drive circuit can reduce power consumption.

Description

Driving circuit, memory device and operating method thereof

[0001] This application claims priority to Chinese Patent Application No. 202311591237.7 filed on November 27, 2023 and Chinese Patent Application No. 202311595907.2 filed on November 27, 2023, and the contents of the above-mentioned Chinese patent application disclosures are hereby incorporated by reference in their entirety as part of this application. Technical Field

[0002] The present disclosure relates to a driving circuit, a memory device, and an operating method thereof. Background Art

[0003] Resistive Random Access Memory (RRAM) is a nonvolatile memory device whose conductivity state can be modulated by applying an external stimulus. It can record and store data based on changes in resistance and features high speed, low power consumption, and a compact size. RRAM has promising applications in fields such as artificial intelligence, neural networks, and memory, and has attracted increasing attention from both academia and industry. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a driving circuit, which includes: a coupled first control circuit, a current limiting circuit, and a second control circuit, wherein the first control circuit is configured to transmit a current limiting operation signal on a current limiting operation signal line to the current limiting circuit when it is turned on; the current limiting circuit is configured to apply a first operation signal to a load signal line connected to an output end of the driving circuit under the control of the current limiting operation signal; and the second control circuit is configured to control the current limiting circuit to stop applying the first operation signal to the load signal line according to a feedback signal from the load signal line when it is turned on.

[0005] For example, in the driving circuit provided by at least one embodiment of the present disclosure, the first control circuit is connected to a first voltage source and a second voltage source, and is configured to receive a first control signal from the first voltage source, receive the current limiting operation signal from the second voltage source, and be turned on or off according to the first control signal, and apply the current limiting operation signal to the first node when turned on; the current limiting circuit is connected to the first control circuit, the third voltage source and the output end, and is configured to be turned on or off according to the level of the first node, and is turned on when the level of the first node is the current limiting operation signal to apply the first operation voltage of the first operation signal received from the third voltage source to the output end; the second control circuit is connected to the output end, the third voltage source and the current limiting circuit, and is configured to be turned on or off according to the feedback signal of the output end, and apply the first operation voltage to the first node when turned on, so that the current limiting circuit is turned off when the level of the first node is the first operation voltage.

[0006] For example, in the driving circuit provided in at least one embodiment of the present disclosure, the first control circuit includes a first transistor, the control electrode of the first transistor is connected to the first voltage source, and the first electrode of the first transistor is connected to the second voltage source; the current limiting circuit includes a second transistor, the control electrode of the second transistor is connected to the second electrode of the first transistor, the first electrode of the second transistor is connected to the third voltage source, and the second electrode of the second transistor is connected to the output end; the second control circuit includes a third transistor, the control electrode of the third transistor is connected to the output end, the first electrode of the third transistor is connected to the third voltage source, and the second electrode of the third transistor is connected to the control electrode of the second transistor.

[0007] For example, in the driving circuit provided in at least one embodiment of the present disclosure, the first transistor, the second transistor, and the third transistor are P-type transistors.

[0008] For example, in the driving circuit provided in at least one embodiment of the present disclosure, when the operating mode of the driving circuit is the self-stop mode, the first control circuit is configured to be turned on according to a first control signal to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit; the current limiting circuit is configured to be turned on according to the current limiting voltage to apply the first operation signal to the load signal line connected to the output end of the driving circuit; the second control circuit is configured to be turned on according to a second control signal to transmit the second operation signal to the current limiting circuit, and control the current limiting circuit to stop applying the first operation signal to the load signal line according to the second operation signal and a feedback signal from the load signal line.

[0009] For example, in the driving circuit provided in at least one embodiment of the present disclosure, the operating mode of the driving circuit also includes a shutdown mode and a current limiting mode. In the shutdown mode, the first control circuit is configured to be turned on according to the first control signal to transmit the shutdown voltage on the current limiting operation signal line to the current limiting circuit to cut off the current limiting circuit; in the current limiting mode, the first control circuit is configured to be turned on according to the first control signal to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit, and the current limiting circuit is configured to limit the current on the load signal line to no higher than a preset current according to the current limiting voltage, and the second control circuit is configured to be cut off according to the second control signal.

[0010] For example, in the driving circuit provided in at least one embodiment of the present disclosure, the current limiting circuit receives the first operating signal through a first operating signal line, and the second control circuit receives the second operating signal through a second operating signal line, or the current limiting circuit and the second control circuit receive the first operating signal and the second operating signal through the same operating signal line, wherein the voltages of the first operating signal and the second operating signal are the same.

[0011] For example, in the driving circuit provided in at least one embodiment of the present disclosure, the second control circuit includes a feedback switching circuit and a sampling circuit, the feedback switching circuit is configured to be turned on or off according to the second control signal to turn on or off the second control circuit, and the sampling circuit is configured to control the current limiting circuit to stop applying the first operation signal to the load signal line according to the feedback signal and the second operation signal when turned on.

[0012] For example, in the driving circuit provided in at least one embodiment of the present disclosure, the first control circuit includes a first switch component, the current limiting circuit includes a second transistor, the sampling circuit includes a third transistor, and the feedback switch circuit includes a fourth transistor. The first end of the first switch component is connected to the first voltage source through the current limiting operation signal line; the control electrode of the second transistor is connected to the second end of the first switch component, the first electrode of the second transistor is connected to the third voltage source to receive the first operation signal, and the second electrode of the second transistor is connected to the load signal line; the control electrode of the fourth transistor is connected to the fifth voltage source to receive the second control signal, the first electrode of the fourth transistor is connected to the fourth voltage source to receive the second operation signal, and the second electrode of the fourth transistor is connected to the first electrode of the third transistor; the control electrode of the third transistor is connected to the load signal line, the first electrode of the third transistor is connected to the second electrode of the fourth transistor to receive the second operation signal, and the second electrode of the third transistor is connected to the control electrode of the second transistor.

[0013] For example, in the driving circuit provided in at least one embodiment of the present disclosure, the first control circuit includes a first switch component, the current limiting circuit includes a second transistor, the sampling circuit includes a third transistor, and the feedback switch circuit includes a fourth transistor. The first end of the first switch component is connected to the first voltage source through the current limiting operation signal line; the control electrode of the second transistor is connected to the second end of the first switch component, the first electrode of the second transistor is connected to the third voltage source to receive the first operation signal, and the second electrode of the second transistor is connected to the load signal line; the control electrode of the fourth transistor is connected to the fifth voltage source to receive the second control signal, the first electrode of the fourth transistor is connected to the second electrode of the third transistor, and the second electrode of the fourth transistor is connected to the control electrode of the second transistor; the control electrode of the third transistor is connected to the load signal line, and the first electrode of the third transistor is connected to the fourth voltage source to receive the second operation signal.

[0014] For example, in the driving circuit provided in at least one embodiment of the present disclosure, the first switching component includes a first N-type transistor and a first P-type transistor, and the driving strength of the first N-type transistor and / or the first P-type transistor and the third transistor jointly determines the threshold voltage for turning off the driving circuit; or, the first switching component includes only the first N-type transistor, and the driving strength of the first N-type transistor and the third transistor jointly determines the threshold voltage for turning off the driving circuit; or, the first switching component includes only the first P-type transistor, and the driving strength of the first P-type transistor and the third transistor jointly determines the threshold voltage for turning off the driving circuit.

[0015] At least one embodiment of the present disclosure further provides a memory device, comprising a drive circuit and a resistive memory device, wherein the drive circuit comprises a coupled first control circuit, a current limiting circuit, and a second control circuit, wherein the first control circuit is configured to transmit a current limiting operation signal on a current limiting operation signal line to the current limiting circuit when the first control circuit is turned on; the current limiting circuit is configured to apply a first operation signal to a load signal line connected to an output end of the drive circuit under control of the current limiting operation signal; and the second control circuit is configured to control the current limiting circuit to stop applying the first operation signal to the load signal line according to a feedback signal from the load signal line when the second control circuit is turned on, wherein the first end of the resistive memory device is connected to the output end of the drive circuit, and the second end of the resistive memory device is connected to a sixth voltage source.

[0016] At least one embodiment of the present disclosure also provides an operating method for a memory device, the operating method comprising: applying a first control signal to the first control circuit to turn on the first control circuit, and applying a current limiting operation signal to the current limiting circuit through the first control circuit to turn on the current limiting circuit, thereby applying a first operating voltage to the resistive memory device connected to the output end of the driving circuit through the current limiting circuit; wherein, the second control circuit is turned on according to a feedback signal on a load signal line connected to the resistive memory device, thereby controlling the current limiting circuit to stop applying the first operating voltage to the load signal line.

[0017] For example, in the operating method provided in at least one embodiment of the present disclosure, the first operating voltage includes an initialization voltage or a set voltage for the resistive memory device.

[0018] For example, the operating method provided by at least one embodiment of the present disclosure further includes: changing the resistance value of the resistive memory device according to the first operating voltage.

[0019] For example, in the operating method provided in at least one embodiment of the present disclosure, the feedback voltage of the feedback signal changes corresponding to the change in the resistance value of the resistive memory device. When the resistance value of the resistive memory device reaches the target resistance value, the feedback voltage reaches a first threshold voltage to turn on the second control circuit.

[0020] For example, the operating method provided by at least one embodiment of the present disclosure further includes: determining the current limiting voltage of the current limiting operation signal according to the target resistance value of the resistive memory device.

[0021] At least one embodiment of the present disclosure also provides a memory device, which includes: one or more memory arrays, each of the memory arrays including one or more columns of memory cells and one or more bit lines respectively connected to the one or more columns of memory cells; a driving module including one or more driving circuits, each of the driving circuits including a coupled first control circuit, a current limiting circuit, and a second control circuit, wherein the first control circuit is configured to transmit a current limiting operation signal on a current limiting operation signal line to the current limiting circuit when turned on; the current limiting circuit is configured to apply a first operation signal to a bit line connected to an output end of the driving circuit under control of the current limiting operation signal; and the second control circuit is configured to control the current limiting circuit to stop applying the first operation signal to the bit line according to a feedback signal from the bit line when turned on.

[0022] For example, in the memory device provided in at least one embodiment of the present disclosure, the output ends of the one or more driving circuits are respectively connected to the one or more bit lines; or, the output ends of the one or more driving circuits are connected to the selected one or more bit lines through the column selection switch circuit; or, the output ends of the one or more driving circuits are respectively connected to the one or more bit lines of the selected memory array in the one or more memory arrays through the array selection switch circuit; or, the output ends of the one or more driving circuits are respectively connected to the selected one or more bit lines in the selected memory array through the array selection switch circuit and the column selection switch circuit.

[0023] At least one embodiment of the present disclosure further provides an operating method for a memory device, wherein the memory device includes one or more memory arrays and a driving module, each of the memory arrays includes one or more columns of memory cells and one or more bit lines respectively connected to the one or more columns of memory cells; the driving module includes one or more driving circuits, each of the driving circuits includes a coupled first control circuit, a current limiting circuit, and a second control circuit, and the operating method includes: in a self-stop mode, applying a first control signal to the driving module to turn on the one or more first control circuits in the driving module, thereby transmitting the current limiting operation signal on the current limiting operation signal line to the current limiting circuit in the turned-on driving circuit; applying a current limiting voltage to the current limiting operation signal line to turn on the current limiting circuit in the turned-on driving circuit, thereby applying the first operation signal to the memory cell connected to the bit line; applying a second control signal to turn on the second control circuit in the turned-on driving circuit, thereby controlling the current limiting circuit to stop applying the first operation signal to the bit line according to the feedback signal on the bit line through the second control circuit.

[0024] For example, the operating method provided by at least one embodiment of the present disclosure also includes: in the shutdown mode, applying the first control signal to turn on the first control circuit, applying the shutdown voltage to the current limiting operation signal line, thereby cutting off the current limiting circuit; or, in the current limiting mode, applying the first control signal to turn on the first control circuit, applying the current limiting voltage to the current limiting operation signal line, limiting the current on the bit line to no higher than a preset current according to the current limiting voltage through the current limiting circuit, and applying the second control signal to cut off the second control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0026] FIG1 is a schematic structural diagram of an exemplary resistive memory device provided by at least one embodiment of the present disclosure;

[0027] FIG2 is a schematic structural diagram of an exemplary storage unit provided by at least one embodiment of the present disclosure;

[0028] FIG3 is a schematic block diagram of a driving circuit provided by at least one embodiment of the present disclosure;

[0029] FIG4 is a schematic structural diagram of an exemplary driving circuit provided by at least one embodiment of the present disclosure;

[0030] FIG5 is a schematic structural diagram of an exemplary memory device provided by at least one embodiment of the present disclosure;

[0031] FIG6 is a schematic structural diagram of an exemplary memory device provided by at least one embodiment of the present disclosure;

[0032] FIG7A is a schematic block diagram of a driving circuit provided by at least one embodiment of the present disclosure;

[0033] 7B-7D are schematic structural diagrams of another exemplary driving circuit provided by at least one embodiment of the present disclosure;

[0034] FIG8 is a timing diagram of a driving circuit provided by at least one embodiment of the present disclosure in different operating modes;

[0035] 9A-9C are schematic structural diagrams of an exemplary memory device according to at least one embodiment of the present disclosure; and

[0036] 10A-10C are schematic structural diagrams of an exemplary memory device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0038] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0039] The present disclosure is described below using several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numeral in each drawing.

[0040] Resistive memory devices are considered to be a potential new type of non-volatile memory due to their fast read and write speed, simple structure and good compatibility with CMOS processes. They have been widely used in information storage, logical operations and neural network computing.

[0041] FIG1 shows a schematic structural diagram of an exemplary resistive memory device. As shown in FIG1 , the resistive memory device R1 includes a resistive layer 111 and an upper electrode 113 and a lower electrode 114 located on both sides, and in at least one example, may further include a functional layer 112. The functional layer 112 is an optional layer, and whether to add it or not may be determined based on the optimization direction of the performance of the resistive memory device R1, and may be designed accordingly. The resistive layer 111 may, for example, be a single layer, including a single type of binary metal oxide (such as NiO, AlOx, etc.), graphene oxide, multi-element perovskite oxide (such as STO, SZO, PCMO, etc.), or it may be a multilayer, such as any optional stack of the above materials, such as a stack of TixN and AlOx.

[0042] Resistive memory devices can store data based on resistance switching characteristics. The resistance switching characteristics of resistive memory devices are related to the conductive filaments. By applying a set voltage or a reset voltage between the upper and lower electrodes of the resistive memory device, the conductive filaments inside the resistive memory device can be restored or broken. When the conductive filaments are connected, the resistive memory device exhibits a low resistance state (Low Resistance State, LRS). At this time, the resistive memory device can be used to store data 0, for example; when the conductive filaments are broken, the resistive memory device exhibits a high resistance state (High Resistance State, HRS). At this time, the resistive memory device can be used to store data 1, for example.

[0043] For example, after a conductive filament is formed inside the resistive memory device R1, the resistive memory device R1 has an operating threshold voltage. When the amplitude of the input voltage applied between the upper electrode 113 and the lower electrode 114 of the resistive memory device R1 is less than the operating threshold voltage of the resistive memory device R1, the resistance value (or conductance value) of the resistive memory device R1 will not change. In this case, the current storage value of the resistive memory device can be read by applying a read voltage to the resistive memory device. The current storage value of the resistive memory device can be, for example, the resistance value of the resistive memory device. The read voltage is less than the operating threshold voltage of the resistive memory device.

[0044] When the amplitude of the input voltage applied between the upper electrode 113 and the lower electrode 114 of the resistive memory device R1 is greater than the operating threshold voltage of the resistive memory device R1, the resistance value (or conductance value) of the resistive memory device R1 can be changed according to the set voltage or reset voltage applied between the upper electrode 113 and the lower electrode 114 of the resistive memory device R1. For example, the set voltage is a positive voltage pulse, and the reset voltage is a negative voltage pulse. In the embodiment of the present disclosure, applying a set voltage to the resistive memory device is referred to as a set operation, and applying a reset voltage to the resistive memory device is referred to as a reset operation. A set operation or a reset operation can be used as a write operation. In the actual application of the resistive memory device, the set operation and the reset operation can be performed multiple times, that is, multiple write operations can be performed.

[0045] The structure of the storage unit and the write operation are described in detail below with reference to FIG. 2 .

[0046] FIG2 shows a schematic diagram of the structure of an exemplary memory cell. The memory cell includes a transistor M1 and a resistive memory device R1. For example, when transistor M1 is an N-type transistor, its gate is connected to a word line WL. For example, when a high level is input to word line WL, transistor M1 is turned on. The first electrode of transistor M1 can be a source electrode and is configured to be connected to a source line SL. For example, transistor M1 can receive a reset voltage through source line SL. The second electrode of transistor M1 can be a drain electrode and is configured to be connected to a second electrode (e.g., a negative electrode) of resistive memory device R1. The first electrode (e.g., a positive electrode) of resistive memory device R1 is connected to a bit line BL. For example, resistive memory device R1 can receive a set voltage through bit line BL. For example, when transistor M1 is a P-type transistor, its gate is connected to the word line WL. For example, when the word line WL input is low, transistor M1 is turned on. The first electrode of transistor M1 can be a source electrode and is configured to be connected to the source line SL. For example, transistor M1 can receive a reset voltage through the source line SL. The second electrode of transistor M1 can be a drain electrode and is configured to be connected to the second electrode (for example, the negative electrode) of the resistive memory device R1. The first electrode (for example, the positive electrode) of the resistive memory device R1 is connected to the bit line BL. For example, the resistive memory device R1 can receive a set voltage through the bit line BL. It should be noted that the structure of the memory cell can also be implemented as other structures, such as a structure in which the second electrode of the resistive memory device R1 is connected to the source line SL, and the embodiments of the present disclosure are not limited to this.

[0047] Taking M1 as an example of an N-type transistor, the function of the word line WL is to apply a corresponding voltage to the gate of the transistor M1, thereby controlling whether the transistor M1 is turned on or off. When performing a write operation on the resistive memory device R1, such as a set operation or a reset operation, it is necessary to turn on the transistor M1 first, that is, it is necessary to apply a turn-on voltage to the gate of the transistor M1 through the word line WL. After the transistor M1 is turned on, for example, a voltage can be applied to the resistive memory device R1 through the source line SL and the bit line BL to change the resistance state of the resistive memory device R1. For example, a set voltage can be applied through the bit line BL to put the resistive memory device R1 in a low resistance state; for another example, a reset voltage can be applied through the source line SL to put the resistive memory device R1 in a high resistance state. For example, the resistance value of the high resistance state is more than one hundred times the resistance value of the low resistance state, for example, more than one thousand times.

[0048] The embodiments of the present disclosure have no restrictions on the type and structure of the memory cell. The structure of the memory cell may be 1T1R (including one transistor and one resistive memory device), 2T2R (including two transistors and two resistive memory devices) or other possible structures. It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (such as MOS field effect transistors) or other switching devices with the same characteristics. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. The embodiments of the present disclosure do not limit the type of transistor used.

[0049] Since there are no conductive filaments inside the resistive memory device when it is prepared, compared to other types of memory, the resistive memory device needs to undergo an additional initialization (Forming) process to obtain the resistance switching characteristics. The initialization process refers to applying a high voltage pulse to the two poles of the resistive memory device, thereby inducing the formation of conductive filaments inside the resistive memory device. During the life cycle of the resistive memory device, the initialization operation usually only needs to be performed once. After the conductive filaments are formed inside the resistive memory device, the resistive memory device can become a low resistance at the set voltage or a high resistance at the reset voltage.

[0050] Since both the initialization operation and the set operation are operations for changing the resistance value of the resistive memory device from a high resistance value to a low resistance value, in the embodiment of the present disclosure, the initialization operation and the set operation are collectively referred to as “low resistance operation”.

[0051] The low-resistance operation requires applying a high voltage pulse to the resistive memory device. Due to the significant differences between resistive memory devices, the pulse duration required to complete the low-resistance operation may not be the same for each resistive memory device. If the same pulse voltage duration is applied to every resistive memory device, some resistive memory devices may fail to achieve low-resistance, thus affecting the performance of the memory cell. Therefore, after performing a low-resistance operation on a resistive memory device, it is usually necessary to perform multiple verification operations on the device to verify that the device has been successfully low-resistance.

[0052] The verification operation refers to obtaining the resistance value of the resistive memory device after the initialization or set voltage is applied through a read operation, and checking whether the resistance value of the resistive memory device has reached the target resistance value. For example, after applying an initialization voltage pulse of a preset time and a preset amplitude to a resistive memory device, it is necessary to apply a read voltage to read the current resistance value of the resistive memory device. If the current resistance value of the resistive memory device does not reach the target resistance value, it means that the resistive memory device has not completed the low-resistance operation, then it is necessary to change the amplitude of the initialization voltage pulse, or change the pulse time applied to the resistive memory device, and then perform a low-resistance operation and a verification operation on the resistive memory device again until it is determined that the resistive memory device has been successfully low-resistance. After completing the low-resistance of one resistive memory device, the above operation is repeated for the next resistive memory device, and eventually all resistive memory devices are successfully low-resistance. However, multiple verifications make the low-resistance process very long, greatly increasing the time cost of production and testing.

[0053] One effective solution to this problem is parallel low-resistance operation. Parallel low-resistance operation involves simultaneously applying the same voltage pulse to multiple RRAM devices in a row, with the duration of the voltage pulse set long enough to ensure that each RRAM device can achieve low-resistance operation. In other words, parallel low-resistance operation shortens the total low-resistance operation time for multiple RRAM devices by extending the duration of a single low-resistance operation. However, parallel low-resistance operation cannot account for the inherent variability of RRAM devices, and the high currents generated by parallel low-resistance operation also pose new challenges to circuit design.

[0054] On the one hand, excessive current in the traces can lead to a serious voltage drop (IR drop) problem, which in turn limits the number of resistive memory devices that can be parallel-lowered. Here, voltage drop refers to the voltage difference V = I * R between the near and far ends of a long trace when a large current flows through the trace due to the existence of the trace resistance. The voltage drop problem causes the voltage obtained by the resistive memory device at the far end of the trace to be much lower than the preset low-resistance voltage. For example, because the word lines in the memristor array are often very long (on the order of millimeters), if the low-resistance current of each column is tens of microamperes, then when a thousand columns are simultaneously low-resistance, the current in the trace will reach tens of milliamperes, which will result in a very large voltage drop. The existence of the voltage drop causes the operating voltage of the resistive memory device at the far end of the trace to drop, resulting in the resistive memory device at the far end of the trace being unable to be successfully low-resistance, thus limiting the number of columns in the memristor array that can be operated in parallel.

[0055] On the other hand, parallel low-resistance may also reduce the performance of resistive memory devices. During parallel low-resistance, in order to ensure that all resistive memory devices can be successfully low-resistance during low-resistance, the pulse time of the low-resistance voltage needs to be set longer to ensure sufficient margin. However, during the period of time when the low-resistance voltage pulse lasts, current will continue to flow through the resistive memory device. Even with current limiting protection measures, applying high voltage to the resistive memory device for a long time may cause the resistive memory device to have poor consistency or excessive low resistance. Therefore, the performance of resistive memory devices with parallel low resistance is often not as good as that of resistive memory devices with low resistance one by one. In addition, long-term high current on the line will also increase power consumption.

[0056] At least one embodiment of the present disclosure provides a drive circuit. The drive circuit includes a coupled first control circuit, a current limiting circuit, and a second control circuit. The first control circuit is configured to transmit a current limiting operation signal on a current limiting operation signal line to the current limiting circuit when the circuit is turned on. The current limiting circuit is configured to apply a first operation signal to a load signal line connected to an output terminal of the drive circuit under the control of the current limiting operation signal. The second control circuit is configured to control the current limiting circuit to stop applying the first operation signal to the load signal line based on a feedback signal from the load signal line when the circuit is turned on.

[0057] At least one embodiment of the present disclosure further provides a memory device, comprising a drive circuit and a resistive memory device. The drive circuit comprises a coupled first control circuit, a current limiting circuit, and a second control circuit, wherein the first control circuit is configured to transmit a current limiting operation signal on a current limiting operation signal line to the current limiting circuit when the drive circuit is turned on; the current limiting circuit is configured to apply a first operation signal to a load signal line connected to an output terminal of the drive circuit under the control of the current limiting operation signal; and the second control circuit is configured to control the current limiting circuit to stop applying the first operation signal to the load signal line based on a feedback signal from the load signal line when the drive circuit is turned on. The first terminal of the resistive memory device is connected to the output terminal of the drive circuit, and the second terminal of the resistive memory device is connected to a sixth voltage source.

[0058] At least one embodiment of the present disclosure also provides an operating method for a memory device. The memory device includes a driving circuit and a resistive memory device, and the driving circuit includes a coupled first control circuit, a current limiting circuit, and a second control circuit. The operating method includes: applying a first control signal to the first control circuit to turn on the first control circuit, and applying a current limiting operation signal to the current limiting circuit through the first control circuit to turn on the current limiting circuit, thereby applying a first operating voltage to the resistive memory device connected to the output terminal of the driving circuit through the current limiting circuit; wherein the second control circuit is turned on according to a feedback signal on a load signal line connected to the resistive memory device, thereby controlling the current limiting circuit to stop applying the first operating voltage to the load signal line.

[0059] At least one embodiment of the present disclosure also provides another memory device. The memory device includes one or more memory arrays and a driving module. Each memory array includes one or more columns of memory cells and one or more bit lines respectively connected to the one or more columns of memory cells. The driving module includes one or more driving circuits, and each driving circuit includes a coupled first control circuit, a current limiting circuit, and a second control circuit. The first control circuit is configured to transmit a current limiting operation signal on a current limiting operation signal line to the current limiting circuit when turned on; the current limiting circuit is configured to apply a first operation signal to a bit line connected to an output end of the driving circuit under the control of the current limiting operation signal; and the second control circuit is configured to control the current limiting circuit to stop applying the first operation signal to the bit line according to a feedback signal from the bit line when turned on.

[0060] At least one embodiment of the present disclosure also provides another method for operating a memory device. The other memory device includes one or more memory arrays and a driver module, each memory array including one or more columns of memory cells and one or more bit lines respectively connected to the one or more columns of memory cells; the driver module includes one or more driver circuits, each driver circuit including a coupled first control circuit, a current limiting circuit, and a second control circuit. The operating method includes: in a self-stop mode, applying a first control signal to the driver module to turn on the one or more first control circuits in the driver module, thereby transmitting the current limiting operation signal on the current limiting operation signal line to the current limiting circuit in the turned-on driver circuit; applying a current limiting voltage to the current limiting operation signal line to turn on the current limiting circuit in the turned-on driver circuit, thereby applying the first operation signal to the memory cell connected to the bit line; applying a second control signal to turn on the second control circuit in the turned-on driver circuit, thereby controlling the current limiting circuit to stop applying the first operation signal to the bit line according to a feedback signal on the bit line through the second control circuit.

[0061] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0062] FIG3 is a schematic block diagram of a drive circuit according to at least one embodiment of the present disclosure. As shown in FIG3 , the drive circuit 10 according to at least one embodiment of the present disclosure includes a control unit (e.g., the first control circuit of the present disclosure), a switch unit (e.g., the current limiting circuit of the present disclosure), and a sampling unit (e.g., the second control circuit of the present disclosure).

[0063] The control unit is connected to a first voltage source U1 and a second voltage source U2, and is configured to receive a first control signal FORM from the first voltage source U1 and a current-limiting operation signal VFORM_I from the second voltage source U2. The control unit is turned on or off based on the first control signal FORM, and when turned on, the current-limiting operation signal VFORM_I is applied to the first node V1. That is, the first control signal FORM is used to turn the control unit on or off, and the current-limiting operation signal VFORM_I is used to turn the switching unit on or off.

[0064] The switching unit is connected to the control unit, the third voltage source U3 and the output terminal OUT, and is configured to be turned on or off according to the level of the first node V1, and is turned on when the level of the first node V1 is the current limiting operation signal VFORM_I to apply the first operating voltage VFORM received from the third voltage source U3 to the output terminal OUT.

[0065] The current-limiting operating signal VFORM_I and the first operating voltage VFORM can jointly regulate the voltage at the output terminal OUT. For example, the output terminal OUT is connected to a load. When the switch unit is turned on, the first operating voltage VFORM is provided to the load. The load can be, for example, a voltage-modulated device, including but not limited to a resistive memory device. The current-limiting operating signal VFORM_I is used to limit the threshold to which the voltage at the output terminal OUT can reach. This threshold can be, for example, a voltage value that just satisfies the load function.

[0066] The sampling unit is connected to the output terminal OUT, the third voltage source U3 and the switching unit, and is configured to be turned on or off according to the feedback voltage VBL (for example, the feedback signal in the present disclosure) of the output terminal OUT, and to apply the first operating voltage VFORM to the first node V1 when being turned on, so that the switching unit is turned off when the level of the first node V1 is the first operating voltage VFORM.

[0067] When the driver circuit 10 is operating, a first control signal FORM is applied to the control unit to activate the control unit. The control unit then applies the received current-limiting operation signal VFORM_I to the switch unit to activate the switch unit. Once activated, the switch unit applies the first operating voltage VFORM to the output terminal OUT. Simultaneously, the sampling unit receives the feedback voltage VBL returned from the output terminal OUT and converts it into a signal to control the switch unit. When the feedback voltage VBL reaches a threshold voltage, the sampling unit turns the switch unit off, thereby blocking the path between the first operating voltage VFORM and the output terminal and automatically stopping the application of the drive voltage to the load at the output terminal.

[0068] FIG4 is a schematic diagram of the structure of an exemplary drive circuit provided in at least one embodiment of the present disclosure. As shown in FIG4 , in at least one embodiment of the present disclosure, the control unit includes a first transistor T1, wherein the control electrode (e.g., gate) of the first transistor T1 is connected to a first voltage source U1, the first electrode (e.g., source) of the first transistor T1 is connected to a second voltage source U2, and the second electrode (e.g., drain) of the first transistor T1 is connected to a first node V1.

[0069] For example, the switching unit includes a second transistor T2, the control electrode (e.g., gate) of the second transistor T2 is connected to the first node V1, the first electrode (e.g., source) of the second transistor T2 is connected to the third voltage source U3, and the second electrode (e.g., drain) of the second transistor T2 is connected to the output terminal OUT.

[0070] For example, the sampling unit includes a third transistor T3, a control electrode (e.g., a gate) of the third transistor T3 is connected to the output terminal OUT, a first electrode (e.g., a source) of the third transistor T3 is connected to the third voltage source U3, and a second electrode (e.g., a drain) of the third transistor T3 is connected to the first node V1.

[0071] For example, in some embodiments of the present disclosure, the first transistor T1, the second transistor T2, and the third transistor T3 are P-type transistors. For example, the first transistor T1, the second transistor T2, and the third transistor T3 may all be PMOS transistors.

[0072] For example, in some other embodiments of the present disclosure, the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors. For example, the first transistor T1, the second transistor T2, and the third transistor T3 may all be NMOS transistors.

[0073] For example, in some other embodiments of the present disclosure, the functions of the control unit, the switch unit, and the sampling unit may be implemented by other switching devices or circuit structures having the same characteristics as transistors. The embodiments of the present disclosure do not limit the specific circuit elements and circuit structures in the control unit, the switch unit, and the sampling unit.

[0074] The driving circuit provided in the above-mentioned embodiment of the present disclosure can limit the voltage value of the output end according to the current limiting operation signal of the control unit, and automatically turn off the switching unit according to the feedback voltage of the output end through the sampling unit, thereby effectively controlling the voltage of the output end, realizing the function of self-stop driving, and reducing power consumption.

[0075] 5 is a schematic diagram of a memory device 100 provided in accordance with at least one embodiment of the present disclosure. As shown in FIG5 , the memory device 100 provided in accordance with at least one embodiment of the present disclosure includes a driving circuit 10 and a resistive memory device R1.

[0076] For example, a first terminal of the resistive memory device R1 is connected to the output terminal OUT of the driving circuit 10, and a second terminal of the resistive memory device R1 is connected to a sixth voltage source U6. For example, the sixth voltage source U6 is grounded.

[0077] For example, the driving circuit 10 can be used to change the resistance value of the resistive memory device R1 in a high resistance state, such as a newly manufactured resistive memory device R1 without a conductive filament formed therein. For example, the driving circuit 10 can convert the resistive memory device R1 from a high resistance state to a low resistance state, and automatically shut down to stop providing the driving voltage when the resistive memory device R1 reaches the expected low resistance state. That is, when the resistive memory device R1 reaches the expected resistance state, the driving circuit 10 no longer continues to provide the first operating voltage VFORM to the resistive memory device R1, thereby effectively preventing over-initialization of the resistive memory device R1 and reducing power consumption to a certain extent.

[0078] At least one embodiment of the present disclosure further provides a method for operating a memory device. The method includes: receiving a first control signal from a first voltage source and a current-limiting operation signal from a second voltage source via a control unit; turning on the control unit according to the first control signal and applying the current-limiting operation signal to a first node to turn on a switch unit; receiving a first operating voltage from a third voltage source via the switch unit and applying the first operating voltage to a resistive memory device connected to an output terminal when the switch unit is turned on; turning on a sampling unit according to a feedback voltage from the output terminal and applying the first operating voltage to a first node to turn off the switch unit.

[0079] For example, in some embodiments of the present disclosure, the first operating voltage includes an initialization voltage for the resistive memory device.

[0080] For example, in some embodiments of the present disclosure, the operating method further includes: changing the resistance value of the resistive memory device according to the first operating voltage.

[0081] For example, in some embodiments of the present disclosure, the feedback voltage changes in response to a change in the resistance value of the resistive memory device. When the resistance value of the resistive memory device reaches a target resistance value, the feedback voltage reaches a first threshold voltage to turn on the sampling unit.

[0082] For example, in some embodiments of the present disclosure, the operating method further includes: determining a current limiting voltage of the current limiting operation signal according to a target resistance value of the resistive memory device.

[0083] The memory device and its operation method can control the initialization process of the resistive random access memory (RRAM) device. By using a current-limiting operation signal of a control unit to limit the lowest resistance that the RRAM device can reach, when the resistance of the RRAM device reaches the lowest resistance, the initialization process of the RRAM device is automatically stopped, and the continued application of the initialization voltage to the RRAM device is stopped, thereby effectively preventing over-initialization of the RRAM device and reducing power consumption.

[0084] The operation method will be described in detail below with reference to the memory device 100 shown in FIG. 5.

[0085] For example, in an example of the embodiment of the present disclosure, the RRAM device R1 is initialized by the driving circuit 10. The control unit, the switching unit, and the sampling unit in the driving circuit 10 are the first P-type transistor T1, the second transistor T2, and the third transistor T3, respectively.

[0086] First, the driving circuit 10 needs to be turned on. For example, a low-level pulse signal is applied to the first transistor T1 as the first control signal FORM to turn on the first transistor T1, so that the current-limiting operation signal VFORM_I is provided to the second transistor T2. The level of the current-limiting operation signal VFORM_I is less than the difference between the first operation voltage VFORM (for example, the initialization voltage) and the threshold voltage VGT3 of the second transistor T2, that is, VFORM_I < VFORM - VGT3. The magnitude of the current-limiting voltage of the current-limiting operation signal VFORM_I can be determined according to the target resistance value of the RRAM device R1. For example, if it is not desired that the resistance value of the RRAM device R1 after initialization is too low, the current-limiting voltage of the current-limiting operation signal VFORM_I can be set to be small, so that the degree of turning on of the second transistor T2 becomes smaller, thereby preventing the RRAM device R1 from being over-initialized.

[0087] Since the resistance value of the original RRAM device R1 is very large, the second transistor T2 is in the linear region and can provide the first operation voltage VFORM to the RRAM device R1 almost without loss, and makes the third transistor T3 in the off state.

[0088] As the first operation voltage VFORM is applied to the RRAM device R1, the resistance value of the RRAM device R1 gradually decreases. When the resistance value of the RRAM device R1 decreases to the target resistance value, it indicates that the RRAM device R1 has been successfully initialized. At this time, the first operation voltage VFORM does not need to be applied to the RRAM device R1 anymore. Continuing to apply the first operation voltage VFORM may cause the resistance value of the RRAM device R1 to be too low, resulting in over-initialization, which is not conducive to the performance of the RRAM device.

[0089] In this case, the sampling unit in the driving circuit 10 starts to function. Since the resistance value of the resistive random access memory device R1 is low at this time, the current flowing through the second transistor T2 becomes high, and the feedback voltage VBL at the output terminal OUT decreases. When the feedback voltage VBL is less than the difference between the first operating voltage VFORM and the threshold voltage VGT2 of the third transistor (VBL < VFORM - VGT2), the third transistor T3 is turned on. That is to say, the feedback voltage VBL can change corresponding to the change in the resistance value of the resistive random access memory device R1. When the resistance value of the resistive random access memory device R1 reaches the target resistance value, the feedback voltage VBL reaches the threshold to turn on the third transistor T3.

[0090] After the third transistor T3 is turned on, the first operating voltage VFORM is transmitted to the first node V1, that is, the first operating voltage VFORM is transmitted to the gate of the second transistor T2, causing the second transistor T2 to quickly turn off, thereby turning off the conduction path between the third voltage source U3 and the output terminal OUT, and stopping applying the first operating voltage VFORM to the resistive random access memory device R1.

[0091] After the second transistor T2 is turned off, the output terminal OUT is floating, and the charge on the bit line (BL) where the resistive random access memory device R1 is located can be gradually discharged through the gate capacitance of the third transistor T3. Therefore, the bit line returns to a low level, and the initialization process of the resistive random access memory device R1 ends.

[0092] For example, in some embodiments of the present disclosure, the first transistor T1, the second transistor T2, and the third transistor T3 can also be NMOS transistors. In this embodiment, the first transistor T1 is turned on when the first control signal FORM is at a high level; the level of the current limiting operation signal VFORM_I should be greater than the difference between the first operating voltage VFORM and the threshold voltage VGT3 of the second transistor T2, that is, VFORM_I > VFORM - VGT3; when the feedback voltage VBL is greater than the difference between the first operating voltage VFORM and the threshold voltage VGT2 of the third transistor (VBL > VFORM - VGT2), the third transistor T3 is turned on. The other operation steps and the change process of the circuit elements except for the above differences are similar to those described above, and will not be elaborated here.

[0093] For example, in some embodiments of the present disclosure, the first operating voltage can also be the set voltage for the resistive random access memory device. For example, this driving circuit can accurately control the resistance value of the resistive random access memory device during the write operation, so that the verification operation after the write operation can be omitted, reducing the time cost. The method of using the driving circuit for the set operation of the resistive random access memory device can refer to the description of the initialization operation in the above embodiments, and will not be elaborated here.

[0094] At least one embodiment of the present disclosure further provides a memory device. The memory device includes a memory array and at least one driving circuit. The memory array includes multiple rows and columns of memory cells arranged in multiple rows and columns, word lines corresponding to each row in the memory array, bit lines corresponding to each row in the memory array, and source lines corresponding to each column in the memory array, wherein each memory cell includes a transistor and a resistive memory device, the gate of the transistor is connected to the word line corresponding to the row where the memory cell is located, the first electrode of the transistor is connected to the source line corresponding to the column where the memory cell is located, the second electrode of the transistor is connected to the first end of the resistive memory device, and the second end of the resistive memory device is connected to the bit line corresponding to the row where the memory cell is located; each driving circuit is coupled to a bit line of the memory array.

[0095] The memory device can perform parallel initialization of a memory array through a driving circuit. During the parallel initialization process, the initialization voltage applied to the resistive memory device that has completed initialization is automatically stopped, thereby effectively alleviating the voltage drop problem, shortening the initialization time, improving the uniformity and reliability of multiple resistive memory devices during parallel initialization, and reducing power consumption.

[0096] FIG6 is a schematic diagram of a memory device 200 according to at least one embodiment of the present disclosure. As shown in FIG6 , the memory device 100 includes a memory array 20 and a plurality of driver circuits 10 . For example, the plurality of driver circuits 10 are used as initialization modules to initialize the resistive memory devices in the memory array 20 .

[0097] For example, the memory array 20 includes a plurality of memory cells, which form an array of M rows and N columns, where M and N are both positive integers. For example, each memory cell includes a switching element (e.g., a transistor) and a resistive memory device. In FIG6 , WL[1], WL[2]…WL[m] respectively represent word lines of the first row, the second row…the Mth row, and the control electrodes (e.g., the gate electrodes of the transistors) of the switching elements in the memory cells in each row are connected to the word lines corresponding to the row; BL[1], BL[2]…BL[n] respectively represent bit lines of the first column, the second column…the Nth column, and one end of the resistive memory device in the memory cells in each column is connected to the bit line corresponding to the column (and the other end is connected to the drain electrode of the switching element in the memory cell, for example); SL[1], SL[2]…SL[n] respectively represent source lines of the first column, the second column…the Nth column, and for example, the source electrodes of the transistors in the memory cells in each column are connected to the source lines corresponding to the column. It should be noted that, in the embodiment of the present disclosure, the directions of rows and columns are not limited to those shown in the figure, but can be determined as needed. The embodiment of the present disclosure does not limit the structure of the memory array 20 .

[0098] For example, the output terminals of the plurality of driving circuits 10 are respectively coupled to the plurality of bit lines of the memory array 20 , so that the initialization degree of the resistive memory devices in each column can be automatically controlled when the resistive memory devices in the memory array 20 are initialized in parallel.

[0099] For example, multiple driving circuits 10 are connected to the initialization voltage bus to receive the first operating voltage VFORM. For example, multiple driving circuits 10 can receive the same second control voltage VFORM_I, so that the resistance values ​​of multiple resistive memory devices initialized in parallel are substantially the same after initialization.

[0100] The process of initializing each resistive memory device by the driving circuit 10 can refer to the detailed description of the operation method of the self-stop initialization in the above embodiment, which will not be repeated here.

[0101] Under normal circumstances, when the parallel initialization operation begins, the current on the VFORM bus increases rapidly. There is no voltage drop problem at the near end of the bus due to the small wire resistance, so the resistive memory device on the column at the near end of the bus can receive the maximum voltage VFORM and start the initialization process under the regulation of this voltage. When the resistance of the resistive memory device in the column drops to a certain value, the initialization of the column automatically stops and the current drops to 0. As more and more branches (columns) are turned off, the total current on the VFORM bus will gradually decrease, making the total current smaller, so the voltage drop problem at the far end of the bus is alleviated. Therefore, the memory array 10 can gradually complete the initialization process from the near end to the far end of the bus.

[0102] Through the self-stop initialization operation method provided by the above-mentioned embodiment of the present disclosure, when initializing multiple resistive memory devices in a row of the memory array 20, when the resistance of the resistive memory devices on a column drops below a certain value, the driving circuit 10 of the column can automatically stop the initialization process, thereby automatically "turning off" this branch. This can improve the uniformity and reliability of the resistive memory devices after the initialization operation of multiple memory cells is performed simultaneously, while avoiding the voltage drop problem, reducing the current on the bus, and reducing power consumption.

[0103] It should be noted that, from a statistical distribution perspective, during parallel initialization, resistive memory devices in the memory array 10 that are closer to the bus may complete initialization faster, while resistive memory devices that are farther from the bus may complete initialization slower. However, due to differences in the resistive memory devices themselves, the order in which the multiple resistive memory devices complete initialization is usually random. In addition, during parallel initialization, the initialization time of multiple resistive memory devices in a row is not necessarily the same, but the resistance values ​​of the multiple resistive memory devices after initialization can be controlled by the drive circuit within a target range. Therefore, the drive circuit, memory device, and operating method thereof provided in at least one embodiment of the present disclosure can also improve the accuracy of resistive memory device initialization and do not require additional verification operations, which can greatly shorten the initialization time and reduce production costs.

[0104] At least one embodiment of the present disclosure also provides another drive circuit. The drive circuit includes a coupled first control circuit, a current limiting circuit, and a second control circuit. When the drive circuit operates in a self-stop mode, the first control circuit is configured to be turned on in response to a first control signal to transmit a current limiting voltage on a current limiting operation signal line to the current limiting circuit; the current limiting circuit is configured to be turned on in response to the current limiting voltage to apply a first operation signal to a load signal line connected to an output terminal of the drive circuit; and the second control circuit is configured to be turned on in response to a second control signal to transmit a second operation signal to the current limiting circuit, and to control the current limiting circuit to stop applying the first operation signal to the load signal line in response to the second operation signal and a feedback signal from the load signal line.

[0105] FIG7A is a schematic block diagram of a driving circuit according to at least one embodiment of the present disclosure. As shown in FIG7A , a driving circuit 31 according to at least one embodiment of the present disclosure includes a first control circuit, a current limiting circuit, and a second control circuit coupled to each other.

[0106] For example, the first control circuit receives a first control signal and a current-limiting operation signal. The first control signal controls the conduction state of the first control circuit. For example, when the first control signal is at a low level, the first control circuit is turned on; when the first control signal is at a high level, the first control circuit is turned off. For example, the first control signal can also be used to determine a threshold voltage at which the drive circuit self-stops.

[0107] For example, a first control circuit is coupled to a current-limiting circuit. After the first control circuit is turned on, a current-limiting operating signal can be applied to the current-limiting circuit. Under the control of the current-limiting operating signal, the current-limiting circuit turns on and begins operating, thereby transmitting the first operating signal to the load signal line. The first operating signal is a drive voltage signal to be applied to the load. For example, when the current-limiting operating signal transmitted on the current-limiting operating signal line is a current-limiting voltage, the current-limiting circuit is turned on. When the current-limiting operating signal transmitted on the current-limiting operating signal line is a shutdown voltage, the current-limiting circuit is turned off. For example, the load signal line is connected to the output end of the driver circuit 31 and is also connected to the second control circuit of the driver circuit 31, thereby transmitting a feedback signal to the second control circuit.

[0108] For example, the second control circuit receives a second control signal and a second operation signal. The second control signal is a signal for controlling whether the second control circuit is turned on. For example, when the second control signal is at a low level, the second control circuit is turned on; when the second control signal is at a high level, the second control circuit is turned off.

[0109] For example, when the second control circuit is turned on, it can receive a feedback signal from the load signal line and, under the control of the feedback signal, apply a second operating signal to the current limiting circuit, thereby controlling the conduction state of the current limiting circuit. For example, when the feedback signal reaches a threshold voltage, the second control circuit turns off the current limiting circuit. After the current limiting circuit is turned off, the first operating signal is no longer applied to the load signal line, thereby achieving a self-stop driving function. This operating mode can be referred to as the self-stop mode of the drive circuit 31.

[0110] For example, the operating modes of the driver circuit 31 also include a shutdown mode and a current-limiting mode. At least one embodiment of the present disclosure can control the operating states of the first and second control circuits, respectively, based on a first control signal and a second control signal, thereby switching between different operating modes. For example, when voltage driving of the load is not required, the driver circuit 31 can be placed in shutdown mode; when only current on the load signal line needs to be controlled, the driver circuit 31 can be placed in current-limiting mode; when automatic termination of load driving is required, the driver circuit 31 can be placed in self-stop mode. For example, the driver circuit 31 can first enter current-limiting mode and then, at a predefined moment or desired time, enter self-stop mode under the control of a second control signal. For example, the first and second control circuits can be simultaneously activated, causing the driver circuit 31 to first enter current-limiting mode and then automatically enter self-stop mode after driving is completed. Therefore, the driver circuit provided in at least one embodiment of the present disclosure can switch between different operating modes using at least the first and second control signals, thereby fully meeting the diverse needs of practical applications. Furthermore, the circuit has a simple structure and is flexible and convenient to operate.

[0111] For example, in shutdown mode, a shutdown voltage is transmitted on the current-limiting operation signal line, thereby transmitting the shutdown voltage to the current-limiting circuit via the first control circuit (in the on state), thereby shutting down the current-limiting circuit. In this case, the first operation signal cannot be applied to the load. For example, in shutdown mode, the second control circuit can be turned on or off by the second control signal. The embodiments of the present disclosure do not limit the operating state of the second control circuit in shutdown mode.

[0112] For example, in current limiting mode, a current limiting voltage is transmitted on the current limiting operation signal line, thereby transmitting the current limiting voltage to the current limiting circuit through the first control circuit (in the on state), turning on the current limiting circuit and limiting the current on the load signal line to no more than a preset current based on the current limiting voltage. For example, the magnitude of the preset current can be determined based on actual needs, or the magnitude of the preset current on the load signal line can be controlled by adjusting the magnitude of the current limiting voltage.

[0113] For example, if the drive circuit is desired to operate only in the current limiting mode and not in the self-stop mode, the second control circuit may be turned off by the second control signal.

[0114] For example, in at least one embodiment of the present disclosure, the second control circuit includes a feedback switch circuit and a sampling circuit.

[0115] For example, the feedback switch circuit receives a second control signal and a second operation signal, and the feedback switch circuit is turned on or off according to the second control signal. For example, when the second control signal is at a low level, the feedback switch circuit is turned on; when the second control signal is at a high level, the feedback switch circuit is turned off.

[0116] For example, the feedback switch circuit is coupled to a sampling circuit. The sampling circuit samples the feedback signal from the load signal line and, under the control of the feedback signal, turns on, thereby applying the second operating signal to the sampling circuit. When the feedback signal reaches a threshold voltage, the sampling circuit turns off the current limiting circuit. After the current limiting circuit turns off, the first operating signal stops being applied to the load signal line, thereby achieving a self-stop driving function.

[0117] The embodiments of the present disclosure do not limit the driving object (load) of the driving circuit. For example, the load can be a resistive switching device (such as a resistive switching memory device, etc.), or it can be other electronic devices, such as electronic devices based on semiconductor materials or other memory devices based on the resistive switching principle, such as magnetoresistive memory, phase change memory device, etc.

[0118] For example, in one example, when the load on the load signal line is a resistive switching device, as the resistance value of the resistive switching device changes from high to low, the voltage of the feedback signal changes from high to low. In response to the voltage of the feedback signal decreasing to a threshold voltage, the sampling circuit automatically turns off the current limiting circuit, thereby ceasing application of the pulse voltage to the resistive switching device, thereby preventing the resistance value of the resistive switching device from changing. For example, the threshold voltage is the voltage at which the resistive switching device reaches a target resistance value.

[0119] For ease of description, the following describes in detail the circuit structure and working mode of the driving circuit by taking the load of the driving circuit as a resistive random access memory as an example.

[0120] Figure 7B is a schematic diagram of the structure of an exemplary driving circuit 32 provided in at least one embodiment of the present disclosure. As shown in Figure 7B, the driving circuit 32 includes a first control circuit, a current limiting circuit, a feedback switch circuit, and a sampling circuit.

[0121] For example, in one example of an embodiment of the present disclosure, the voltages of the first operating signal VFS_BL and the second operating signal VFS_FB are the same, for example, both are provided by a third voltage source (not shown in the figure), or provided by different voltage sources (not shown in the figure).

[0122] For example, the first control circuit of the driving circuit 32 includes a first switching component, the first switching component includes a first N-type transistor T1_N and a first P-type transistor T1_P, the current limiting circuit of the driving circuit 32 includes a second transistor T2, the feedback switching circuit includes a fourth transistor T4, and the sampling circuit includes a third transistor T3.

[0123] The structures of the functional circuits such as the first control circuit, current limiting circuit, feedback switch circuit, and sampling circuit in the driving circuit 32 shown in FIG7B are merely exemplary and non-restrictive. As required, each functional circuit may have fewer or more transistors, or have switch components of other types or structures. For example, in some embodiments of the present disclosure, the first switch component may also be composed of only one transistor, such as only one N-type transistor or only one P-type transistor.

[0124] For example, the first end of the first switch component is connected to a first voltage source (not shown) via a current-limiting operation signal line to receive a current-limiting operation signal VSC_PG for turning on (or off) the second transistor (current-limiting transistor) T2. For example, the current-limiting voltage determines the saturation current of the second transistor T2, and the current-limiting voltage can be used to limit the final resistance variation range of the resistive memory device connected to the load signal line (e.g., the bit line BL).

[0125] For example, as shown in FIG7B , the control electrode (e.g., gate) of the first N-type transistor T1_N receives the first control signal VSC_EN, and the control electrode (e.g., gate) of the first P-type transistor T1_P receives the first control signal VSC_ENB. For example, when the first control signal VSC_EN is high, the first N-type transistor T1_N is turned on, and when the first control signal VSC_ENB is low, the first P-type transistor T1_P is turned on. In other words, when the first control signal VSC_EN is high and / or the first control signal VSC_ENB is low, the first control circuit can be turned on, and when the first control signal VSC_EN is low and the first control signal VSC_ENB is high, the first control circuit can be turned off.

[0126] In some embodiments of the present disclosure, the driving strength of the transistor in the first switch component and the driving strength of the third transistor T3 jointly determine the threshold voltage for turning off the driving circuit.

[0127] For example, in the driving circuit 32 shown in Figure 7B, when only the first N-type transistor T1_N is used to control the opening of the first control circuit, the threshold voltage for closing the driving circuit is jointly determined by the driving strengths of the first transistor T1_N and the third transistor T3; when only the first P-type transistor T1_P is used to control the opening of the first control circuit, the threshold voltage for closing the driving circuit is jointly determined by the driving strengths of the first P-type transistor T1_P and the third transistor T3; when the first N-type transistor T1_N and the first P-type transistor T1_P are used to jointly control the opening of the first control circuit, the threshold voltage for closing the driving circuit is jointly determined by the driving strengths of the first N-type transistor T1_N, the first P-type transistor T1_P and the third transistor T3.

[0128] For example, in some other embodiments of the present disclosure, the first switch component may include only N-type transistors or only P-type transistors. For example, when the first switch component includes only the first N-type transistor, the driving strength of the first N-type transistor and the third transistor jointly determines the threshold voltage for shutting down the drive circuit; when the first switch component includes only the first P-type transistor, the driving strength of the first P-type transistor and the third transistor jointly determines the threshold voltage for shutting down the drive circuit.

[0129] A control electrode (e.g., gate) of the second transistor T2 is connected to the second end of the first switch component, a first electrode of the second transistor T2 is connected to a third voltage source to receive a first operating signal VFS_BL, and a second electrode of the second transistor T2 is connected to a load signal line (e.g., bit line BL).

[0130] A control electrode (e.g., a gate) of the fourth transistor T4 is connected to a fifth voltage source (not shown) to receive the second control signal VSCFB_ENB, a first electrode of the fourth transistor T4 is connected to the fourth voltage source to receive the second operating signal VFS_FB, and a second electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3.

[0131] The control electrode of the third transistor T3 is connected to the load signal line (for example, the bit line BL) to receive the feedback signal from the bit line BL, the first electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4 to receive the second operating signal VFS_FB, and the second electrode of the third transistor T3 is connected to the control electrode of the second transistor T2.

[0132] For example, in the above example, the second transistor T2 , the fourth transistor T4 , and the third transistor T3 are all P-type transistors.

[0133] For example, the driving circuit provided in at least one embodiment of the present disclosure has three operating modes: shutdown mode, current limiting mode, and self-stop mode.

[0134] As shown in FIG8 , in shutdown mode, for example, the first control signal VSC_ENB is at a low level (e.g., VSC_ENB=0), and the first control signal VSC_EN is at a low level (e.g., VSC_EN=0). Therefore, the first control circuit is turned on, that is, the first P-type transistor T1_P transmits the current limiting operation signal VSC_PG to the gate of the second transistor T2. In shutdown mode, a shutdown voltage is transmitted on the current limiting operation signal line. In this example, the shutdown voltage is a high level (e.g., VSC_PG=VDDH, and VDDH>VFS_BL-|VTHP|, where VTHP is the gate-source voltage at which the second transistor T2 is turned on). Therefore, the second transistor T2 is turned off, that is, the current limiting circuit is not conducting, thereby disconnecting the first operation signal VFS_BL from the bit line BL. At this time, the driver circuit 32 is not operating. For example, in shutdown mode, the second control signal VSCFB_ENB can be low (eg, VSCFB_ENB=0) to turn on the fourth transistor T4, or the second control signal VSCFB_ENB can be high (eg, VSCFB_ENB=VDDH) to turn off the fourth transistor T4.

[0135] For example, in current limiting mode, when the first control signal VSC_ENB is at a high level (e.g., VSC_ENB = VDDH) and the first control signal VSC_EN is at a high level (e.g., VSC_EN = VDDH), the first control circuit is turned on, that is, the first N-type transistor T1_N transmits the current limiting operation signal to the gate of the second transistor T2. In current limiting mode, a current limiting voltage is transmitted on the current limiting operation signal line. The magnitude of the current limiting voltage can be determined based on the target resistance value to be achieved by the resistive memory device. After the current limiting voltage is transmitted to the gate of the second transistor T2 by the first N-type transistor T1_N, the second transistor T2 is turned on, and the second transistor T2 transmits the first operation signal VFS_BL to the bit line BL.

[0136] For example, in the current limiting mode, the first operation signal VFS_BL is a low-resistance operation voltage, that is, the first operation signal VFS_BL can be an initialization voltage for performing an initialization operation on the resistive memory device, or a set voltage for performing a set operation on the resistive memory device. For example, in the current limiting mode, the second control signal VSCFB_ENB is at a high level (for example, VSCFB_ENB=VDDH), thereby turning off the fourth transistor T4. Since the fourth transistor T4 is turned off, the feedback branch is disconnected, so the feedback switch circuit and the sampling circuit do not play a feedback role. As the low-resistance operation proceeds, the resistance of the resistive memory device gradually decreases, and the voltage on the bit line BL also decreases. The second transistor T2 enters the saturation region to maintain the stability of the saturation current. The voltage on the bit line BL is basically stabilized at a fixed value due to the limitation of the saturation current. As shown in Figure 8, in the current limiting mode, the voltage on BL gradually decreases, and the current I R Gradually increases, after a period of time, the voltage and current I on BL R are restricted to fixed values.

[0137] For example, in self-stop mode, the first control signal VSC_ENB is at a high level (e.g., VSC_ENB = VDDH). The first control signal VSC_EN is a high-level voltage capable of adjusting the feedback strength, thereby enabling the first control circuit to be turned on. In other words, the first N-type transistor T1_N transmits the current-limiting operation signal to the gate of the second transistor T2. In self-stop mode, the current-limiting operation signal VSC_PG can still remain at the current-limiting voltage, but the second control signal VSCFB_ENB is at a low level (e.g., VSCFB_ENB = 0), thereby turning on the fourth transistor T4. As a result, the feedback branch is opened, and the sampling circuit receives the second operation signal VFS_FB.

[0138] For example, in the self-stop mode, the first operation signal VFS_BL and the second operation signal VFS_FB are low-resistance operation voltages, that is, the first operation signal VFS_BL can be an initialization voltage for performing an initialization operation on the resistive memory device, or a set voltage for performing a set operation on the resistive memory device.

[0139] For example, during low-resistance operation, because the second transistor T2 is initially on, the resistance of the resistive memory device is high, and the second transistor T2 is in the linear region. The first operating signal VFS_BL is transmitted to the bit line BL almost intact, while the third transistor T3 is off. As the high voltage applied to the bit line BL gradually reduces the resistance of the resistive memory device, the voltage on the bit line BL also gradually decreases as the resistance of the resistive memory device decreases. As the voltage on the bit line BL gradually decreases, that is, the voltage of the feedback signal gradually decreases, the third transistor T3 gradually turns on, and then the gate-source voltage of the third transistor T3 continuously increases, gradually strengthening the pull-up capability of the third transistor T3, causing the voltage at node VP to slowly increase. When the voltage of the feedback signal on the bit line BL drops to the threshold voltage, the voltage at node VP rises to VFS_BL - |VTHP|, where VTHP is the gate-source voltage at which the second transistor T2 turns on. That is, the voltage at node VP reaches the turn-off threshold voltage of the second transistor T2, causing the second transistor T2 to enter the off state, thereby stopping the application of the first operating signal VFS_BL to the resistive memory device connected to the bit line BL. Finally, the bit line BL is quickly discharged to 0, and the low-resistance operation of the resistive memory device ends.

[0140] For example, in at least one embodiment of the present disclosure, the operating voltage ranges of signals such as the first operating signal VFS_BL, the current limiting operating signal VSC_PG, and the first control signal VSC_EN may depend on different semiconductor processes, and the embodiments of the present disclosure do not limit the operating voltage ranges of each signal. For example, at a 28nm process node, for example, when performing an initialization operation on a resistive memory device, the typical operating voltage range of the first operating signal VFS_BL is 1V to 5V, the typical operating voltage range of the current limiting operating signal VSC_PG is 0 to 4V, and the typical operating voltage range of the first control signal VSC_EN is 0 to 5V. For example, at a 28nm process node, for example, when performing a set operation on a resistive memory device, the typical operating voltage range of the first operating signal VFS_BL is 0.8V to 4V, the typical operating voltage range of the current limiting operating signal VSC_PG is 0 to 3V, and the typical operating voltage range of the first control signal VSC_EN is 0 to 3V.

[0141] For example, in at least one embodiment of the present disclosure, in the shutdown mode, the current limiting mode, and the self-stop mode, it is possible to choose to turn on only the first N-type transistor T1_N, or to choose to turn on only the first P-type transistor T1_P, or to choose to turn on both the first N-type transistor T1_N and the first P-type transistor T1_P at the same time, and the control method is flexible and diverse.

[0142] For example, in at least one embodiment of the present disclosure, when a driver circuit is used to perform a low-resistance operation on a resistive memory device, the driver circuit may select to perform the low-resistance operation on the resistive memory device only in the current limiting mode, or may select to perform the low-resistance operation on the resistive memory device only in the self-stop mode, or may select to first enable the current limiting mode and then enable the self-stop mode to perform the low-resistance operation on the resistive memory device (as shown in FIG8 ). It should be noted that when the resistive memory device is only operated in the self-stop mode, in response to the voltage (feedback signal) on the BL reaching the threshold voltage, the driver circuit will immediately turn off the current limiting circuit.

[0143] For example, in at least one embodiment of the present disclosure, the current limiting circuit receives the first operating signal through the first operating signal line, and the second control circuit receives the second operating signal through the second operating signal line.

[0144] For example, as shown in Figure 7B, the driving circuit 32 also includes a first operating signal line VFS1 and a second operating signal line VFS2. The first operating signal line VFS1 is connected to the current limiting circuit (the second transistor T2), thereby providing the first operating signal VFS_BL to the current limiting circuit, and the second operating signal line VFS2 is connected to the feedback switching circuit (the fourth transistor T4), thereby providing the second operating signal VFS_FB to the sampling circuit (the third transistor T3).

[0145] For example, in the above example, the first electrode of the second transistor T2 is connected to the third voltage source via the first operating signal line VFS1 to receive the first operating signal VFS_BL. The first electrode of the fourth transistor T4 is connected to the fourth voltage source via the second operating signal line VFS2 to receive the second operating signal VFS_FB. The first operating signal VFS_BL and the second operating signal VFS_FB have the same voltage. When the feedback switch circuit (the fourth transistor T4) is turned on, a current branch exists from VFS_FB to the fourth transistor T4, the third transistor T3, the first P-type transistor T1_P, the first N-type transistor T1_N, and then to VSC_PG. The current in this branch is very small, for example, less than 50 nanoamperes (nA). Because the first operating signal line VFS1 and the second operating signal line VFS2 are separate lines, the current does not flow into the second operating signal line VFS2, thereby reducing the voltage drop on the second operating signal line VFS2 during low-resistance operation of the resistive memory device.

[0146] In at least one embodiment of the present disclosure, as shown in FIG7C , the current limiting circuit and the second control circuit receive the first operating signal and the second operating signal through the same operating signal line, and the first operating signal and the second operating signal have the same voltage.

[0147] Figure 7C is a schematic diagram of the structure of an exemplary drive circuit 32 provided in at least one embodiment of the present disclosure. Aside from the number and connection method of the operating signal lines, the rest of the circuit structure of the drive circuit 33 shown in Figure 7C is identical to the circuit structure of the drive circuit 32 shown in Figure 7B . For a detailed description of the circuit structure and operating mode of the drive circuit 33, please refer to the detailed description above, and any repetitions will not be repeated here.

[0148] For example, as shown in FIG7C , the first electrode of the second transistor T2 is connected to the third voltage source via the operating signal line VFS to receive the first operating signal VFS_BL. The first electrode of the fourth transistor T4 is connected to the third voltage source via the operating signal line VFS to receive the second operating signal VFS_FB. The first operating signal VFS_BL and the second operating signal VFS_FB have the same voltage. The second transistor T2 and the fourth transistor T4 receive the same operating voltage via the same operating signal line VFS, which can reduce the number of traces, area, and complexity of circuit design. Furthermore, since the current on the operating signal line VFS is very small, a significant voltage drop is not introduced.

[0149] In at least one embodiment of the present disclosure, as shown in FIG. 7D , the positions of the fourth transistor T4 and the third transistor T3 may be interchanged.

[0150] FIG7D is a schematic diagram of the structure of an exemplary drive circuit 34 according to at least one embodiment of the present disclosure. Aside from the connection between the fourth transistor T4 and the third transistor T3, the rest of the circuit structure of the drive circuit 34 shown in FIG7D is identical to the circuit structure of the drive circuit 32 shown in FIG7B . For a detailed description of the circuit structure and operating mode of the drive circuit 34, please refer to the detailed description above, and any repetitions will not be repeated here.

[0151] For example, as shown in FIG7D , the first electrode of the second transistor T2 is connected to the third voltage source via the first operating signal line VFS1 to receive the first operating signal VFS_BL. The first electrode of the third transistor T3 is connected to the fourth voltage source via the second operating signal line VFS2 to receive the second operating signal VFS_FB. The first operating signal VFS_BL and the second operating signal VFS_FB have the same voltage. The second electrode of the third transistor T3 is connected to the first electrode of the fourth transistor T4, and the control electrode of the third transistor T3 is connected to the load signal line BL. The second electrode of the fourth transistor T4 is connected to the control electrode of the second transistor T2, and the control electrode of the fourth transistor T4 is connected to the fifth voltage source to receive the second control signal VSCFB_ENB.

[0152] The driving circuit provided in the above-mentioned embodiments of the present disclosure can automatically turn off the current limiting circuit according to the feedback signal of the output end, thereby realizing the function of self-stop driving, thereby effectively controlling the voltage of the output end, controlling the resistance value of the load on the load signal line, and avoiding the operating voltage from being continuously applied to the load, thereby significantly reducing power consumption.

[0153] As mentioned above, performing low-resistance operation on multiple resistive memory devices in a memory array in parallel can reduce verification operations and reduce the time cost of production and testing, but parallel low-resistance operation will cause serious voltage drop problems and may further affect the uniformity and reliability of the device. In this regard, at least one embodiment of the present disclosure provides a memory device, which includes one or more memory arrays and a driving module. The memory device performs low-resistance operation on the resistive memory devices in the memory array through the driving circuit in the driving module, and can automatically stop the low-resistance process of the resistive memory device when the resistance of the resistive memory device reaches the target resistance value, and stop applying the operating voltage to the resistive memory device, thereby effectively preventing the resistive memory device from being excessively low-resistance. In at least one example, the memory device performs low-resistance operation on multiple resistive memory devices in parallel through multiple driving circuits, which can avoid the problem of voltage drop, improve the uniformity and reliability of the device after the low-resistance operation, improve the low-resistance operation speed of the array, and reduce power consumption.

[0154] For example, each memory array includes one or more columns of memory cells and one or more bit lines respectively connected to the one or more columns of memory cells. For example, the driver module includes one or more driver circuits, each driver circuit includes a first control circuit, a current limiting circuit, and a second control circuit coupled to each other. When the driver circuit operates in a self-stop mode, the first control circuit is configured to be turned on according to a first control signal to transmit a current limiting voltage on a current limiting operation signal line to the current limiting circuit; the current limiting circuit is configured to be turned on according to the current limiting voltage to apply a first operation signal to a bit line connected to an output terminal of the driver circuit; the second control circuit is configured to be turned on according to a second control signal to transmit a second operation signal to the current limiting circuit, and control the current limiting circuit to stop applying the first operation signal to the bit line according to the second operation signal and a feedback signal from the bit line.

[0155] For example, the memory cell in the memory array includes at least one resistive memory device (or other memory based on the resistive memory principle) and at least one switching element, and may be, for example, the structure of the memory cell as shown in FIG2 , which will not be described in detail here.

[0156] For example, in some embodiments of the present disclosure, a memory array includes a plurality of memory cells, and the plurality of memory cells form an array of N rows and M columns, where N and M are both positive integers. For example, the memory array includes N rows of word lines, M columns of bit lines, and N rows of source lines. The control electrodes (e.g., gate electrodes of transistors) of switching elements in each row of memory cells are connected to the word lines corresponding to the row, the memory cells in each column of memory cells are connected to the bit lines corresponding to the column, and the sources of transistors in each row of memory cells are connected to the source lines corresponding to the row.

[0157] For example, the driving circuit may be the driving circuit 32 shown in FIG. 7B , the driving circuit 33 shown in FIG. 7C , or the driving circuit 34 shown in FIG. 7D . For specific descriptions of the driving circuit, reference may be made to the detailed descriptions of the previous embodiments, and repeated descriptions will not be repeated.

[0158] For example, after the low-resistance operation instruction begins, the resistive memory cells in a row begin to perform low-resistance operation at the same time. As the resistance of the device decreases, the current on the trace that provides the low-resistance operation signal increases rapidly. The near end of the trace has no voltage drop problem due to the small wire resistance, so the low-resistance operation speed is faster. The wire resistance at the far end of the trace is large, the voltage drop problem is large, and the low-resistance operation speed is slow. When the device resistance at the near end of the trace drops to a certain value, the low-resistance operation of this branch automatically stops, and the current drops to 0. As more and more branches are turned off, the total current on the trace gradually decreases. Since the total current decreases, the voltage drop problem at the far end of the trace is alleviated, and the actual operating voltage of the device at the far end of the trace can basically reach the voltage of the first operation signal, so that the resistive memory array can gradually complete the low-resistance operation from the near end to the far end.

[0159] Figures 9A-9C are schematic diagrams of the structure of an exemplary memory device provided by at least one embodiment of the present disclosure. As shown in Figures 9A-9C, each driver circuit is connected to two separate operating signal lines. For example, the current limiting circuit in each driver circuit receives a first operating signal via the first operating signal line VFS1, and the second control circuit in each driver circuit receives a second operating signal via the second operating signal line VFS2. Because the first operating signal line VFS1 and the second operating signal line VFS2 are separate lines, current does not flow into the first operating signal line VFS1, thereby reducing the voltage drop on the first operating signal line VFS1 during low-resistance operation of the resistive memory device.

[0160] Figures 10A-10C are schematic diagrams of the structure of an exemplary memory device provided by at least one embodiment of the present disclosure. As shown in Figures 10A-10C, each driver circuit shares a common operating signal line VFS. For example, the current limiting circuit and the second control circuit in each driver circuit receive a first operating signal and a second operating signal through the same operating signal line. The first and second operating signals have the same voltage, thereby reducing the number of traces, area, and circuit design complexity. Furthermore, since the current on the operating signal line VFS is very low, a significant voltage drop is not introduced.

[0161] In the memory devices provided in some embodiments of the present disclosure, the output terminals of one or more driver circuits are respectively connected to one or more bit lines. As shown in the memory device 51 of FIG9A or the memory device 61 of FIG10A , each of the memory devices 51 and 61 includes only one memory array, which includes m memory columns (memory column 0 to memory column m), corresponding to the bit lines BL0 to BLm, respectively, and each bit line is connected to a driver circuit.

[0162] For example, in the memory devices provided in some embodiments of the present disclosure, the output terminals of one or more driver circuits are connected to one or more selected bit lines through a column selection switch circuit. As shown in the memory device 52 of FIG9B or the memory device 62 of FIG10B , the memory array includes m×n storage columns (storage column 0 to storage column mn), corresponding to bit lines BL0 to BLmn, respectively. For example, the column selection switch circuit may include multiple column selection switches, and the function of the column selection switch circuit is, for example, to select one (or more) column of bit lines from n columns of bit lines to connect to the driver circuit. For example, in one example, n=3, then every three bit lines in the memory array are connected to one column selection switch in the column selection switch circuit. When the memory array is operated in parallel with low resistance, m bit lines are selected from 3m bit lines through the m column selection switches of the column selection switch circuit. The m bit lines are connected to the m driver circuits, for example, through the load signal lines GBL0 to GBLm, one-to-one.

[0163] For example, in the memory devices provided in some embodiments of the present disclosure, the output terminals of one or more driver circuits are respectively connected to one or more bit lines of a selected memory array from one or more memory arrays through an array selection switch circuit. As shown in the memory device 53 of FIG9C or the memory device 63 of FIG10C , the memory device may include n memory arrays 1 to n, each memory array, for example, including multiple rows and columns of memory cells, for example, each memory array including m columns of memory columns. For example, the array selection switch circuit includes multiple array selection switches, and the function of the array selection switch circuit is, for example, to select one memory array from n memory arrays, and the multiple bit lines in the selected memory array are respectively connected to the multiple driver circuits in a one-to-one correspondence. For example, the resistive memory devices in memory arrays 1 to n can be sequentially subjected to parallel low-resistance operations.

[0164] The memory device may include any combination of the block selection switch circuits, column selection switch circuits, or array selection switch circuits described in the above embodiments, and the embodiments of the present disclosure are not limited thereto. For example, in one embodiment, the memory device includes an array selection switch circuit and a column selection switch circuit, and the output terminals of one or more driver circuits are connected to one or more selected bit lines in a selected memory array via the array selection switch circuit and the column selection switch circuit, respectively.

[0165] At least one embodiment of the present disclosure also provides an operating method for the above-mentioned memory device, which includes: in a self-stop mode, turning on one or more first control circuits in a driving module according to a first control signal to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit of each driving circuit; turning on the current limiting circuit of each driving circuit according to the current limiting voltage, thereby applying the first operation signal to the storage unit connected to the bit line; turning on the second control circuit of each driving circuit according to a second control signal to transmit the second operation signal to the current limiting circuit of each driving circuit; and controlling the current limiting circuit to stop applying the first operation signal to the bit line according to the second operation signal and the feedback signal on the bit line through the second control circuit of each driving circuit.

[0166] For example, each driving circuit controls the current branches on one or more bit lines of the memory array. Through the self-stop operation method of the driving circuit, the low-resistance operation process can be automatically stopped when the resistance of the resistive memory device on each bit line drops below a certain value, and the branch where it is located is turned off, so that the current on the operating signal line (bus) is reduced. In this way, the problem of voltage drop on the bus can be avoided, the uniformity and reliability of the resistive memory device after parallel operation can be improved, the low-resistance operation speed of the array can be increased, and power consumption can be reduced.

[0167] For example, in the operating method provided in at least one embodiment of the present disclosure, the first operating signal includes an initialization voltage or a set voltage for the memory cell.

[0168] For example, the operating method provided by at least one embodiment of the present disclosure also includes: in the shutdown mode, turning on the first control circuit according to the first control signal, transmitting the shutdown voltage on the current limiting operation signal line to the current limiting circuit to turn off the current limiting circuit; or, in the current limiting mode, turning on the first control circuit according to the first control signal to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit, limiting the current on the bit line to no higher than a preset current according to the current limiting voltage through the current limiting circuit, and turning off the second control circuit according to the second control signal.

[0169] For example, in the shutdown mode, the first control signal controls multiple first control circuits of multiple driving circuits in the memory device to be in an on state, and the current limiting operation signal is, for example, at a high level, thereby turning off the current limiting circuit to cut off the connection between the first operation signal and multiple bit lines BL (for example, bit lines BL0 to BLm).

[0170] For example, in one example, when performing a parallel low-resistance operation on memory cells of a memory array, the current limiting mode is first enabled, and then the self-stop mode is enabled.

[0171] For example, in current limiting mode, a first control signal controls multiple first control circuits of multiple driver circuits in the memory device to be in an on state. A current limiting voltage is transmitted to the current limiting circuit via the first control circuit. At this point, the current limiting circuit is turned on, thereby transmitting a first operating signal to multiple bit lines BL, thereby performing parallel low-resistance operation on multiple resistive memory devices on the multiple bit lines BL. For example, when performing an initialization operation on the memory array, the first operating signal is an initialization voltage, such as 5V; when performing a set operation on the memory array, the first operating signal is a set voltage, such as 3V.

[0172] For example, in current limiting mode, the second control signal is at a high level, thereby shutting down multiple second control circuits (or feedback switch circuits as shown in FIG. 7B , FIG. 7C , or FIG. 7D ) of multiple driver circuits in the memory device. Consequently, the sampling circuit in each driver circuit is cut off, disconnecting the feedback branch. Consequently, the feedback switch circuit and the sampling circuit do not function as feedback. As low-resistance operation proceeds, the resistance of multiple resistive memory devices in a row gradually decreases, and the voltage on the bit line BL also decreases accordingly. The voltage on the bit line BL is essentially stabilized at a fixed value due to the saturation current.

[0173] For example, when the self-stop mode is enabled, the second control signal is, for example, at a low level, thereby enabling multiple feedback switch circuits of multiple drive circuits in the memory device. As a result, multiple feedback branches are opened, and the sampling circuit in each drive circuit begins to receive the second operating signal. As the high voltage applied to the bit line BL gradually reduces the resistance of the resistive memory device, the voltage on the bit line BL also gradually decreases as the resistance of the resistive memory device decreases. The voltage of the feedback signal also gradually decreases, and the pull-up capability of the sampling circuit gradually increases. Under the action of the second operating signal, the current limiting circuit gradually enters the off state, thereby ceasing to apply the first operating signal to the multiple resistive memory devices connected to the multiple bit lines BL. Finally, as the multiple bit lines BL are rapidly discharged to 0, the low-resistance operation of all resistive memory devices ends. It should be noted that due to the differences between the resistive memory devices themselves, the time it takes for multiple resistive memory devices on multiple bit lines BL to complete low resistance is not necessarily the same. After the current on the bit line BL where the resistive memory device that completes low resistance first is located becomes 0, the total current on the operating signal line also decreases. As more and more branches are turned off, the total current on the bus becomes smaller and smaller, and the voltage drop problem is greatly alleviated.

[0174] Although the present disclosure has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made based on the embodiments of the present disclosure. Therefore, such modifications or improvements, as long as they do not depart from the spirit of the present disclosure, are within the scope of protection claimed by the present disclosure.

[0175] Regarding this disclosure, the following points need to be explained:

[0176] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0177] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale.

[0178] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0179] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A driving circuit, comprising: A first control circuit, a current limiting circuit and a second control circuit are coupled, wherein: The first control circuit is configured to transmit a current limiting operation signal on the current limiting operation signal line to the current limiting circuit when turned on; The current limiting circuit is configured to apply a first operation signal to a load signal line connected to an output terminal of the driving circuit under the control of the current limiting operation signal; The second control circuit is configured to control the current limiting circuit to stop applying the first operation signal to the load signal line according to a feedback signal from the load signal line when the second control circuit is turned on.

2. The driving circuit according to claim 1, wherein: The first control circuit is connected to a first voltage source and a second voltage source, and is configured to receive a first control signal from the first voltage source, receive the current limiting operation signal from the second voltage source, and be turned on or off according to the first control signal, and apply the current limiting operation signal to the first node when turned on; The current limiting circuit is connected to the first control circuit, the third voltage source and the output terminal, and is configured to be turned on or off according to the level of the first node, and to be turned on to apply the first operation voltage of the first operation signal received from the third voltage source to the output terminal when the level of the first node is the current limiting operation signal; The second control circuit is connected to the output terminal, the third voltage source and the current limiting circuit, and is configured to be turned on or off according to a feedback signal from the output terminal, and to apply the first operating voltage to the first node when turned on, so that the current limiting circuit is turned off when the level of the first node is the first operating voltage.

3. The driving circuit according to claim 1 or 2, wherein: The first control circuit comprises a first transistor, a control electrode of the first transistor is connected to the first voltage source, and a first electrode of the first transistor is connected to the second voltage source; The current limiting circuit comprises a second transistor, a control electrode of the second transistor is connected to a second electrode of the first transistor, a first electrode of the second transistor is connected to the third voltage source, and a second electrode of the second transistor is connected to the output end; The second control circuit includes a third transistor, a control electrode of the third transistor is connected to the output end, a first electrode of the third transistor is connected to the third voltage source, and a second electrode of the third transistor is connected to the control electrode of the second transistor.

4. The driving circuit according to claim 3, wherein: The first transistor, the second transistor and the third transistor are P-type transistors.

5. The driving circuit according to claim 1, wherein: When the working mode of the driving circuit is the self-stop mode, The first control circuit is configured to be turned on according to a first control signal to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit; The current limiting circuit is configured to be turned on according to the current limiting voltage to apply the first operation signal to a load signal line connected to an output terminal of the driving circuit; The second control circuit is configured to be turned on according to a second control signal to transmit a second operating signal to the current limiting circuit, and to control the current limiting circuit to stop applying the first operating signal to the load signal line according to the second operating signal and a feedback signal from the load signal line.

6. The driving circuit according to claim 5, wherein: The working mode of the driving circuit also includes a shutdown mode and a current limiting mode. In the shutdown mode, the first control circuit is configured to be turned on according to the first control signal to transmit the shutdown voltage on the current limiting operation signal line to the current limiting circuit to turn off the current limiting circuit; In the current limiting mode, the first control circuit is configured to be turned on according to the first control signal to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit, the current limiting circuit is configured to limit the current on the load signal line to no higher than a preset current according to the current limiting voltage, and the second control circuit is configured to be turned off according to the second control signal.

7. The driving circuit according to claim 5, wherein: The current limiting circuit receives the first operation signal through the first operation signal line, and the second control circuit receives the second operation signal through the second operation signal line. or, The current limiting circuit and the second control circuit receive the first operation signal and the second operation signal through the same operation signal line, The voltages of the first operation signal and the second operation signal are the same.

8. The driving circuit according to any one of claims 5 to 7, wherein: The second control circuit includes a feedback switch circuit and a sampling circuit. The feedback switch circuit is configured to be turned on or off according to the second control signal to open or close the second control circuit. The sampling circuit is configured to control the current limiting circuit to stop applying the first operating signal to the load signal line according to the feedback signal and the second operating signal when it is turned on.

9. The driving circuit according to claim 8, wherein: The first control circuit includes a first switch component, the current limiting circuit includes a second transistor, the sampling circuit includes a third transistor, and the feedback switch circuit includes a fourth transistor. The first end of the first switch component is connected to the first voltage source through the current limiting operation signal line; The control electrode of the second transistor is connected to the second end of the first switch component, the first electrode of the second transistor is connected to a third voltage source to receive the first operation signal, and the second electrode of the second transistor is connected to the load signal line; The control electrode of the fourth transistor is connected to the fifth voltage source to receive the second control signal, the first electrode of the fourth transistor is connected to the fourth voltage source to receive the second operation signal, and the second electrode of the fourth transistor is connected to the first electrode of the third transistor; The control electrode of the third transistor is connected to the load signal line, the first electrode of the third transistor is connected to the second electrode of the fourth transistor to receive the second operation signal, and the second electrode of the third transistor is connected to the control electrode of the second transistor.

10. The driving circuit according to claim 8, wherein: The first control circuit includes a first switch component, the current limiting circuit includes a second transistor, the sampling circuit includes a third transistor, and the feedback switch circuit includes a fourth transistor. The first end of the first switch component is connected to the first voltage source through the current limiting operation signal line; The control electrode of the second transistor is connected to the second end of the first switch component, the first electrode of the second transistor is connected to a third voltage source to receive the first operation signal, and the second electrode of the second transistor is connected to the load signal line; The control electrode of the fourth transistor is connected to the fifth voltage source to receive the second control signal, the first electrode of the fourth transistor is connected to the second electrode of the third transistor, and the second electrode of the fourth transistor is connected to the control electrode of the second transistor; The control electrode of the third transistor is connected to the load signal line, and the first electrode of the third transistor is connected to a fourth voltage source to receive the second operation signal.

11. The driving circuit according to claim 9 or 10, wherein: The first switch component includes a first N-type transistor and a first P-type transistor, and the driving strength of the first N-type transistor and / or the first P-type transistor and the third transistor jointly determines a threshold voltage for shutting down the driving circuit; or, The first switch component includes only a first N-type transistor, and the driving strengths of the first N-type transistor and the third transistor jointly determine a threshold voltage for shutting down the driving circuit; or, The first switch component includes only a first P-type transistor, and the driving strengths of the first P-type transistor and the third transistor jointly determine a threshold voltage for shutting down the driving circuit.

12. A memory device comprising a driving circuit and a resistive memory device, in, The driving circuit includes a first control circuit, a current limiting circuit and a second control circuit coupled to each other. The first control circuit is configured to transmit a current limiting operation signal on the current limiting operation signal line to the current limiting circuit when turned on; The current limiting circuit is configured to apply a first operation signal to a load signal line connected to an output terminal of the driving circuit under the control of the current limiting operation signal; The second control circuit is configured to control the current limiting circuit to stop applying the first operating signal to the load signal line according to the feedback signal from the load signal line when the second control circuit is turned on, A first terminal of the resistive memory device is connected to the output terminal of the driving circuit, and a second terminal of the resistive memory device is connected to a sixth voltage source.

13. A method for operating a memory device, comprising: Applying a first control signal to the first control circuit to turn on the first control circuit, and applying a current limiting operation signal to the current limiting circuit through the first control circuit to turn on the current limiting circuit, thereby applying a first operation voltage to the resistive memory device connected to the output terminal of the driving circuit through the current limiting circuit; The second control circuit is turned on according to a feedback signal on a load signal line connected to the resistive memory device, thereby controlling the current limiting circuit to stop applying the first operating voltage to the load signal line.

14. The operating method according to claim 13, wherein: The first operating voltage includes an initialization voltage or a set voltage for the resistive memory device.

15. The operating method according to claim 13 or 14, further comprising: The resistance value of the resistive memory device is changed according to the first operating voltage.

16. The operating method according to claim 13 or 14, wherein: The feedback voltage of the feedback signal changes in accordance with the change in the resistance value of the resistive memory device. When the resistance value of the resistive memory device reaches a target resistance value, the feedback voltage reaches a first threshold voltage to turn on the second control circuit.

17. The operating method according to claim 13 or 14, further comprising: The current limiting voltage of the current limiting operation signal is determined according to the target resistance value of the resistive memory device.

18. A memory device comprising: One or more memory arrays, each of the memory arrays comprising one or more columns of memory cells and one or more bit lines respectively connected to the one or more columns of memory cells; The driving module includes one or more driving circuits, each of which includes a coupled first control circuit, a current limiting circuit and a second control circuit, wherein: The first control circuit is configured to transmit a current limiting operation signal on the current limiting operation signal line to the current limiting circuit when turned on; The current limiting circuit is configured to apply a first operation signal to a bit line connected to an output terminal of the driving circuit under the control of the current limiting operation signal; The second control circuit is configured to control the current limiting circuit to stop applying the first operation signal to the bit line according to a feedback signal from the bit line when the second control circuit is turned on.

19. The memory device of claim 18, wherein: The output terminals of the one or more driving circuits are respectively connected to the one or more bit lines; or, The output terminals of the one or more driving circuits are connected to the selected one or more bit lines through a column selection switch circuit; or, The output terminals of the one or more driving circuits are respectively connected to one or more bit lines of a selected memory array among the one or more memory arrays through an array selection switch circuit; or, The output terminals of the one or more driving circuits are respectively connected to the selected one or more bit lines in the selected memory array through the array selection switch circuit and the column selection switch circuit.

20. A method for operating a memory device, wherein: The memory device includes one or more memory arrays and a driving module, each of the memory arrays includes one or more columns of memory cells and one or more bit lines respectively connected to the one or more columns of memory cells; the driving module includes one or more driving circuits, each of the driving circuits includes a coupled first control circuit, a current limiting circuit and a second control circuit, The operation method comprises: In the self-stop mode, applying a first control signal to the driving module to turn on one or more first control circuits in the driving module, thereby transmitting the current limiting operation signal on the current limiting operation signal line to the current limiting circuit in the turned-on driving circuit; Applying a current limiting voltage to the current limiting operation signal line to turn on the current limiting circuit in the turned-on driving circuit, thereby applying the first operation signal to the storage unit connected to the bit line; A second control signal is applied to turn on the second control circuit in the turned-on driving circuit, so that the second control circuit controls the current limiting circuit to stop applying the first operation signal to the bit line according to the feedback signal on the bit line.

21. The operating method according to claim 20, further comprising: In the shutdown mode, applying the first control signal to turn on the first control circuit, applying a shutdown voltage to the current limiting operation signal line, thereby turning off the current limiting circuit; or, In the current limiting mode, the first control signal is applied to turn on the first control circuit, a current limiting voltage is applied to the current limiting operation signal line, the current on the bit line is limited to no higher than a preset current according to the current limiting voltage by the current limiting circuit, and the second control signal is applied to turn off the second control circuit.

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