Doherty power ampifier with baseband controlled auxiliary amplifier

Abstract

A negative resistance Doherty power amplifier (NRDA) with a baseband controlled auxiliary amplifier is disclosed. The NRDA includes a main amplifier configured to receive and amplify an input signal. An impedance transformer having a transmission line, a reactive circuit element and / or a transformer is configured to receive and couple the amplified input signal to an external load through an impedance transformation. The NRDA also includes an auxiliary amplifier configured to be responsive to an envelope of the input signal to provide a negative resistance in parallel with a load impedance of the external load as seen at an output of the power amplifier.

Description

[0001] DOHERTY POWER AMPIFIER WITH BASEBAND CONTROLLED AUXILIARY

[0002] AMPLIFIER

[0003] TECHNICAL FIELD

[0004] The present disclosure relates to wireless communications, and in particular, to a Doherty power amplifier having a baseband controlled auxiliary amplifier.

[0005] BACKGROUND

[0006] The Third Generation Partnership Project (3GPP) has developed and is developing standards for Fourth Generation (4G) (also referred to as Long Term Evolution (LTE)) and Fifth Generation (5G) (also referred to as New Radio (NR)) wireless communication systems. Such systems provide, among other features, broadband communication between network nodes, such as base stations, and mobile wireless devices (WD), as well as communication between network nodes and between WDs. The 3GPP is also developing standards for Sixth Generation (6G) wireless communication networks.

[0007] Introduction

[0008] The Doherty amplifier, shown in FIG. 1, has been well known for almost a century. The Doherty amplifier is useful at most frequency ranges, i.e., from frequency range one (FR1) to frequency range two (FR2) and beyond.

[0009] In FIG. 1, the Doherty amplifier concept is shown, starting from the Radio Frequency (RF) input (RF in), the input RF signal is divided into two signals, one is feed to the carrier / main-amplifier, the other is fed to a phase compensating circuit, which then feeds the peaking / Auxiliary (Aux)-amplifier. The carrier / main-amplifier output is connected to a quarterwave-length impedance transformer, which connected to the peaking / Aux-amplifier, and the output load (ZL). When the carrier / main-amplifier operates without gain compression, the peaking / Aux-amplifier is turned OFF and amplification is only performed by the carrier / main- amplifier. Further, as the output power increases, the carrier / main-amplifier compresses and the peaking / Aux-amplifier generates power, as current. This affects the impedance transformation provide by the impedance transformer, between the peaking / Aux-amplifier and the carrier / main- amplifier. The result is that the carrier / main-amplifier load-impedance decreases, which prevents the compression, but this decrease in impedance is limited to ZL / 2.

[0010] The current behavior of a Doherty amplifier is shown in FIG. 2. FIG. 2 shows that for low input power the carrier current before the quarter- wave-length transmission line (impedance transformer) barely increases as input power increases. But when the input power becomes high, the carrier current before the quarter- wave-length transmission line (impedance transformer) increases significantly as input power increases. The transition occurs because the auxiliary amplifier begins to operate as the input power increases. This results in a continuous carrier current after the quarter- wave-length transmission line (impedance transformer), which reflects the true functionality of the Doherty amplifier. In this example (Fig. 2), most of the current is delivered by the peaking / Aux-amplifier and not the carrier / main-amplifier. This is also shown in the output power characteristics shown in FIG. 3. The carrier / main-amplifier delivery rate of power is decreased after it compresses and therefore limits operation of the peaking / Aux- amplifier’s ability to modulate the load (ZL, in FIG. 1). This is caused by feeding current in a way that increases the impedance seen by the quarter-wave-length transformation circuit between the ZL / Aux-amplifier and the output of the carrier / main-amplifier.

[0011] A Doherty amplifier at mm-Wave may be implemented using complementary metal oxide semiconductor (CMOS) technology, for example via a 22nm fully depleted silicon on insulator (FD-SOI) technology. Further, 3-stack amplifier structures may be used for both the main- and Aux-amplifier. This improves overall voltage handling of the amplifiers and may be implemented with all passives implemented on a chip. The most important passive components are 2 output transformers, 2 interstage matching transformers, 2 input transformers and a phase compensating function, implemented as a quadrature power splitter. Further, the Doherty amplifier operates with an impedance ratio of ZL / 2, and this will limit output power due to the breakdown-voltage / reliability of the power amplifier (PA) transistors. The linearity of the overall amplifier may be achieved using adaptive biasing, capacitive neutralization and an interstage matching inductor. Finally, the Doherty amplifier is shown in FIG. 4 with the overall system to the left and the 3 -stacked PA stage shown to the right.

[0012] In recent years, dynamic / adaptive amplitude modulation-amplitude modulation (AM- AM) distortion and amplitude modulation-phase modulation (AM-PM) distortion compensations have been shown. The main idea is to use an Amplitude Linearizer (AL) and a Phase Linearizer (PL), i.e., a transistor implementation of a parallel resistor and capacitor, controlled by an envelope detector, as shown in FIG. 5.

[0013] A main limitation of a Doherty amplifier is the limited load-modulation that may be achieved. This limits the maximum power that the carrier / main-amplifier may deliver, due to voltage compression, and this also reduces the reliability of the active devices used, due to breakdown-voltage. Further, in case of discrete active devices, a correlation to breakdownvoltage and price also exists. Therefore, to maximize the performance of an expensive device is important. Another limitation of a Doherty amplifier is the requirement to drive both the carrier / main- and peaking / Aux-amplifier with RF / mm-Wave signal power. This results in at least a doubling in drive requirements of the drivers and this also requires a phase compensating function with high precision and low loss. The phase compensating function must supply the correct signal with high precision to the peaking / Aux- amplifier. Finally, in a fully integrated Doherty amplifier, it is common that the carrier / main- and peaking / Aux-amplifier have individual drivers. It would be difficult to drive both amplifiers with a single driver, but not impossible. Improvements have been made in the load-modulation properties of the Doherty amplifier. Some improvements have been made to remove the driver and to remove or simplify the phase compensating function related to the peaking / Aux-amplifier. This will reduce the amount of extra hardware required for a Doherty amplifier function and also the requirement of system blocks that remain will have small to no effect on the overall performance, because they are unchanged.

[0014] For linearizers, a main limitation of dynamic linearizers is associated with their placement. If placed prior to the PA, driver capabilities will be limited, but if placed at the input of the PA driver, the compensation may be maintained, while a lower performance degradation is possible. Furthermore, another limitation of the present linearizes is that they are affected by the gate-bias voltage of the PA / driver, if connected to the gate of the PA / driver. This will limit the rate of the correction possible from the linearizer, this is mainly for a phase linearizer (P)L, which is affected by the voltage biasing of the devices.

[0015] SUMMARY

[0016] Some embodiments advantageously provide a Doherty power amplifier with a baseband controlled auxiliary amplifier.

[0017] Some embodiments include simplification of the conventional Doherty amplifier using less high-frequency and high-precision electronics. In some embodiments, a carrier / main- amplifier includes an improved Doherty style load-modulation with reduced hardware. In some embodiments, to further improve AM-PM linearity, a dynamic phase linearizer is positioned at the input of the driver, which may operate without the effects of the gate-bias voltage of the driver. To further improve the performance, in some embodiments, adaptive-biasing of the carrier / main- and peaking / Aux-amplifier may be used as well, and this enables improved performance and reliability. Improved reliability AM-AM and AM-PM distortion is strongly related to the improved load-modulation and the increase in gate-voltage by the adaptive-biasing.

[0018] Some embodiments include a Doherty style amplifier including a main amplifier with a quarter- wave-length impedance transformer, and a negative resistance baseband-controlled auxiliary amplifier. The negative resistance provided by the auxiliary amplifier is determined in relation to an input signal magnitude. The negative resistance of the auxiliary amplifier increases the load-modulation of the main amplifier and increase the output power, in some embodiments.

[0019] The negative resistance baseband-controlled auxiliary amplifier may be tuned for high peak-efficiency and improved back-off-efficiency. The negative resistance controls the impedance seen by the main amplifier output, which improves power gain, output-compression- point, and reliability of the complete amplifier.

[0020] In some embodiments, a PA driver may be used to drive the main amplifier with an AM- PM compensation circuit at the driver input. The AM-PM compensation is de-coupled from the driver input bias voltage, widening the range of the AM-PM compensation.

[0021] According to one aspect, a power amplifier is provided. The power amplifier includes a main amplifier configured to receive and amplify an input signal. The power amplifier also includes an impedance transformer having a transmission line, a reactive circuit element and / or a transformer, the impedance transformer configured to receive and couple the amplified input signal to an external load through an impedance transformation. The power amplifier further includes an auxiliary amplifier configured to provide a negative resistance responsive to an envelope of the input signal, the negative resistance being provided in parallel with a load impedance of the external load as seen at an output of the power amplifier.

[0022] According to this aspect, in some embodiments, the power amplifier includes a drive amplifier, configured to provide the input signal to the main amplifier. In some embodiments, the drive amplifier is configured to phase compensate the input signal to the main amplifier. In some embodiments, the power amplifier includes adaptive bias circuitry configured to provide amplitude modulation to amplitude modulation, AM-AM, and amplitude modulation to phase modulation, AM-PM, distortion compensation. In some embodiments, the adaptive bias circuitry operates at baseband. In some embodiments, the adaptive bias circuitry includes digital circuitry. In some embodiments, the power amplifier includes a first transformer between the drive amplifier and the main amplifier, the first transformer being center tapped, the center tap being coupled to the adaptive bias circuitry. In some embodiments, the adaptive bias circuitry is configured to receive the envelope of the input signal and to output a gate bias voltage responsive to the envelope of the input signal, the output gate bias voltage being input to the auxiliary amplifier. In some embodiments, the power amplifier includes a dynamic phase linearizer preceding the drive amplifier, the dynamic phase linearizer being configured to provide amplitude modulation to phase modulation, AM-PM, distortion compensation. In some embodiments, the dynamic phase linearizer is further configured to decouple the AM-PM distortion compensation from an input bias voltage of the drive amplifier. In some embodiments, the power amplifier includes a second transformer configured to put the dynamic phase linearizer and a drive amplifier input into resonance. In some embodiments, the negative resistance is configured to increase the impedance transformation by the impedance transformer when the negative resistance is activated and to not increase the impedance transformation by the impedance transformer when the negative resistance is not activated. In some embodiments, the negative resistance is configured to lower the load impedance. In some embodiments, the power amplifier includes a peak detector preceding the auxiliary amplifier and configured to detect the envelope of the input signal to produce a baseband envelope signal. In some embodiments, the power amplifier includes delay circuitry between the peak detector and the auxiliary amplifier, the delay circuitry being configured to align the baseband envelope signal with a signal waveform at an output of the auxiliary amplifier. In some embodiments, the external load includes an antenna. In some embodiments, the power amplifier includes control circuitry to activate and deactivate the negative resistance based at least in part on an output power of the power amplifier. In some embodiments, the auxiliary amplifier includes a cascode amplifier with controlled positive feedback. In some embodiments, the controlled positive feedback is provided at least in part by cross-coupling outputs of transistors to gates of the transistors, the gates of the transistors being coupled to the envelope of the input signal. In some embodiments, the controlled positive feedback is provided at least in part by one of capacitors and transformers coupled to the transistor gates and bias resistors coupled to the transistor gates and / or sources. In some embodiments, the main amplifier and the auxiliary amplifier are discrete components. In some embodiments, the negative resistance is based at least in part on a gate voltage of the main amplifier.

[0023] According to another aspect, a radio frequency, RF, front end. The RF front end includes at least one antenna and a power amplifier. The power amplifier includes a main amplifier configured to receive and amplify an input signal. The power amplifier includes an impedance transformer having a transmission line, a reactive circuit element and / or a transformer, the impedance transformer configured to receive and couple the amplified input signal to an external load through an impedance transformation. The power amplifier also includes an auxiliary amplifier configured to provide a negative resistance responsive to an envelope of the input signal, the negative resistance being provided in parallel with a load impedance of the external load as seen at an output of the power amplifier.

[0024] According to this aspect, in some embodiments, the RF front end includes a circulator coupled to an antenna port of the at least one antenna. In some embodiments, the at least one antenna is an array of antennas. In some embodiments, the RF front end includes a plurality of circulators, there being one circulator for each antenna port of the array of antennas. In some embodiments, the array of antennas include split transmit and receive antennas.

[0025] BRIEF DESCRIPTION OF THE DRAWINGS

[0026] A more complete understanding of the present embodiments, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

[0027] FIG. l is a block diagram of a known Doherty amplifier configuration;

[0028] FIG. 2 illustrates current behavior of a known Doherty amplifier configuration;

[0029] FIG. 3 illustrates output power behavior of a known Doherty amplifier configuration;

[0030] FIG. 4 is a schematic of a known Doherty amplifier configuration;

[0031] FIG. 5 is a schematic of an amplitude linearizer, phase linearizer and envelope detector;

[0032] FIG. 6 is a schematic diagram of an example network architecture illustrating a communication system according to principles disclosed herein;

[0033] FIG. 7 is a block diagram of a network node in communication with a wireless device over a wireless connection according to some embodiments of the present disclosure;

[0034] FIG. 8 is a block diagram of one embodiment for providing negative resistance in the negative resistance Doherty amplifier (NRDA);

[0035] FIG. 9 is an example of an NRDA that includes a main amplifier and a baseband controlled auxiliary amplifier;

[0036] FIG. 10 is one example implementation of an auxiliary amplifier constructed in accordance with principles disclosed herein to provide negative resistance;

[0037] FIG. 11 is another example implementation of an auxiliary amplifier constructed in accordance with principles disclosed herein;

[0038] FIG. 12 is a schematic of one embodiment of an NRDA;

[0039] FIG. 13 is a 3-stack amplifier with all the back-gates connected to GND;

[0040] FIG. 14 is one example of a driver amplifier;

[0041] FIG. 15 is one example of a phase linearizer;

[0042] FIG. 16 is a graph of results of a simulation at a center frequency of 26.75 GHz;

[0043] FIG. 17 is simulated performance at 26.75 GHz;

[0044] FIG. 18 illustrates AM- AM and AM-PM distortion;

[0045] FIG. 19 illustrates the AM-PM behavior of the active amplifiers; FIG. 20 are example output waveforms of voltages for an NRDA constructed according to principles disclosed herein;

[0046] FIG. 21 are example output waveforms of currents for an NRDA constructed according to principles disclosed herein;

[0047] FIG. 22 illustrates output power contributions from a main amplifier and an auxiliary amplifier;

[0048] FIG. 23 illustrate total power consumption and power consumption for different amplifiers;

[0049] FIG. 24 is a frequency response of an NRDA as disclosed herein for three different input powers;

[0050] FIG. 25 is an another example of an NRDA constructed according to principles disclosed herein;

[0051] FIG. 26 is yet another example of an NRDA constructed according to principles disclosed herein using discrete components;

[0052] FIG. 27 is an example of a known Doherty amplifier configuration used for comparison to the NRDA of FIGS. 12 and 25;

[0053] FIG. 28 is a comparison of an NRDA disclosed herein and a known Doherty amplifier;

[0054] FIG. 29 is a higher order implementation of an NRDA according to principles disclosed herein; and

[0055] FIG. 30 is an example higher order NRDA circuit.

[0056] DETAILED DESCRIPTION

[0057] Before describing in detail exemplary embodiments, it is noted that the embodiments reside primarily in combinations of apparatus components and processing steps related to a Doherty power amplifier with a baseband controlled auxiliary amplifier. Accordingly, components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

[0058] As used herein, relational terms, such as “first” and “second,” “top” and “bottom,” and the like, may be used solely to distinguish one entity or element from another entity or element without necessarily requiring or implying any physical or logical relationship or order between such entities or elements. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts described herein. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and / or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0059] In embodiments described herein, the joining term, “in communication with” and the like, may be used to indicate electrical or data communication, which may be accomplished by physical contact, induction, electromagnetic radiation, radio signaling, infrared signaling or optical signaling, for example. One having ordinary skill in the art will appreciate that multiple components may interoperate and modifications and variations are possible of achieving the electrical and data communication.

[0060] In some embodiments described herein, the term “coupled,” “connected,” and the like, may be used herein to indicate a connection, although not necessarily directly, and may include wired and / or wireless connections. For example, connected or coupled may mean electrically connected or electrically coupled,

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts described herein. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and / or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0062] The term “network node” used herein may be any kind of network node comprised in a radio network which may further comprise any of base station (BS), radio base station, base transceiver station (BTS), base station controller (BSC), radio network controller (RNC), g Node B (gNB), evolved Node B (eNB or eNodeB), Node B, multi-standard radio (MSR) radio node such as MSR BS, multi-cell / multicast coordination entity (MCE), relay node, donor node controlling relay, radio access point (AP), transmission points, transmission nodes, Remote Radio Unit (RRU) Remote Radio Head (RRH), a core network node (e.g., mobile management entity (MME), self-organizing network (SON) node, a coordinating node, positioning node, MDT node, etc.), an external node (e.g., 3rdparty node, a node external to the current network), nodes in distributed antenna system (DAS), a spectrum access system (SAS) node, an element management system (EMS), etc. The network node may also comprise test equipment. The term “radio node” used herein may be used to also denote a wireless device (WD) such as a wireless device (WD) or a radio network node.

[0063] In some embodiments, the non-limiting terms wireless device (WD) or a user equipment (UE) are used interchangeably. The WD herein may be any type of wireless device capable of communicating with a network node or another WD over radio signals, such as wireless device (WD). The WD may also be a radio communication device, target device, device to device (D2D) WD, machine type WD or WD capable of machine to machine communication (M2M), low-cost and / or low-complexity WD, a sensor equipped with WD, Tablet, mobile terminals, smart phone, laptop embedded equipped (LEE), laptop mounted equipment (LME), USB dongles, Customer Premises Equipment (CPE), an Internet of Things (loT) device, or a Narrowband loT (NB-IOT) device etc.

[0064] Also, in some embodiments the generic term “radio network node” is used. It may be any kind of a radio network node which may comprise any of base station, radio base station, base transceiver station, base station controller, network controller, RNC, evolved Node B (eNB), Node B, gNB, Multi-cell / multicast Coordination Entity (MCE), relay node, access point, radio access point, Remote Radio Unit (RRU) Remote Radio Head (RRH).

[0065] Note that although terminology from one particular wireless system, such as, for example, 3GPP LTE and / or New Radio (NR), may be used in this disclosure, this should not be seen as limiting the scope of the disclosure to only the aforementioned system. Other wireless systems, including without limitation Wide Band Code Division Multiple Access (WCDMA), Worldwide Interoperability for Microwave Access (WiMax), Ultra Mobile Broadband (UMB) and Global System for Mobile Communications (GSM), may also benefit from exploiting the ideas covered within this disclosure.

[0066] Note further, that functions described herein as being performed by a wireless device or a network node may be distributed over a plurality of wireless devices and / or network nodes. In other words, it is contemplated that the functions of the network node and wireless device described herein are not limited to performance by a single physical device and, in fact, may be distributed among several physical devices.

[0067] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0068] Some embodiments are directed to a negative resistance Doherty amplifier (NRDA) that includes a baseband controlled auxiliary amplifier. The NRDA replaces the classical auxiliary amplifier by a negative resistance, which is controlled by a baseband envelope of an input signal of the NRDA. This means that the auxiliary amplifier will enhance the Doherty style loadmodulation for the main-amplifier and furthermore, the auxiliary amplifier will not require a high frequency input signal and a phase compensating function at the input, all that is required is a time-aligned baseband envelope representation. The enhance load-modulation from the negative resistance will improve the performance, reliability and reduce complexity of this Doherty based amplifier, by increasing the load impedance ZL, which results in a much lower impedance seen by the output of the main PA. To further improve the AM- AM and AM-PM, adaptive-biasing and a dynamic phase linearizer is used, adaptive-biasing is used for the main- and negative resistance-PA and the dynamic phase linearizer is placed at the input of the PA driver, to give an overall improvement without any severe performance degradation. This improves the linearity of the whole system and compensates for the non-linear behavior of a Doherty amplifier.

[0069] Returning again to the drawing figures in which like elements are referred to by like reference numerals, there is shown in FIG. 6 a schematic diagram of a communication system 10, according to an embodiment, such as a 3 GPP -type cellular network that may support standards such as LTE and / or NR (5G), which comprises an access network 12, such as a radio access network, and a core network 14. The access network 12 comprises a plurality of network nodes 16a, 16b, 16c (referred to collectively as network nodes 16), such as NBs, eNBs, gNBs or other types of wireless access points, each defining a corresponding coverage area 18a, 18b, 18c (referred to collectively as coverage areas 18). Each network node 16a, 16b, 16c is connectable to the core network 14 over a wired or wireless connection 20. A first wireless device (WD) 22a located in coverage area 18a is configured to wirelessly connect to, or be paged by, the corresponding network node 16a. A second WD 22b in coverage area 18b is wirelessly connectable to the corresponding network node 16b. While a plurality of WDs 22a, 22b (collectively referred to as wireless devices 22) are illustrated in this example, the disclosed embodiments are equally applicable to a situation where a sole WD is in the coverage area or where a sole WD is connecting to the corresponding network node 16. Note that although only two WDs 22 and three network nodes 16 are shown for convenience, the communication system may include many more WDs 22 and network nodes 16. Also, it is contemplated that a WD 22 may be in simultaneous communication and / or configured to separately communicate with more than one network node 16 and more than one type of network node 16. For example, a WD 22 may have dual connectivity with a network node 16 that supports LTE and the same or a different network node 16 that supports NR. As an example, WD 22 may be in communication with an eNB for LTEZE-UTRAN and a gNB for NR / NG-RAN.

[0070] A network node 16 (eNB or gNB) is Configured to include a network node (NN) negative resistance Doherty amplifier (NDRA) 24 which is configured to provide a negative resistance in parallel with a load impedance of the external load as seen at an output of the power amplifier. A wireless device 22 is configured to include a WD NRDA 26 which is configured to provide a negative resistance in parallel with a load impedance of the external load as seen at an output of the power amplifier.

[0071] Example implementations, in accordance with an embodiment, of the WD 22 and network node 16 discussed in the preceding paragraphs will now be described with reference to FIG. 2.

[0072] The communication system 10 includes a network node 16 provided in a communication system 10 and including hardware 28 enabling it to communicate with the WD 22. The hardware 28 may include a radio interface 30 for setting up and maintaining at least a wireless connection 32 with a WD 22 located in a coverage area 18 served by the network node 16. The radio interface 30 may be formed as or may include, for example, one or more RF transmitters, one or more RF receivers, and / or one or more RF transceivers. The radio interface 30 includes an array of antennas 34 to radiate and receive signal(s) carrying electromagnetic waves. The radio interface 30 is configured to include a network node (NN) negative resistance Doherty amplifier (NDRA) 24 which is configured to provide a negative resistance in parallel with a load impedance of the external load as seen at an output of the power amplifier.

[0073] In the embodiment shown, the hardware 28 of the network node 16 further includes processing circuitry 36. The processing circuitry 36 may include a processor 38 and a memory 40. In particular, in addition to or instead of a processor, such as a central processing unit, and memory, the processing circuitry 36 may comprise integrated circuitry for processing and / or control, e.g., one or more processors and / or processor cores and / or FPGAs (Field Programmable Gate Array) and / or ASICs (Application Specific Integrated Circuitry) adapted to execute instructions. The processor 38 may be configured to access (e.g., write to and / or read from) the memory 40, which may comprise any kind of volatile and / or nonvolatile memory, e.g., cache and / or buffer memory and / or RAM (Random Access Memory) and / or ROM (Read-Only Memory) and / or optical memory and / or EPROM (Erasable Programmable Read-Only Memory).

[0074] Thus, the network node 16 further has software 42 stored internally in, for example, memory 40, or stored in external memory (e.g., database, storage array, network storage device, etc.) accessible by the network node 16 via an external connection. The software 42 may be executable by the processing circuitry 36. The processing circuitry 36 may be configured to control any of the methods and / or processes described herein and / or to cause such methods, and / or processes to be performed, e.g., by network node 16. Processor 38 corresponds to one or more processors 38 for performing network node 16 functions described herein. The memory 40 is configured to store data, programmatic software code and / or other information described herein. In some embodiments, the software 42 may include instructions that, when executed by the processor 38 and / or processing circuitry 36, causes the processor 38 and / or processing circuitry 36 to perform the processes described herein with respect to network node 16.

[0075] The communication system 10 further includes the WD 22 already referred to. The WD 22 may have hardware 44 that may include a radio interface 46 configured to set up and maintain a wireless connection 32 with a network node 16 serving a coverage area 18 in which the WD 22 is currently located. The radio interface 46 may be formed as or may include, for example, one or more RF transmitters, one or more RF receivers, and / or one or more RF transceivers. The radio interface 46 includes an array of antennas 48 to radiate and receive signal(s) carrying electromagnetic waves. The radio interface 46 also includes the WD NRDA 26 which is configured to provide a negative resistance in parallel with a load impedance of the external load as seen at an output of the power amplifier.

[0076] The hardware 44 of the WD 22 further includes processing circuitry 50. The processing circuitry 50 may include a processor 52 and memory 54. In particular, in addition to or instead of a processor, such as a central processing unit, and memory, the processing circuitry 50 may comprise integrated circuitry for processing and / or control, e.g., one or more processors and / or processor cores and / or FPGAs (Field Programmable Gate Array) and / or ASICs (Application Specific Integrated Circuitry) adapted to execute instructions. The processor 52 may be configured to access (e.g., write to and / or read from) memory 54, which may comprise any kind of volatile and / or nonvolatile memory, e.g., cache and / or buffer memory and / or RAM (Random Access Memory) and / or ROM (Read-Only Memory) and / or optical memory and / or EPROM (Erasable Programmable Read-Only Memory).

[0077] Thus, the WD 22 may further comprise software 56, which is stored in, for example, memory 54 at the WD 22, or stored in external memory (e.g., database, storage array, network storage device, etc.) accessible by the WD 22. The software 56 may be executable by the processing circuitry 50. The software 56 may include a client application 58. The client application 58 may be operable to provide a service to a human or non-human user via the WD 22.

[0078] The processing circuitry 50 may be configured to control any of the methods and / or processes described herein and / or to cause such methods, and / or processes to be performed, e.g., by WD 22. The processor 52 corresponds to one or more processors 52 for performing WD 22 functions described herein. The WD 22 includes memory 54 that is configured to store data, programmatic software code and / or other information described herein. In some embodiments, the software 56 and / or the client application 58 may include instructions that, when executed by the processor 52 and / or processing circuitry 50, causes the processor 52 and / or processing circuitry 50 to perform the processes described herein with respect to WD 22.

[0079] In some embodiments, the inner workings of the network node 16 and WD 22 may be as shown in FIG. 7 and independently, the surrounding network topology may be that of FIG. 6.

[0080] The wireless connection 32 between the WD 22 and the network node 16 is in accordance with the teachings of the embodiments described throughout this disclosure. More precisely, the teachings of some of these embodiments may improve the data rate, latency, and / or power consumption and thereby provide benefits such as reduced user waiting time, relaxed restriction on file size, better responsiveness, extended battery lifetime, etc. In some embodiments, a measurement procedure may be provided for the purpose of monitoring data rate, latency and other factors on which the one or more embodiments improve.

[0081] Note that processor 38, 52 may be implemented such that a portion of the unit is stored in a corresponding memory within the processing circuitry. In other words, the units may be implemented in hardware or in a combination of hardware and software within the processing circuitry.

[0082] Having described the general process flow of arrangements of the disclosure and having provided examples of hardware and software arrangements for implementing the processes and functions of the disclosure, the sections below provide details and examples of arrangements for a Doherty power amplifier with a baseband controlled auxiliary amplifier.

[0083] Proposed Circuits and Systems with Simulations

[0084] FIG. 8 is a block diagram of one embodiment for providing negative resistance in the negative resistance Doherty amplifier (NRDA) 24, 26. The NDRA 24, 26 has a current source Imain, representing the main amplifier 60, an impedance transformer 62, which may be a quarterwave-length transformation circuit shown as the X / 4 stub, and a negative resistance amplifier 64 represented as the variable resistor -R. In the drawing figures that follow, the impedance transformer 62 will be labeled as a X / 4 stub, it is to be understood that other impedance transformation circuitry or transmission line configurations may be implemented, instead of or in addition to the X / 4 stub, to achieve an impedance transformation in accordance with principles disclosed herein. The NRDA 24, 26 is electrically coupled to a load impedance 66 represented as the resistor RL. The load impedance 66 may be the impedance present at a port of an antenna 34, 48, for example. When output power is low, the negative resistance 64 may be turned OFF and the current source iMain (main amplifier 60) sees the resulting impedance of the load impedance 66. As the output power increases to a medium or high level, the negative resistance 64 may be activated. Then, as R increases, the impedance presented at the output of the impedance transformer 62 by the parallel combination of -R and RL increases. When this parallel impedance is high, a transformation from the high impedance to a low impedance is performed by the impedance transformer 62. This presents a low impedance to the output of the main amplifier 60, which creates a more ideal current interface between the current source IMain and the impedance transformer 62 and further reduces the voltage swing across the current source IMain. However, the voltage across -R and RL will increase further, the voltage across RL is wanted, but the voltage across -R may require implementation of a transformer (as shown in FIG. 12, TA 100) will require some additional consideration during implementation.

[0085] FIG. 9 is another embodiment of a NRDA 24, 26 that includes a main amplifier 60 and a baseband controlled auxiliary amplifier 68. In FIG 9, an input signal (Pin) is fed to the main amplifier 60 (Gwain) and to a Peak-Detector (PD) 70 , the PD 70 output is the envelope of the input signal, which is then time-aligned by the delay 72 (T), to the match the signal waveform at the output of the auxiliary amplifier GAUX 68. The main amplifier Gwain 60 is connected to impedance transformer 62, which may be a X / 4 transformer. The impedance transformer 62 may be electrically connected to both the output of the auxiliary amplifier 68 GAUX and a load 66, which in the example of FIG. 9 is shown as an antenna 34, 48.

[0086] FIG. 10 is one example implementation of the auxiliary amplifier 68 constructed in accordance with principles disclosed herein to provide negative resistance 64. The auxiliary amplifier 68 of FIG. 10 is a 2-stack version of a cascode amplifier with controlled positive feedback. The output of the auxiliary amplifier 68 is labeled “To Load,” The transformer TA 74 may be a voltage step-up transformer and may function to improve the reliability of auxiliary amplifier GAUX 68. A gain and drive of this type of amplifier is high, due to the positive feedback. The positive feedback is implemented by the cross-coupling at the output to the inputs / gates of the Common-Source (CS) transistors MAJ 76. The feedback network consists of the gate capacitors Cg78, the bias resistors Rg80, and the total gate-capacitance Cggof the common source transistors MAJ 76. The feedback-factor may be statically controlled by the ratio of Cg78 and Cgg, and the bias resistors Rg80 are used to feed the baseband envelope representation (Vil) to the gates of MAJ 76 This feedback is used as a dynamic control of the feedback-factor, by varying the gain Gmof MAJ 76. FIG. 11 is another example implementation of the auxiliary amplifier 68 constructed in accordance with principles disclosed herein.

[0087] The cascode / Common-Gate (CG) transistors MA, 2 82 are used to improve the total breakdown-voltage of GAUX and MA, 282 is biased by the voltage Vc.

[0088] FIG. 12 is a schematic of one embodiment of an NRDA 24, 26. An input of the NRDA 24, 26 may be modeled as an input resistance Rs 84 and input source Vs86. The input signal from Vs 86 is sensed with a PD 70 which detects an envelope of the input signal. This envelope provided as a voltage VEnveiope to the adaptive bias system 88. The adaptive bias system 88 enables control of different adaptive bias control functions described herein. These adaptive bias control functions may be implemented in baseband and / or in the digital domain. For example, at least one or more adaptive bias control functions may be performed by digital signal processing circuitry.

[0089] In some embodiments, the control signals in digital form may be input to a digital-to- analog converter (DAC). A purely analog or digital approach may be preferred.

[0090] Returning to the input signal shown as being provided by the input source Vs86 is an input one-to-one (1 : 1) transformer Tin 90. The input transformer Tin 90 is used provide an input to a driver amplifier (Goriver) 92 and to drive the input of the driver amplifier 92 and a dynamic phase linearizer (Cdyn) 94 into resonance. Note that conjugate matching may also be performed. The driver amplifier Goriver 92 may be biased by a static bias voltage (VGB,D). This voltage may be changed, but normally not in a dynamic fashion, i.e., not during normal operation. For example, the static bias voltage VGB,D may be change for the use of different frequency bands. The dynamic phase linearizer Cdyn 94 is controlled by a voltage Vun, which has a relation to the input / output-power and is set, so the dynamic phase linearizer Cdyn 94 compensates for AM-PM distortion, primarily when the Doherty functionality is enabled. The driver amplifier Goriver 92 is connected to a two-to-one (2: 1) transformer (TD) 96. Transformer TD 96 up-transforms the input impedance of the main amplifier 60 to a higher impedance. The signal voltage at the output of the driver amplifier Goriver 92 is stepped-down to a lower signal voltage. The signal current output by the driver amplifier GDriver92 is stepped-up. Finally, the driver amplifier Goriver 92 is provided with a supply voltage (VDDJ) through a center-tap of the primary of the transformer TD 96. The supply voltage VDDJ is a lower voltage than a voltage fed to the main amplifier 60 and the auxiliary amplifier 68. The main amplifier (GMain) 60 is gate-biased with an adaptive-bias voltage VGB.M, fed to a center-tap of the secondary of the transformer TD 96. This gate biasing configuration may improve the AM-AM distortion compensation, AM-PM distortion compensation, and reliability of the main amplifier GMain 60. An output one-to-one (1 : 1) transformer (TM) 98 receives the output of the main amplifier GMain 60. A purpose of transformer TM 98 is to keep the output voltage of the main amplifier GMain 60 at a reliable, desired or predictable level notwithstanding the Doherty load-modulation functionality of the X / 4 stubs, even at the maximum output power (Psat). Therefore no step-up transformer is required. The output primary of the transformer (TM) 98 has a center-tap to feed a high supply voltage (VDD,2) to the main amplifier G ain 60. The voltage VDD,2 is set by the break-down voltage of transistors of the main amplifier G ain 60 and the number of stacked transistors in the main amplifier GMain 60. The impedance transformers 62 may be X / 4 stubs with Zo=5O Q. The impedance transformers 62 may be implemented with transmission-lines (T-line), transformers and / or with a lumped element circuit. The outputs of the impedance transformers 62 are electrically connected across the load resistance RL 66. The output the outputs of the auxiliary amplifier GAUX 68 are input to a one-to-two (1 :2) transformer (TA) 100. The secondary of the transformer TA 100 is electrically connected across the load resistance RL 66. In some embodiments, circuit elements for matching of the load resistance RL 66 may be included. The transformer TA 100 is a voltage step-up transformer and an impedance down-transformer, as seen from the output of the auxiliary amplifier GAUX 68. However, as seen from the output of the NRDA 24, 26, the transformer TA 100 is a voltage step-down and an impedance up-transformer. This minimizes the loading of the output of the NRDA 24, 26. As the load-modulation of the load seen by the main amplifier GMain 60 decreases the output load of GMain, the voltage across the load resistance RL 66 and the secondary of the transformer TA 100 becomes very high, due to the voltage step-up by the impedance transformer 62. Therefore, the voltage step-down of transformer TA 100 from secondary to primary improves reliability of the transistors of the auxiliary amplifier GAUX 68. Also, because the auxiliary amplifier GAUX 68 is a cross-coupled circuit, power gain, drive capabilities, and stability is a different design concern. It is known that a cross-coupled circuit requires smaller transistors for a given output power. The gate-bias voltage (VGB,A), which depends on the envelope of the input signal from the peak detector 70 and the compression behavior of the main amplifier GMain 60. The gate bias voltage VGB.A controls the gain, output power, and negative resistance of the auxiliary amplifier GAUX 68. The additional components used to control the auxiliary amplifier GAUX 68 are Rg80 and Cg78. Cg78 is part of a capacitive voltage-divider with the input capacitance Cggof the auxiliary amplifier GAUX 68 and Rg80 is a bias resistor that isolates high-frequency voltage from the low-frequency voltage.

[0091] Examples of active circuits shown in FIGS. 13, 14 and 15. The circuit used for the main and auxiliary amplifiers are shown in FIG. 13. FIG. 13 is a 3-stack amplifier with all the back- gates connected to GND. This gives other values for the threshold-voltage (Vth). Further, the CS- stage Mi 102 has its gate connected to a differential input signal that is referred to signal -ground (GND). The drain of Mi 102 is connected to the source of the first cascode device M2, 104 which in its turn has its gate connected to a passive network consisting of the capacitor Cc,i 106 and the resistor Rc.i, 108 which is connected to the cascode-bias voltage Vc,i and the drain of M2 104 is connected to the source of the second cascode M3 110. The drain of M3 110 is connected to the output / transformer 74 and the gate of M3 110 is connected to the same type of passive network as M2 104 but the capacitance value (Cc,2) 112 is different and the resistor Rc,2 114 is connected to a different bias-voltage Vc,2. This passive network is designed to divide the voltage swing in the OFF-state (Mi 102, M2 104, and M3 110 are all OFF on one side of the circuit) evenly over the devices and supply the gates with the right amount of voltage in the ON-state. The driver amplifier 92 is shown in FIG. 14, and is a classic cascode amplifier with a CS-stage (Mi) 116 and a CG-stage (M2) 118. M2 118 is gate-biased with a voltage Vc.

[0092] Also, the input of the driver amplifier 92 is connected to a dynamic phase linearizer 94, as shown in FIG. 15. The dynamic phase linearizer 94 includes two transistors, depicted as Mi 120. The gates of these transistors are connected a DC-block CDC 122and a bias resistor RDC 124 connected to a baseband control voltage (Vi in 1), and finally drain and source are connected to an additional baseband control voltage (Vi in ?). These baseband control voltages are generated in the adaptive-biasing system 88 shown in FIG. 12 and may be used to turn ON or OFF the Mi transistors 120 for different amounts of the RF-period. Like a varactor, these baseband control voltages may be used in a differential, sequential, and / or overlapping manner.

[0093] Parameters used for the simulations of the NRDA are shown in Table 1. Transformer (analogLib mind and ind) k=0.85 and all transistor back-gates are connected to GND (=0V) and are Super-low Vt NFETs with the “Metallization option” C3.

[0094] Table 1

[0095] FIG. 16 is a graph of results of a simulation at a center frequency of 26.75 GHz, the voltage functions for the adaptive-bias voltages are shown. The VGB.A, that controls the gate-bias voltage of the auxiliary amplifier GAUX 68 at low input powers is low and was kept at OV, VGB,A<0 may also be used. At higher input power than -14 dBm, the voltage increases in order to control the negative resistance of the auxiliary amplifier GAUX 68. At a highest input power, the voltage VGB,A=0.4 V is chosen to maintain maximum system power added efficiency (PAE) at highest output powers. Further, the adaptive gate-bias voltage of the main amplifier Gwain 60, VGB.M, is used to improve the AM-AM, the AM-PM, PAE, and the reliability of the main amplifier Gwain 60. The voltage VGB.M is kept close to Vth (-0.26 V) for class AB operation at low input powers and is increased to 0.41 V for the top 4-6 dB of the input power. The maximum input power used is approx. 0 dBm. For the control voltages for the phase-linearizer, Vi in i and Vi in ?, are, differential signals, but some embodiments are not limited to this type of signal characteristics. The same is true for VGB.A and VGB.M. For example, signals may be independent of each other and a more complex signal distribution may be beneficial. In this case, Viin i and Vi in ? show the most non-linear behavior of all the control signals. But this is mainly because a power amplifier shows a very non-linear phase behavior. By including the phase-linearizer, it is proven that the NRDA 24, 26 may be linearized without Digital-Pre-Distortion (DPD). The voltages Vi in i and may be selected so the transistors of FIG. 15 are biased in the OFF- region at low input powers. This means that the minimum gate capacitance Cggis present at the gate, during an entire signal period. The transistors are turned off during low output power and turned ON for a greater portion of the signal period as the output power increases. This results in a higher gate capacitance over the entire signal period. For these simulations of the NRDA 24, 26 disclosed herein, polynomials functions of Pin are used for VGB.A (1) and VGB.M (2), while the Viin i and Viin ? were developed with experimentation.

[0096] VGB>A= 0.0005P;3n+ 0.015P2n+ 0.1826P / n+ 0.943 (la)

[0097] 0 V < VGB A< 0.4 V (lb)

[0098] VGB>M= -0.0007P;4n- 0.0015P;3n+ 0.1083P;2n+ 0.9177P / n+ 2.4458

[0099] (2a)

[0100] 0.26 V < VGBiM< 0.41 V (2b)

[0101] The simulated performance at 26.75 GHz is shown in FIG. 17, the peak output power (Psat) is 26.5 dBm and the power gain is approx. 30 dB. By observing the input-referred 1 dB compression-point ICPidB, it is at an input power of -2.4 dBm, while the output power is 26.3 dBm, which is very close to Psat. The system PAE is 35.5 % at ICPidB and is at 27.2 % at 6 dB back-off, at -8 dBm, if a peak input power of -2 dBm is assumed. If only the PAE of the PAs, Guam 60 and GAUX 68 are observed, then the PAE is 37.8 % at ICPidB and is at 30.6 % at 6 dB back-off, while operating with the same peak input power.

[0102] In FIG. 18, the AM- AM and AM-PM distortion is shown. The AM- AM distortion is minimized by selection of the adaptive-bias voltage for Giuain 60 and GAUX 68 as well as the Doherty functionality and the linearization of the AM-PM distortion is performed by the phase- linearizer 94. Furthermore, the AM-AM below the ICPidB is less than 0.6 dB and is dominated by the gain compression at high output power. A comparison between the original AM-PM and the linearized AM-PM is shown and the improvement from a peak AM-PM of 20.5 deg error to a linearized AM-PM of 2.9 deg is achieved. Additionally, the resulting AM-PM behavior and the AM-PM behavior of the active amplifiers are shown in FIG. 19. This verifies the improved functionality / range of the phase-linearizer 94, which may improve a very large AM-PM, while not degrading the AM-AM.

[0103] The output waveforms of the voltages and the currents are shown in FIGS. 20 and 21, where FIG. 20 is the voltage and FIG. 21 is the current. Further, in FIG. 20 the voltage across the load RL increases with input power, until the PAs reaches saturation, and the behavior of the voltages show some load-modulation from the impedance transformer 62. The load-modulation is most apparent for Viuain-PA, the voltage across the primary of the transformer TM 98, at an input power of -7 dBm and until the input power where the auxiliary amplifier 68 begins to compress.

[0104] In addition, the voltage across the primary of the transformer TA 100 VAUX-PA, increases until the auxiliary amplifier 68 reaches saturation. This may also be observed from the currents shown in FIG. 21, by looking at the output current of the impedance transformer 62. This is the behavior of the load-modulation and the main amplifier 60 sees a lower load impedance. The output power contributions from the main amplifier 60 and the auxiliary amplifier 68, and the drain efficiency (q) of the main- and auxiliary amplifier are all shown in FIG. 22. By reflecting over these four curves, it shows that the main amplifier 60 delivers power to the load for the whole power range, but as the main amplifier 60 starts to compress, the auxiliary amplifier 68 starts to operate and supplies extra power to the load. When P0Ut,Main-PA and Pout, AUX-PA are approximately equal, the power delivered from the main amplifier 60 increases. The drain efficiency of the main amplifier 60 and the auxiliary amplifier 68 shows that the efficiency of the auxiliary amplifier 68 is 6 p.p. (percent points) higher, the main reason is that the auxiliary amplifier 68 does not require a driver, which will consume extra power. This is shown by the drain efficiency of the main amplifier 68, which also includes the power consumption of the driver amplifier 92.

[0105] Furthermore, the total power consumption and the power consumption of all the different amplifiers are shown in FIG. 23. The peak total power consumption is approx. 1.2 W, while the main amplifier 60 consumes 0.66 W, the auxiliary amplifier 68 consumes 0.5 W, and the driver consumes 72 mW.

[0106] Note that all transistor drain-source voltages (Vds) may be kept at or below 1.6 V when the NRDA 24, 26 is at the compression-point, which reflects a performance and reliability tradeoff. This also makes it easier to benchmark the proposed solution with a known Doherty PA. In addition, all gate-source voltages (Vgs) may be kept below 850 mV, in order to maintain a desired level of reliability. The NRDA 24, 26 was also simulated with a PA supply voltage of 2.4 V, to further improve the reliability / The performance degradation was 0.5 dB for the output power and 0.3 p.p for the PAE.

[0107] In addition, a simulation was run with only the main amplifier 60 connected through the X / 4 stub 62 to RL 66, to verify the improvements achieved for the disclosed NRDA 24, 26. The performance is limited by the transistor reliability of the main amplifier 60 and for an equivalent transistor Vds of 1.6 V, the maximum input power is -8 dBm. This gives the following peak performance: an output power of 20.2 dBm, a 28.3 dB power gain, and a system PAE of 24.7 %. When the load modulation of the disclosed NRDA 24, 26 is extended to higher output powers, then the output power may be further improved. Also, the reliability of the main amplifier 60, which may be driven harder without the risk of exceeding the breakdown of the individual transistors in the amplifier, is improved.

[0108] Frequency Response of the Proposed Solution

[0109] FIG. 24 shows a frequency response of the NRDA 24, 26 for three different input powers to show that the solution may cover the whole 28GHz-band (24 GHz-30 GHz). Additional Embodiments

[0110] In some embodiments, to control the auxiliary amplifier 68 with envelope feedback, an operational amplifier (OpAamp) (AEFB) 134 and a PD 136 at the output of the auxiliary amplifier 68 may be used as shown in FIG. 25. Envelope feedback may ensure that the power gain of the NRDA 24, 26 is constant, so that the voltage signal levels are measured at the input and output. A loop that includes the auxiliary amplifier 68, OpAamp 134 and PD 136 may ensure that the input-output ratio of the NRDA 24, 26 is the same for all input powers. If the gain is decreased in the main amplification path (Gwain 60 and GDriver92), then the negative resistance 64 is increased, in order to compensate for the lack of power gain from the main amplification path.

[0111] Many Doherty amplifiers used today for macro base stations use discrete transistors and discrete passive components. The RF performance of these types of solutions are very high and include advanced digital predistortion (DPD) algorithms but are mainly used with the FRl / Sub-6 GHz frequency bands. Some embodiments disclosed herein may be implemented with discrete components, as shown in FIG. 26, which is appropriate for implementation with discrete components. This system consists of an input matching network (MNi) 138, a main-amplifier MOSFET (MM) 140, a main-amplifier matching network (MNM) 142, the / 4 stub 62, a Colpitts oscillator 144, and an output / antenna matching network (MNA) 146. The Colpitts oscillator 144 includes the RF-Choke (RFC2) 148, a feedback network, consisting of Li, Ci, and C2, and the auxiliary amplifier MOSFET (MA) 150. Furthermore, the gate voltage of MA 150 is used to control the negative resistance 64 of the auxiliary amplifier 68. The discrete component circuit of FIG. 26 may have the same functionality as in embodiments where some or all components are integrated. Other ways to implement the negative resistance auxiliary amplifier 68 is to use other oscillator-topologies or by implementing a phase-shift, which ensures that the gate-source voltage and the signal at the drain is out-of-phase for MA 150. Basically, any non-stable amplifier may be used if the behavior / negative resistance may be controlled by a baseband signal. Comparison with Traditional Doherty Amplifier

[0112] The Doherty amplifier circuit shown in the example of FIG. 27 was simulated using the parameters shown in Table 2. To achieve the best comparison, transistor values are kept the same, and both a traditional and proposed Doherty amplifiers are operated with the same adaptive bias settings. However, the output transformer of the traditional auxiliary amplifier is re-tuned to resonance, resulting in a lower turn-ratio. Furthermore, the driver chain for the traditional auxiliary amplifier is kept the same as for the main amplifier chain and this has a small impact on the final result, in comparison to the topology.

[0113] Table 2: Simulation parameters for the Trad. Doherty PA, k=0.85 for all Transformers

[0114] In FIG. 28, the comparison between the disclosed NRDA 24, 26 and a traditional Doherty PA is shown, simulated at 26.75 GHz. The simulated NRDA 24, 26 has a 0.65 dB higher output power, and has approximately 4 p.p. higher PAE. Note that the main amplifier in the traditional system has more than 10% higher signal voltage levels than when used with the NRDA 24, 26, e.g., when compared at the compression point.

[0115] Additional Embodiments

[0116] Some embodiments include a higher order circuit, an example of which is shown in FIG. 29, where two stages of impedance transformation and negative resistance are provided. Higher orders may be implemented. One example of the higher order amplifier system of FIG. 29 (FIG. 29 shows negative resistance 64 as 64a and 64b). is shown in FIG. 30 where 2 stubs (X / 4) 62a and 62b and 2 baseband controlled auxiliary amplifiers 68a and 68b (GAUXI and GAUX2).

[0117] Additional matching circuitry may be implemented, include circuitry for filtering, harmonic-tuning, and circuit-biasing.

[0118] Some embodiments may include one or more of the following:

[0119] A power amplifier circuit and methods associated for communication, the power amplifier circuit comprising:

[0120] Embodiment 1. An individual amplifier comprising at least a. A main amplifier, consisting of active components and passive circuit elements. b. An impedance transformer, consisting of a transmission line, a reactive circuit element and / or a transformer. c. An auxiliary amplifier, consisting of a negative resistance.

[0121] Embodiment 2. Embodiment 1, and where: a. A drive amplifier, supplying signal power to (Embodiment la) b. The drive amplifier, consisting of active components and passive circuit elements. c. The drive amplifier input, includes a phase-compensation, consisting of active components and passive circuit elements. d. The auxiliary amplifier, negative resistance, increases the impedance transform of (Embodiment lb), lowering the load impedance of (Embodiment la).

[0122] Embodiment 3. All above included in a system being one of: a. a single antenna TRx; b. an array with a circulator at each antenna port; and c. an array with split Tx / Rx antennas.

[0123] As will be appreciated by one of skill in the art, the concepts described herein may be embodied as a method, data processing system, computer program product and / or computer storage media storing an executable computer program. Accordingly, the concepts described herein may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects all generally referred to herein as a “circuit” or “module.” Any process, step, action and / or functionality described herein may be performed by, and / or associated to, a corresponding module, which may be implemented in software and / or firmware and / or hardware. Furthermore, the disclosure may take the form of a computer program product on a tangible computer usable storage medium having computer program code embodied in the medium that may be executed by a computer. Any suitable tangible computer readable medium may be utilized including hard disks, CD-ROMs, electronic storage devices, optical storage devices, or magnetic storage devices.

[0124] Some embodiments are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems and computer program products. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer (to thereby create a special purpose computer), special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0125] These computer program instructions may also be stored in a computer readable memory or storage medium that may direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instruction means which implement the function / act specified in the flowchart and / or block diagram block or blocks.

[0126] The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0127] It is to be understood that the functions / acts noted in the blocks may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality / acts involved. Although some of the diagrams include arrows on communication paths to show a primary direction of communication, it is to be understood that communication may occur in the opposite direction to the depicted arrows.

[0128] Computer program code for carrying out operations of the concepts described herein may be written in an object oriented programming language such as Python, Java® or C++. However, the computer program code for carrying out operations of the disclosure may also be written in conventional procedural programming languages, such as the "C" programming language. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer. In the latter scenario, the remote computer may be connected to the user's computer through a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0129] Many different embodiments have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious and obfuscating to literally describe and illustrate every combination and subcombination of these embodiments. Accordingly, all embodiments may be combined in any way and / or combination, and the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.

[0130] Abbreviations that may be used in the preceding description include:

[0131] Abbreviation Explanation

[0132] AL Amplitude Linearizer

[0133] AM-AM Amplitude Modulation to Amplitude Modulation

[0134] AM-PM Amplitude Modulation to Phase Modulation

[0135] Aux Auxiliary

[0136] CG Common Gate

[0137] CMOS Complementary Metal Oxide Semiconductor

[0138] CS Common Source

[0139] DAC Digital to Analog Converter

[0140] FD-SOI Fully Depleted Silicon On Insulator

[0141] FR1 Frequency Range One FR2 Frequency Range Two

[0142] GND GrouND

[0143] MOSFET Metal Oxide Semiconductor Field-Effect Transistor

[0144] Opamp OPerational-AMPlifier

[0145] PAE Power Added Efficiency

[0146] PA Power Amplifier

[0147] PD Peak Detector

[0148] PL Phase Linearizer

[0149] P.P. Percent Points

[0150] RF Radio Frequency

[0151] RFC Radio Frequency Choke

[0152] Vth Threshold voltage

[0153] TX Transmitter

[0154] It will be appreciated by persons skilled in the art that the embodiments described herein are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings without departing from the scope of the following claims.

Claims

CLAIMS:

1. A power amplifier (24, 26), comprising: a main amplifier (60) configured to receive and amplify an input signal; an impedance transformer (62) having a transmission line, a reactive circuit element and / or a transformer, the impedance transformer (62) configured to receive and couple the amplified input signal to an external load through an impedance transformation; and an auxiliary amplifier (68) configured to provide a negative resistance responsive to an envelope of the input signal, the negative resistance being provided in parallel with a load impedance of the external load as seen at an output of the power amplifier (24, 26).

2. The power amplifier (24, 26) of Claim 1, further comprising a drive amplifier, configured to provide the input signal to the main amplifier (60).

3. The power amplifier (24, 26) of Claim 2, wherein the drive amplifier is configured to phase compensate the input signal to the main amplifier (60).

4. The power amplifier (24, 26) of any of Claims 2 and 3, further comprising adaptive bias circuitry configured to provide amplitude modulation to amplitude modulation, AM-AM, and amplitude modulation to phase modulation, AM-PM, distortion compensation.

5. The power amplifier (24, 26) of Claim 4, wherein the adaptive bias circuitry operates at baseband.

6. The power amplifier (24, 26) of any of Claims 4 and 5, wherein the adaptive bias circuitry includes digital circuitry.

7. The power amplifier (24, 26) of any of Claims 4-6, further comprising a first transformer between the drive amplifier and the main amplifier (60), the first transformer being center tapped, the center tap being coupled to the adaptive bias circuitry.

8. The power amplifier (24, 26) of any of Claims 4-7, wherein the adaptive bias circuitry is configured to receive the envelope of the input signal and to output a gate bias voltage responsive to the envelope of the input signal, the output gate bias voltage being input tothe auxiliary amplifier (68).

9. The power amplifier (24, 26) of any of Claims 2-7, further comprising a dynamic phase linearizer preceding the drive amplifier, the dynamic phase linearizer being configured to provide amplitude modulation to phase modulation, AM-PM, distortion compensation.

10. The power amplifier (24, 26) of Claim 9, wherein the dynamic phase linearizer is further configured to decouple the AM-PM distortion compensation from an input bias voltage of the drive amplifier.

11. The power amplifier (24, 26) of any of Claims 9 and 10, further comprising a second transformer configured to put the dynamic phase linearizer and a drive amplifier input into resonance12. The power amplifier (24, 26) of any of Claims 1-11, wherein the negative resistance is configured to increase the impedance transformation by the impedance transformer (62) when the negative resistance is activated and to not increase the impedance transformation by the impedance transformer (62) when the negative resistance is not activated.

13. The power amplifier (24, 26) of any of Claims 1-12, wherein the negative resistance is configured to lower the load impedance.

14. The power amplifier (24, 26) of any of Claims 1-13, further comprising a peak detector preceding the auxiliary amplifier (68) and configured to detect the envelope of the input signal to produce a baseband envelope signal.

15. The power amplifier (24, 26) of Claim 14, further comprising delay circuitry between the peak detector and the auxiliary amplifier (68), the delay circuitry being configured to align the baseband envelope signal with a signal waveform at an output of the auxiliary amplifier (68).

16. The power amplifier (24, 26) of any of Claims 1-15, wherein the external load includes an antenna.

17. The power amplifier (24, 26) of any of Claims 1-16, further comprising control circuitry to activate and deactivate the negative resistance based at least in part on an output power of the power amplifier (24, 26).

18. The power amplifier (24, 26) of any of Claims 1-17, wherein the auxiliary amplifier (68) includes a cascode amplifier with controlled positive feedback.

19. The power amplifier (24, 26) of Claim 18, wherein the controlled positive feedback is provided at least in part by cross-coupling outputs of transistors to gates of the transistors, the gates of the transistors being coupled to the envelope of the input signal.

20. The power amplifier (24, 26) of Claim 18 wherein the controlled positive feedback is provided at least in part by at least one of capacitors, transformers, inductors and / or bias resistors coupled to the transistor gates and / or sources.

21. The power amplifier (24, 26) of any of Claims 1-19, wherein the main amplifier (60) and the auxiliary amplifier (68) are discrete components.

22. The power amplifier (24, 26) of Claim 1, wherein the negative resistance is based at least in part on a gate voltage of the main amplifier (60).

23. An radio frequency, RF, front end, the RF front end comprising: at least one antenna; and a power amplifier (24, 26) comprising: a main amplifier (60) configured to receive and amplify an input signal; an impedance transformer (62) having a transmission line, a reactive circuit element and / or a transformer, the impedance transformer (62) configured to receive and couple the amplified input signal to an external load through an impedance transformation; and an auxiliary amplifier (68) configured to provide a negative resistance responsive to an envelope of the input signal, the negative resistance being provided in parallel with a load impedance of the external load as seen at an output of the power amplifier (24, 26).

24. The RF front end of Claim 23, further comprising a circulator coupled to an antenna port of the at least one antenna.

25. The RF front end of any of Claims 23 and 24, wherein the at least one antenna is an array of antennas.

26. The RF front end of Claim 25, further comprising a plurality of circulators, there being one circulator for each antenna port of the array of antennas.

27. The RF front end of any of Claims 25 and 26 wherein the array of antennas include split transmit and receive antennas.

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