Successive approximation register (SAR) analog to digital converter and method for such a converter

Abstract

The invention concerns a converter circuit (2) comprising: - A sampling and conversion unit (4), configured to - sample and store an analog input signal Vin and - to receive a digital input signal Vref and convert the digital input signal into a signal VDAC by a digital-to-analog converter (DAC) and - to combine the analog input signal Vin and the signal VDAC to form an output signal Vin- VDAC by a subtraction of the signal VDAC; - An amplifier unit (6) for amplifying the output signal of the sampling and conversion unit; - A decision unit for determining, whether an output signal of the amplifier unit has a positive or negative sign; - a clock and phase generator (10); and - a successive approximation register (SAR) unit (12); wherein the converter circuit (2) further comprises an equalizer circuit (14) which is interposed between the sampling and conversion unit and the amplifier unit. The invention further concerns a method for such a converter.

Description

[0001] 2023PF00731 - 1 - SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG TO DIGITAL CONVERTER AND METHOD FOR SUCH A CONVERTER DESCRIPTION TECHNICAL FIELD The invention relates to an analog to digital converter with successive approximation register. It also relates to a corresponding method. BACKGROUND Successive approximation register analog to digital converter (SAR ADC) is one of the indispensable blocks in analog systems because of the robustness and simplicity of its architecture in producing a digital signal from an analog one. It consists of the following major blocks: - a digital to analog converter (DAC) which can be a capacitive type, a resistive type or mix type of resistive and capacitive. - A comparator, which is operable to compare two input signals and might comprise a Pre-amplifier and a Latch. - A Clock and Phase generation network - A successive approximation register (SAR) Logic. In general, the DAC provides an output signal to be feed into the comparator. Another input signal is provided by a sample and hold unit, sampling an input signal for feeding into the comparator as second signal. The comparator compares both input signals one to the other and takes a decision in form of a sign-function. Based on the sign function a “0” bit or a “1” bit is fed into the register. If within the comparison for one of the bits, the output sign at the comparator is erroneous, the output in the SAR is erroneous. The clock and 2023PF00731 - 2 - phase generation network is responsible for synchronization of the different steps within the circuit. SAR ADC algorithm with redundancy, Tomohiko Ogawa et al. APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, Conference Paper, IEEE describes a redundant algorithm for high reliable successive approximation Register, where mistakes can be digitally corrected. This method works by defining redundancy in generalized non-binary search algorithm. However, the inclusion of redundancies into conversion circuits makes it necessary, to include a larger digital to analog converter and makes the calculation more time intensive. According to the state-of-the-art SAR ADC circuits comprises a capacitive DAC (CDAC). Such a CDAC comprises capacitive elements as well as switches. A capacitive element has a settling time, which results in the CDAC having a settling time itself. Such a settling time gives a minimal time for the operation in the CDAC to be able to provide a correct output signal. For increasing the speed of SAR ADC, the settling time of the CDAC is one of the bottlenecks for the following reasons: If the latch-based comparator gets triggered before the CDAC settling, SAR ADC will converge to a wrong output code. An SAR ADC without redundancy cannot converge to a correct output once a wrong decision is made within a comparator unit for example by a latch. Missing codes, differential non- linearity (DNL), integral non-linearity (INL) and signal-to noise-and-distortion-ratio (SNDR) degradation can be seen when a wrong decision occurs. It is an object of the present invention to provide a method and a device for increasing the performance of the conversion. It is a further object of the invention to provide a method and a device for increasing the speed of the conversion. 2023PF00731 - 3 - SUMMARY In accordance with the invention a converter circuit comprises: a sampling and conversion unit, configured to sample and store an analog input signal Vin, to receive a digital input signal and convert the digital input signal Vrefinto a signal VDACby a digital-to-analog converter (DAC) and to combine the analog input signal Vin and the signal VDACto form an output signal Vin-Vrefby a subtraction of the signal VDAC; an amplifier unit for amplifying the output signal of the sampling and conversion unit; a decision unit for determining, whether an output signal of the amplifier unit has a positive or negative sign; a clock and phase generator; and a successive approximation register (SAR) unit; the converter circuit further comprises an equalizer circuit which is interposed between the sampling and conversion unit and the amplifier unit. The clock and phase generator is connected at least with the sampling unit, the amplifier unit, and the latch unit, in order to provide a time signal for synchronizing the different operations. It is preferably as well connected to the SAR. The equalizer circuit interposed between the sampling and conversion unit and the amplifier unit has the function to drive the amplifier unit and to improve the conversions that are critical to the correct output. The present circuit has the advantage, that no redundancy has to be incorporated into the circuit. According to an embodiment the DAC is a capacitive DAC (CDAC). Such a capacitive DAC comprises switches and capacitive elements. The amplifier unit might be a pre-amplifier. 2023PF00731 - 4 - Preferably the decision unit comprises a latch. The latch is a possible embodiment for the decision unit. The equalizer circuit is in particular a continuous equalizer circuit. The equalizer circuit is in particular a time linear equalizer circuit. In particular, the equalizer circuit is a continuous time linear equalizer circuit. In particular, the equalizer circuit processes the output of sampling and conversion unit by a function of the type , wherein s is the incoming signal and ωz1 is the zero of the equalizer circuit, ωp1 the pole of the capacitive DAC and ωp2 a pole of the equalizer circuit, wherein preferably ωz1<ωp1< ωp2. Preferably the equalizer circuit processes the output signal of the DAC by applying a function: wherein s is the incoming signal and ωz1 is the zero of the equalizer circuit ωz2 is a second zero of the equalizer circuit, ωp1 the pole of the capacitive DAC and ωp2 a pole of the equalizer circuit, wherein preferably ωz1<ωp1< ωp2. According to an embodiment the function can be further extended by multiplying one or more terms 2023PF00731 - 5 - According to an embodiment, the time constant of the capacitive elements within the CDAC is such that the capacitive elements are not settled within one clock period. Preferably, the equalizer circuit comprises a first and second oscillator circuit as well as a tuned circuit. In particular, the equalizer circuit further comprises an active inductor boost circuit. According to a further embodiment, the circuit may additionally comprise a feed-back loop for subtracting a signal tail of previous bit conversions, the feed-back signal to be subtracted from the signal to be amplified at the amplifier unit. This additional feed-back loop is in particular advantageous to be employed with a CDAC having a long settling time. In accordance with the invention a method for converting an analog signal into a digital signal, the method comprising: sampling and storing an analog input signal Vin and receiving a digital input signal and converting the digital input signal Vrefinto a signal VDACby a digital-to-analog converter (DAC) and combining the analog input signal Vinand the signal VDACto form an output signal Vin- VDACby a subtraction of the reference signal; amplifying the signal Vin- VDAC; determining, whether an output signal of the amplifier unit has a positive or negative sign; Performing a successive approximation by a successive approximation register (SAR) unit; wherein the method further comprises performing a time equalization operation on the output signal Vin- VDACbefore the amplification. In particular, the equalization operation is a continuous and / or time linear equalization operation. 2023PF00731 - 6 - According to an embodiment the time equalization operation may apply a function of the type wherein s is the incoming signal and ωz1 is the zero of the equalizer circuit, ωp1 the pole of the capacitive DAC and ωp2 a pole of the equalizer circuit, wherein preferably ωz1<ωp1< ωp2. According to an embodiment the time equalization operation may apply a function of the type: wherein s is the incoming signal and ωz1 is the zero of the equalizer circuit ωz2 is a second zero of the equalizer circuit, ωp1 the pole of the capacitive DAC and ωp2 a pole of the equalizer circuit, wherein preferably ωz1<ωp1<ωp2. According to an embodiment the function can be further extended by multiplying one or more terms According to a further embodiment, the time constant of the capacitive elements within the CDAC is such that the capacitive elements are not settled within one clock period. According to a further embodiment, the method may further comprise at the beginning of one period, determining the signal residue of the previous period, subtracting the signal residue from the signal before amplification, for amplifying a net signal applying a sign function on the net signal before feeding it into the successive approximation. 2023PF00731 - 7 - These and other features, embodiments, objectives, and advantages of the invention will become apparent from the subsequent description. BRIEF DESCRIPTION OF THE DRAWINGS Exemplary embodiments of the invention are discussed below with reference to the accompanying drawings. FIG. 1 shows a block diagram of a SAR ADC converter according to the state of the art. FIG. 2 shows a clock scheme. FIG. 3a shows an ideal output signal of a sampling and conversion unit. FIG. 3b shows a typical output signal of a sampling and conversion unit including capacitive elements. FIG. 4 shows a diagram of the function of the continuous time equalization unit. FIG. 5 shows a block diagram of the according to the present invention. FIGs. 6a and 6b show implementation embodiments of the continuous time equalization unit. DETAILED DESCRIPTION FIG. 1 shows an SAR ADC converter circuit 2 according to the state of the art. The sampling and conversion unit 4 depicted at the right has an input for an analog signal Vin which is sampled for a predetermined time period. Thus, the sampling and conversion unit 4 comprises a sample and hold unit (S / H). 2023PF00731 - 8 - The sampling and conversion unit 4 comprises a further input for a reference signal Vrefwhich might be split into a positive VRefalso named as VRefpor a negative Vrefalso named as VRefn. The sampling and conversion unit further comprise a capacitive element 40 and one or more switches 42. The sampling and conversion unit 4 is adapted to transform the signal VRef, in particular VRefpoder VRefninto an analog signal by a CDAC. The conversion with the CDAC needs the time to load or unload the capacitive elements having a time constant depending on RC. The time constant of the CDAC is further called TCDAC. In the depicted block diagram, a switch 42 is assigned to each of the signal inputs. The signal Vinis compared to an output signal of a digital to analog converter DAC by subtraction in order to receive an output signal Vin-VCDAC. The VCDACdepends on the clock signal as consecutively a value for one of the bits is evaluated. In particular, the switching of the switches 42 in the sampling and conversion unit 4 is controlled by the clock signal of the clock and phase generator 10. The output signal Vin- VCDACis then send to an amplifier unit 6. The amplifier unit 6 might be in particular a preamplifier. The difference signal Vin-VCDACis amplified in the amplifier unit. The amplifier unit 6 can be connected to the clock and phase generator 10 as well. The amplifier unit needs as well a certain time Tampto amplify a signal. After amplification the signal is forwarded to the decision unit, which is in the present case a latch 8 that determines the sign of the signal. The time for the latch to decide the sign of the signal is called Tlatch. However, Tlatchis very small compared to the TCDACresp. Tamp. Depending on the sign, the output is either a “1” or a ”0”. This signal is fed into the SAR logic. The cycle is then repeated for the next bit until each bit is evaluated. FIG. 2 shows a clocking scheme of the SAR ADC. The clock and phase generator 10 generates a clock phase. After an initial 2023PF00731 - 9 - sampling and offset cancellation phase, the conversion starts. After this initial phase, within one clock cycle one bit is evaluated and the next bit is evaluated in the next clock cycle. Thus, the evaluation starts for bit number N, followed by bit number N-1 until the last bit 1. For each bit evaluation cycle a VCDACvoltage is compared with the input signal within the sampling and conversion unit 4, while the amplifier unit 6 is reset, the output signal of the sampling and conversion unit 4 is moved to the amplifier unit 6 for amplifying the signal, which is passed after amplification to the latch 8 during a latch enabling phase. The latch 8 decides about the sign of the signal and to pass the latch output signal to the SAR register for storage. Afterwards the latch is reset again. This cycle is repeated for each bit, wherein the time- consuming operations are the DAC comparison and the amplification. FIG. 2 shows a clocking scheme for a 10-bit SAR ADC, thus N is 10. In the present embodiment VDAC is equal to for the ithbit . FIG. 3a shows a conversion of with an ideal behavior of the CDAC, when the settling time is very short compared to the clock cycle. The dotted lines show a first conversion for four conversion cycles. The first conversion starts in the second clock cycle, raising the cycle above 0-line, having a value of Vin-VCDAC= Vref / 4+Vlsb / 2, wherein Vlsb is the least significant bit. Vin-VCDAC drops below zero for the next three conversions but is slowly approaching the 0-Level. The other dashed line shows an alternative conversion. The first conversion starts in the second clock cycle, raising the cycle just below 0-line, having a value of Vin-VCDAC= Vref / 4-Vlsb / 2. Vin-VCDAC raises for the second conversion above zero for the next three conversion but slowly approaching the 0-Level. In this case of ideal behavior, the 2023PF00731 - 10 - signal is clearly larger or smaller as zero, in order not to induce any error in the determination of the sign. However, with a real settling time the settling time of the CDAC might be in the order of the clock cycle, such that at certain conversions, as shown here for the second cycle, the signal is below zero even though it should be above, which induces an error into the conversion. Such a conversion is shown in FIG. 3b. For the second conversion, the signal of Vin-VCDAC does not raise above zero, independently on whether Vin- VCDAC= Vref / 4+Vlsb / 2 or Vin-VCDAC= Vref / 4-Vlsb / 2. Thus, an error is induced if Vin-VCDAC= Vref / 4+Vlsb / 2. FIG. 4 shows a diagram of the of the CDAC response itself, as well as the response of the continuous time linear equalization (CTLE) circuit, as gain depending on the frequency ω. The response of the CDAC is horizontal until ωp and drops linearly afterwards. The response of the CTLE starts horizontally until a frequency ωz1, and rises until a frequency ωp2. A combination of both responses leads to an increase of the bandwidth. FIG. 5 shows a block diagram of the conversion circuit. The circuit comprises the same elements as shown in FIG. 1. In this circuit, a continuous time linear equalization unit is additionally interposed between the sampling and conversion unit and the amplifier unit. The continuous time linear equalization unit transforms the gain of the signal Vin-VCDACand drives the amplifier. The induced transformation enhances in particular the higher frequencies and reduces the error of the transformation significantly. FIG. 6a and 6b shows examples of a continuous time linear equalization unit. FIG. 6a shows an example of a circuit providing the onto the signal. The circuit is provided with a tuned subcircuit 50 comprising a tunable capacitive element 52 and a resistive element 54 to provide a means for generating the 2023PF00731 - 11 - FIG. 6b shows another example of a circuit providing a time linear equalization with a function: The embodiment shown in FIG. 6b is an example where with an active inductor 56 for further boosting the bandwidth, comprising switching elements and a further power source.

[0002] 2023PF00731 - 12 - LIST OF REFERENCE SIGNS Sampling and conversion unit 4 Amplifier unit 6 Latch 8 Clock and phase generator 10 SAR Logic 12 Equalizer circuit 14 Capacitive element 40 Switch 42 Subcircuit 50 Tunable capacitive element 52 Resistive element 54 Active inductor 56 Input signal VinReference signal VRefPositive reference signal VRefpNegative reference signal VRefn

Claims

2023PF00731 - 13 - CLAIMS 1. Converter circuit (2) comprising: - A sampling and conversion unit (4), configured to - sample and store an analog input signal Vin and - to receive a digital input signal Vrefand convert the digital input signal into a signal VDACby a digital- to-analog converter (DAC) and - to combine the analog input signal Vinand the signal VDACto form an output signal Vin- VDACby a subtraction of the signal VDAC; - An amplifier unit (6) for amplifying the output signal of the sampling and conversion unit; - A decision unit for determining, whether an output signal of the amplifier unit has a positive or negative sign; - a clock and phase generator (10); and - a successive approximation register (SAR) unit (12); wherein the converter circuit (2) further comprises an equalizer circuit (14) which is interposed between the sampling and conversion unit and the amplifier unit.

2. Converter circuit (2) of claim 1, wherein the DAC is a Capacitive DAC (CDAC).

3. Converter circuit (2) of claim 1 or 2, wherein the decision unit comprises a latch.

4. Converter circuit (2) according to one of the previous claims, wherein the equalizer circuit (14) processes the output of sampling and conversion unit by a function of the typewherein s is the frequency of the incoming signal and ωz1 is the zero of the equalizer circuit, ωp1 the pole of the capacitive DAC and ωp2 a pole of the equalizer circuit, wherein preferably ωz1<ωp1<ωp2.2023PF00731 - 14 - 5. Converter circuit (2) according to one of the previous claims, wherein the equalizer circuit (14) processes the output signal of the DAC by applying a function:wherein s is the frequency of the incoming signal and ωz1 is the zero of the equalizer circuit ωz2 is a second zero of the equalizer circuit, ωp1 the pole of the capacitive DAC and ωp2 a pole of the equalizer circuit, wherein preferably ωz1<ωp1<ωp2.

6. Converter circuit (2) according to claim 5, wherein the function is further multiplied by one or more terms7. Converter circuit (2) according to one of the previous claims, wherein the time constant of the capacitive elements within the CDAC is such that the capacitive elements are not settled within one clock period.

8. Converter circuit (2) according to one of the previous claims, wherein the equalizer circuit comprises a first and second oscillator circuit as well as a tuned circuit.

9. Converter circuit (2) according to claim 5, wherein the equalizer circuit further comprises an active inductor boost circuit (56).

10. Converter circuit (2) according to one of the previous claims further comprising a feed-back loop for subtracting a signal tail of previous bit conversions, the feed-back signal to be subtracted from the signal to be amplified at the amplifier unit.2023PF00731 - 15 - 11. Method for converting an analog signal into a digital signal, the method comprising: - sampling and storing an analog input signal Vin and - receiving a digital input signal and converting the digital input signal Vrefinto a signal VDACby a digital-to-analog converter (DAC) and - combining the analog input signal Vinand the signal VDACto form an output signal Vin- VDACby a subtraction of the signal VDAC; - amplifying the signal Vin- VDAC; - determining, whether an output signal of the amplifier unit has a positive or negative sign; - Performing a successive approximation by a successive approximation register (SAR) unit; wherein the method further comprises performing a time equalization operation on the output signal Vin- VDACbefore the amplification.

12. Method according to claim 11, wherein time equalization operation applies a function of the typewherein s is the incoming signal and ωz1 is the zero of the equalizer circuit, ωp1 the pole of the capacitive DAC and ωp2 a pole of the equalizer circuit, wherein preferably ωz1<ωp1<ωp2.

13. Method according to claim 11, wherein time equalization operation applies a function of the type:wherein s is the incoming signal and ωz1 is the zero of the equalizer circuit ωz2 is a second zero of the equalizer circuit, ωp1 the pole of the capacitive DAC2023PF00731 - 16 - and ωp2 a pole of the equalizer circuit, wherein preferably ωz1<ωp1<ωp2.

14. Method according to claim 13, wherein the function is further multiplied by one or more terms15. Method according to one of claims 11-14, wherein the time constant of the capacitive elements within the CDAC is such that the capacitive elements are not settled within one clock period.

16. Method according to one of the previous claims further comprising, - at the beginning of one period, determining the signal residue of the previous period, - subtracting the signal residue from the signal before amplification, for amplifying a net signal, - applying a sign function on the net signal before feeding it into the successive approximation.

Images