Method for operating a DC-DC converter

Abstract

The invention relates to a method for operating a DC-DC converter (1), comprising: - a primary side (P) having at least two half-bridges (HB1, HB2) each having a high-side switch in the form of a semiconductor switch (S1, S3) and each having a low-side switch in the form of a semiconductor switch (S2, S4), - a secondary side (S) having at least two half-bridges (HB3, HB4) each having a high-side switch in the form of a semiconductor switch (S5, S7, D) and each having a low-side switch in the form of a semiconductor switch (S6, S8, D), - at least one LC resonant circuit (2.1, 2.2) in the form of a series resonant circuit, which is arranged between a centre tap of one of the half-bridges (HB1, HB2) on the primary side (P) and a centre tap of one of the half-bridges (HB3, HB4) on the secondary side (S), and - at least one further LC resonant circuit (2.1, 2.2) in the form of a series resonant circuit or a capacitor (C1, C2), which is arranged between a centre tap of a further one of the half-bridges (HB1, HB2) on the primary side (P) and a centre tap of a further one of the half-bridges (HB3, HB4) on the secondary side (S), wherein the primary side (P) is connected to a DC voltage source (3), and wherein the secondary side (S) is connected to a sink (4). In the method, provision is made for the high-side switch of a first half-bridge (HB1, HB2) and the low-side switch of a second half-bridge (HB3, HB4) to be switched at a clock frequency on the primary side (P) at least substantially in push-pull configuration with respect to the low-side switch of the first half-bridge (HB1, HB2) and the high-side switch of the second half-bridge (HB3, HB4), wherein the high-side switch of each half-bridge (HB1, HB2) is switched on only when the low-side switch of the same half-bridge (HB1, HB2) has been switched off and vice versa.

Description

[0001] Method for operating a DC / DC converter

[0002] The invention relates to a method for operating a DC / DC converter according to the preamble of claim 1 or 7.

[0003] If two high-voltage systems are coupled via a voltage converter, the two voltage systems are interdependent. Depending on the operating principle of the voltage converter, this interdependence can be more or less pronounced. In principle, a distinction can be made between galvanically coupled voltage converters and galvanically isolated voltage converters (isolating DC / DC converters). Depending on the application, it is advantageous or necessary to use an isolating or coupled DC / DC converter. Galvanically coupled DC / DC converters are characterized by high efficiency (provided the transformation ratio is not too high) and high power density.

[0004] Isolating DC / DC converters are constructed with a transformer for power transmission. As a result, the transformer with galvanic isolation creates two independent high-voltage systems on the primary and secondary sides. They are characterized by the freedom to choose the reference potential on the secondary side. This results in the advantage that the potential distribution on the primary side does not affect the secondary side. This also means that the insulation design on the secondary side is independent of the primary side, since an insulation fault has no influence on the secondary side. Furthermore, isolating DC / DC converters with a transformer on the secondary side are all-pole de-energized when no AC voltage is generated at the primary winding.

[0005] Isolating voltage converters offer an efficiency advantage over galvanically coupled DC / DC converters at high transformation ratios. The main application areas of isolating DC / DC converters are the energy transfer from a high-voltage system to a low-voltage system where touch protection cannot be implemented. Furthermore, they are used in smaller versions to generate a voltage that is above the high-voltage operating voltage for gate control of high-side semiconductors (the secondary side's independent reference allows the two voltages to be added together). Disadvantages of isolating DC / DC converters are the lower power density, the higher component complexity, and the limited variation in the transformation ratio, as this is primarily determined by the transformer and its control.

[0006] EP 4 147 344 A1 describes a power converter circuit comprising: a full-bridge inverter, a resonant circuit, and a control circuit. The full-bridge consists of a first branch and a second branch, each branch having two switches and a switching node between the switches, wherein the switches of the first branch are different from those of the second branch. The resonant circuit is connected between the switching nodes and comprises an inductance in series with a capacitance. The control circuit generates control signals for the switches according to a predefined scheme with two excitation phases and two passive conduction phases with a configurable duty cycle to achieve zero-voltage switching.

[0007] From Sunghyuk Choi et al.: Phase Control using Network Node Voltage Feedback for Capacitor-Coupled Dual Active Bridge DC-DC Converters, IEEE Energy Conversion Congress and Exposition (ECCE), 2021, 3023-3038, and Jin-Su Hong et al.: Common mode current minimization of Capacitor-Coupled Dual-Active-Bridge for SIPO MVDC- LVDC Distribution Converter, IECON - 45th Annual Conference of the IEEE Industrial Electronics Society, 2019, 5733-5738, capacitively coupled dual active bridge DC-DC converters are known.

[0008] From Nicola Blasuttigh et al.: Comparative Study of Single-phase and Three-phase DAB for EV Charging, 24th European Conference on Power Electronics and Applications (EPE'22 ECCE Europe), 2022, P1 - P9, single-phase and three-phase dual-active bridge DC-DC converters for charging electric vehicles are known.

[0009] A switching power supply is known from US 020030169027 A1.

[0010] The invention is based on the object of providing a novel method for operating a DC / DC converter as mentioned above. This object is achieved according to the invention by a method having the features of claim 1 or 7.

[0011] Advantageous embodiments of the invention are the subject of the subclaims.

[0012] A DC / DC converter is proposed, comprising:

[0013] - a primary side with at least two half-bridges, each with a high-side switch designed as a semiconductor switch and a low-side switch designed as a semiconductor switch,

[0014] - a secondary side with at least two half-bridges, each with a high-side switch designed as a semiconductor switch and a low-side switch designed as a semiconductor switch,

[0015] - at least one LC resonant circuit designed as a series resonant circuit, which is arranged between a center tap of one of the half-bridges on the primary side and a center tap of one of the half-bridges on the secondary side,

[0016] - at least one further LC resonant circuit designed as a series resonant circuit or a capacitor which is arranged between a center tap of another of the half-bridges on the primary side and a center tap of another of the half-bridges on the secondary side.

[0017] In one embodiment, a source capacitance or an intermediate circuit capacitor is arranged on the primary side and / or a sink capacitance is arranged on the secondary side.

[0018] In one embodiment, the semiconductor switches on the primary side are designed as MOSFETs or IGBTs and / or the semiconductor switches on the secondary side are designed as MOSFETs, IGBTs or diodes.

[0019] According to one aspect of the present invention, a method for operating the DC / DC converter described above is proposed, wherein the primary side is or will be connected to a DC voltage source, wherein the secondary side is or will be connected to a sink. According to the invention, on the primary side, the high-side switch of a first half-bridge and the low-side switch of a second half-bridge are switched at least substantially in push-pull to the low-side switch of the first half-bridge and the high-side switch of the second half-bridge at a clock frequency, wherein the high-side switch of each half-bridge is only switched on when the low-side switch of the same half-bridge has been switched off and vice versa.This mode of operation can be used in a buck mode, where the voltage at the DC source is higher than at the sink, and also as the basis of a boost mode, where the voltage at the DC source is lower than at the sink.

[0020] In one embodiment, the clock frequency for resonant switching is set at a natural frequency of the LC resonant circuit or lower.

[0021] In one embodiment, in boost mode, at the same time as the high-side switch of one of the half-bridges on the primary side is switched on, the low-side switch of the half-bridge on the secondary side connected to it via one of the LC resonant circuits or the capacitor or the high-side switch of the other half-bridge on the secondary side is initially switched on, wherein this low-side switch or high-side switch on the secondary side is controlled with the same clock frequency but a smaller duty cycle than the semiconductor switches on the primary side that are switched on at the same time.

[0022] In one embodiment, the semiconductor switches of the primary side are only switched off when a choke current through the at least one LC resonant circuit has decreased to zero.

[0023] In one embodiment, the semiconductor switches on the primary side are controlled with a duty cycle of less than 0.5. An example value is 0.45.

[0024] In one embodiment, the secondary-side semiconductor switches are controlled in boost mode with a duty cycle that must be selected to be smaller than the duty cycle of the primary-side semiconductor switches. The duty cycle of the secondary-side semiconductor switches depends on the transformation ratio of the DC / DC converter to be represented, i.e., the ratio of secondary voltage to primary voltage. The duty cycle of the switches on the secondary side approaches the duty cycle of the switches on the primary side when the transformation ratio needs to increase. An example value in the simulation for boosting from 400V to 600V is 0.2.

[0025] According to one aspect of the present invention, a method for operating the above-described DC / DC converter, particularly in buck mode, is proposed, wherein the primary side is or will be connected to a DC voltage source, and the secondary side is or will be connected to a sink. The DC / DC converter is designed as a three-phase converter.

[0026] - the primary side has three half-bridges, each with a high-side switch designed as a semiconductor switch and a low-side switch designed as a semiconductor switch,

[0027] - wherein the secondary side comprises three half-bridges, each with a high-side switch configured as a semiconductor switch and a low-side switch configured as a semiconductor switch. According to the invention, on the primary side, the high-side switches of each half-bridge and the low-side switches of the same half-bridge are switched at least substantially in push-pull mode at a clock frequency, wherein the three half-bridges are controlled with a phase offset of 120°.

[0028] The DC / DC converter and the described methods can be used, for example, to charge a high-voltage battery of an electrically powered vehicle at a DC charging station.

[0029] The solution according to the invention provides a voltage converter that fulfills some of the advantages of a galvanically isolating voltage converter based on a transformer and can still have a power density like a galvanically coupled voltage converter.

[0030] The key feature of the voltage converter with LC resonant circuit is that the positive HV potential of the primary side is not directly connected to the positive HV potential of the secondary side, and that the negative HV potential of the primary side has no direct connection to the negative HV potential of the secondary side. The connection between the HV potentials of the primary and secondary sides is made via an LC resonant circuit for each potential. The capacitor ensures galvanic isolation. Via semiconductor switches on the primary side, a square-wave voltage with a reversal of sign is generated from the DC operating voltage by alternately switching the semiconductor switches. Due to the AC component of this square-wave voltage, the capacitors do not represent an interruption during operation, but rather an impedance. The inductors serve to limit the current during the switching process of the semiconductor switches.

[0031] The voltage converter has DC isolation. Therefore, it is

[0032] Secondary terminals are voltage-free and galvanically isolated from the HV potentials of the primary side at both connections as long as the clocking of the primary side is deactivated. This makes it suitable as a connecting element between system boundaries where galvanic isolation is required before commissioning, e.g., as with contactors within the battery or with isolating DC / DC converters with a transformer from one HV voltage to a second HV voltage. The voltage converter represents an interruption for DC currents at all poles. It can therefore be used to transfer power to a less well-insulated HV system with a lower insulation rating, e.g., from 800 V (1000 V insulation rating) to 400 V (500 V insulation rating). The potential distribution of the secondary side is independent of the primary side in the long term. The potential difference between the primary and secondary sides can be adjusted by a superimposed DC voltage across the capacitors.This converter concept can be used to implement both a buck and a boost converter. The implementation of current-free switching operations is possible to increase efficiency. The LC resonant circuit(s) can be made smaller and less complex than a transformer. The voltage converter is therefore smaller than an isolating voltage converter with a transformer: it is lighter, cheaper, and more efficient (no stray flux in the transformer, no iron losses). The voltage converter is not limited to a transformation ratio of 2 like a charge pump. Interleaved operation is possible to increase the frequency of an interference suppression filter and thus make the filter smaller.

[0033] Embodiments of the invention are explained in more detail below with reference to drawings.

[0034] Showing:

[0035] Fig. 1 is a schematic diagram of a capacitively galvanically isolating DC / DC converter with two LC resonant circuits,

[0036] Fig. 2 is a schematic diagram of the DC / DC converter in buck mode,

[0037] Fig. 3 is a schematic diagram of the DC / DC converter in buck mode with premature opening of two semiconductor switches,

[0038] Fig. 4 is a schematic diagram of the DC / DC converter in buck mode in a subsequent phase, Fig. 5 is a schematic diagram of the DC / DC converter in buck mode with premature opening of two further semiconductor switches,

[0039] Fig. 6 is a schematic diagram of a simulation circuit of the DC / DC converter in buck mode,

[0040] Fig. 7 is a schematic diagram of signals of the simulation circuit,

[0041] Fig. 8 is a schematic view of a simulation circuit of a three-phase DC / DC converter with three LC resonant circuits,

[0042] Fig. 9 is a schematic diagram of signals of the simulation circuit of Figure 8,

[0043] Fig. 10 is a schematic view of the DC / DC converter of Figure 1 in a boost mode,

[0044] Fig. 11 is a schematic view of the DC / DC converter in boost mode in a subsequent state,

[0045] Fig. 12 is a schematic view of the DC / DC converter in boost mode in a state following Figure 11 when two semiconductor switches are opened prematurely,

[0046] Fig. 13 is a schematic view of the DC / DC converter in boost mode in a further subsequent state,

[0047] Fig. 14 is a schematic view of the DC / DC converter in boost mode in a further subsequent state,

[0048] Fig. 15 is a schematic view of the DC / DC converter in boost mode in a subsequent freewheeling phase,

[0049] Fig. 16 is a schematic diagram of a simulation circuit of the DC / DC converter in boost mode and

[0050] Fig. 17 is a schematic diagram of signals of the simulation circuit of Figure 16. Corresponding parts are provided with the same reference numerals in all figures.

[0051] Figure 1 is a schematic circuit diagram of a capacitively galvanically isolating DC / DC converter 1 with two LC resonant circuits 2.1, 2.2. A DC voltage source 3 with a source capacitance CX_P is arranged on a primary side P of the DC / DC converter 1. A consumer or a sink 4 with a sink capacitance CX_S is arranged on a secondary side S of the DC / DC converter 1. The primary side P has two half-bridges HB1, HB2, each with two semiconductor switches S1, S2 and S3, S4. The secondary side S has two half-bridges HB3, HB4, each with two semiconductor switches S5, S6 and S7, S8. The semiconductor switches S1 to S8 can be MOSFETs or IGBTs, for example.

[0052] In the DC / DC converter 1 shown, neither a positive high-voltage potential HV+1 of the primary side P is directly connected to a positive high-voltage potential HV+2 of the secondary side S, nor is a negative high-voltage potential HV-1 of the primary side P directly connected to a negative high-voltage potential HV-2 of the secondary side S.

[0053] The connection between the high-voltage potentials HV+1, HV+2, HV-1, HV-2 of the primary and secondary sides P, S is made via an LC resonant circuit 2.1, 2.2, in particular a series resonant circuit, for each high-voltage potential HV+1, HV+2, HV-1, HV-2, which is arranged between a center tap of one of the half-bridges HB1, HB2 on the primary side P and between a center tap of one of the half-bridges HB3, HB4 on the secondary side S. Galvanic isolation is ensured by a capacitor C1, C2 in each of the LC resonant circuits 2.1, 2.2. Via the semiconductor switches S1 to S4 on the primary side P, a square-wave voltage with a change in sign is generated from a DC voltage of the DC voltage source 3 by alternately switching the semiconductor switches S1, S3 and S2, S4. Due to the AC component of this square wave voltage, the capacitors 01, 02 do not represent an interruption during operation, but an impedance with the value C=1 / (Ü) C). The LC resonant circuits 2.1 , 2.2 each have an inductance L1 , L2, which serves to limit the current in the switching process of the semiconductor switches S1 to S4 (w— >°°, ie c — >0). In addition, the inductors L1, L2 can be used to construct an LC resonant circuit 2.1, 2.2 with the capacitances or capacitors O1, O2, thus enabling zero current switching (ZCS) or zero voltage switching (ZVS) in the semiconductor switches S1 to S4. Both serve to avoid and / or reduce switching losses in the semiconductor switches S1 to S4 and thus increase the efficiency of the DC / DC converter 1.

[0054] To build a resonant circuit, at least one of the two inductors L1 and L2 is necessary (ie the other way around: instead of a total of two inductors L1, L2, one can be omitted in a path).

[0055] However, to achieve the benefits of galvanic isolation, both capacitances C1 and C2 are always necessary.

[0056] The secondary side S also has four semiconductor switches S5 to S8. However, it is also possible to replace the semiconductor switches S5 to S8 of the secondary side S with diodes D (see Figure 6). This would make the DC / DC converter 1 unidirectional.

[0057] The DC / DC converter 1 can function both as a buck converter (i.e. the input voltage is always greater than the output voltage) and as a boost converter (i.e. the output voltage is higher than the input voltage).

[0058] Figure 2 is a schematic circuit diagram of the DC / DC converter 1 in buck mode. Initially, the semiconductor switches S1 and S4 on the primary side P are or will be switched on. The semiconductor switches S2 and S3 remain open. The semiconductor switches S5 to S8 on the secondary side are opened and function as diodes D via their respective body diodes. A current I flows from the

[0059] DC voltage source 3 via semiconductor switch S1, LC resonant circuit 2.1, sink 4, LC resonant circuit 2.2, and semiconductor switch S4 back to DC voltage source 3. The temporal current profile corresponds to the first half-oscillation of a sine function. If semiconductor switches S1 and S4 remain closed during this half-sine oscillation, semiconductor switches S1 and S4 can subsequently be opened without current. The following voltage is ultimately established across capacitors C1 and C2:

[0060] These include:

[0061] U_C1 is the voltage across the capacitor C1, U_C2 is the voltage across the capacitor C2,

[0062] UP is the input voltage or voltage of the DC voltage source 3, Us is the output voltage or voltage at the sink 4.

[0063] The peak value of the current depends on the input and output voltage of the DC / DC converter 1 as well as on the resistive components in the circuit.

[0064] Figure 3 is a schematic circuit diagram of DC / DC converter 1 in buck mode during premature opening of semiconductor switches S1 and S4, as shown in Figure 2. If semiconductor switches S1 and S4 are opened while a current I is still flowing, a smaller voltage is established across capacitors C1 and C2. The switching process would then lead to switching losses in semiconductor switches S1, S4. High current values ​​can be avoided by switching faster than the resonant frequency of the LC resonant circuit 2.1, 2.2.

[0065] If semiconductor switches S1 and S4 are opened, even though a positive current is applied to inductor L1 and a negative current to inductor L2, a current flow (reverse current) occurs from the LC resonant circuit 2.1 via the body diode of semiconductor switch S5, drain 4, the body diode of semiconductor switch S8, the LC resonant circuit 2.2, the body diode of semiconductor switch S3, the DC voltage source 3, and the body diode of semiconductor switch S2 back to the LC resonant circuit 2.1. This condition is eliminated with resonant switching at the natural frequency of the LC resonant circuit 2.1, 2.2.

[0066] The current flow through the DC voltage source 3 can be prevented if either the semiconductor switch S4 or the semiconductor switch S1 remains closed in this state. Alternatively, an intermediate circuit capacitor can be placed at the input of the DC / DC converter 1 to reduce or prevent the reverse current.

[0067] Figure 4 is a schematic diagram of DC / DC converter 1 in buck mode during a subsequent phase in which semiconductor switches S2 and S3 are switched on. This results in a state comparable to that shown in Figure 2, in which semiconductor switches S1 and S4 are switched on. However, the polarity of the current flow in inductors L1 and L2 is reversed. Thus, capacitors C1 and C2 are discharged and charged in opposite directions.

[0068] Figure 5 is a schematic circuit diagram of the DC / DC converter 1 in buck mode when the semiconductor switches S2 and S3 open prematurely, as shown in Figure 4. If the semiconductor switches S2 and S3 are opened, even though a positive current is applied to the inductor L1 and a negative current to the inductor L2, a current flow (reverse current) occurs from the LC resonant circuit 2.1 via the body diode of the semiconductor switch S1, the DC voltage source 3, the body diode of the semiconductor switch S4, the LC resonant circuit 2.2, the body diode of the semiconductor switch S7, the drain 4, and the body diode of the semiconductor switch S6 back to the LC resonant circuit 2.1. This condition is eliminated with resonant switching at the resonant circuit's natural frequency. The current flow via the DC voltage source 3 can be avoided if either the semiconductor switch S2 or the semiconductor switch S3 remains closed in this state.

[0069] Figure 6 is a schematic diagram of a simulation circuit of the DC / DC converter 1 in buck mode.

[0070] The DC / DC converter 1 can be operated in buck mode, for example, in the following configuration: The DC voltage source 3 can be, for example, a DC voltage charging station for an electrically powered vehicle. The voltage of the DC voltage source 3 is, for example, 800 V. The sink 4 can be, for example, a high-voltage battery of an electrically powered vehicle. A nominal voltage of the sink 4 is, for example, 400 V. The DC / DC converter 1 can be configured to limit the current I via the chokes L1, L2 when it reaches 50 A and to switch it on again at 30 A. A clock frequency f from two clock generators 5 of, for example, 200 kHz is superimposed. The inductances L1, L2 are, for example, 10 pH. The capacitances C1, C2 are, for example, 100 pF. The duty cycle d of the two clock generators 5 is, for example, 0.45.

[0071] Figure 7 is a schematic diagram of signals from the simulation circuit in Figure 6. It shows the time profile of a source current l_Q through the DC voltage source 3, a control signal Gate_S1+S4 at the gates of the semiconductor switches S1 and S4, a control signal Gate_S2+S3 at the gates of the semiconductor switches S2 and S3, an inductor current l_L1 through the inductor L1, an inductor current l_L2 through the inductor L2, a capacitor voltage U_C1 across the capacitor C1, a capacitor voltage U_C2 across the capacitor C2 and a sink current l_S through the sink 4. The source current l_Q is always positive because the DC / DC converter 1 has the source capacitance CX_P between its H-bridge (semiconductor switches S1 to S4) and the DC voltage source 3, which prevents current fluctuations with a reverse current via the DC voltage source 3.The control signals Gate_S1+S4, Gate_S2+S3 indicate that the clock frequency f was chosen quite high, so that the upper cutoff threshold of 50 A is not yet reached in the LC resonant circuits 2.1, 2.2. The capacitor voltages U_C1, U_C2 fluctuate around a DC value of approximately 0 V.

[0072] The principle of the DC / DC converter 1 can in principle also be applied to multi-phase, for example three-phase DC / DC converters 1.

[0073] Figure 8 is a schematic circuit diagram of a simulation example of a three-phase DC / DC converter 1 with three LC resonant circuits 2.1, 2.2, 2.3. A DC voltage source 3 with a source capacitance CX_P is arranged on a primary side P of the DC / DC converter 1. A consumer or sink 4 with a sink capacitance CX_S is arranged on a secondary side S of the DC / DC converter 1. The primary side P has three half-bridges HB1, HB2, HB3, each with two semiconductor switches S1, S2 and S3, S4 and S5, S6. The secondary side S has three half-bridges HB4, HB5, HB6, each with two semiconductor switches S7, S8 and S9, S10 and S11, S12. The semiconductor switches S1 to S12 can be MOSFETs or IGBTs, for example.

[0074] In the DC / DC converter 1 shown, neither a positive high-voltage potential HV+1 of the primary side P is directly connected to a positive high-voltage potential HV+2 of the secondary side S, nor is a negative high-voltage potential HV-1 of the primary side P directly connected to a negative high-voltage potential HV-2 of the secondary side S.

[0075] The connection between the high-voltage potentials HV+1, HV+2, HV-1, HV-2 of the primary and secondary sides P, S is made via an LC resonant circuit 2.1, 2.2, 2.3, in particular a series resonant circuit, for each high-voltage potential HV+1, HV+2, HV-1, HV-2, which is arranged between a center tap of one of the half-bridges HB1, HB2, HB3 on the primary side P and between a center tap of one of the half-bridges HB4, HB5, HB6 on the secondary side S. Galvanic isolation is ensured by a capacitor C1, C2, C3 in each of the LC resonant circuits 2.1, 2.2, 2.3. The half-bridges HB1 to HB3 are controlled with a phase offset of 120° to one another (similar to fundamental frequency clocking in inverters). The DC / DC converter 1 can be operated in buck mode, for example, in the following configuration: The DC voltage source 3 can, for example, be a DC voltage charging station for an electrically powered vehicle.A voltage of the DC voltage source 3 is, for example, 800 V. The sink 4 can, for example, be a high-voltage battery of an electrically powered vehicle.

[0076] A nominal voltage of the sink 4 is, for example, 400 V. The semiconductor switches S1 to S6 are controlled with a clock frequency f from a clock generator 5 of, for example, 200 kHz. The inductances L1, L2, L3 are, for example, 10 pF. The capacitances O1, O2, O3 are, for example, 10 pF. The duty cycle d of the clock generator 5 is, for example, 0.5.

[0077] Figure 9 is a schematic diagram of signals from the simulation circuit in Figure 8. It shows the time course of a source current l_Q through the DC voltage source 3, of control signals Gate_S1, Gate_S3, Gate_S5 at the gates of the semiconductor switches S1, S3 and S5, of the inductor currents l_L1, l_L2, l_L3 through the inductors L1, L2, L3, of the capacitor voltages U_C1, U_C2, U_C3 across the capacitors O1, O2, O3, and of a sink current l_S through the sink 4.

[0078] Compared to DC / DC converter 1 with two half-bridges HB1, HB2, the three LC resonant circuits 2.1, 2.2, and 2.3 are not operated simultaneously, but rather with a 120° phase shift. The input and output frequency of the current ripple is accordingly three times higher than the frequency of the currents in the resonant circuits 2.1, 2.2, and 2.3.

[0079] The following refers again to the DC / DC converter 1 shown in Figure 1. If an insulation fault occurs on one of the two sides during operation of the DC / DC converter 1 in Figure 1, it is initially transferred to the other side. However, as the process continues, the side without the potential fault automatically rebalances and achieves a high-voltage potential distribution relative to a potential equalization line PA as it existed before the insulation fault occurred. The connection side with the insulation fault still remains completely asymmetrical with regard to the high-voltage potentials HV+1, HV+2, HV-1, and HV-2.

[0080] If the insulation fault occurs, for example, on the primary side P from the positive high-voltage potential HV+1 to the equipotential bonding line PA, this initially causes a shift in the high-voltage potentials HV+2, HV-2 on the secondary side S. If the insulation on the secondary side S is designed to be weaker (e.g., at 500 V), this could lead to a brief overload of the insulation. However, within a few seconds, the HV potential distribution returns to its original state. The two capacitors C1, C2 in the LC resonant circuit 2.1, 2.2 are charged with a DC value corresponding to half the primary voltage.

[0081] Figure 10 is a schematic view of the DC / DC converter 1 of Figure 1 in boost mode.

[0082] Semiconductor switches S1, S4, and S6 are switched on. If the output voltage across drain 4 is higher than the input voltage at DC voltage source 3 on the primary side P, energy must first be stored in a choke L1, L2, similar to a galvanically coupled (inductive) boost converter. In a second phase, this energy and the voltage induced by the choke L1, L2 are used to achieve a higher voltage level on the secondary side S.

[0083] In the capacitively isolating converter, the inductors L1 and L2 are used for this purpose. In a first phase, a short circuit is created on the secondary side S by closing the semiconductor switch S6. The current I flows from the DC voltage source 3 via the semiconductor switch S1, the LC resonant circuit 2.1, the semiconductor switch S6, the body diode of the semiconductor switch S8, the LC resonant circuit 2.2 and the semiconductor switch S4 back to the DC voltage source 3. The current in the chokes L1 and L2 increases linearly while remaining in this operating state. Alternatively, the semiconductor switch S7 can be closed instead of the semiconductor switch S6, so that the current flows via the body diode of the semiconductor switch S5. During this phase, no power is transferred to the secondary side S.

[0084] Figure 11 is a schematic view of the DC / DC converter 1 in boost mode in a state following Figure 10. The previously opened semiconductor switch S6 or S7 is opened. The current impressed in the chokes L1 and L2 generates an induced voltage, which allows a current flow to the secondary side S to a higher voltage level. Power is now transferred to the secondary side S. The current flows from the DC voltage source 3 via the semiconductor switch S1, the LC resonant circuit 2.1, the body diode of the semiconductor switch S5, the drain 4, the body diode of the semiconductor switch S8, the LC resonant circuit 2.2 and the semiconductor switch S4 back to the DC voltage source 3. Figure 12 is a schematic view of the DC / DC converter 1 in boost mode in a state following Figure 11 with the semiconductor switches S1 and S4 opening prematurely. If these are opened, although in the LC resonant circuits 2.1 , 2.2, a reverse current results from the LC resonant circuit 2.1 via the body diode of the semiconductor switch S5, the sink 4, the body diode of the semiconductor switch S8, the LC resonant circuit 2.2, the body diode of the semiconductor switch S3, the DC voltage source 3 and the body diode of the semiconductor switch S2 back to the LC resonant circuit 2.1. This situation can be avoided by waiting until the current in the LC resonant circuits 2.1, 2.2 has dropped to zero. This is called intermittent operation. The advantage is that current-free switching on and off of the semiconductor switches S1 and S4 on the primary side P is possible, whereby the switching losses there can be avoided. In addition, by avoiding the reverse current via the DC voltage source 3, ohmic losses in this circuit are avoided.

[0085] Figure 13 is a schematic view of the DC / DC converter 1 in boost mode in a subsequent state, wherein the semiconductor switches S2, S3, and S8 are switched on. This results in a state comparable to that in Figure 10, where the semiconductor switches S1, S4, and S6 are switched on. However, the polarity of the current flow in the inductors L1 and L2 is reversed. In a first phase, a short circuit is generated on the secondary side S by the closure of the semiconductor switch S8. The current flows from the DC voltage source 3 via the semiconductor switch S3, the LC resonant circuit 2.2, the semiconductor switch S8, the body diode of the semiconductor switch S6, the LC resonant circuit 2.1, and the semiconductor switch S2 back to the DC voltage source 3. The current in the inductors L1 and L2 increases linearly over the course of this operating state. Thus, the capacitors C1 and C2 are discharged and oppositely charged.No power is transferred to the secondary side S. As an alternative to the semiconductor switch S8, the semiconductor switch S5 can also be closed.

[0086] Figure 14 is a schematic view of the DC / DC converter 1 in boost mode in a subsequent state, wherein the previously opened semiconductor switch S8 or S5 is opened. The current impressed in the inductors L1 and L2 generates an induced voltage, allowing a current flow to the secondary side S to a higher voltage level. Thus, the capacitors C1 and C2 are discharged and oppositely charged. Power is now transferred to the secondary side S. The current I flows from the DC voltage source 3 via the semiconductor switch S3, the LC resonant circuit 2.2, the body diode of the semiconductor switch S7, the drain 4, the body diode of the semiconductor switch S6, the LC resonant circuit 2.1, and the semiconductor switch S2 back to the DC voltage source 3.

[0087] Figure 15 is a schematic view of DC / DC converter 1 in boost mode during a subsequent freewheeling phase, in which all semiconductor switches S1 to S8 are opened and / or remain open, with a negative current l_L1 (toward the primary side P) flowing in the inductor L1. This state is comparable to the state in which all semiconductor switches S1 to S8 are opened and a positive current l_L1 (toward the secondary side S) is impressed in the inductor L1.

[0088] Figure 16 is a schematic diagram of a simulation circuit of the DC / DC converter 1 in boost mode.

[0089] The DC / DC converter 1 can be operated in boost mode, for example, in the following configuration: The DC voltage source 3 can be, for example, a DC voltage charging station for an electrically powered vehicle. The voltage of the DC voltage source 3 is, for example, 400 V. The sink 4 can be, for example, a high-voltage battery of an electrically powered vehicle. A nominal voltage of the sink 4 is, for example, 600 V. A clock frequency f from four clock generators 5 of, for example, 20 kHz is used for the semiconductor switches S1 to S4, S6 and S8. The inductances L1, L2 are, for example, 100 pH. The capacitances C1, C2 are, for example, 10 pF. The duty cycle d of the two clock generators 5 for the semiconductor switches S1 to S4 is, for example, 0.45. The duty cycle d2 of the two clock generators 5 for the semiconductor switches S6 and S8 is, for example, 0.2.

[0090] Figure 17 is a schematic diagram of signals from the simulation circuit in Figure 16. It shows the time profile of a source current l_Q through the DC voltage source 3, a control signal Gate_S1+S4 at the gates of the semiconductor switches S1 and S4, a control signal Gate_S6 at the gate of the semiconductor switch S6, a control signal Gate_S2+S3 at the gates of the semiconductor switches S2 and S3, a control signal Gate_S8 at the gate of the semiconductor switch S8, an inductor current l_L1 through the inductor L1, an inductor current l_L2 through the inductor L2, a capacitor voltage U_C1 across the capacitor C1, a capacitor voltage U_C2 across the capacitor C2 and a sink current l_S through the sink 4. It can be seen how the semiconductor switches S6, S8 on the secondary side S are controlled for a shorter time. During this time, the inductor current l_L1, l_L2 in the inductors L1 and L2 increases in magnitude. The sink current l_S in sink 4 remains at 0 A during this time.As soon as the semiconductor switches S6, S8 on the secondary side S are opened, the inductor currents l_L1, l_L2 in the inductors L1 and L2 are reduced and a sink current l_S is transferred to the sink 4. Now the semiconductor switches S1 to S4 on the primary side P are opened and a reverse current occurs via the DC voltage source 3. This can be avoided by later opening of the semiconductor switches S1 to S4 on the primary side P.

[0091] In a simulation of the method of one embodiment, the semiconductor switches on the primary side are controlled with a duty cycle of less than 0.5. In Figure 17, a duty cycle of 0.45 was assumed as an exemplary value for the simulation.

[0092] In addition, the secondary-side semiconductor switches are controlled in boost mode with a duty cycle that must be selected to be smaller than the duty cycle of the primary-side semiconductor switches. The duty cycle of the secondary-side semiconductor switches depends on the transformation ratio of the DC / DC converter to be represented, i.e., the ratio of secondary voltage to primary voltage. The duty cycle of the secondary-side switches approaches the duty cycle of the primary-side switches when the transformation ratio needs to increase. An example value in the simulation in Figure 17 for boosting from 400V to 600V is 0.2.

[0093] List of reference symbols

[0094] DC / DC converter

[0095] 2.1 , 2.2, 2.3 LC resonant circuit

[0096] 3 DC voltage source

[0097] 4 depression

[0098] 5 Clock generator

[0099] D-diode

[0100] P Primary side

[0101] S Secondary side

[0102] C1, C2, C3 capacitor, capacitance

[0103] CX_P source capacity

[0104] CX_S sink capacity

[0105] Gate_S1 control signal

[0106] Gate_S3 control signal

[0107] Gate_S5 control signal

[0108] Gate_S6 control signal

[0109] Gate_S8 control signal

[0110] Gate_S1+S4 control signal

[0111] Gate_S2+S3 control signal

[0112] HB1 to HB6 half bridge

[0113] HV+1, HV+2, HV-1, HV-2 high voltage potential

[0114] I current l_L1 choke current l_L2 choke current l_L3 choke current l_Q source current

[0115] LS sink current

[0116] L1, L2, L3 inductance, choke

[0117] S1 to S12 semiconductor switches

[0118] U_C1 capacitor voltage

[0119] U_C2 Capacitor voltage

[0120] U_C3 Capacitor voltage

Claims

Patent claims 1. A method for operating a DC / DC converter (1), comprising: - a primary side (P) with at least two half-bridges (HB1, HB2), each with a high-side switch designed as a semiconductor switch (S1, S3) and a low-side switch designed as a semiconductor switch (S2, S4), - a secondary side (S) with at least two half-bridges (HB3, HB4), each with a high-side switch designed as a semiconductor switch (S5, S7, D) and a low-side switch designed as a semiconductor switch (S6, S8, D), - at least one LC resonant circuit (2.1, 2.2) designed as a series resonant circuit, which is arranged between a center tap of one of the half-bridges (HB1, HB2) on the primary side (P) and a center tap of one of the half-bridges (HB3, HB4) on the secondary side (S), and - at least one further LC resonant circuit designed as a series resonant circuit (2.1, 2.2) or a capacitor (C1, C2) arranged between a center tap of another of the half-bridges (HB1, HB2) on the primary side (P) and a center tap of another of the half-bridges (HB3, HB4) on the secondary side (S), wherein the primary side (P) is or will be connected to a DC voltage source (3), and wherein the secondary side (S) is or will be connected to a sink (4), characterized in that on the primary side (P), the high-side switch of a first half-bridge (HB1, HB2) and the low-side switch of a second half-bridge (HB3, HB4) are switched at least substantially in push-pull to the low-side switch of the first half-bridge (HB1, HB2) and the high-side switch of the second half-bridge (HB3, HB4) at a clock frequency, wherein the high-side switch of each half-bridge (HB1, HB2) is only switched on when the Low-side switch of the same half-bridge (HB1, HB2) was turned off and vice versa.

2. Method according to claim 1, characterized in that the clock frequency for resonant switching is set at a natural frequency of the LC resonant circuit (2.1, 2.2) or higher.

3. Method according to claim 1 or 2, characterized in that in a boost mode, at the same time as the high-side switch of one of the half-bridges (HB1, HB2) of the primary side (P) is switched on, the low-side switch of the half-bridge (HB3, HB4) on the secondary side (S) connected thereto via one of the LC resonant circuits (2.1, 2.2) or the capacitor (C1, C2) or the high-side switch of the other half-bridge (HB3, HB4) of the secondary side (S) is first switched on, wherein this low-side switch or high-side switch of the secondary side (S) is controlled with the same clock frequency but a smaller duty cycle than the simultaneously switching on semiconductor switches (S1 to S4) of the primary side (P).

4. Method according to one of claims 1 to 3, characterized in that the semiconductor switches (S1 to S4) of the primary side (P) are only switched off when a choke current (l_L1, l_L2) through the at least one LC resonant circuit (2.1, 2.2) has returned to zero.

5. Method according to one of claims 1 to 4, characterized in that the control of the semiconductor switches (S1 to S4) of the primary side (P) takes place with a duty cycle of maximum 0.

5.

6. Method according to one of claims 1 to 5, characterized in that the control of the semiconductor switches (S5 to S8) of the secondary side (S) takes place with a duty cycle which is selected to be smaller than the duty cycle of the semiconductor switches (S1 to S4) of the primary side.

7. Method for operating a DC / DC converter (1), comprising: - a primary side (P) with at least two half-bridges (HB1, HB2), each with a high-side switch designed as a semiconductor switch (S1, S3) and one each as Low-side switch designed as a semiconductor switch (S2, S4), - a secondary side (S) with at least two half-bridges (HB3, HB4), each with a high-side switch designed as a semiconductor switch (S5, S7, D) and a low-side switch designed as a semiconductor switch (S6, S8, D), - at least one LC resonant circuit (2.1, 2.2) designed as a series resonant circuit, which is arranged between a center tap of one of the half-bridges (HB1, HB2) on the primary side (P) and a center tap of one of the half-bridges (HB3, HB4) on the secondary side (S), and - at least one further LC resonant circuit (2.1, 2.2) designed as a series resonant circuit or a capacitor (C1, 02) which is arranged between a center tap of another of the half-bridges (HB1, HB2) on the primary side (P) and a center tap of another of the half-bridges (HB3, HB4) on the secondary side (S), wherein the primary side (P) is or will be connected to a DC voltage source (3), wherein the secondary side (S) is or will be connected to a sink (4), - wherein the primary side (P) has three half-bridges (HB1, HB2, HB3), each with a high-side switch designed as a semiconductor switch (S1, S3, S5) and a low-side switch designed as a semiconductor switch (S2, S4, S6), and - wherein the secondary side (S) has three half-bridges (HB4, HB5, HB6), each with a high-side switch designed as a semiconductor switch (S7, S9, S11, D) and a low-side switch designed as a semiconductor switch (S8, S10, S12, D), characterized in that on the primary side (P) the high-side switch of each half-bridge (HB1, HB2, HB3) and the low-side switch of the same half-bridge (HB1, HB2, HB3) are switched at least substantially in push-pull with a clock frequency, wherein the three half-bridges (HB1, HB2, HB3) are controlled with a phase offset of 120°.

8. Method according to one of claims 1 to 7, characterized in that a source capacitance (CX_P) or an intermediate circuit capacitor is arranged on the primary side (P) and / or that a sink capacitance (CX_S) is arranged on the secondary side (S).

9. Method according to one of claims 1 to 8, characterized in that the semiconductor switches (S1 to S4) on the primary side (P) are designed as MOSFET or IGBT and / or that the semiconductor switches (S5 to S8) on the secondary side (S) are designed as MOSFET, IGBT or diode (D).

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