Semiconductor device

Abstract

Provided is a semiconductor device having a small footprint. A semiconductor device includes a first and a second transistors and a first to a third insulating layers. The first transistor includes a first and a second conductive layers, a first semiconductor layer, a gate insulating layer, and a first gate electrode. The second transistor includes a third and a fourth conductive layers, a second semiconductor layer, a gate insulating layer, and a second gate electrode. The third conductive layer, the first insulating layer, the first conductive layer, the second insulating layer, and the third insulating layer are provided in this order, and the second and fourth conductive layers are provided on the third insulating layer. The second conductive layer, the third insulating layer, and the second insulating layer include a first opening reaching the first conductive layer, and the first semiconductor layer is provided in a manner such as to cover the first opening. The fourth conductive layer, the third insulating layer, the second insulating layer, and the first insulating layer include a second opening reaching the third conductive layer, and the second semiconductor layer is provided in a manner such as to cover the second opening. The gate insulating layer is located on the first semiconductor layer and the second semiconductor layer. The first gate electrode and the second gate electrode are located on the gate insulating layer.

Description

Semiconductor Devices

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices including transistors are widely used in electronic devices. For example, in display devices, pixel size can be reduced by reducing the area occupied by a transistor, and resolution can be increased. Therefore, miniaturized transistors are in demand.

[0005] As devices requiring high-definition display devices, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR) are being actively developed.

[0006] 2. Description of the Related Art As display devices, for example, light-emitting devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs) have been developed.

[0007] Patent Document 1 discloses a high-definition display device using organic EL elements.

[0008] In a light-emitting device, a source follower circuit is an analog circuit for outputting an output voltage according to an input voltage, in which a bias current flows through a transistor to which a bias voltage is applied, thereby obtaining an output voltage according to the input voltage (see Patent Documents 2 and 3).

[0009] International Publication No. 2016 / 038508 Japanese Patent Application Laid-Open No. 2004-201297 Japanese Patent Application Laid-Open No. 2001-298663

[0010] An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with a small size. Another object is to provide a semiconductor device including a transistor with a short channel length. Another object is to provide a semiconductor device including a transistor with high on-state current. Another object is to provide a semiconductor device including a transistor with high field-effect mobility. Another object is to provide a semiconductor device including a transistor with a small occupancy area. Another object is to provide a semiconductor device including a transistor with high saturation. Another object is to provide a semiconductor device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device that operates at high speed. Another object is to provide a semiconductor device with a small occupancy area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a high-resolution display device. Another object is to provide a display device with high display quality. Another object is to provide a method for manufacturing a semiconductor device or display device with high productivity. Another object is to provide a novel transistor, a semiconductor device, a display device, or a manufacturing method thereof.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a first semiconductor layer, a gate insulating layer, and a first gate electrode. The second transistor includes a third conductive layer, a fourth conductive layer, a second semiconductor layer, a gate insulating layer, and a second gate electrode. The first insulating layer is located on the third conductive layer. The first conductive layer is located on the first insulating layer. The second insulating layer is located on the first conductive layer and the first insulating layer. The third insulating layer is located on the second insulating layer. The second conductive layer and the fourth conductive layer are located on the third insulating layer. The second conductive layer, the third insulating layer, and the second insulating layer have a first opening reaching the first conductive layer. The first semiconductor layer has a region in contact with the top surface of the first conductive layer, the side surface of the second insulating layer, the side surface of the third insulating layer, and the side surface of the second conductive layer in the first opening. The fourth conductive layer, the third insulating layer, the second insulating layer, and the first insulating layer have a second opening reaching the third conductive layer. The second semiconductor layer has a region in contact with the top surface of the third conductive layer, the side surface of the first insulating layer, the side surface of the second insulating layer, the side surface of the third insulating layer, and the side surface of the fourth conductive layer in the second opening. A gate insulating layer is located on the first semiconductor layer and the second semiconductor layer. The first semiconductor layer has a region overlapping with the first gate electrode through the gate insulating layer in the first opening. The second semiconductor layer has a region overlapping with the second gate electrode through the gate insulating layer in the second opening.

[0013] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a first semiconductor layer, a first gate insulating layer, a first gate electrode, a second gate insulating layer, and a second gate electrode. The second transistor includes a third conductive layer, a fourth conductive layer, a second semiconductor layer, the first gate insulating layer, and a third gate electrode. The first insulating layer is located on the third conductive layer. The first conductive layer is located on the first insulating layer. The second insulating layer is located on the first conductive layer and the first insulating layer. The second gate electrode is located on the second insulating layer. The third insulating layer is located on the second gate electrode and the second insulating layer. The second conductive layer and the fourth conductive layer are located on the third insulating layer. The second conductive layer, the third insulating layer, the second gate electrode, and the second insulating layer have a first opening that reaches the first conductive layer. The second gate insulating layer is provided along a sidewall of the first opening. The first semiconductor layer has a region that contacts, in the first opening, an upper surface of the first conductive layer, an upper surface and a side surface of the second gate insulating layer, and a side surface of the second conductive layer. The fourth conductive layer, the third insulating layer, the second insulating layer, and the first insulating layer have a second opening that reaches the third conductive layer. The second semiconductor layer has a region that contacts, in the second opening, an upper surface of the third conductive layer, a side surface of the first insulating layer, a side surface of the second insulating layer, a side surface of the third insulating layer, and a side surface of the fourth conductive layer. The first gate insulating layer is located on the first semiconductor layer and the second semiconductor layer. The first semiconductor layer has, in the first opening, a region overlapping with the first gate electrode via the first gate insulating layer and a region overlapping with the second gate electrode via the second gate insulating layer, and the second semiconductor layer has, in the second opening, a region overlapping with the third gate electrode via the first gate insulating layer.

[0014] In the above-described semiconductor device, the second insulating layer preferably has a portion located between the second gate insulating layer and the first conductive layer.

[0015] In the semiconductor device, the second transistor preferably includes a layer that is in contact with an upper surface and a side surface of the second gate electrode and that contains oxygen and an element contained in the second gate electrode.

[0016] In the semiconductor device, the second transistor preferably includes a layer. The layer is preferably in contact with an upper surface and a side surface of the second gate electrode. The second gate electrode preferably includes aluminum. The layer preferably includes aluminum and oxygen.

[0017] In the above-described semiconductor device, the first conductive layer preferably has a region overlapping with the third conductive layer.

[0018] In the semiconductor device, the first semiconductor layer and the second semiconductor layer preferably contain metal oxide, and the first insulating layer preferably has a region having a higher hydrogen concentration than the second insulating layer.

[0019] In the semiconductor device described above, the first semiconductor layer and the second semiconductor layer each preferably contain a metal oxide. The first insulating layer preferably contains silicon, nitrogen, and hydrogen. The second insulating layer preferably contains silicon and nitrogen. The third insulating layer preferably contains silicon and oxygen.

[0020] The semiconductor device preferably includes a fourth insulating layer. The fourth insulating layer is preferably located between the second conductive layer, the fourth conductive layer, and the third insulating layer. The fourth insulating layer preferably contains silicon and nitrogen.

[0021] The semiconductor device preferably includes a fourth insulating layer. The fourth insulating layer is preferably located between the second conductive layer, the fourth conductive layer, and the third insulating layer. The fourth insulating layer preferably contains one or both of aluminum and hafnium, and oxygen.

[0022] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor can be provided. Alternatively, a semiconductor device including a transistor with a short channel length can be provided. Alternatively, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with high field-effect mobility can be provided. Alternatively, a semiconductor device including a transistor with a small occupancy area can be provided. Alternatively, a semiconductor device including a transistor with high saturation property can be provided. Alternatively, a semiconductor device including a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device that operates at high speed can be provided. Alternatively, a semiconductor device with a small occupancy area can be provided. Alternatively, a semiconductor device with low wiring resistance can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a display device with high display quality can be provided. Alternatively, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Alternatively, a novel transistor, semiconductor device, or display device, or a manufacturing method thereof can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0024] FIG. 1A is a top view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIGS. 2A to 2D are perspective views showing an example of a semiconductor device. FIG. 3A is a top view showing an example of a semiconductor device. FIGS. 3B and 3C are cross-sectional views showing an example of a semiconductor device. FIG. 4A is a top view showing an example of a semiconductor device. FIG. 4B is a cross-sectional view showing an example of a semiconductor device. FIG. 5A is a top view showing an example of a semiconductor device. FIGS. 5B and 5C are cross-sectional views showing an example of a semiconductor device. FIG. 6A is a top view showing an example of a semiconductor device. FIGS. 6B and 6C are cross-sectional views showing an example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing an example of a semiconductor device. FIG. 8 is a cross-sectional view showing an example of a semiconductor device. FIG. 9A is a top view showing an example of a semiconductor device. FIGS. 9B and 9C are cross-sectional views showing an example of a semiconductor device. FIGS. 10A and 10B are cross-sectional views showing an example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of a semiconductor device. FIGS. 12A to 12H are cross-sectional views showing an example of a semiconductor device. 13A to 13C are cross-sectional views showing an example of a semiconductor device. FIG. 14A is a top view showing an example of a semiconductor device. FIGS. 14B and 14C are cross-sectional views showing an example of a semiconductor device. FIGS. 15A to 15C are cross-sectional views showing an example of a semiconductor device. FIGS. 16A to 16C are cross-sectional views showing an example of a semiconductor device. FIGS. 17A and 17B are cross-sectional views showing an example of a semiconductor device. FIGS. 18A and 18B are cross-sectional views showing an example of a semiconductor device. FIG. 19 is a cross-sectional view showing an example of a semiconductor device. FIGS. 20A to 20C are cross-sectional views showing an example of a semiconductor device. FIGS. 21A and 21B are cross-sectional views showing an example of a semiconductor device. FIGS. 22A and 22B are cross-sectional views showing an example of a semiconductor device. FIG. 23 is a top view showing an example of a semiconductor device. FIGS. 24A and 24B are cross-sectional views showing an example of a semiconductor device. FIGS. 25A to 25C are cross-sectional views showing an example of a semiconductor device. FIGS. 26A to 26F are cross-sectional views showing an example of a manufacturing method of a semiconductor device. 27A to 27E are cross-sectional views showing an example of a method for manufacturing a semiconductor device.28A to 28D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 29A to 29D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 30A and 30B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 31A is a perspective view showing an example of a display device. FIG. 31B is a block diagram showing an example of a display device. FIGS. 32A to 32E are circuit diagrams of pixel circuits. FIGS. 33A to 33C are circuit diagrams of pixel circuits. FIG. 34 is a top view showing an example of a pixel layout. FIG. 35 is a top view showing an example of a pixel layout. FIG. 36 is a cross-sectional view showing an example of a pixel configuration. FIGS. 37A to 37C are top views showing an example of a pixel layout. FIGS. 38A to 38C are top views showing an example of a pixel layout. FIGS. 39A to 39C are top views showing an example of a pixel layout. FIGS. 40A and 40B are top views showing an example of a pixel layout. FIG. 41 is a cross-sectional view showing an example of a pixel configuration. FIG. 42 is a block diagram showing a configuration example of a semiconductor device. FIG. 43 is a block diagram showing a configuration example of a semiconductor device. FIG. 44A is a block diagram showing a configuration example of a semiconductor device. FIG. 44B is a circuit diagram showing a configuration example of a semiconductor device. FIG. 45 is a circuit diagram showing a configuration example of a semiconductor device. FIG. 46 is a circuit diagram showing a configuration example of a semiconductor device. FIGS. 47A and 47B are circuit diagrams showing a configuration example of a semiconductor device. FIGS. 48A and 48B are circuit diagrams showing a configuration example of a semiconductor device. FIG. 49 is a circuit diagram showing a configuration example of a semiconductor device. FIG. 50 is a circuit diagram showing a configuration example of a semiconductor device. FIGS. 51A and 51B are cross-sectional views showing an example of a display device. FIG. 52 is a cross-sectional view showing an example of a display device. FIGS. 53A to 53C are cross-sectional views showing an example of a display device. FIGS. 54A and 54B are cross-sectional views showing an example of a display device. FIG. 55 is a cross-sectional view showing an example of a display device. FIG. 56 is a cross-sectional view showing an example of a display device. FIG. 57 is a cross-sectional view showing an example of a display device. FIG. 58 is a cross-sectional view showing an example of a display device. FIGS. 59A and 59B are cross-sectional views showing an example of a display device. 60A to 60F are cross-sectional views showing an example of a method for manufacturing a display device.Fig. 61A to Fig. 61D are diagrams showing an example of an electronic device. Fig. 62A to Fig. 62F are diagrams showing an example of an electronic device. Fig. 63A to Fig. 63G are diagrams showing an example of an electronic device. Fig. 64A to Fig. 64C are diagrams showing Id-Vg characteristics of a transistor according to an example. Fig. 65 is a photograph of the display state of an OLED panel according to an example.

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0027] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0028] In this specification, the ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0029] In this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", or "[m, n]" may be added to the reference numeral. Furthermore, when explaining matters common to multiple elements to which an identification numeral is added, or when it is not necessary to distinguish between them, the elements may be described without the identification numeral.

[0030] The words "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0031] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0032] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. The source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, depending on the situation.

[0033] The terms "gate" and "back gate" can be used interchangeably. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0034] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0035] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0036] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0037] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0038] In this specification, unless otherwise specified, the on-state current refers to the drain current (also referred to as Id) when a transistor is in an on state (also referred to as a conductive state). Unless otherwise specified, the on state refers to a state in which the gate-source voltage (also referred to as Vg or Vgs) is equal to or higher than a threshold voltage (also referred to as Vth) for an n-channel transistor, or a state in which the gate-source voltage is equal to or lower than the threshold voltage for a p-channel transistor.

[0039] In this specification and the like, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and the source is lower than the threshold voltage in an n-channel transistor, and higher than the threshold voltage in a p-channel transistor.

[0040] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0041] In this specification, the phrase "top surface shapes that match or approximately match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes that match or approximately match" may also be used. Furthermore, when the top surface shapes match or approximately match, it can also be said that "edges match or approximately match" or "edges are aligned or approximately aligned."

[0042] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0043] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution due to the alignment accuracy of the metal mask. Furthermore, devices with an MML structure can eliminate the need for equipment for manufacturing metal masks and a metal mask cleaning process. Furthermore, devices with an MML structure are suitable for mass production because they can keep manufacturing costs low.

[0044] In this specification and the like, a structure in which light-emitting layers are separately formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, thereby widening the range of material and configuration options and facilitating improvements in brightness and reliability.

[0045] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0046] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

[0047] In this specification, the sacrificial layer is located above at least the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that constitute the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0048] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0049] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 25C.

[0050] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer.

[0051] The first transistor includes a first conductive layer, a second conductive layer, a first semiconductor layer, a gate insulating layer, and a first gate electrode, and the first conductive layer functions as one of a source electrode and a drain electrode, and the second conductive layer functions as the other of the source electrode and the drain electrode.

[0052] The second transistor includes a third conductive layer, a fourth conductive layer, a second semiconductor layer, a gate insulating layer, and a second gate electrode, and the third conductive layer functions as one of a source electrode and a drain electrode, and the fourth conductive layer functions as the other of the source electrode and the drain electrode.

[0053] The first insulating layer is located on the third conductive layer. The first conductive layer is located on the first insulating layer. The second insulating layer is located on the first conductive layer and the first insulating layer. The third insulating layer is located on the second insulating layer. The second conductive layer and the fourth conductive layer are located on the third insulating layer. The second conductive layer, the third insulating layer, and the second insulating layer have a first opening that reaches the first conductive layer. The first semiconductor layer has, in the first opening, a region that contacts the top surface of the first conductive layer, a side surface of the second insulating layer, a side surface of the third insulating layer, and the side surface of the second conductive layer. The fourth conductive layer, the third insulating layer, the second insulating layer, and the first insulating layer have a second opening that reaches the third conductive layer. The second semiconductor layer has an area in contact with the top surface of the third conductive layer, the side surface of the first insulating layer, the side surface of the second insulating layer, the side surface of the third insulating layer, and the side surface of the fourth conductive layer in the second opening.

[0054] The gate insulating layer is located on the first semiconductor layer and the second semiconductor layer, the first semiconductor layer has a region that overlaps with the first gate electrode through the gate insulating layer in the first opening, and the second semiconductor layer has a region that overlaps with the second gate electrode through the gate insulating layer in the second opening.

[0055] The channel lengths of the first transistor and the second transistor can be controlled by the thickness of an insulating layer sandwiched between the source electrode and the drain electrode. In other words, the channel lengths of the first transistor and the second transistor are not affected by the exposure performance of an exposure apparatus used for fabrication. Therefore, the channel lengths of the first transistor and the second transistor can be shorter than the minimum dimension that the exposure apparatus can expose (hereinafter also referred to as the minimum dimension). By shortening the channel length, the transistor can have a large on-state current. Furthermore, since the source electrode, the layer having the channel formation region, and the drain electrode can be provided overlapping with each other, the area occupied by the transistor can be reduced. Therefore, the area occupied by a semiconductor device including the transistor can be reduced.

[0056] The formation surface of the first conductive layer and the formation surface of the third conductive layer are different from each other, and the first conductive layer and the third conductive layer are formed in different processes. The first conductive layer and the third conductive layer are electrically insulated by a first insulating layer. By making the formation surface of the first conductive layer and the formation surface of the third conductive layer different, the spacing between these conductive layers can be shortened without being affected by design rules in photolithography, and the occupation area of ​​the semiconductor device can be reduced. Furthermore, by having a region where the first conductive layer overlaps with the third conductive layer, the occupation area of ​​the semiconductor device can be further reduced.

[0057] A more specific example will be described below with reference to the drawings.

[0058] <Configuration Example 1> A semiconductor device according to one embodiment of the present invention will be described. FIG. 1A shows a top view (also referred to as a plan view) of a semiconductor device 10. FIG. 1B shows a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 1C shows cross-sectional views of cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4. Note that some components of the semiconductor device 10 (such as a gate insulating layer) are omitted in FIG. 1A. As with FIG. 1A, some components are omitted in the top views of the semiconductor device in the following drawings. Also, some hidden lines may be omitted.

[0059] The semiconductor device 10 includes a transistor 100, a transistor 200, an insulating layer 110, and an insulating layer 107. The semiconductor device 10 is provided on an insulating surface. FIGS. 1B and 1C show a configuration in which the semiconductor device 10 is provided on a substrate 102 having an insulating surface. Note that an insulating film may be provided on the substrate 102, and the semiconductor device 10 may be provided on the insulating film. The transistor 100 and the transistor 200 can be formed on the same substrate by sharing some of the steps.

[0060] 2A and 2B show perspective views of the transistor 100. FIG. 2B shows a cross section taken along dashed-dotted line C1-C2 in FIG. 2A. FIGS. 2C and 2D show perspective views of the transistor 200. FIG. 2D shows a cross section taken along dashed-dotted line C3-C4 in FIG. 2C. In FIGS. 2A to 2D, the insulating layers 110 and 106 are shown in a transparent manner, with their outlines indicated by dashed lines. FIG. 3B shows an enlarged view of the transistor 100 shown in FIG. 1B, and FIG. 3C shows an enlarged view of the transistor 200.

[0061] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. In the transistor 100, the conductive layer 104 functions as a gate electrode, the insulating layer 106 functions as a gate insulating layer, the conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other of the source electrode and drain electrode. The semiconductor layer 108 includes a channel formation region of the transistor 100.

[0062] The transistor 200 includes a conductive layer 204, an insulating layer 106, a semiconductor layer 208, a conductive layer 212a, and a conductive layer 212b. In the transistor 200, the conductive layer 204 functions as a gate electrode, the insulating layer 106 functions as a gate insulating layer, the conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other of the source electrode and drain electrode. The semiconductor layer 208 includes a channel formation region of the transistor 200.

[0063] An insulating layer 195 is provided to cover the transistor 100 and the transistor 200. The insulating layer 195 functions as a protective layer for the transistor 100 and the transistor 200. Note that the insulating layer 195 is omitted in the perspective views shown in FIGS.

[0064] A conductive layer 212a is provided over the substrate 102, an insulating layer 107 is provided over the conductive layer 212a, and a conductive layer 112a is provided over the insulating layer 107. The insulating layer 107 has a region in contact with the top surface and side surfaces of the conductive layer 212a and the top surface of the substrate 102. The surface on which the conductive layer 212a is to be formed (here, the top surface of the substrate 102) is different from the surface on which the conductive layer 112a is to be formed (here, the top surface of the insulating layer 107). Furthermore, the conductive layer 212a can be formed in a different process from that of the conductive layer 112a. By forming the conductive layer 212a and the conductive layer 112a in different processes, different materials can be used for the conductive layer 212a and the conductive layer 112a, thereby widening the range of material selection.

[0065] When photolithography is used to fabricate a semiconductor device, each component of the semiconductor device is arranged according to a design rule. Examples of components formed using photolithography include the layers of the transistor 100 and the transistor 200 (here, the semiconductor layer 108, the conductive layers 112a and 212a, etc.). Furthermore, the openings 141, 143, 241, and 243 are also arranged according to a design rule. When the semiconductor device has wiring formed using photolithography, the wiring is also arranged according to a design rule. Examples of design rules include the width of a layer (hereinafter also referred to as a line), the width of a wiring, and the spacing between layers in the same layer (hereinafter also referred to as a space), the spacing between a layer and a wiring, and the spacing between wirings. The size of the opening is also included in the design rule. By forming the conductive layer 112a of the transistor 100 and the conductive layer 212a of the transistor 200 in different processes, the distance between the conductive layers 112a and 212a is not affected by design rules, and the distance between the conductive layers 112a and 212a can be reduced. This reduces the distance between the transistors, thereby reducing the area occupied by a semiconductor device including the transistors. Furthermore, the conductive layer 112a can have a region overlapping with the conductive layer 212a. This reduces the area occupied by the semiconductor device. Furthermore, by forming the conductive layer 112a on a surface different from the surface on which the conductive layer 212a is formed, the degree of freedom in layout is increased, and the area occupied by the semiconductor device can be reduced. Note that the top surface shape of a layer, an opening, and a wiring formed by photolithography, or a photoresist used to form these layers, may be referred to as a pattern.

[0066] 1A to 1C show a structure in which the conductive layer 112a does not overlap with the conductive layer 212a in a region thereof, but one embodiment of the present invention is not limited to this. The conductive layer 112a may have a region overlapping with the conductive layer 212a.

[0067] 4A and 4B show examples of a configuration different from that shown in FIGS. 1A to 1C. FIG. 4A is a top view of the semiconductor device 10. FIG. 4B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 shown in FIG. 4A. For cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4, refer to FIG. 1B.

[0068] 4A and 4B , the conductive layer 212a has an overlapping region with the conductive layer 112a. The semiconductor device 10 has an overlapping region in which the conductive layer 212a, the insulating layer 107, and the conductive layer 112a overlap in this order, with no other layers in between. This allows the semiconductor device to occupy a smaller area. The insulating layer 107 is located between the conductive layer 112a and the conductive layer 212a, and the conductive layer 112a and the conductive layer 212a are electrically insulated from each other by the insulating layer 107.

[0069] The conductive layer 112a and the conductive layer 212a overlap with each other, thereby providing a capacitor including these conductive layers as a pair of electrodes. FIGS. 4A and 4B show a capacitor 150 including the conductive layer 112a, the conductive layer 212a, and an insulating layer 107 sandwiched between the conductive layer 112a and the conductive layer 212a. The conductive layer 112a functions as one of the source and drain electrodes of the transistor 100 and also functions as one electrode of the capacitor 150. The conductive layer 212a functions as one of the source and drain electrodes of the transistor 200 and also functions as the other electrode of the capacitor 150. One of the source and drain electrodes of the transistor 100 is electrically connected to one electrode of the capacitor 150. One of the source and drain electrodes of the transistor 200 is electrically connected to the other electrode of the capacitor 150. Note that there is no particular limitation on the connection between the transistor and the capacitor included in the semiconductor device.

[0070] 5A to 5C show examples of configurations different from those shown in Figures 1A to 1C, 4A, and 4B. Figure 5A is a top view of semiconductor device 10. Figure 5B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in Figure 5A, and Figure 5C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0071] 5A to 5C , the conductive layer 212a has a region overlapping with the transistor 100. The conductive layer 212a has a region overlapping with one or more of the conductive layer 112a, the conductive layer 112b, the semiconductor layer 108, and the conductive layer 104. FIGS. 5A to 5C show a configuration in which the semiconductor device 10 has a region in which the conductive layer 212a, the insulating layer 107, the conductive layer 112a, the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 overlap in this order without any other layers therebetween. This can reduce the area occupied by the semiconductor device. Furthermore, the degree of freedom in the layout of the conductive layer 112a and the conductive layer 212a is increased, and the area occupied by the semiconductor device can be further reduced.

[0072] 1B and other figures, an insulating layer 110 is provided over the conductive layer 112a. The insulating layer 110 has a region in contact with the top surface and side surfaces of the conductive layer 112a and the top surface of the insulating layer 107.

[0073] The conductive layer 112b and the conductive layer 212b are provided over the insulating layer 110. The conductive layer 112b and the conductive layer 212b each have a region in contact with the top surface of the insulating layer 110. The conductive layer 112b has a region overlapping with the conductive layer 112a with the insulating layer 110 interposed therebetween. It can also be said that the insulating layer 110 has a region sandwiched between the conductive layer 112a and the conductive layer 112b. The conductive layer 212b has a region overlapping with the conductive layer 212a with the insulating layer 110 and the insulating layer 107 interposed therebetween. It can also be said that the insulating layer 110 and the insulating layer 107 have a region sandwiched between the conductive layer 212a and the conductive layer 212b. The conductive layer 212b can be formed in the same process as the conductive layer 112b. For example, the conductive layer 112b and the conductive layer 212b can be formed by forming a film to become the conductive layer 112b and the conductive layer 212b and then processing the film. Alternatively, the conductive layer 212b can be formed in a different process from that of the conductive layer 112b. By forming the conductive layer 212b and the conductive layer 112b in different processes, different materials can be used for the conductive layer 212b and the conductive layer 112b, thereby widening the range of material selection.

[0074] The insulating layer 110 has an opening 141 that reaches the conductive layer 112a. The insulating layer 110 and the insulating layer 107 have an opening 241 that reaches the conductive layer 212a. It can be said that the conductive layer 112a is exposed in the opening 141, and the conductive layer 212a is exposed in the opening 241. The opening 241 can be formed in the same process as the opening 141. For example, a first film that will become the insulating layer 107 is formed on the conductive layer 212a, the conductive layer 112a is formed on the first film, and a second film that will become the insulating layer 110 is formed on the first film and the conductive layer 112a. Then, the first film and the second film are processed to form the insulating layer 110 and the insulating layer 107 that have the opening 141 and the opening 241. Alternatively, the opening 241 can be formed in a process different from that for the opening 141.

[0075] The conductive layer 112b has an opening 143 in a region overlapping with the conductive layer 112a. The opening 143 is provided in a region overlapping with the opening 141. Note that in FIG. 1B and the like, the opening 141 in the insulating layer 110 and the opening 143 in the conductive layer 112b are denoted by different reference numerals, but these openings can be collectively referred to as one opening. In other words, the insulating layer 110 and the conductive layer 112b can be said to have openings that reach the conductive layer 112a.

[0076] The conductive layer 212b has an opening 243 in a region overlapping with the conductive layer 212a. The opening 243 is provided in a region overlapping with the opening 241. The opening 243 can be formed in the same process as the opening 241. Alternatively, the opening 243 can be formed in a process different from that for the opening 241. Note that in FIG. 1B and the like, the opening 241 in the insulating layer 110 and the insulating layer 107 and the opening 243 in the conductive layer 212b are denoted by different reference numerals, but these openings can be collectively referred to as one opening. In other words, the insulating layer 110, the insulating layer 107, and the conductive layer 212b can be said to have openings that reach the conductive layer 212a.

[0077] The semiconductor layer 108 is provided to cover the openings 141 and 143. The semiconductor layer 108 is provided along the openings 141 and 143. The semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a in the opening 141, a region in contact with the side surface of the insulating layer 110 in the opening 141, and a region in contact with the side surface of the conductive layer 112b in the opening 143. Furthermore, the semiconductor layer 108 preferably has a region in contact with the top surface of the conductive layer 112b. The semiconductor layer 108 has a shape that follows the shapes of the top surface and side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the top surface of the conductive layer 112a. The region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source region and drain region of the transistor 100, and the region in contact with the conductive layer 112b functions as the other of the source region and drain region.

[0078] The semiconductor layer 208 is provided so as to cover the openings 241 and 243. The semiconductor layer 208 is provided along the openings 241 and 243. The semiconductor layer 208 has a region in contact with the top surface of the conductive layer 212a in the opening 241, a region in contact with the side surface of the insulating layer 110 in the opening 241, a region in contact with the side surface of the insulating layer 107 in the opening 241, and a region in contact with the side surface of the conductive layer 212b in the opening 243. Furthermore, the semiconductor layer 208 preferably has a region in contact with the top surface of the conductive layer 212b. The semiconductor layer 208 has a shape that follows the shapes of the top surface and side surface of the conductive layer 212b, the side surface of the insulating layer 110, the side surface of the insulating layer 107, and the top surface of the conductive layer 212a. A region of the semiconductor layer 208 in contact with the conductive layer 212a functions as one of the source and drain regions of the transistor 200, and a region of the semiconductor layer 208 in contact with the conductive layer 212b functions as the other of the source and drain regions.

[0079] The conductive layer 112b preferably has a region sandwiched between the insulating layer 110 and the semiconductor layer 108. When the semiconductor layer 108 is in contact with not only the side surface but also the top surface of the conductive layer 112b, the contact area between the semiconductor layer 108 and the conductive layer 112b is increased, and the contact resistance between the semiconductor layer 108 and the conductive layer 112b can be reduced. This can increase the on-state current of the transistor 100. Note that although FIG. 1B and other drawings illustrate a structure in which an end of the semiconductor layer 108 is in contact with the top surface of the conductive layer 112b, one embodiment of the present invention is not limited thereto. The end of the semiconductor layer 108 can be aligned or approximately aligned with an end of the conductive layer 112b on a side that does not face the opening 143. Alternatively, the semiconductor layer 108 can cover the end of the conductive layer 112b on the side that does not face the opening 143, and the end of the semiconductor layer 108 can be in contact with the top surface of the insulating layer 110. Note that a structure in which the semiconductor layer 108 is not in contact with the top surface of the conductive layer 112b but is in contact with only the side surface of the conductive layer 112b on the opening 143 side can be used. For the conductive layer 212b and the semiconductor layer 208, the descriptions of the conductive layer 112b and the semiconductor layer 108 can be referred to.

[0080] The semiconductor layer 208 can be formed in the same process as the semiconductor layer 108. For example, the semiconductor layer 108 and the semiconductor layer 208 can be formed by forming films that will become the semiconductor layer 108 and the semiconductor layer 208 and processing the films. Note that the semiconductor layer 108 and the semiconductor layer 208 can also be formed in different processes. By forming the semiconductor layer 108 and the semiconductor layer 208 in different processes, different materials can be used for the semiconductor layer 108 and the semiconductor layer 208, thereby widening the range of material selection.

[0081] As shown in FIG. 1A and other figures, the top shapes of the openings 141 and 143 can be identical or substantially identical to each other. In this case, as shown in FIGS. 1B and 1C and other figures, it is preferable that the bottom edge of the conductive layer 112b on the opening 143 side be identical or substantially identical to the top edge of the insulating layer 110 on the opening 141 side. The bottom surface of the conductive layer 112b refers to the surface on the insulating layer 110 side. The top surface of the insulating layer 110 refers to the surface on the conductive layer 112b side. Note that the top shapes of the openings 141 and 143 may not be identical to each other. When the top shape of the opening 143 does not match the top shape of the opening 141, it is preferable that the opening 143 encompasses the opening 141 in a top view (also referred to as a plan view). When the top shape of the opening 143 is identical to the top shape of the opening 141 or when the opening 143 encompasses the opening 141 in a top view, coverage of the semiconductor layer 108 can be improved. For the openings 241 and 243, the description of the openings 141 and 143 can be referred to.

[0082] In this specification and the like, the top surface shape of opening 141 refers to the shape of the top surface end portion of insulating layer 110 on the opening 141 side. The top surface shape of opening 143 refers to the shape of the bottom surface end portion of conductive layer 112b on the opening 143 side. The top surface shape of opening 241 refers to the shape of the top surface end portion of insulating layer 110 on the opening 241 side. The top surface shape of opening 243 refers to the shape of the bottom surface end portion of conductive layer 212b on the opening 243 side.

[0083] An insulating layer 106 is provided over the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112a, the conductive layer 212b, and the insulating layer 110. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the semiconductor layer 208, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the conductive layer 212b, and the top surface of the insulating layer 110. A part of the insulating layer 106 functions as a gate insulating layer of the transistor 100, and the other part functions as a gate insulating layer of the transistor 200. The insulating layer 106 is provided to cover the openings 141, 143, 241, and 243, and has a shape following the shapes of the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the semiconductor layer 208, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the conductive layer 212b, and the top surface of the insulating layer 110.

[0084] The conductive layer 104 and the conductive layer 204 are provided over the insulating layer 106. The conductive layer 104 and the conductive layer 204 each have a region in contact with the insulating layer 106 and have shapes that follow the shapes of the top surface and side surface of the insulating layer 106.

[0085] The conductive layer 104 has a region that overlaps with the semiconductor layer 108 with the insulating layer 106 interposed therebetween in the opening 141. A region of the semiconductor layer 108 that overlaps with the conductive layer 104 with the insulating layer 106 interposed therebetween, between the source region and the drain region, functions as a channel formation region of the transistor 100. The conductive layer 204 has a region that overlaps with the semiconductor layer 208 with the insulating layer 106 interposed therebetween, in the opening 241. A region of the semiconductor layer 208 that overlaps with the conductive layer 204 with the insulating layer 106 interposed therebetween, between the source region and the drain region, functions as a channel formation region of the transistor 200. The conductive layer 104 is provided to cover the opening 141 and has a shape that follows the shape of the top surface and side surface of the insulating layer 106 in the openings 141 and 143. The conductive layer 204 is provided to cover the openings 241 and 243 and has a shape that follows the shape of the top surface and side surface of the insulating layer 106 in the openings 241 and 243. The conductive layer 204 can be formed in the same process as the conductive layer 104. For example, the conductive layer 104 and the conductive layer 204 can be formed by forming films to become the conductive layer 104 and the conductive layer 204 and processing the films. Note that the conductive layer 104 and the conductive layer 204 can also be formed in different processes. By forming the conductive layer 104 and the conductive layer 204 in different processes, different materials can be used for the conductive layer 104 and the conductive layer 204, thereby widening the range of material selection.

[0086] In the transistor 100 and the transistor 200, the source electrode and the drain electrode are located at different heights relative to the surface of the substrate 102, which is the surface on which the transistors are formed, and the drain current flows in a direction perpendicular or approximately perpendicular to the surface of the substrate 102. In other words, since the channel length direction can be said to have a component in the height direction (vertical direction), the transistors 100 and 200 can also be called VFETs (Vertical Field Effect Transistors), vertical transistors, vertical channel transistors, vertical channel transistors, etc. Note that in the transistor 100, the conductive layer 112a can be called a lower electrode, and the conductive layer 112b can be called an upper electrode. Similarly, in the transistor 200, the conductive layer 212a can be called a lower electrode, and the conductive layer 212b can be called an upper electrode.

[0087] The channel lengths of the transistors 100 and 200 can be controlled by the thickness of the insulating layer sandwiched between the source electrode and the drain electrode. Therefore, the transistors 100 and 200 can be manufactured with high precision, each having a channel length shorter than the minimum exposure dimension of the exposure equipment used to manufacture the transistors. Furthermore, the reduction in the characteristic variations of multiple transistors stabilizes the operation of the semiconductor device 10, improving its reliability. Furthermore, the reduction in the characteristic variations of transistors increases the degree of freedom in circuit design, allowing the operating voltage of the semiconductor device 10 to be lowered. Therefore, the power consumption of the semiconductor device 10 can be reduced.

[0088] The transistor 100 and the transistor 200 can each have a source electrode, a semiconductor layer, and a drain electrode that are stacked together. Therefore, the area occupied by each of the transistors 100 and 200 can be significantly reduced compared to a so-called planar transistor in which these electrodes are arranged in a plane. This allows for a compact semiconductor device.

[0089] The conductive layers 112a, 112b, and 104 can each function as wirings, and the transistor 100 can be provided in a region where these wirings overlap. Similarly, the conductive layers 212a, 212b, and 204 can each function as wirings, and the transistor 200 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100, the transistor 200, and wirings, the area occupied by these can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided.

[0090] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be obtained.Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (for example, one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

[0091] By making the formation surfaces of the lower electrodes of the transistors 100 and 200 different, the distance between them can be reduced, thereby reducing the distance between the transistors 100 and 200. This reduces the area occupied by the semiconductor device. Furthermore, by providing a region where the lower electrode of the transistor 100 overlaps with the lower electrode of the transistor 200, the area occupied by the semiconductor device can be further reduced.

[0092] The semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: Oxide Semiconductor). Note that these semiconductor materials may contain impurities as dopants.

[0093] The crystallinity of the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. The use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0094] The semiconductor layer 108 and the semiconductor layer 208 can each be made of, for example, silicon. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using amorphous silicon for its channel formation region can be formed on a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon for its channel formation region has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for its channel formation region has higher field-effect mobility than a transistor using amorphous silicon and can operate at high speed. Note that a transistor using silicon for its channel formation region may be referred to as a Si transistor, and a transistor using LTPS for its channel formation region may be referred to as an LTPS transistor.

[0095] The semiconductor layer 108 and the semiconductor layer 208 each preferably contain a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the semiconductor layer 108 and the semiconductor layer 208 can each be referred to as a metal oxide layer. The band gap of the metal oxide used for the semiconductor layer 108 and the semiconductor layer 208 is preferably 2.0 eV or more, more preferably 2.5 eV or more.

[0096] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0097] The insulating layer 110 can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0098] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0099] The insulating layer 110 has a region in contact with the semiconductor layer 108 and a region in contact with the semiconductor layer 208. When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable that at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 and at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 208 contain oxygen in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110 and the interface characteristics between the semiconductor layer 208 and the insulating layer 110. In particular, it is preferable that the portion of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 and the portion of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 208 contain oxygen. One or more of an oxide and an oxynitride can be suitably used for the portion of the insulating layer 110 in contact with the channel formation region.

[0100] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable that at least a part of a region of the insulating layer 110 in contact with the semiconductor layer 108 and at least a part of a region of the insulating layer 110 in contact with the semiconductor layer 208 each release oxygen when heated. In particular, it is preferable that a portion of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 and a portion of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 208 each release oxygen when heated. As a result, oxygen is supplied from the insulating layer 110 to the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies (V Ｏ : Oxygen Vacancy), and oxygen deficiency (V Ｏ ) into which hydrogen has entered (hereinafter referred to as V Ｏ H) can be reduced.

[0101] Here, V is added to the metal oxide. Ｏ As H increases, V Ｏ Carriers may be generated by H, increasing the carrier concentration. In particular, if the carrier concentration in the channel formation region is high, the threshold voltage of the transistor may shift, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may increase. For example, in the case of an n-channel transistor, the threshold voltage may shift to the negative side, increasing the cutoff current. In addition, the reliability of the transistor may decrease. Oxygen vacancies (V Ｏ ) and V Ｏ By reducing H, it is possible to prevent the carrier concentration in the channel formation region from increasing. As a result, a shift in threshold voltage is prevented, a transistor with a small cutoff current can be obtained, and a semiconductor device with low power consumption can be obtained. In addition, a highly reliable transistor and semiconductor device can be obtained.

[0102] The insulating layer 110 preferably has a stacked structure. In Fig. 1B and other drawings, the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can each be made of the materials listed for the insulating layer 110.

[0103] The insulating layer 110b preferably contains oxygen, and preferably uses one or more of the oxides and oxynitrides described above. As a result, at least a region of the semiconductor layer 108 in contact with the insulating layer 110b can function as a channel formation region of the transistor 100. The conductive layer 104 has a portion that overlaps with the channel formation region of the transistor 100 with the insulating layer 106 interposed therebetween. Similarly, at least a region of the semiconductor layer 208 in contact with the insulating layer 110b can function as a channel formation region of the transistor 200. The conductive layer 204 has a portion that overlaps with the channel formation region of the transistor 200 with the insulating layer 106 interposed therebetween. The insulating layer 110b preferably contains silicon and oxygen. For example, one or both of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 110b. Note that although two regions of the semiconductor layer 108 in contact with the insulating layer 110b are shown in cross-sectional views such as FIG. 3A , these regions are connected to one another in a top view. The same applies to the semiconductor layer 208.

[0104] It is more preferable to use a material that releases oxygen when heat is applied for the insulating layer 110b. When heat is applied during the manufacturing process of the semiconductor device 10, the insulating layer 110b releases oxygen, which allows oxygen to be supplied to the semiconductor layer 108 and the semiconductor layer 208. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108 and the semiconductor layer 208, particularly to the channel formation region, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Ｏ H can be reduced. Therefore, the transistors 100 and 200 can have favorable electrical characteristics and high reliability.

[0105] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied by forming a film on the top surface of the insulating layer 110b by sputtering in an oxygen-containing atmosphere. The film can then be removed. When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the metal oxide film that becomes the semiconductor layer 108 and the semiconductor layer 208 is preferably formed in an oxygen-containing atmosphere. This allows oxygen to be supplied to the insulating layer 110b. Then, oxygen is supplied from the insulating layer 110b to the semiconductor layer 108 and the semiconductor layer 208 in a later step, and oxygen vacancies (V Ｏ ) and V Ｏ It is possible to reduce H. Note that a method for supplying oxygen to the insulating layer 110b will be specifically described in Embodiment 2.

[0106] The insulating layer 110b is preferably formed by a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method. In particular, by forming the insulating layer 110b by a method that does not use a gas containing a hydrogen element (e.g., hydrogen gas or ammonia gas) as a deposition gas, a film with an extremely low hydrogen content can be obtained. The sputtering method is particularly suitable for forming the insulating layer 110b. This can suppress the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 100 and the transistor 200.

[0107] Here, by using a material with high conductivity for the semiconductor layer 108 and the semiconductor layer 208, the transistor 100 and the transistor 200 can have large on-state current. However, when a material with high conductivity is used, oxygen vacancies (V Ｏ ) is easily formed, and V Ｏ H may increase. ＯThe increase in H may shift the threshold voltage of the transistor and increase the cutoff current. By providing the insulating layer 110b, oxygen is supplied to at least the region in contact with the insulating layer 110b, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. As a result, a shift in the threshold voltage can be suppressed, and the transistors 100 and 200 can have both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0108] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a and the insulating layer 107. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b and the conductive layer 212b. The insulating layer 110a and the insulating layer 110c preferably release small amounts of impurities (e.g., hydrogen and water) from themselves. Furthermore, the insulating layer 110a and the insulating layer 110c preferably are impermeable to substances (e.g., atoms, molecules, and ions). The insulating layer 110a and the insulating layer 110c can also function as barrier films. Specifically, the insulating layer 110a and the insulating layer 110c preferably are impermeable to impurities. This can prevent impurities contained in the insulating layer 110a and the insulating layer 110c from diffusing into the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208. Therefore, the transistor 100 and the transistor 200 can have excellent electrical characteristics and high reliability.

[0109] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby suppressing the substance from permeating the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0110] The insulating layer 110b is in contact with the insulating layer 110a and the insulating layer 110c and has a region sandwiched between them. The insulating layer 110a and the insulating layer 110c are preferably made of a material that is difficult for oxygen to permeate. This prevents oxygen contained in the insulating layer 110b from diffusing toward the insulating layer 110a and toward the insulating layer 110c, thereby increasing the amount of oxygen supplied from the insulating layer 110b to the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208, thereby reducing oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 100 and the transistor 200 can have favorable electrical characteristics and high reliability. Furthermore, when oxygen is supplied to the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b, they may be oxidized, resulting in increased electrical resistance. By providing the insulating layer 110a between the conductive layer 112a and the insulating layer 110b and between the conductive layer 212a and the insulating layer 110b and by providing the insulating layer 110c between the conductive layer 112b and the insulating layer 110b and between the conductive layer 212b and the insulating layer 110b, oxygen diffusion into these conductive layers can be suppressed, thereby suppressing an increase in the electrical resistance of these conductive layers. Therefore, the transistor 100 and the transistor 200 can have a large on-state current.

[0111] The insulating layers 110a and 110c, which function as barrier films, can each be made of, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layers 110a and 110c can each be made of, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. In particular, the insulating layers 110a and 110c each preferably contain silicon and nitrogen. The insulating layers 110a and 110c can each be made of, for example, silicon oxide and / or silicon oxynitride. The insulating layers 110a and 110c can each be made of the same material. Alternatively, the insulating layers 110a and 110c can each be made of different materials.

[0112] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0113] The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c each preferably contain a small amount of impurities. Furthermore, the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c each preferably release a small amount of impurities. In particular, it is preferable that the amount of impurities containing hydrogen elements (for example, hydrogen and water) released is small. Furthermore, it is preferable that the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c each have as little impurities containing hydrogen elements as possible. This prevents oxygen deficiency (V) in the semiconductor layer 108 and the semiconductor layer 208. Ｏ ) and V Ｏ The increase in H can be suppressed.

[0114] By using an oxide or an oxynitride for the insulating layer 110c, oxygen can be supplied to the insulating layer 110b or the insulating film that will become the insulating layer 110b when the insulating layer 110c or the insulating film that will become the insulating layer 110c is formed. This allows the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 and the semiconductor layer 208 to be increased, and oxygen deficiency (V Ｏ ) and V Ｏ H can be efficiently reduced. For example, an aluminum oxide film can be formed by sputtering using an aluminum target in an oxygen-containing atmosphere as the insulating layer 110c or the insulating film that will become the insulating layer 110c. This allows oxygen to be supplied to the insulating layer 110b or the insulating film that will become the insulating layer 110b while the aluminum oxide film is being formed. In particular, the insulating layer 110c preferably contains one or both of aluminum and hafnium, and oxygen. The insulating layer 110c can be preferably made of one or more of aluminum oxide, hafnium oxide, and hafnium aluminate.

[0115] The insulating layer 110b can also function as a barrier film. The above-described materials can be used as the barrier film. For example, silicon nitride can be suitably used as the insulating layer 110b. The insulating layer 110 can have a single-layer structure of a silicon nitride film. When the insulating layer 110b functions as a barrier film, impurities can be prevented from diffusing into the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208, thereby enabling the transistors 100 and 200 to exhibit favorable electrical characteristics and high reliability. Note that depending on the material used for the insulating layer 110b, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 and the semiconductor layer 208 may be reduced. In this case, it is preferable that at least the portion of the insulating layer 106 in contact with the channel formation region of the semiconductor layer 108 and the portion in contact with the channel formation region of the semiconductor layer 208 contain oxygen. Furthermore, it is more preferable to use a material that releases oxygen when heat is applied to these portions. The insulating layer 106 releases oxygen due to heat applied during the manufacturing process of the semiconductor device 10, and oxygen can be supplied to the semiconductor layer 108 and the semiconductor layer 208. By supplying oxygen from the insulating layer 106 to the semiconductor layer 108 and the semiconductor layer 208, particularly to the channel formation region, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. For example, one or more of silicon oxide, silicon oxynitride, and aluminum oxide can be suitably used for a portion of the insulating layer 106 in contact with the semiconductor layer 108 and a portion of the insulating layer 106 in contact with the semiconductor layer 208.

[0116] Note that although the insulating layer 110 has a three-layer structure here, one embodiment of the present invention is not limited to this. The insulating layer 110 preferably includes at least the insulating layer 110b. For example, the insulating layer 110a may not be provided. The insulating layer 110 may have a two-layer, four or more-layer structure, or a single-layer structure.

[0117] The insulating layer 107 can be formed using the same material as the insulating layer 110. The insulating layer 107 can be formed using the same material as the insulating layer 110a and the insulating layer 110c.

[0118] The insulating layer 107 can function as a barrier film, similar to the insulating layers 110a and 110c. For example, silicon nitride or silicon nitride oxide can be suitably used for the insulating layer 107. Note that the insulating layer 107, the insulating layer 110a, and the insulating layer 110c can be made of the same material, or different materials can be used for them.

[0119] The insulating layer 107 can be made of a material that releases impurities that increase the conductivity (which can also be said to reduce the electrical resistance) of the semiconductor layer 208. When a metal oxide is used for the semiconductor layer 208, the elements contained in the impurities (hereinafter also referred to as impurity elements) can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. The impurity element is preferably one or more of hydrogen, boron, phosphorus, aluminum, magnesium, and silicon, and particularly preferably hydrogen. Note that in this specification and the like, hydrogen may be used as an example of an impurity element.

[0120] When a metal oxide is used for the semiconductor layer 208, the impurities released from the insulating layer 107 preferably contain hydrogen. The hydrogen reacts with oxygen that is bonded to a metal atom of the metal oxide to form water, which causes an oxygen deficiency (V Ｏ ) is formed. Furthermore, oxygen vacancies (V Ｏ ) with hydrogen (V Ｏ H) functions as a donor and generates electrons as carriers. This increases the carrier concentration in a region of the semiconductor layer 208 that is in contact with the insulating layer 107, thereby reducing the electrical resistance of the region.

[0121] The insulating layer 107 contains an impurity element. The insulating layer 107 preferably contains nitrogen and is preferably formed using one or more of the above-described nitrides and nitride oxides. That is, the insulating layer 107 preferably contains nitrogen and an impurity element. When hydrogen is used as the impurity element, the insulating layer 107 preferably contains silicon, nitrogen, and hydrogen. For example, the insulating layer 107 can be preferably formed using silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen.

[0122] Impurities released from the insulating layer 107 diffuse into the semiconductor layer 208. The region of the semiconductor layer 208 in contact with the insulating layer 107 contains impurities, so that the region can be a low-resistance region. The semiconductor layer 208 can have a low-resistance region between the region in contact with the conductive layer 212a (one of the source region and drain region of the transistor 200) and the channel formation region. The low-resistance region can function as a buffer region for reducing the drain electric field. Note that these low-resistance regions may function as source or drain regions.

[0123] By providing a low-resistance region between the drain and the channel formation region, a high electric field is less likely to be generated near the drain, which can suppress the generation of hot carriers and the deterioration of the transistor. For example, in the transistor 200, when the conductive layer 212 a functions as a drain electrode and the conductive layer 212 b functions as a source electrode, by forming a region of the semiconductor layer 208 in contact with the insulating layer 107 as a low-resistance region, a high electric field is less likely to be generated near the drain, which can suppress the generation of hot carriers and the deterioration of the transistor.

[0124] When a region of the semiconductor layer 208 in contact with the insulating layer 107 functions as a source region or a drain region of the transistor 200, the distance from the source region to the gate electrode or the distance from the drain region to the gate electrode of the semiconductor layer 208 can be made more uniform. This makes it possible to make the electric field of the gate electrode applied to the channel formation region of the transistor 200 more uniform.

[0125] It is more preferable to use a material that releases impurities that reduce the electrical resistance of the conductive layers 112a and 212a for the insulating layer 107. The impurities released from the insulating layer 107 diffuse into the conductive layers 112a and 212a. The conductive layers 112a and 212a each contain impurities, thereby reducing the electrical resistance of these conductive layers. For example, when a metal oxide is used for the conductive layers 112a and 212a, the electrical resistance of the conductive layers 112a and 212a can be reduced by using a material that releases impurities (e.g., hydrogen) for the insulating layer 107. Furthermore, the conductive layers 112a and 212a can function as wirings, thereby providing a semiconductor device with low wiring resistance. Note that the impurities that reduce the electrical resistance of the conductive layers 112a and 212a may be the same as or different from the impurities that reduce the electrical resistance of the semiconductor layer 208.

[0126] Impurities released from the insulating layer 107 may diffuse into the semiconductor layer 108 through the conductive layer 112a and into the semiconductor layer 208 through the conductive layer 212a. When the region of the semiconductor layer 108 in contact with the conductive layer 112a contains impurities, the carrier concentration of the region is increased, which can reduce the electrical resistance of one of the source region and the drain region of the transistor 100. Similarly, the carrier concentration of the region of the semiconductor layer 208 in contact with the conductive layer 212a is increased, which can reduce the electrical resistance of one of the source region and the drain region of the transistor 200.

[0127] The materials that can be used for the conductive layer 112a and the conductive layer 212a are as described above. Note that the conductive layer 112a and the conductive layer 212a preferably easily transmit impurities. The conductive layer 112a and the conductive layer 212a preferably do not easily adsorb impurities.

[0128] The insulating layer 107 can be formed using a gas containing an impurity. When hydrogen is used as the impurity element, the insulating layer 107 can be formed using a gas containing a hydrogen element. For example, silane (SiH ４ ), disilane (Si ２ H ６ ), trisilane (Si ３ H８ ), TEOS (Tetraethoxysilane, Si(OC ２ H ５ ) ４ ), hydrogen (H ２ ), and ammonia (NH ３ When a silicon nitride film is formed as the insulating layer 107 by using the PECVD method, silane (SiH ４ ), nitrogen (N ２ ) and ammonia (NH ３ ) can be used. At this time, the amount of hydrogen released from the insulating layer 107 can be adjusted by changing the ratio of the flow rate of ammonia gas to the total flow rate of the film formation gas (hereinafter also referred to as the ammonia flow rate ratio). For example, by increasing the ammonia flow rate ratio, the amount of hydrogen contained in the insulating layer 107 can be increased, and the amount of hydrogen released by heat applied to the insulating layer 107 can be increased.

[0129] Here, impurities released from the insulating layer 107 may diffuse into the channel formation region of the semiconductor layer 208 through a region of the semiconductor layer 208 that is in contact with the insulating layer 107. When the impurity element is hydrogen, the hydrogen released from the insulating layer 107 may diffuse into the channel formation region of the semiconductor layer 208. However, oxygen is supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 208, causing oxygen vacancies (V Ｏ ) is reduced, so even if hydrogen diffuses, V Ｏ In addition, the increase of H in the channel formation region is suppressed. Ｏ ) and V Ｏ Even if H is generated, oxygen deficiency (V Ｏ ) and V ＯH is reduced. Therefore, at least a region of the semiconductor layer 208 in contact with the insulating layer 110b functions as a channel formation region, and the transistor 200 exhibits favorable electrical characteristics and is highly reliable. Note that the diffusion coefficient of oxygen in the semiconductor layer 208 is smaller than that of hydrogen, and therefore the electrical resistance of the conductive layer 212a and the conductive layer 212b is unlikely to increase due to oxygen released from the insulating layer 110b. Therefore, the electrical resistance of these regions can be kept low. The same applies to the semiconductor layer 108, the conductive layer 112a, and the conductive layer 112b.

[0130] The insulating layer 107 has an impurity element concentration of 1×10 ２１ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Below 1 × 10, preferably ２１ atoms / cm ３ 5x10 or more ２２ atoms / cm ３ Less than or equal to 5×10, more preferably ２１ atoms / cm ３ 5x10 or more ２２ atoms / cm ３ For example, when the impurity contains a hydrogen element, the insulating layer 107 preferably includes a portion in which the hydrogen concentration is in the above range.

[0131] Note that the concentration of the impurity element may vary in the thickness direction of the layer (also referred to as having a concentration gradient). When analyzing the concentration of the impurity element in the thickness direction of the layer, it is preferable that the maximum value of the concentration in the layer be in the above-mentioned range.

[0132] If the concentration of the impurity element in the insulating layer 107 is high, the amount of impurities diffusing from the insulating layer 107 to the channel formation region may become too large. By setting the concentration of the impurity element in the insulating layer 107 within the above range, oxygen vacancies (V Ｏ ) and V Ｏ The increase in H can be suppressed.

[0133] A region of the semiconductor layer 208 in contact with the insulating layer 107 contains an element (impurity element) contained in the impurities released from the insulating layer 107. The region of the semiconductor layer 208 in contact with the insulating layer 107 preferably has a portion having a higher concentration of the impurity element than the channel formation region.

[0134] It is preferable to provide the insulating layer 110a between the insulating layer 107 and the insulating layer 110b. By providing the insulating layer 110a functioning as a barrier film, impurities released from the insulating layer 107 can be prevented from diffusing into the channel formation region of the semiconductor layer 208 through the insulating layers 110a and 110b. Similarly, impurities released from the insulating layer 107 can be prevented from diffusing into the channel formation region of the semiconductor layer 108 through the conductive layer 112a, the insulating layer 110a, and the insulating layer 110b. This allows the transistor 100 and the transistor 200 to have favorable electrical characteristics and high reliability.

[0135] The insulating layer 107 preferably has a region where the concentration of impurity elements is higher than that of the insulating layer 110a. For example, the insulating layer 107 preferably has a region where the concentration of hydrogen is higher than that of the insulating layer 110a.

[0136] The amount of released hydrogen can be adjusted by differentiating the deposition conditions for the insulating layer 107 and the insulating layer 110a. Specifically, it is preferable to make the deposition conditions for the insulating layer 107 and the insulating layer 110a different from one another in one or more of the deposition power (deposition power density), deposition pressure, deposition gas type, deposition gas flow rate ratio, deposition temperature, and the distance between the substrate and the electrode. For example, by making the deposition power density for the insulating layer 107 lower than the deposition power density for the insulating layer 110a, the hydrogen content in the insulating layer 107 can be made higher than the hydrogen content in the insulating layer 110a. This can increase the amount of hydrogen released from the insulating layer 107 due to heat applied to the insulating layer 107.

[0137] The hydrogen content in the deposition gas used to form the insulating layer 107 is preferably higher than the hydrogen content in the deposition gas used to form the insulating layer 110a. Specifically, when silicon nitride films or silicon nitride oxide films are formed by PECVD as the insulating layer 107 and the insulating layer 110a, the ammonia flow ratio of the deposition gas used to form the insulating layer 107 is preferably higher than the ammonia flow ratio of the deposition gas used to form the insulating layer 110a. By forming the insulating layer 107 under conditions with a high ammonia flow ratio, the hydrogen content in the insulating layer 107 can be increased. Furthermore, the amount of hydrogen released from the insulating layer 107 due to heat applied to the insulating layer 107 can be increased. For example, the insulating layer 107 can be formed using ammonia gas, and the insulating layer 110a can be formed without using ammonia gas (the flow rate of ammonia gas can be said to be zero). In this case, the ammonia flow ratio of the deposition gas used to form insulating layer 110a can be said to be zero, and the ammonia flow ratio of the deposition gas used to form insulating layer 107 can be said to be higher than the ammonia flow ratio of the deposition gas used to form insulating layer 110a.

[0138] The film density of the insulating layer 110a is preferably higher than that of the insulating layer 107. This can prevent hydrogen contained in the insulating layer 107 from diffusing into the channel formation region of the semiconductor layer 208 through the insulating layers 110a and 110b. The film density can be evaluated by, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image. Therefore, in a transmission electron (TE) image, the insulating layer 110a may appear as a denser (darker) image than the insulating layer 107. Even if the same material is used for the insulating layer 107 and the insulating layer 110a, the film densities are different, and therefore the boundary between them may be observed as a difference in contrast in a cross-sectional TEM image.

[0139] The concentrations of impurity elements in the semiconductor layer 108, the semiconductor layer 208, the insulating layer 107, and the insulating layer 110 can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectrometry (XPS), or electron spectrometry for chemical analysis (ESCA). When XPS analysis is used, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side of the sample with XPS analysis. Note that in a low concentration region, quantification may be difficult or the concentration may be below the detection limit.

[0140] 1B and other examples show that in the transistor 100, the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the openings 141 and 143, and in the transistor 200, the semiconductor layer 208, the insulating layer 106, and the conductive layer 204 cover the openings 241 and 243, but one embodiment of the present invention is not limited to this. In the transistor 100, a step may be formed between the insulating layer 110 and the conductive layer 112b and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step. Similarly, in the transistor 200, a step may be formed between the insulating layer 107, the insulating layer 110, the conductive layer 212b, and the conductive layer 212a, and the semiconductor layer 208, the insulating layer 106, and the conductive layer 204 are provided along the step.

[0141] [Semiconductor Layer 108, Semiconductor Layer 208] Metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 will be specifically described. Examples of metal oxides include indium oxide (also referred to as indium oxide), gallium oxide (also referred to as gallium oxide), and zinc oxide (also referred to as zinc oxide). The metal oxide preferably contains at least indium or zinc. The metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0142] The semiconductor layer 108 and the semiconductor layer 208 may be made of, for example, indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium tungsten oxide (In—W oxide, also referred to as IWO), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al— Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Alternatively, examples of usable materials include indium tin oxide containing silicon (ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0143] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0144] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0145] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When a plurality of elements are contained as the element M, the sum of the ratios of the number of atoms of the element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of the element M.

[0146] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0147] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, resulting in a normally-off transistor. Furthermore, the transistor can have a small off-state current. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, resulting in improved reliability.

[0148] The electrical characteristics and reliability of the transistor 100 and the transistor 200 vary depending on the composition of the metal oxide used in the semiconductor layer 108 and the semiconductor layer 208. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0149] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M Examples of suitable compositions include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0150] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0151] When the element M contains a plurality of elements, the atomic ratio of the element M can be the sum of the atomic ratios of these elements.

[0152] By using a material with a high indium content for the semiconductor layer 108 and the semiconductor layer 208, the on-state current or the field-effect mobility of the transistor 100 and the transistor 200 can be increased. Furthermore, by containing the element M, oxygen vacancies (V Ｏ ) can be suppressed. The content of element M in the metal oxide contained in the semiconductor layer 108 and the semiconductor layer 208 is preferably 0.1% to 25% inclusive, more preferably 0.1% to 20% inclusive, even more preferably 0.1% to 10% inclusive, even more preferably 0.1% to 8% inclusive, even more preferably 0.1% to 6% inclusive, and even more preferably 0.1% to 4% inclusive. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide of In:M:Zn=40:1:10 or a metal oxide thereof in the same range. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides of In:Sn:Zn=40:1:10 or a metal oxide thereof in the same range can be preferably used. Alternatively, metal oxides of In:Al:Zn=40:1:10 or a metal oxide thereof in the same range can be preferably used.

[0153] Here, when a polycrystalline metal oxide is used for the semiconductor layers 108 and 208, crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Furthermore, when a polycrystalline metal oxide is used for the semiconductor layers 108 and 208, the unevenness of the surfaces of the semiconductor layers 108 and 208 may increase. This may increase the step on the surface where a layer (e.g., the insulating layer 106) formed on the semiconductor layers 108 and 208 is to be formed, which may cause defects such as discontinuities or voids in the layer. When a metal oxide having a composition that easily results in a polycrystalline structure is used for the semiconductor layers 108 and 208, it is preferable to include an element that inhibits crystallization. This prevents the semiconductor layers 108 and 208 from becoming polycrystalline, resulting in a transistor with a large on-state current. Furthermore, the coverage of a layer (e.g., the insulating layer 106) formed on the semiconductor layers 108 and 208 can be improved, which may prevent defects such as discontinuities or voids in the layer.

[0154] For example, compared with indium tin oxide (ITO), indium tin oxide containing silicon (ITSO) is less likely to form a polycrystalline structure, and therefore can be suitably used for the semiconductor layer 108 and the semiconductor layer 208. When ITSO is used, the silicon content is preferably 1% to 20%, more preferably 3% to 20%, even more preferably 3% to 15%, and even more preferably 5% to 15%. As the atomic ratio of metal elements, for example, In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof can be suitably used. When indium tin oxide containing silicon (ITSO) is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable that the ITSO have crystallinity. Note that the semiconductor layer 108 may have an amorphous region or may be amorphous.

[0155] A metal oxide that does not contain element M can be applied to the semiconductor layer 108 and the semiconductor layer 208. When the metal oxide is an In—Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions close to these can be mentioned. Furthermore, the atomic ratio of In is more preferably equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0156] The compositions of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis can be performed by combining a plurality of these techniques. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit.

[0157] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). Thermal ALD or PEALD can be used as the ALD. When forming a metal oxide by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may be reduced to about 50% of that of the sputtering target. Alternatively, the PECVD method can be used to form the metal oxide.

[0158] It is preferable to use a crystalline metal oxide for the semiconductor layer 108 and the semiconductor layer 208. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide, the density of defect states in the semiconductor layer 108 and the semiconductor layer 208 can be reduced, and a highly reliable semiconductor device can be realized.

[0159] The semiconductor layer 108 and the semiconductor layer 208 are preferably formed using a CAAC-OS or an nc-OS.

[0160] The CAAC-OS has multiple layered crystals. The c-axes of the crystals are oriented in the normal direction to the surface where the semiconductor layer 108 and the semiconductor layer 208 are preferably layered crystals parallel or approximately parallel to the surface where the semiconductor layer 108 is formed. For example, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the top surface of the conductive layer 112a in a region in contact with the top surface of the conductive layer 112a. In particular, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110, which is the surface where the semiconductor layer 108 is formed, in the opening 141. With this structure, the layered crystals of the semiconductor layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, thereby enabling the transistor to have a large on-state current. Similarly, the layered crystals of the semiconductor layer 208 are formed parallel or approximately parallel to the channel length direction of the transistor 200, thereby enabling the transistor to have a large on-state current.

[0161] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced, while by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0162] The higher the substrate temperature during metal oxide formation, the higher the crystallinity of the resulting metal oxide. The substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. Furthermore, the higher the ratio of the flow rate of oxygen gas to the total flow rate of film formation gas (hereinafter also referred to as oxygen flow rate ratio) or the higher the oxygen partial pressure in the processing chamber, the higher the crystallinity of the resulting metal oxide.

[0163] The crystallinity of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed by, for example, X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis can be performed by combining a plurality of these techniques.

[0164] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, impurities such as water and hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the Ｏ By using a metal oxide in which impurities such as H are sufficiently reduced in a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0165] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the carrier concentration of the channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ It is more preferable that the carrier concentration in the channel formation region is less than 1×10. −９ cm −３ It can be said that:

[0166] As described above, the region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source and drain regions of the transistor 100, and the region of the semiconductor layer 208 in contact with the conductive layer 112b functions as the other of the source and drain electrodes. The region of the semiconductor layer 208 in contact with the conductive layer 212a functions as one of the source and drain regions of the transistor 200, and the region of the semiconductor layer 208 in contact with the conductive layer 212b functions as the other of the source and drain regions. The source and drain regions of the semiconductor layer 108 and the semiconductor layer 208 have lower electrical resistance than the channel formation region. The source and drain regions can also be said to have a higher carrier concentration and a higher oxygen defect density than the channel formation region.

[0167] At least one of the region of the semiconductor layer 108 in contact with the insulating layer 110a and the region of the semiconductor layer 108 in contact with the insulating layer 110c can be a low-resistance region. By using a material that releases impurities (e.g., water and hydrogen) in the insulating layer 110a, the region of the semiconductor layer 108 in contact with the insulating layer 110a can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between one of the source region and the drain region and the channel formation region. Similarly, by using a material that releases impurities in the insulating layer 110c, the region of the semiconductor layer 108 in contact with the insulating layer 110c can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the other of the source region and the drain region and the channel formation region. The low-resistance region can function as a buffer region for reducing the drain electric field. Note that these low-resistance regions can also function as source or drain regions. The same applies to the semiconductor layer 208.

[0168] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0169] The semiconductor layer 108 and the semiconductor layer 208 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0170] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0171] The semiconductor layer 108 and the semiconductor layer 208 can each have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 can be the same or approximately the same. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 are the same or approximately the same, the boundary (interface) between these metal oxide layers may not be clearly identified.

[0172] When the semiconductor layer 108 and the semiconductor layer 208 each have a two-layer structure of a first metal oxide layer and a second metal oxide layer on the first metal oxide layer, the surface on which the second metal oxide layer is formed is the surface of the first metal oxide layer, and therefore the crystallinity of the second metal oxide layer may be increased. Furthermore, by performing heat treatment after the second metal oxide layer is formed, the crystallinity of the first metal oxide layer can be increased. This heat treatment can also be called a crystallization treatment.

[0173] A first metal oxide layer is formed, and then a second metal oxide layer having higher crystallinity than the first layer is formed. For example, ALD can be suitably used to form the first metal oxide layer, and sputtering can be suitably used to form the second metal oxide layer. By performing heat treatment after the formation of the second metal oxide layer, the crystallinity of the first metal oxide layer and the second metal oxide layer can be further increased. In this case, the crystals contained in the second metal oxide layer grow continuously toward the first metal oxide layer, and the boundary between the first metal oxide layer and the second metal oxide layer may not be clearly identified. It is particularly preferable that the second metal oxide layer has a CAAC structure. This allows the crystals having the CAAC structure of the second metal oxide layer to serve as nuclei or seeds to increase the crystallinity of the first metal oxide layer.

[0174] A three-layer structure having a third metal oxide layer on the second metal oxide layer can be formed. For example, the first metal oxide layer and the third metal oxide layer can be formed by an ALD method, and the second metal oxide layer can be formed by a sputtering method. Heat treatment after the formation of the third metal oxide layer can increase the crystallinity of the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer. In this case, crystals contained in the second metal oxide layer grow continuously toward the first metal oxide layer and the third metal oxide layer, and the boundary between the first metal oxide layer and the second metal oxide layer and the boundary between the second metal oxide layer and the third metal oxide layer may not be clearly identified. When the second metal oxide layer has a CAAC structure, the crystals having the CAAC structure of the second metal oxide layer can be used as nuclei or seeds to increase the crystallinity of the first metal oxide layer and the third metal oxide layer.

[0175] By stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity, continuous crystal growth occurs between them in the thickness direction, thereby increasing the crystallinity throughout the metal oxide layer. Alternatively, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity and then performing heat treatment, continuous crystal growth occurs between them in the thickness direction, thereby increasing the crystallinity throughout the metal oxide layer. This allows for the realization of a highly reliable transistor. The thickness direction refers to a direction perpendicular or approximately perpendicular to the surface on which the metal oxide layer is formed. A metal oxide layer with such increased crystallinity can be called an axial growth CAAC (AG CAAC). In addition to the crystal growth occurring in the thickness direction, crystal growth may also occur in a direction parallel or approximately parallel to the surface on which the metal oxide layer is formed.

[0176] The temperature of the heat treatment can be 100°C or higher and lower than the strain point of the substrate. The temperature of the heat treatment is preferably 100°C or higher and 800°C or lower, more preferably 250°C or higher and 650°C or lower, and even more preferably 350°C or higher and 550°C or lower. The heat treatment time is, for example, preferably 1 minute to 1 hour, more preferably 10 minutes to 30 minutes, at a temperature of 350°C to 550°C or lower. The heating device used for the heat treatment is not particularly limited, and a device that heats the workpiece by heat conduction or heat radiation from a heating element (e.g., a resistance heating element) can be used. For the heat treatment, for example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats a workpiece by radiating light (electromagnetic waves) emitted from a lamp (e.g., a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, and a high-pressure mercury lamp). The GRTA apparatus is an apparatus that heats a workpiece by using a high-temperature gas.

[0177] [Insulating Layer 110] As described above, the insulating layer 110 preferably has a stacked-layer structure. The insulating layer 110b has a function of supplying oxygen to the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208. The insulating layer 110a and the insulating layer 110c function as barrier films.

[0178] If the thickness T110a of the insulating layer 110a and the thickness T110c of the insulating layer 110c are small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112a and the conductive layer 212a through the insulating layer 110a, and to the conductive layer 112b and the conductive layer 212b through the insulating layer 110c. This may reduce the amount of oxygen supplied to the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208, and may increase the electrical resistance of the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b. On the other hand, if the thickness T110a and the thickness T110c are large, the amount of impurities released from the insulating layer 110a and the insulating layer 110c may increase, resulting in an increase in the amount of impurities diffusing into the channel formation region. 3B and 3C, the thickness T110a can be the shortest distance between the surface on which the insulating layer 110a is to be formed (here, the upper surface of the conductive layer 112a or the upper surface of the insulating layer 107) and the upper surface of the insulating layer 110a in a cross-sectional view. The thickness T110c can be the shortest distance between the surface on which the insulating layer 110c is to be formed (here, the upper surface of the insulating layer 110b) and the upper surface of the insulating layer 110c in a cross-sectional view.

[0179] The thickness T110c is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, even more preferably 3 nm or more and 50 nm or less, even more preferably 3 nm or more and 30 nm or less, even more preferably 3 nm or more and 20 nm or less, even more preferably 3 nm or more and 10 nm or less, and even more preferably 5 nm or more and 10 nm or less.

[0180] The thickness T110a can be greater than the thickness T110c. When the region of the semiconductor layer 108 in contact with the insulating layer 110a functions as the source region or drain region of the transistor 100, the distance from the source region or drain region to the gate electrode can be made more uniform by increasing the thickness T110a. Similarly, when the region of the semiconductor layer 208 in contact with the insulating layer 110a functions as the source region or drain region of the transistor 200, the distance from the source region or drain region to the gate electrode can be made more uniform by increasing the thickness T110a. This makes it possible to make the electric field of the gate electrode applied to the channel formation region more uniform. The thickness T110a of the insulating layer 110a is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, even more preferably 10 nm or more and 300 nm or less, even more preferably 20 nm or more and 300 nm or less, even more preferably 50 nm or more and 300 nm or less, even more preferably 100 nm or more and 300 nm or less, even more preferably 100 nm or more and 250 nm or less, even more preferably 150 nm or more and 250 nm or less.

[0181] By setting the thickness T110a and the thickness T110c within the above-mentioned ranges, the amount of oxygen supplied to the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208 can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. In addition, it is possible to prevent the electrical resistance of the conductive layers 112a, 112b, 212a, and 212b from increasing due to oxygen contained in the insulating layer 110b. Note that the thicknesses T110a and T110c are not limited to the above-described ranges.

[0182] Note that impurities released from the insulating layer 110a may diffuse into the channel formation region of the semiconductor layer 108 through the insulating layer 110b or through a region of the semiconductor layer 108 in contact with the insulating layer 110a. Similarly, impurities released from the insulating layer 110c may diffuse into the channel formation region of the semiconductor layer 108 through the insulating layer 110b or through a region of the semiconductor layer 108 in contact with the insulating layer 110c. When the impurity is hydrogen, hydrogen released from the insulating layer 110a or the insulating layer 110c may diffuse into the channel formation region of the semiconductor layer 108. However, oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, and a transistor having both a small cutoff current and a large on-state current can be obtained. The same applies to the semiconductor layer 208. Therefore, a semiconductor device having both low power consumption and high performance can be obtained.

[0183] However, if the amount of impurities released from the insulating layer 110a and the insulating layer 110c becomes too large, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ The amount of impurities released from the insulating layer 110a and the insulating layer 110c may be greater than the amount of H. Even when a material that releases impurities is used for the insulating layer 110a and the insulating layer 110c, it is more preferable that the amount of impurities released from these layers be small.

[0184] One or more of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can have a stacked structure.

[0185] When the insulating layer 110c has a stacked structure, the layers constituting the insulating layer 110c can be made of the materials listed for the insulating layer 110c. An oxide or an oxynitride can be preferably used for the layer provided on the insulating layer 110b side. More specifically, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly preferably used for the layer provided on the insulating layer 110b side. By using an oxide or an oxynitride for the layer provided on the insulating layer 110b side, oxygen can be supplied to the insulating layer 110b (or the insulating film that will become the insulating layer 110b) during the formation of the layer (or the film that will become the layer), which is preferable. The insulating layer 110c can have, for example, a stacked structure of a first film containing an oxide or oxynitride and a second film containing a nitride or nitride oxide on the first film. More specifically, the insulating layer 110c can have, for example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0186] [Opening 141, Opening 143, Opening 241, Opening 243] The top surface shapes of openings 141, 143, 241, and 243 are not limited and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or other polygonal shape, or a shape with rounded corners of these polygons. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 1A and other figures, the top surface shapes of openings 141, 143, 241, and 243 are preferably circular. By making the top surface shapes of the openings circular, the processing accuracy when forming the openings can be improved, allowing for the formation of openings of finer sizes. When the top surface shapes of the openings 141 and 143 are circular, the openings 141 and 143 may or may not be concentric. The same applies to the openings 241 and 243. In this specification and the like, a circle is not limited to a perfect circle.

[0187] The channel lengths and channel widths of the transistors 100 and 200 will be described with reference to FIGS. 3A to 3C. FIG. 3A is a top view of the transistors 100 and 200 shown in FIG. 1A. FIG. 3B is a cross-sectional view of the transistor 100 shown in FIG. 1B, and FIG. 3C is a cross-sectional view of the transistor 200.

[0188] In FIG. 3B , the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. The channel length L100 of the transistor 100 corresponds to the length of the side surface of the insulating layer 110b on the opening 141 side in a cross-sectional view. In other words, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ100 between the side surface of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the top surface of the insulating layer 110a). In FIG. 3C , the channel length L200 of the transistor 200 is indicated by a dashed double-headed arrow. The channel length L200 of the transistor 200 corresponds to the length of the side surface of the insulating layer 110b on the opening 241 side in a cross-sectional view. That is, the channel length L200 is determined by the thickness T110b of the insulating layer 110b and the angle θ200 between the side surface of the insulating layer 110b on the opening 241 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, the channel lengths L100 and L200 can be set to values ​​smaller than the minimum exposure dimension of the exposure tool, enabling the realization of a fine-sized transistor. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized with conventional exposure tools used in the mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is also possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure tools used in cutting-edge LSI technology.

[0189] The channel length L100 and the channel length L200 may each be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 may be 100 nm or more and 1 μm or less.

[0190] By shortening the channel lengths L100 and L200, the on-state current of the transistor 100 and the transistor 200 can be increased. By using the transistor 100 and the transistor 200, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0191] The channel length L100 can be controlled by adjusting the thickness T110b and the angle θ100. Similarly, the channel length L200 can be controlled by adjusting the thickness T110b and the angle θ200.

[0192] The thickness T110b may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. The thickness T110b may be appropriately set to obtain the desired channel length L100 and channel length L200. As shown in FIG. 3B , the thickness T110b may be the shortest distance between the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a) and the upper surface of the insulating layer 110b in a cross-sectional view.

[0193] Preferably, the angles θ100 and θ200 are each 90 degrees or less. By reducing the angles θ100 and θ200, the coverage of layers (e.g., the semiconductor layer 108 and the semiconductor layer 208) formed on the insulating layer 110 can be improved. Furthermore, when the angle θ100 is 90 degrees or less, the smaller the angle θ100, the longer the channel length L100 can be, and the larger the angle θ100, the shorter the channel length L100 can be. The same applies to the angle θ200 and the channel length L200.

[0194] 3B and other figures, the angles θ100 and θ200 are each shown as being less than 90 degrees, but this is not a limitation of one embodiment of the present invention. The angles θ100 and θ200 can each be set to 90 degrees or approximately 90 degrees. This allows the channel lengths L100 and L200 to be shortened.

[0195] The angles θ100 and θ200 can each be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more, and can be 90 degrees or less, 85 degrees or less, or 80 degrees or less. The angles θ100 and θ200 can also be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less. The angles θ100 and θ200 can be appropriately set so as to obtain the desired channel lengths L100 and L200, respectively.

[0196] By making the angle θ200 the same as or approximately the same as the angle θ100, the channel length L200 becomes the same as or approximately the same as the channel length L100. For example, by forming the opening 141 and the opening 241 in the same process, the angles θ100 and θ200 can be made the same as or approximately the same. Alternatively, the angles θ100 and θ200 can be made different from each other. For example, by forming the opening 141 and the opening 241 in different processes and making the angles θ100 and θ200 different from each other, the channel lengths L100 and L200 can be made different from each other. For example, when the angle θ200 is 90 degrees or less, by making the angle θ200 smaller, the channel length L200 becomes longer, and the saturation of the transistor 200 can be improved.

[0197] In this specification and the like, a small change in current in the saturation region in the Id-Vd characteristics of a transistor may be expressed as "high saturation."

[0198] When the angles θ100 and θ200 are large, it is preferable to use a film formation method with higher coverage for forming the layers provided in the openings 141 and 143 and the openings 241 and 243. For example, when the angles θ100 and θ200 are 85 degrees or greater and 90 degrees or less, the ALD method can be suitably used for forming the insulating layer 106, the semiconductor layer 108, and the semiconductor layer 208. On the other hand, when the angles θ100 and θ200 are small, a film formation method with higher productivity can be suitably used. For example, when the angles θ100 and θ200 are less than 85 degrees, the PECVD method can be suitably used for forming the insulating layer 106, and sputtering can be suitably used for forming the semiconductor layer 108 and the semiconductor layer 208.

[0199] 1B and the like show a cross-sectional view in which the shape of the side surface of the insulating layer 110 on the opening 141 side and the shape of the side surface of the opening 241 side are linear, but one embodiment of the present invention is not limited to this. In a cross-sectional view, the shape of the side surface of the insulating layer 110 on the opening 141 side and the shape of the side surface of the opening 241 side can be curved. Alternatively, a structure can be used in which the shape of the side surface includes both a linear region and a curved region.

[0200] Here, the conductive layer 112b is preferably not provided inside the opening 141. Specifically, the conductive layer 112b preferably does not have a region in contact with the side surface of the insulating layer 110 on the opening 141 side. If the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 becomes shorter than the length of the side surface of the insulating layer 110b, which may make it difficult to control the channel length L100. Therefore, it is preferable that the top shape of the opening 143 coincides with the top shape of the opening 141, or that the opening 143 encompasses the opening 141 in a top view. The same applies to the conductive layer 212b and the opening 241.

[0201] In Figures 3A and 3B, the width D141 of the opening 141 is indicated by a double-headed, dashed arrow, and in Figures 3A and 3C, the width D241 of the opening 241 is indicated by a double-headed, dashed arrow. Figure 3A shows an example in which the top surface shapes of the openings 141 and 241 are each circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 is the perimeter of the circle. That is, the channel width W100 is π × D141. Similarly, when the top surface shape of the opening 241 is circular, the channel width W200 of the transistor 200 is π × D241. When the top surface shapes of the openings 141 and 241 are circular, the transistors 100 and 200 can be realized with smaller channel widths than those with other shapes.

[0202] The widths D141 and D241 may vary in the depth direction. For example, the widths D141 and D241 may be the average values ​​of the diameters at the highest and lowest points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view, and the diameters at the midpoints between these. Alternatively, the widths D141 and D241 may be any of the diameters at the highest and lowest points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view, or the diameters at the midpoints between these.

[0203] When the openings 141 and 241 are formed using photolithography, the widths D141 and D241 are equal to or greater than the minimum exposure dimension of the exposure device. The widths D141 and D241 may be, for example, equal to or greater than 20 nm, equal to or greater than 50 nm, equal to or greater than 100 nm, equal to or greater than 200 nm, equal to or greater than 300 nm, equal to or greater than 400 nm, or equal to or greater than 500 nm, and may be less than 5 μm, equal to or less than 4.5 μm, equal to or less than 4 μm, equal to or less than 3.5 μm, equal to or less than 3 μm, equal to or less than 2.5 μm, equal to or less than 2 μm, equal to or less than 1.5 μm, or equal to or less than 1 μm.

[0204] 3A and other figures show a configuration in which the width D141 and the width D241 are the same, but one embodiment of the present invention is not limited to this. The width D141 and the width D241 may be different. By making the width D141 and the width D241 different, the channel width W100 and the channel width W200 can be made different.

[0205] Note that although the example described here is a structure in which a region of the semiconductor layer 108 in contact with the insulating layer 110b serves as the channel formation region of the transistor 100 and a region of the semiconductor layer 208 in contact with the insulating layer 110b serves as the channel formation region of the transistor 200, one embodiment of the present invention is not limited to this. A region of the semiconductor layer 108 in contact with the insulating layer 110a may also serve as the channel formation region. A region of the semiconductor layer 108 in contact with the insulating layer 110c may also serve as the channel formation region. The same applies to the semiconductor layer 208.

[0206] [Conductive Layer 112a, Conductive Layer 112b, Conductive Layer 104, Conductive Layer 212a, Conductive Layer 212b, and Conductive Layer 204] The conductive layers 112a, 112b, 104, 212a, 212b, and 204 can each have a single-layer structure or a stacked structure of two or more layers. Materials that can be used for these layers include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the aforementioned metals. The conductive layers 112a, 112b, 104, 212a, 212b, and 204 can each be preferably made of a conductive material with low electrical resistivity, such as one or more of copper, silver, gold, and aluminum. Copper or aluminum is particularly preferred due to its excellent mass productivity.

[0207] An oxide conductor can be used for each of the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204. Examples of oxide conductors include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also referred to as ITO containing silicon, or ITSO), zinc oxide to which gallium is added, and In—Ga—Zn oxide. In particular, an oxide conductor containing indium is preferable because of its high conductivity.

[0208] The conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can each have a stacked structure of a conductive film containing the above-described oxide conductor and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0209] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may also be applied to each of the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204. By using a Cu-X alloy film, it can be processed by wet etching, thereby reducing manufacturing costs.

[0210] Note that the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can be formed using the same material, or at least one of them can be formed using a different material.

[0211] The semiconductor layer 108 is formed after the conductive layer 112a and the conductive layer 112b are formed, and the semiconductor layer 208 is formed after the conductive layer 212a and the conductive layer 212b are formed. When the semiconductor layer 108 and the semiconductor layer 208 contain oxygen or are formed in an atmosphere containing oxygen, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a and the semiconductor layer 108, between the conductive layer 112b and the semiconductor layer 108, between the conductive layer 212a and the semiconductor layer 208, and between the conductive layer 212b and the semiconductor layer 208, which may prevent electrical conduction therebetween. Therefore, for the conductive layers 112a, 112b, 212a, and 212b, a conductive material that is not easily oxidized, a conductive material that keeps low electrical resistance even when oxidized, or an oxide conductor is preferably used.

[0212] For the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel, respectively. These are preferable because they are conductive materials that are resistant to oxidation or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, or the conductive layer 212b has a stacked structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with the semiconductor layer 108 and the layer in contact with the semiconductor layer 208.

[0213] The conductive layer 112 a, the conductive layer 112 b, the conductive layer 212 a, and the conductive layer 212 b can each be formed using any of the above-described oxide conductors. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide doped with gallium can be used.

[0214] The conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b can each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer 104 and the conductive layer 204 can each be made of the nitride conductors described above.

[0215] [Insulating Layer 106] The insulating layer 106 preferably has one or more inorganic insulating layers. The insulating layer 106 can be made of the same material as that used for the insulating layer 110.

[0216] The insulating layer 106 is provided over the semiconductor layer 108, the semiconductor layer 208, the conductive layer 212b, and the insulating layer 110. When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, any of the above-described oxides and oxynitrides is preferably used for at least a film in contact with the semiconductor layer 108 and the semiconductor layer 208 among films constituting the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be preferably used for the insulating layer 106.

[0217] Note that in a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0218] 1B and the like, the insulating layer 106 has a single-layer structure, but one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers.

[0219] [Insulating Layer 195] The insulating layer 195, which functions as a protective layer for the transistors 100 and 200, is preferably made of a material through which impurities do not easily diffuse. By providing the insulating layer 195, diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen.

[0220] The insulating layer 195 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, an inorganic material such as oxide, oxynitride, nitride oxide, or nitride can be suitably used for the insulating layer 195. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, one or more of acrylic resin and polyimide resin can be used as the organic material. A photosensitive material can be used as the organic material. Two or more of the above insulating films can also be stacked. The insulating layer 195 can have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0221] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is provided can be used as the substrate 102. Alternatively, a substrate on which an insulating film is formed on the surface can be used as the substrate 102. The shapes of the semiconductor substrate and the insulating substrate are not particularly limited and may be circular or rectangular.

[0222] A flexible substrate can be used as the substrate 102, and the transistor 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100 and the like. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0223] The following describes a configuration example of a semiconductor device that is partially different from the configuration example described above. Note that, in the following, descriptions of parts that overlap with the configuration example described above may be omitted. Furthermore, in the drawings shown below, parts that have the same functions as the configuration example described above may be hatched with the same pattern and may not be assigned reference numerals.

[0224] 6A shows a top view of a semiconductor device 10A according to one embodiment of the present invention, FIG. 6B shows a cross-sectional view of the semiconductor device 10A taken along dashed dotted line A1-A2 in FIG. 6A , and FIG. 6C shows cross-sectional views of the semiconductor device 10A taken along dashed dotted line B1-B2 and dashed dotted line B3-B4 in FIG.

[0225] The semiconductor device 10A includes a transistor 100A, a transistor 200, an insulating layer 110, and an insulating layer 107. The transistor 100A is different from the transistor 100 shown in FIG. 1B and the like mainly in that the transistor 100A includes a conductive layer 103, a layer 105, and an insulating layer 116. The above description of the transistor 200 can be referred to.

[0226] FIG. 7A shows an enlarged view of the transistor 100A shown in FIG. 6B . The transistor 100A includes a conductive layer 103 and a layer 105 between an insulating layer 110a and an insulating layer 110b. The conductive layer 103 is provided over the insulating layer 110a, and the layer 105 is provided on the top surface and side surface of the conductive layer 103. The insulating layer 110, the layer 105, and the conductive layer 103 have an opening 141 that reaches the conductive layer 112a. The insulating layer 116 has a region in contact with the side surface of the insulating layer 110 and the side surface of the layer 105 in the opening 141. Because the insulating layer 116 is provided along the side surface of the insulating layer 110 and the side surface of the layer 105 in the opening 141, it can be referred to as a sidewall or a sidewall insulating layer. The side surface of the insulating layer 110 and the side surface of the layer 105 in the opening 141 can also be referred to as the sidewall of the opening 141. It can also be said that the insulating layer 116 is provided along the sidewall of the opening 141. The insulating layer 116 has a region in contact with the top surface of the insulating layer 110a in the opening 141. The semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110a, and the top surface and side surface of the insulating layer 116 in the opening 141. The insulating layer 116 is located between the conductive layer 103 and the layer 105 and the semiconductor layer 108, and the conductive layer 103 and the semiconductor layer 108 are electrically insulated from each other by the insulating layer 116.

[0227] As shown in FIG. 6B and other figures, the upper surface of the insulating layer 116 may be sloped, making it difficult to distinguish between the upper surface and the side surface.

[0228] For example, after forming the openings 141 and 143, or openings that will become the openings 141 and 143, a film that will become the insulating layer 116 is provided so as to cover these openings. Parts of the film are removed to expose the top surface of the insulating layer 110, the top surface of the conductive layer 112a, and the top and side surfaces of the conductive layer 112b, thereby forming the insulating layer 116. For example, an anisotropic etching method can be suitably used to form the insulating layer 116.

[0229] In the transistor 100A, the semiconductor layer 108 has a region that overlaps with the conductive layer 104 with the insulating layer 106 interposed therebetween and with the conductive layer 103 with the insulating layer 116 interposed therebetween. In other words, the semiconductor layer 108 has a region sandwiched between the conductive layer 104 with the insulating layer 106 interposed therebetween and the conductive layer 103 with the insulating layer 116 interposed therebetween.

[0230] In the transistor 100A, the conductive layer 104 functions as a gate electrode (also referred to as a first gate electrode). Part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 103 functions as a back gate electrode (also referred to as a second gate electrode). The insulating layer 116 functions as a back gate insulating layer (also referred to as a second gate insulating layer). Alternatively, in the transistor 100A, the conductive layer 104 can function as a back gate electrode, part of the insulating layer 106 can function as a back gate insulating layer, the conductive layer 103 can function as a gate electrode, and the insulating layer 116 can function as a gate insulating layer. Note that hereinafter, the conductive layer 103 may be described as a back gate electrode.

[0231] By providing a back gate electrode to the transistor 100A, the potential of the back gate electrode side (also referred to as the back channel side) of the semiconductor layer 108 is fixed, thereby improving the saturation of the Id-Vd characteristics. Furthermore, fixing the potential of the back channel side of the semiconductor layer 108 can suppress a shift in the threshold voltage. Therefore, a transistor with a small cutoff current can be obtained, leading to a semiconductor device with low power consumption. For example, by applying the transistor 100A to a transistor that requires high saturation and the transistor 200 to a transistor that requires a large on-state current, a high-performance semiconductor device can be obtained by utilizing the advantages of each transistor.

[0232] For the conductive layer 103, the same materials as those for the conductive layers 112a, 112b, 104, 212a, 212b, and 204 can be used.

[0233] The insulating layer 116 can be made of a material that can be used for the insulating layer 106 and the insulating layer 110. When a metal oxide is used for the semiconductor layer 108, it is preferable to use any of the above-mentioned oxides and oxynitrides for at least a film that is in contact with the semiconductor layer 108 among the films that constitute the insulating layer 116. The insulating layer 116 preferably has a region that is in contact with the insulating layer 110. It is preferable that the insulating layer 116 particularly has a region that is in contact with the insulating layer 110b. Oxygen released from the insulating layer 110b by heat applied during the manufacturing process of the semiconductor device is supplied to the insulating layer 116, and further oxygen can be supplied from the insulating layer 116 to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, particularly to the channel formation region, through the insulating layer 116, oxygen deficiency (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 100A can have favorable electrical characteristics and high reliability.

[0234] When a metal oxide is used for the semiconductor layer 108, the metal oxide film to be the semiconductor layer 108 is preferably formed in an atmosphere containing oxygen. This allows oxygen to be supplied to the insulating layer 116. Then, in a later step, oxygen is supplied from the insulating layer 116 to the semiconductor layer 108, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0235] The layer 105 is located between the conductive layer 103 and the insulating layer 110 and between the conductive layer 103 and the insulating layer 116. The layer 105 has a region in contact with the top surface and side surface of the conductive layer 103. The conductivity of the layer 105 is not particularly limited. The layer 105 preferably functions as a barrier film. When the layer 105 functions as a barrier film, the conductive layer 103 can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which can prevent the electrical resistance from increasing. Furthermore, the amount of oxygen supplied from the insulating layer 110b to the insulating layer 116 can be increased, thereby increasing the amount of oxygen supplied to the channel formation region of the semiconductor layer 108. Therefore, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0236] The materials that can be used as the barrier film are as described above. The layer 105 can be formed using, for example, one or more of an oxide, a nitride, an oxynitride, and a nitride oxide. The layer 105 preferably contains a component contained in the conductive layer 103. When an oxide is used for the layer 105, the layer 105 preferably contains an element contained in the conductive layer 103 and oxygen. When a nitride is used for the layer 105, the layer 105 preferably contains an element contained in the conductive layer 103 and nitrogen. The conductive layer 103 is preferably formed using a material that is easily oxidized or nitrided. For example, aluminum can be suitably used for the conductive layer 103. When aluminum is used for the conductive layer 103, the layer 105 preferably contains aluminum and oxygen. For example, aluminum can be used for the conductive layer 103, and aluminum oxide can be used for the layer 105.

[0237] When an oxide is used for the layer 105, the layer 105 can be formed by oxidizing the conductive layer 103 or a film that will become the conductive layer 103. When a nitride is used for the layer 105, the layer 105 can be formed by nitriding the conductive layer 103 or a film that will become the conductive layer 103. Note that the boundary between the conductive layer 103 and the layer 105 may be unclear, and therefore, in Figure 7A and the like, the boundary is indicated by a dashed line.

[0238] The treatment for oxidizing the conductive layer 103 (hereinafter also referred to as oxidation treatment) or nitriding the conductive layer 103 (hereinafter also referred to as nitriding treatment) can be, for example, plasma treatment. The atmosphere used for the oxidation treatment preferably contains oxygen. For example, the atmosphere may contain oxygen (O ２ ), nitrous oxide (N ２ O), nitrogen dioxide (NO ２ An atmosphere containing one or more of nitrogen (N), carbon monoxide, and carbon dioxide can be suitably used. The atmosphere used in the nitriding treatment preferably contains nitrogen. ２ ) can be suitably used.

[0239] For example, after forming the layer that will become the conductive layer 103 and before forming the film that will become the insulating layer 110b, the conductive layer 103 is subjected to oxidation treatment or nitriding treatment to form an oxide or nitride on the surface of the layer that will become the conductive layer 103. Furthermore, after forming the opening 141 or the opening that will become the opening 141 and before forming the insulating layer 116, the conductive layer 103 is subjected to oxidation treatment or nitriding treatment to form an oxide or nitride on the surface of the conductive layer 103 that faces the opening 141. This allows the layer 105 to be formed on the top surface and side surface of the conductive layer 103.

[0240] 7A , the channel length L100 of the transistor 100A is indicated by a dashed double-headed arrow. The channel length L100 corresponds to the length of a region where the insulating layer 116 and the semiconductor layer 108 are in contact with each other in a cross-sectional view. When the insulating layer 116 is provided on the side surfaces of the conductive layer 103, the layer 105, and the insulating layer 110, the channel length L100 can be controlled by the sum of the thicknesses of the conductive layer 103, the layer 105, and the insulating layer 110, and the angle θ100 between the side surface of the insulating layer 110 on the opening 141 side and the surface on which the insulating layer 110 is to be formed (here, the upper surface of the conductive layer 112a).

[0241] The channel length L100 of the transistor 100A corresponds to the length of the region where the insulating layer 116 and the semiconductor layer 108 contact each other, whereas the channel length of the transistor 200 corresponds to the length of the region where the insulating layer 110b and the semiconductor layer 208 contact each other (see "L200" in FIG. 3C). Therefore, the channel length L100 of the transistor 100A may be longer than the channel length of the transistor 200. This can further improve the saturation of the Id-Vd characteristics of the transistor 100A.

[0242] By providing the insulating layer 116 along the sidewall of the opening 141, the step of the surface on which a layer (e.g., the semiconductor layer 108 and the insulating layer 106) formed on the insulating layer 116 is formed is reduced, and the coverage of the layer can be improved. This can prevent defects such as step discontinuities or voids from occurring in the layer. Furthermore, the improved coverage of the insulating layer 106 can improve the breakdown voltage of the gate insulating layer, resulting in a highly reliable transistor.

[0243] The conductive layer 103 can be electrically connected to the conductive layer 112a. For example, an opening can be formed in a region of the insulating layer 110a that overlaps with the conductive layer 112a, and the conductive layer 103 can be provided to cover the opening, thereby making the conductive layer 103 and the conductive layer 112a in contact with each other. The electrical connection between the conductive layer 112a and the conductive layer 103 allows one of the source electrode and the drain electrode to have the same potential as the back gate electrode. For example, when the conductive layer 112a functions as a source electrode, a shift in the threshold voltage of the transistor 100A can be suppressed. Furthermore, the reliability of the transistor 100A can be improved. Note that the conductive layer 103 can also be formed in contact with the top surface of the conductive layer 112a without providing the insulating layer 110a.

[0244] The conductive layer 103 can be electrically connected to the conductive layer 104. For example, openings are provided in regions of the insulating layers 110b, 110c, and 106 that overlap with the conductive layer 103, and the conductive layer 104 is provided to cover the openings, so that the conductive layer 103 and the conductive layer 104 are in contact with each other. When the conductive layer 104 that functions as a gate electrode is electrically connected to the conductive layer 103 that functions as a back gate electrode, the back gate electrode and the gate electrode can have the same potential, and the on-state current of the transistor 100A can be increased.

[0245] As shown in FIG. 7A and other figures, the insulating layer 110a preferably has a region located between the conductive layer 112a and the insulating layer 116. The insulating layer 116 has a region in contact with the top surface of the insulating layer 110a. It can also be said that the insulating layer 110a has a portion that protrudes beyond the end of the layer 105 on the opening 141 side. By providing the insulating layer 110a, which functions as a barrier film, between the insulating layer 116 and the conductive layer 112a, it is possible to prevent oxygen from being supplied from the insulating layer 116 to the conductive layer 112a. This can prevent the conductive layer 112a from being oxidized and the electrical resistance of the conductive layer 112a from increasing.

[0246] 7A, the thickness of the region of insulating layer 110a that contacts the lower surface of insulating layer 116 may be thinner than the thickness of the region that contacts the lower surface of conductive layer 103. In this case, insulating layer 116 has regions that contact the upper and side surfaces of insulating layer 110a. Note that, as shown in FIG. 7B, the thickness of the region of insulating layer 110a that contacts the lower surface of insulating layer 116 may be the same as or approximately the same as the thickness of the region that contacts the lower surface of conductive layer 103.

[0247] As shown in FIG. 8 , the insulating layer 116 can be in contact with the conductive layer 112a. In this case, the insulating layer 116 preferably includes a barrier film. FIG. 8 illustrates a structure example in which the insulating layer 116 has a stacked structure of an insulating layer 116a and an insulating layer 116b over the insulating layer 116a. The insulating layer 116a in contact with the conductive layer 112a preferably functions as a barrier film. Materials that can be used for the barrier film are as described above. For the insulating layer 116b, the description of the insulating layer 116 can be referred to. For example, aluminum oxide can be preferably used for the insulating layer 116a, and silicon oxynitride can be preferably used for the insulating layer 116b. The insulating layer 116a in contact with the conductive layer 112a functions as a barrier film, which can prevent oxygen released from the insulating layer 110b and the insulating layer 116b from diffusing into the conductive layer 112a through the insulating layer 116a. This can prevent the electrical resistance of the conductive layer 112a from increasing.

[0248] Although the semiconductor device in FIG. 6A and the like includes a transistor having a backgate electrode and a transistor not having a backgate electrode, one embodiment of the present invention is not limited to this.

[0249] 9A to 9C show examples of configurations different from those shown in Fig. 6A to 6C. Fig. 9A is a top view of a semiconductor device 10B. Fig. 9B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in Fig. 9A, and Fig. 9C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0250] 6A to 6C in that the transistor 200A includes a conductive layer 203, a layer 205, and an insulating layer 216. The above description of the transistor 100A can be referred to.

[0251] FIG. 10A shows an enlarged view of the transistor 200A. The transistor 200A includes a conductive layer 203 and a layer 205 between the insulating layer 110a and the insulating layer 110b. The conductive layer 203 is provided on the insulating layer 110a, and the layer 205 is provided on the top and side surfaces of the conductive layer 203. The insulating layer 107, the insulating layer 110, the layer 205, and the conductive layer 203 have an opening 241 that reaches the conductive layer 212a. The insulating layer 216 has a region in contact with the side surface of the insulating layer 110 and the side surface of the layer 205 in the opening 241. Because the insulating layer 216 is provided along the side surface of the insulating layer 110 and the side surface of the layer 205 in the opening 241, it can be called a sidewall or sidewall insulating layer. The insulating layer 216 has a region in contact with the top surface of the insulating layer 110a in the opening 241. In the opening 241, the semiconductor layer 208 has a region in contact with the top surface of the conductive layer 212a, the side surface of the insulating layer 107, the side surface of the insulating layer 110a, and the side surface of the insulating layer 216. The insulating layer 216 is located between the semiconductor layer 208 and the conductive layer 203 and the layer 205, and the conductive layer 203 and the semiconductor layer 208 are electrically insulated from each other by the insulating layer 216. For the conductive layer 203, the layer 205, and the insulating layer 216, the descriptions regarding the conductive layer 103, the layer 105, and the insulating layer 116 can be referred to. The insulating layer 216 can be formed, for example, in the same process as the insulating layer 116.

[0252] In the transistor 200A, the conductive layer 204 functions as a gate electrode (also referred to as a first gate electrode). Part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 203 functions as a back gate electrode (also referred to as a second gate electrode). The insulating layer 216 functions as a back gate insulating layer (also referred to as a second gate insulating layer).

[0253] By providing a back gate electrode in the transistor 200A, the potential on the back channel side of the semiconductor layer 208 is fixed, and the saturation of the Id-Vd characteristics can be improved. Furthermore, by fixing the potential on the back channel side of the semiconductor layer 208, a shift in the threshold voltage can be suppressed. Therefore, a transistor with a small cutoff current can be obtained, and a semiconductor device with low power consumption can be provided.

[0254] One or both of the insulating layer 110a and the insulating layer 107 preferably have a region located between the conductive layer 212a and the insulating layer 216. Furthermore, at least one of the layers located between the conductive layer 212a and the insulating layer 216 preferably functions as a barrier film. FIG. 10A and other drawings show a configuration in which the insulating layer 110a and the insulating layer 107 have a region located between the conductive layer 212a and the insulating layer 216. The insulating layer 216 has a region in contact with the top surface of the insulating layer 110a. It can also be said that the insulating layer 110a and the insulating layer 107 have portions that protrude beyond the end of the layer 205 on the opening 241 side. By providing the insulating layer 110a, which functions as a barrier film, between the insulating layer 216 and the conductive layer 212a, oxygen can be prevented from being supplied from the insulating layer 216 to the conductive layer 212a. This can prevent the conductive layer 212a from being oxidized and the electrical resistance of the conductive layer 212a from increasing.

[0255] 10A , the thickness of the region of insulating layer 110a that contacts the lower surface of insulating layer 216 may be thinner than the thickness of the region that contacts the lower surface of conductive layer 203. In this case, insulating layer 216 has regions that contact the upper and side surfaces of insulating layer 110a. Note that, as shown in FIG. 10B , the thickness of the region of insulating layer 110a that contacts the lower surface of insulating layer 216 may be the same as or approximately the same as the thickness of the region that contacts the lower surface of conductive layer 203.

[0256] 11A, the insulating layer 216 can be in contact with the insulating layer 107. In this case, the insulating layer 107 preferably functions as a barrier film. The materials that can be used for the barrier film are as described above.

[0257] 11B, the insulating layer 216 can be in contact with the conductive layer 212a. In this case, the insulating layer 216 preferably has a barrier film. FIG. 11B shows a structure example in which the insulating layer 216 has a stacked structure of an insulating layer 216a and an insulating layer 216b over the insulating layer 216a. The insulating layer 216a in contact with the conductive layer 212a preferably functions as a barrier film. For the insulating layer 216a and the insulating layer 216b, the description of the insulating layer 116a and the insulating layer 116b can be referred to.

[0258] 7A illustrates a structure in which the height of the top surface of the insulating layer 116 is the same as or approximately the same as the height of the top surface of the insulating layer 110; however, one embodiment of the present invention is not limited to this. Structural examples in which the heights of the top surfaces of the insulating layer 116 and the insulating layer 216 are different from the height of the top surface of the insulating layer 110 are illustrated in FIGS.

[0259] 12A shows a configuration in which the height of the top surface of the insulating layer 116 is the same as or approximately the same as the height of the top surface of the conductive layer 112b. By making the height of the top surface of the insulating layer 116 the same as or approximately the same as the height of the top surface of the conductive layer 112b, the step on the surface on which the insulating layer 116 and a layer (e.g., the semiconductor layer 108) provided on the conductive layer 112b are formed is reduced, thereby preventing defects such as discontinuities or voids in the layer. Similarly, as shown in FIG. 12B, the height of the top surface of the insulating layer 216 can be made the same as or approximately the same as the height of the top surface of the conductive layer 212b.

[0260] FIG. 12C shows a configuration in which the height of the top surface of the insulating layer 116 is lower than the height of the top surface of the conductive layer 112b but higher than the height of the top surface of the insulating layer 110c. The semiconductor layer 108 contacts the top surface and side surfaces of the conductive layer 112b. By contacting the semiconductor layer 108 with the side surfaces of the conductive layer 112b, the contact area between the semiconductor layer 108 and the conductive layer 112b is increased, thereby reducing the contact resistance between the semiconductor layer 108 and the conductive layer 112b. Similarly, as shown in FIG. 12D, the height of the top surface of the insulating layer 216 can be lower than the height of the top surface of the conductive layer 212b but higher than the height of the top surface of the insulating layer 110c. Alternatively, as shown in FIG. 12E, the height of the top surface of the insulating layer 116 can be lower than the height of the top surface of the insulating layer 110c but higher than the height of the top surface of the insulating layer 110b. As shown in FIG. 12F, the height of the top surface of the insulating layer 216 can be lower than the height of the top surface of the insulating layer 110c but higher than the height of the top surface of the insulating layer 110b.

[0261] 12G, the height of the top surface of insulating layer 116 can be lower than the height of the top surface of insulating layer 110b and higher than the height of the top surface of layer 105. By contacting insulating layer 110b with semiconductor layer 108, oxygen can be supplied from insulating layer 110b to semiconductor layer 108. It is preferable that insulating layer 116 be in contact with at least the entire side surface of layer 105 on the opening 141 side. Similarly, as shown in FIG. 12H, the height of the top surface of insulating layer 216 can be lower than the height of the top surface of insulating layer 110b and higher than the height of the top surface of layer 205.

[0262] 13A and 13B are cross-sectional views of a semiconductor device 10C according to one embodiment of the present invention. For a top view of the semiconductor device 10C, see FIG. 6A . FIG. 13A is a cross-sectional view of the cut surface taken along dashed line A1-A2 in FIG. 6A , and FIG. 13B is a cross-sectional view of the cut surface taken along dashed line A1-A2.

[0263] The semiconductor device 10C includes a transistor 100A, a transistor 200B, an insulating layer 110, and an insulating layer 107. The transistor 200B differs from the transistor 200 shown in FIG. 6A and the like mainly in that the transistor 200B includes an insulating layer 216. The above description of the transistor 100A can be referred to.

[0264] 13C is an enlarged view of the transistor 200B shown in FIG. 13A. The insulating layer 216 has a region in contact with the side surface of the insulating layer 110 in the opening 241. The insulating layer 116 also has a region in contact with the top surface of the insulating layer 110a.

[0265] By providing the insulating layer 216 along the sidewall of the opening 241, the step of the surface on which a layer (e.g., the semiconductor layer 208 and the insulating layer 106) formed on the insulating layer 216 is formed is reduced, and the coverage of the layer can be improved. This can prevent defects such as step discontinuities or voids in the layer. Furthermore, the improved coverage of the insulating layer 106 can improve the withstand voltage of the gate insulating layer, resulting in a highly reliable transistor. The above description can be referred to for the insulating layer 216.

[0266] Note that the structures of the conductive layer 103, the layer 105, the insulating layer 116, the conductive layer 203, the layer 205, and the insulating layer 216 shown in Structural Example 2 can also be applied to other structural examples.

[0267] Although the configuration example has been shown in which the formation surface of the bottom electrode of one VFET and the formation surface of the bottom electrode of the other VFET included in the semiconductor device are different from each other, one embodiment of the present invention is not limited to this. The formation surfaces of these bottom electrodes may also be the same. A configuration example of a semiconductor device 10D according to one embodiment of the present invention is shown in FIGS. 14A to 14C . FIG. 14A is a top view of the semiconductor device 10D. FIG. 14B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 14A , and FIG. 14C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0268] The semiconductor device 10D includes a transistor 100A, a transistor 100B, and an insulating layer 110.

[0269] The transistor 100B includes a conductive layer 104s, an insulating layer 106, a semiconductor layer 108s, a conductive layer 112as, and a conductive layer 112bs. In the transistor 100B, the conductive layer 104s functions as a gate electrode, the insulating layer 106 functions as a gate insulating layer, the conductive layer 112as functions as one of a source electrode and a drain electrode, and the conductive layer 112bs functions as the other of the source electrode and the drain electrode. The semiconductor layer 108s includes a channel formation region of the transistor 100B. The transistor 100B has a structure similar to that of the transistor 100. The conductive layer 104s, the semiconductor layer 108s, the conductive layer 112as and the conductive layer 112bs, and the openings 141s and 143s of the transistor 100B correspond to the conductive layer 104, the semiconductor layer 108, the conductive layer 112a and the conductive layer 112b, and the openings 141 and 143 of the transistor 100. The above description can be referred to for the transistor 200A.

[0270] The formation surface of the lower electrode of the transistor 100A and the formation surface of the lower electrode of the transistor 100B can be the same. Figures 14B and 14C show a structure example in which the conductive layer 112a and the conductive layer 112as are both provided in contact with the top surface of the substrate 102. The conductive layer 112as can be formed in the same process as the conductive layer 112a. For example, the conductive layer 112a and the conductive layer 112as can be formed by forming a film that will become the conductive layer 112a and the conductive layer 112as and then processing the film. This can improve the productivity of the semiconductor device.

[0271] Note that the structures of the conductive layers 112a and 112as described in Structural Example 2 can be applied to other structural examples.

[0272] 15A is a cross-sectional view of a semiconductor device 10E according to one embodiment of the present invention. For a top view of the semiconductor device 10E, see FIG. 1A. FIG. 15A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0273] The semiconductor device 10E includes a transistor 100C, a transistor 200C, an insulating layer 110, and an insulating layer 107. The semiconductor device 10E differs from the semiconductor device 10 shown in FIG. 1B and the like mainly in that the insulating layer 110 includes an insulating layer 110d and an insulating layer 110e.

[0274] FIG. 15B shows an enlarged view of the transistor 100C shown in FIG. 15A, and FIG. 15C shows an enlarged view of the transistor 200C. The insulating layer 110 includes an insulating layer 110d, an insulating layer 110a on the insulating layer 110d, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110e on the insulating layer 110c. The insulating layer 110d and the insulating layer 110e can be made of the same material as the insulating layer 107, the insulating layer 110a, and the insulating layer 110c. The insulating layer 110d and the insulating layer 110e can be made of, for example, silicon nitride or silicon nitride oxide. The insulating layer 110d and the insulating layer 110e can be made of the same material, or different materials.

[0275] The insulating layer 110d is provided between the insulating layer 110a and the conductive layer 112a and the insulating layer 107. The insulating layer 110d is provided so as to cover the conductive layer 112a and the insulating layer 107. The insulating layer 110d has regions in contact with the top surface and side surfaces of the conductive layer 112a, the top surface of the insulating layer 107, the side surface of the semiconductor layer 108, and the side surface of the semiconductor layer 208.

[0276] The insulating layer 110e is provided between the insulating layer 110c and the conductive layer 112b and the conductive layer 212b. The insulating layer 110e has regions in contact with the top surface of the insulating layer 110c, the bottom surface of the conductive layer 112b, the bottom surface of the conductive layer 212b, the bottom surface of the insulating layer 106, the side surface of the semiconductor layer 108, and the side surface of the semiconductor layer 208.

[0277] The insulating layers 110d and 110e are preferably formed using a material that releases impurities that increase the conductivity of the semiconductor layers 108 and 208, respectively. For elements contained in the impurities, refer to the description of the insulating layer 107. When a metal oxide is used for the semiconductor layers 108 and 208, the impurities released by the insulating layers 110d and 110e preferably contain hydrogen.

[0278] The insulating layer 110d and the insulating layer 110e each preferably contain nitrogen and preferably use one or more of the above-mentioned nitrides and nitride oxides. That is, the insulating layer 110d and the insulating layer 110e each preferably contain nitrogen and an impurity element. When hydrogen is used as the impurity element, the insulating layer 110d and the insulating layer 110e each preferably contain silicon, nitrogen, and hydrogen. For example, the insulating layer 110d and the insulating layer 110e can preferably use silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen.

[0279] Impurities released from the insulating layer 110d and the insulating layer 110e diffuse into the semiconductor layer 108 and the semiconductor layer 208. The regions of the semiconductor layer 108 in contact with the insulating layer 110d, the region of the semiconductor layer 108 in contact with the insulating layer 110e, the region of the semiconductor layer 208 in contact with the insulating layer 110d, and the region of the semiconductor layer 208 in contact with the insulating layer 110e each contain impurities, so that these regions can be low-resistance regions. The semiconductor layer 108 can have low-resistance regions between the region in contact with the conductive layer 112a (one of the source region and the drain region of the transistor 100C) and the channel formation region, and between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region. Similarly, the semiconductor layer 208 may have low-resistance regions between the region in contact with the conductive layer 212a (one of the source and drain regions of the transistor 200C) and the channel formation region, and between the region in contact with the conductive layer 212b (the other of the source and drain regions) and the channel formation region. These low-resistance regions can function as buffer regions for alleviating the drain electric field. By providing a low-resistance region between the drain and the channel formation region, a high electric field is less likely to occur near the drain, which can suppress the generation of hot carriers and the degradation of the transistor. Note that these low-resistance regions may function as source or drain regions.

[0280] In the transistor 200C, by using a material that releases impurities for the insulating layer 107 and the insulating layer 110d, the region of the semiconductor layer 208 in contact with the insulating layer 107 and the region in contact with the insulating layer 110d can be made into a low-resistance region. In this case, the insulating layer 110a preferably functions as a barrier film. Materials that can be used for the barrier film are as described above. Alternatively, by using a material that releases impurities for the insulating layer 110d, the insulating layer 107 can also function as a barrier film.

[0281] It is more preferable to use a material for the insulating layer 110d that emits impurities that lower the electrical resistance of the conductive layers 112a and 212a. Similarly, it is more preferable to use a material for the insulating layer 110e that emits impurities that lower the electrical resistance of the conductive layers 112b and 212b. The impurities emitted from the insulating layer 110d diffuse into the conductive layer 112a and then diffuse into the conductive layer 212a via the insulating layer 107. The impurities emitted from the insulating layer 110e diffuse into the conductive layer 112b and 212b. By including impurities in the conductive layers 112a, 112b, 212a, and 212b, respectively, the electrical resistance of these conductive layers can be lowered. For example, when a metal oxide is used for the conductive layers 112a, 112b, 212a, and 212b, the electrical resistance of the conductive layers 112a, 112b, 212a, and 212b can be reduced by using a material that releases impurities containing hydrogen for the insulating layers 110d and 110e. This allows a semiconductor device with low wiring resistance to be obtained. Note that the impurities that reduce the electrical resistance of the conductive layers 112a and 212a may be the same as or different from the impurities that reduce the electrical resistance of the semiconductor layers 108 and 208.

[0282] The insulating layers 110d and 110e can be formed using a gas containing an impurity. When hydrogen is used as the impurity, the insulating layers 110d and 110e can be formed using a gas containing a hydrogen element. For the formation of the insulating layers 110d and 110e, the description of the formation of the insulating layer 107 can be referred to.

[0283] The insulating layer 110d has an impurity element concentration of 1×10 ２１ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Below 1 × 10, preferably ２１ atoms / cm ３ 5x10 or more ２２ atoms / cm ３ Less than or equal to 5×10, more preferably ２１ atoms / cm ３ 5x10 or more ２２ atoms / cm３ The same applies to the insulating layer 110e. For example, the insulating layer 110d and the insulating layer 110e each preferably include a portion having a hydrogen concentration in the above-mentioned range.

[0284] It is preferable that the insulating layer 110a be provided between the insulating layer 110d and the insulating layer 110b, and the insulating layer 110c be provided between the insulating layer 110e and the insulating layer 110b. By providing the insulating layer 110a and the insulating layer 110c functioning as barrier films, it is possible to prevent impurities released from the insulating layer 110d from diffusing into the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208 through the insulating layers 110a and 110b, or to prevent impurities released from the insulating layer 110e from diffusing into the channel formation regions of the semiconductor layer 108 and the semiconductor layer 208 through the insulating layers 110a and 110b, or through the insulating layers 110c and 110b. This makes it possible to provide the transistor 100C and the transistor 200C with good electrical characteristics and high reliability.

[0285] The insulating layer 110d preferably has a region having a higher impurity element concentration than the insulating layer 110a. For example, the insulating layer 110d preferably has a region having a higher hydrogen concentration than the insulating layer 110a. The amount of released hydrogen can be adjusted by differentiating the deposition conditions for the insulating layer 110d and the insulating layer 110a. For example, the hydrogen content in the deposition gas used to form the insulating layer 110d is preferably higher than the hydrogen content in the deposition gas used to form the insulating layer 110a. Furthermore, the film density of the insulating layer 110a is more preferably higher than that of the insulating layer 110d. For the insulating layer 110a and the insulating layer 110d, the descriptions regarding the insulating layer 110a and the insulating layer 107 can be referred to.

[0286] The insulating layer 110e preferably has a region where the concentration of impurity elements is higher than that of the insulating layer 110c. For example, the insulating layer 110e preferably has a region where the concentration of hydrogen is higher than that of the insulating layer 110c. The film density of the insulating layer 110c is more preferably higher than that of the insulating layer 110e. For the insulating layer 110c and the insulating layer 110e, the descriptions regarding the insulating layer 110a and the insulating layer 107, and the insulating layer 110a and the insulating layer 110d can be referred to.

[0287] Although the insulating layer 110 has a five-layer structure here, one embodiment of the present invention is not limited to this. A structure in which one of the insulating layer 110d and the insulating layer 110e is not provided is also possible. The insulating layer 110 can also have a two-layer, three-layer, four-layer, or six or more-layer structure. Alternatively, the insulating layer 110 can have a single-layer structure.

[0288] The configuration of the insulating layer 110 shown in Configuration Example 3 can also be applied to other configuration examples.

[0289] 16A is a cross-sectional view of a semiconductor device 10F according to one embodiment of the present invention. For a top view of the semiconductor device 10F, see FIG. 1A. FIG. 16A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

[0290] The semiconductor device 10F includes a transistor 100D, a transistor 200D, an insulating layer 110, an insulating layer 107, and an insulating layer 109. The semiconductor device 10F differs from the semiconductor device 10 shown in FIG. 1B and the like mainly in that the semiconductor device 10F includes the insulating layer 109 and that the insulating layer 110 includes an insulating layer 110e.

[0291] FIG. 16B shows an enlarged view of the transistor 100D shown in FIG. 16A , and FIG. 16C shows an enlarged view of the transistor 200D. The insulating layer 109 is provided between the insulating layer 107 and the conductive layer 212a and the substrate 102. The insulating layer 109 is provided over the substrate 102, the conductive layer 212a is provided over the insulating layer 109, the insulating layer 107 is provided over the conductive layer 212a, and the conductive layer 112a is provided over the insulating layer 107. The insulating layer 109 has regions in contact with the lower surface of the conductive layer 212a, the lower surface of the insulating layer 107, and the upper surface of the substrate 102. The conductive layer 212a has regions in contact with the insulating layer 109 and the insulating layer 107 and sandwiched therebetween. The above description can be referred to for the insulating layer 110e.

[0292] The insulating layer 109 is preferably made of a material that releases impurities that reduce the electrical resistance of the semiconductor layer 108 and the semiconductor layer 208. For elements contained in the impurities, the description of the insulating layer 107 can be referred to. When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the impurities released by the insulating layer 109 more preferably contain hydrogen. For the insulating layer 109, the descriptions of the insulating layer 107, the insulating layer 110d, and the insulating layer 110e can be referred to.

[0293] The impurities released from the insulating layer 109 diffuse into the region of the conductive layer 212a that is in contact with the insulating layer 109. The impurities diffused into the conductive layer 212a also diffuse into the region of the semiconductor layer 208 that is in contact with the conductive layer 212a. This can reduce the electrical resistance of the region of the semiconductor layer 208 that is in contact with the conductive layer 212a. Similarly, the impurities released from the insulating layer 109 diffuse into the conductive layer 112a via the insulating layer 107, and the impurities diffused into the conductive layer 112a also diffuse into the region of the semiconductor layer 108 that is in contact with the conductive layer 112a. This can reduce the electrical resistance of the region of the semiconductor layer 108 that is in contact with the conductive layer 112a. Therefore, the transistors 100D and 200D can have large on-state currents, and can operate at high speed.

[0294] It is more preferable that the insulating layer 109 be formed using a material that releases impurities that reduce the electrical resistance of the conductive layers 112a and 212a. This can reduce the electrical resistance of the conductive layers 112a and 212a. For example, when a metal oxide is used for the conductive layers 112a and 212a, the impurities preferably contain hydrogen.

[0295] 16A and other drawings show the insulating layer 110 having a four-layer structure of insulating layers 110a, 110b, 110c, and 110e, but one embodiment of the present invention is not limited to this. For example, the insulating layer 110 can have a three-layer structure of insulating layers 110a, 110b, and 110c. Alternatively, the insulating layer 110 can have a five-layer structure of insulating layers 110a, 110b, 110c, 110d, and 110e.

[0296] The configuration of the insulating layer 109 shown in the fourth structural example can also be applied to the other structural examples.

[0297] 17A to 18B are cross-sectional views of a semiconductor device 10G according to one embodiment of the present invention. For a top view of the semiconductor device 10G, refer to FIG. 1A. 17A to 18B are cross-sectional views of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A.

[0298] The semiconductor device 10G includes a transistor 100E, a transistor 200E, an insulating layer 110, and an insulating layer 107. The transistor 100E differs from the transistor 100 shown in FIG. 1B and the like mainly in that the conductive layer 112a has a stacked structure. The transistor 200E differs from the transistor 200 mainly in that the conductive layer 212a has a stacked structure.

[0299] 17A and 17B show a configuration in which the conductive layer 112a has a two-layer structure of a conductive layer 112a_1 and a conductive layer 112a_2 over the conductive layer 112a_1, and the conductive layer 212a has a two-layer structure of a conductive layer 212a_1 and a conductive layer 212a_2 over the conductive layer 212a_1.

[0300] For the conductive layer 112a_2 having a region in contact with the semiconductor layer 108, a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor is preferably used. For materials that can be used for the conductive layer 112a_2, the description of the conductive layer 112a can be referred to.

[0301] The conductive layer 112a_1 does not have a region in contact with the semiconductor layer 108, and therefore the material used is not particularly limited. For example, the conductive layer 112a_1 is preferably made of a material having lower electrical resistivity than the conductive layer 112a_2. This can reduce the electrical resistance of the conductive layer 112a. For example, In—Sn—Si oxide (ITSO) can be preferably used for the conductive layer 112a_2, and copper or tungsten can be preferably used for the conductive layer 112a_1.

[0302] 17A , the edge of the conductive layer 112a_2 can be aligned or substantially aligned with the edge of the conductive layer 112a_1. For example, the conductive layer 112a can be formed by forming a first film to be the conductive layer 112a_1 and a second film to be the conductive layer 112a_2, and then processing the first film and the second film. By processing the first film and the second film in the same process, manufacturing costs can be reduced.

[0303] The end of the conductive layer 112a_2 may not be aligned with the end of the conductive layer 112a_1. As shown in FIG. 17B, the conductive layer 112a_2 may be provided so as to cover the conductive layer 112a_1. The conductive layer 112a_2 has a region in contact with the top surface and side surface of the conductive layer 112a_1. It can also be said that the conductive layer 112a_2 has a portion protruding beyond the end of the conductive layer 112a_1. For example, the conductive layer 112a_1 may be formed, a film to become the conductive layer 112a_2 may be formed on the conductive layer 112a_1, and the film may be processed to form the conductive layer 112a_2. By making the conductive layer 112a_2 protrude beyond the end of the conductive layer 112a_1, the step of the formation surface of a layer (e.g., the insulating layer 110) formed on the conductive layer 112a is reduced, thereby improving the coverage of the layer. This can prevent defects such as discontinuities or voids in the layer.

[0304] As shown in Figures 17A and 17B, some or all of the layers constituting the conductive layer 112a may have different thicknesses. The electrical resistance of the conductive layer 112a can be reduced by making the thickness of a layer using a material with low electrical resistivity thicker than the other layers. For example, a material with lower electrical resistivity than the conductive layer 112a_1 can be used for the conductive layer 112a_1, and the thickness of the conductive layer 112a_1 can be made thicker than the thickness of the conductive layer 112a_2. This reduces the electrical resistance of the conductive layer 112a. The thicknesses of the layers constituting the conductive layer 112a can also be the same or approximately the same.

[0305] For the conductive layers 212a_1 and 212a_2, the description of the conductive layers 112a_1 and 112a_2 can be referred to.

[0306] 18A and 18B show a configuration in which the conductive layer 112a has a three-layer structure of a conductive layer 112a_3, a conductive layer 112a_1 on the conductive layer 112a_3, and a conductive layer 112a_2 on the conductive layer 112a_1, and the conductive layer 212a has a three-layer structure of a conductive layer 212a_3, a conductive layer 212a_1 on the conductive layer 212a_3, and a conductive layer 212a_2 on the conductive layer 212a_1.

[0307] As shown in FIG. 18A , the end of the conductive layer 112a_1 can be in contact with the top surface of the conductive layer 112a_3. The conductive layer 112a_2 has regions in contact with the top surface and side surface of the conductive layer 112a_1 and the top surface of the conductive layer 112a_3. That is, it can be said that the conductive layers 112a_2 and 112a_3 each have portions that protrude beyond the end of the conductive layer 112a_1. It can also be said that the top surface, side surface, and bottom surface of the conductive layer 112a_1 are surrounded by the conductive layers 112a_2 and 112a_3. The conductive layer 112a_3 is preferably made of a material that has high adhesion to the surface on which the conductive layer 112a_3 is formed (here, the top surface of the insulating layer 107). The end of the conductive layer 112a_3 can be aligned or approximately aligned with the end of the conductive layer 112a_2. For example, a first film to be the conductive layer 112a_3 is formed, a conductive layer 112a_1 is formed on the first film, and a second film to be the conductive layer 112a_2 is formed on the first film and the conductive layer 112a_1. Then, by processing the first film and the second film, the conductive layer 112a including the conductive layer 112a_3, the conductive layer 112a_1, and the conductive layer 112a_2 can be formed. By processing the first film and the second film in the same process, manufacturing costs can be reduced.

[0308] As described above, the conductive layer 112a_1 is preferably formed using a material with low electrical resistivity. However, depending on the material, adhesion between the conductive layer 112a_1 and a surface on which the conductive layer 112a_1 is to be formed (e.g., the top surface of the insulating layer 107) may be low, which may result in a low manufacturing yield of the semiconductor device. By using a material for the conductive layer 112a_3 that has higher adhesion to the surface on which the conductive layer 112a_1 is to be formed than the conductive layer 112a_1, the manufacturing yield of the semiconductor device can be increased. Note that the thickness of the conductive layer 112a_3 is preferably a thickness that effectively increases the adhesion of the conductive layer 112a to the surface on which the conductive layer 112a is to be formed, and can be thinner than the thicknesses of the conductive layer 112a_1 and the conductive layer 112a_2. Reducing the thickness of the conductive layer 112a_3 can reduce manufacturing costs.

[0309] For example, In—Sn—Si oxide (ITSO) can be preferably used for the conductive layer 112a_3, copper can be preferably used for the conductive layer 112a_1, and In—Sn—Si oxide (ITSO) can be preferably used for the conductive layer 112a_2. Furthermore, using the same material for the conductive layer 112a_2 and the conductive layer 112a_3 facilitates processing when the conductive layer 112a_2 and the conductive layer 112a_3 are formed in the same process, thereby increasing the manufacturing yield of the semiconductor device.

[0310] 18B , the edge of the conductive layer 112a_3 can be aligned or substantially aligned with the edge of the conductive layer 112a_1. For example, a first film to be the conductive layer 112a_3 is formed, a second film to be the conductive layer 112a_1 is formed on the first film, and the first and second films are processed to form the conductive layer 112a_3 and the conductive layer 112a_1. Then, the conductive layer 112a can be formed by forming the conductive layer 112a_2 on the conductive layer 112a_3 and the conductive layer 112a_1. By processing the first film and the second film in the same process, manufacturing costs can be reduced.

[0311] For the conductive layers 212a_1, 212a_2, and 212a_3, the description of the conductive layers 112a_1, 112a_2, and 112a_3 can be referred to.

[0312] Here, the conductive layer 112a and the conductive layer 212a each have a stacked structure of two or three layers, but one embodiment of the present invention is not limited to this. The conductive layer 112a and the conductive layer 212a may also have a stacked structure of four or more layers. The conductive layer 112a and the conductive layer 212a may also have different structures.

[0313] Note that the structures of the conductive layer 112a and the conductive layer 212a shown in Structural example 5 can also be applied to other structural examples.

[0314] 19 is a cross-sectional view of a semiconductor device 10H according to one embodiment of the present invention. For a top view of the semiconductor device 10H, refer to FIG. 1A. FIG. 19 is a cross-sectional view of the cut surface taken along dashed line A1-A2 in FIG. 1A.

[0315] The semiconductor device 10H includes a transistor 100F, a transistor 200F, an insulating layer 110, and an insulating layer 107. The transistors 100F and 200F are different from the transistors 100 and 200 shown in FIG. 1B and the like mainly in that the insulating layer 106 has a stacked structure. FIG. 19 shows a configuration in which the insulating layer 106 has a two-layer structure of an insulating layer 106a and an insulating layer 106b over the insulating layer 106a.

[0316] In the case where the insulating layer 106 has a stacked-layer structure, the insulating layer (the insulating layer 106a here) on the semiconductor layer 108 and the semiconductor layer 208 side preferably contains oxide or oxynitride. For example, the insulating layer 106a can be preferably made of one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

[0317] It is preferable to provide a layer that functions as a barrier film in at least one of the layers that constitute the insulating layer 106. This can prevent metal components contained in the conductive layer 104 and the conductive layer 204 and impurities (e.g., water and hydrogen) contained in layers formed on the transistors 100F and 200F from diffusing into the semiconductor layer 108 and the semiconductor layer 208 through the insulating layer 106. Furthermore, it can prevent oxygen contained in the semiconductor layer 108 and the semiconductor layer 208 from diffusing into the conductive layer 104 and the conductive layer 204 through the insulating layer 106. This can prevent oxygen deficiency (V Ｏ ) and V Ｏ The increase in H can be suppressed. Furthermore, the conductive layer 104 and the conductive layer 204 can be prevented from being oxidized by oxygen contained in the semiconductor layer 108 and the semiconductor layer 208, and the increase in the electrical resistance of the conductive layer 104 and the conductive layer 204 can be suppressed. As a result, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics. The layer functioning as a barrier film preferably uses one or more of the above-described nitrides and nitride oxides. Alternatively, one or more of oxides and oxynitrides can also be used for the layer, and aluminum oxide can be preferably used, for example.

[0318] For example, silicon oxynitride can be used for the insulating layer 106a, and silicon nitride can be used for the insulating layer 106b. Alternatively, silicon oxynitride can be used for the insulating layer 106a, and aluminum oxide can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a, and silicon oxynitride can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a, and silicon nitride can be used for the insulating layer 106b.

[0319] Although the insulating layer 106 has a two-layer structure in this example, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a three-layer or more layer structure.

[0320] The configuration of the insulating layer 106 shown in Configuration Example 6 can also be applied to other configuration examples.

[0321] 20A is a cross-sectional view of a semiconductor device 10I according to one embodiment of the present invention. For a top view of the semiconductor device 10I, refer to FIG. 1A. FIG. 20A is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A.

[0322] The semiconductor device 10I includes a transistor 100G, a transistor 200G, an insulating layer 110, and an insulating layer 107. The semiconductor device 10I is mainly different from the semiconductor device 10 shown in FIG. 1B and the like in that the semiconductor layer 108 and the semiconductor layer 208 each have a stacked structure.

[0323] Fig. 20B shows an enlarged view of the transistor 100G shown in Fig. 20A, and Fig. 20C shows an enlarged view of the transistor 200G. Fig. 20A to Fig. 20C show a configuration in which the semiconductor layer 108 has a three-layer structure of a semiconductor layer 108a, a semiconductor layer 108b on the semiconductor layer 108a, and a semiconductor layer 108c on the semiconductor layer 108b, and the semiconductor layer 208 has a three-layer structure of a semiconductor layer 208a, a semiconductor layer 208b on the semiconductor layer 208a, and a semiconductor layer 208c on the semiconductor layer 208b.

[0324] The semiconductor layer 108a, the semiconductor layer 108b, the semiconductor layer 108c, the semiconductor layer 208a, the semiconductor layer 208b, and the semiconductor layer 208c can be made of the materials listed for the semiconductor layer 108 and the semiconductor layer 208, respectively. The semiconductor layer 108a, the semiconductor layer 108b, the semiconductor layer 108c, the semiconductor layer 208a, the semiconductor layer 208b, and the semiconductor layer 208c each preferably contain a metal oxide exhibiting semiconductor characteristics. The semiconductor layer 108a can be made of the same material as the semiconductor layer 208a, the semiconductor layer 108b can be made of the same material as the semiconductor layer 208b, and the semiconductor layer 108c can be made of the same material as the semiconductor layer 208c.

[0325] For example, the semiconductor layer 108a and the semiconductor layer 208a can be formed in the same process. The semiconductor layer 108b and the semiconductor layer 208b can be formed in the same process. The semiconductor layer 108c and the semiconductor layer 208c can be formed in the same process. The semiconductor layer 108 and the semiconductor layer 208 can be formed by forming a first film that will become the semiconductor layer 108a and the semiconductor layer 208a, forming a second film that will become the semiconductor layer 108b and the semiconductor layer 208b, and forming a third film that will become the semiconductor layer 108c and the semiconductor layer 208c, and processing the first film, the second film, and the third film. Alternatively, the layers included in the semiconductor layer 108 can be formed in a process different from that of the semiconductor layer 208.

[0326] The band gap of each of the first metal oxide included in the semiconductor layer 108a and the semiconductor layer 208a, the second metal oxide included in the semiconductor layer 108b and the semiconductor layer 208b, and the third metal oxide included in the semiconductor layer 108c and the semiconductor layer 208c is preferably 2.0 eV or more, more preferably 2.5 eV or more.

[0327] The band gap of the first metal oxide is preferably larger than the band gap of the second metal oxide. The band gap of the third metal oxide is preferably larger than the band gap of the second metal oxide. The semiconductor layer 108b is sandwiched between the semiconductor layers 108a and 108c, which have larger band gaps than the semiconductor layer 108b, to form a buried channel. As a result, the semiconductor layer 108b serves as the main current path in the semiconductor layer 108. Similarly, the semiconductor layer 208b is sandwiched between the semiconductor layers 208a and 208c to form a buried channel. As a result, the semiconductor layer 208b serves as the main current path in the semiconductor layer 208.

[0328] In the following, the semiconductor layer 108 including the semiconductor layer 108a, the semiconductor layer 108b, and the semiconductor layer 108c will be described as an example, and a description of the semiconductor layer 208 may be omitted. Regarding the semiconductor layer 208, the description of the semiconductor layer 108a, the semiconductor layer 108b, and the semiconductor layer 108c can be read as the semiconductor layer 208a, the semiconductor layer 208b, and the semiconductor layer 208c.

[0329] The difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, even more preferably 0.3 eV or more, and even more preferably 0.5 eV or more. The difference between the band gap of the third metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, even more preferably 0.3 eV or more, and even more preferably 0.5 eV or more.

[0330] The conduction band minimum of the first metal oxide is preferably closer to the vacuum level than the conduction band minimum of the second metal oxide. The conduction band minimum of the third metal oxide is preferably closer to the vacuum level than the conduction band minimum of the second metal oxide. In other words, the electron affinity of the first metal oxide is preferably smaller than the electron affinity of the second metal oxide. The electron affinity of the third metal oxide is preferably smaller than the electron affinity of the second metal oxide.

[0331] The band gaps of the first metal oxide, the second metal oxide, and the third metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy (XPS or ESCA), or X-ray absorption fine structure (XAFS). Alternatively, analysis can be performed by combining a plurality of these techniques. The electron affinity or the conduction band minimum can be determined from the ionization potential, which is the energy difference between the vacuum level and the valence band maximum, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0332] Trap levels due to impurities or defects can be formed at and near the interface between the insulating layer 110 and the semiconductor layer 108. Examples of such impurities include residual components of an etchant or etching gas used to form the opening 141 and components of the conductive layer 112a that adhere to the side surface of the insulating layer 110 when the opening 141 is formed. By providing the semiconductor layer 108a between the semiconductor layer 108b and the insulating layer 110, the semiconductor layer 108b can be kept away from the trap levels.

[0333] Damage may occur to the interface between the insulating layer 106 and the semiconductor layer 108 and its vicinity when the insulating layer 106 is formed. As a result, trap states may be formed at the interface between the insulating layer 106 and the semiconductor layer 108 and its vicinity. By providing the semiconductor layer 108c between the semiconductor layer 108b and the insulating layer 106, the semiconductor layer 108b can be kept away from the trap states.

[0334] By sandwiching the semiconductor layer 108b, which is the main current path of the semiconductor layer 108, between the semiconductor layer 108a and the semiconductor layer 108c, it is possible to reduce trap levels at the interface of the semiconductor layer 108b and in the vicinity of the interface. This makes it possible to provide a transistor with high on-state current and high reliability. Therefore, it is possible to provide a semiconductor device that achieves both high-speed operation and high reliability.

[0335] The composition of the first metal oxide is preferably different from the composition of the second metal oxide. The composition of the third metal oxide is preferably different from the composition of the second metal oxide. By varying the compositions of the metal oxides, the band gap can be adjusted. Specifically, the content of element M in the first metal oxide and the content of element M in the third metal oxide are preferably higher than the content of element M in the second metal oxide. This allows the band gap of the first metal oxide and the band gap of the third metal oxide to be larger than the band gap of the second metal oxide.

[0336] The indium content of the second metal oxide is preferably higher than the indium content of the first metal oxide and the indium content of the third metal oxide, thereby enabling a transistor with a large on-state current to be obtained.

[0337] For example, when the first metal oxide and the second metal oxide are In-M-Zn oxides, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 40:1:10 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:10 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:40 (atomic ratio) or thereabout. It is particularly preferable to use one or more of gallium, aluminum, and tin as the element M. The element M in the first metal oxide, the element M in the second metal oxide, and the element M in the third metal oxide can have the same structure. Alternatively, some or all of these elements can be different. Furthermore, when one or more of the first metal oxide, the second metal oxide, and the third metal oxide contain multiple elements M, each of the elements M may be the same as the element M contained in the other metal oxide, or some or all of the elements M may be different.

[0338] More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=40:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=10:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, the second metal oxide may preferably have a composition of In:Sn:Zn=10:1:40 [atomic ratio] or a composition thereabout, and the third metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout.

[0339] The second metal oxide may be configured to not contain the element M. For example, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=4:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout. Alternatively, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=1:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout. Alternatively, the first metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, the second metal oxide may preferably have a composition of In:Zn=1:4 [atomic ratio] or a composition thereabout, and the third metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout.

[0340] FIG. 21A shows an enlarged view of the side surfaces of the semiconductor layer 108 and the insulating layer 110 and their vicinity, and FIG. 21B shows an enlarged view of the side surfaces of the semiconductor layer 208 and the insulating layer 110 and their vicinity. In FIG. 21A, the thickness T108a of the semiconductor layer 108a, the thickness T108b of the semiconductor layer 108b, and the thickness T108c of the semiconductor layer 108c are each indicated by solid arrows. In FIG. 21B, the thickness T208a of the semiconductor layer 208a, the thickness T208b of the semiconductor layer 208b, and the thickness T208c of the semiconductor layer 208c are each indicated by solid arrows. Here, the thickness of the semiconductor layer 108 is defined as the shortest distance between the insulating layer 110b and the insulating layer 106 in the region in contact with the semiconductor layer 108 in a cross-sectional view. The thickness of each layer of the semiconductor layer 108 can be, for example, the thickness of each layer of the semiconductor layer 108 at the midpoint between the height of the top surface and the height of the bottom surface of the insulating layer 110. The same applies to the semiconductor layer 208 .

[0341] By increasing the thickness T108b of the semiconductor layer 108b, which is the main current path of the semiconductor layer 108, the transistor 100G can have a large on-state current. The thickness T108b is preferably greater than the thickness T108a and the thickness T108c. However, if the thickness T108b is too thick, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ The amount of H may be greater than the amount of H. The thickness T108b is preferably 1 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, even more preferably 3 nm or more and 20 nm or less, even more preferably 5 nm or more and 20 nm or less, and even more preferably 5 nm or more and 15 nm or less.

[0342] The thickness T108c is preferably thicker than the thickness T108a. By increasing the thickness T108c, the semiconductor layer 108b can be separated from trap levels that may be formed at the interface between the insulating layer 106 and the semiconductor layer 108 and in the vicinity thereof. Furthermore, damage to the semiconductor layer 108b during the formation of the insulating layer 106 can be suppressed. If the thickness T108c is too thick, the distance between the conductive layer 104, which functions as a gate electrode, and the semiconductor layer 108b increases, which may result in a small on-state current. The thickness T108c is preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, even more preferably 1 nm or more and 10 nm or less, and even more preferably 2 nm or more and 10 nm or less.

[0343] The oxygen contained in the insulating layer 110 is supplied to the semiconductor layer 108b through the semiconductor layer 108a. Therefore, it is preferable that the semiconductor layer 108a is easily permeable to oxygen. By making the thickness T108a thinner than the thickness T108c, the oxygen contained in the insulating layer 110 can be efficiently supplied to the semiconductor layer 108b. This reduces the oxygen vacancy (V Ｏ ) and V Ｏ H can be reduced. If the thickness T108a is too thin, the distance between the semiconductor layer 108b and the trap levels at or near the interface between the insulating layer 110 and the semiconductor layer 108 becomes short, which may result in a small on-state current. Furthermore, reliability may be deteriorated. The thickness T108a is preferably 0.1 nm to 10 nm, more preferably 0.3 nm to 5 nm, even more preferably 0.5 nm to 5 nm, and even more preferably 0.5 nm to 3 nm.

[0344] The descriptions regarding the thickness T108a, the thickness T108b, and the thickness T108c can be read as the thickness T208a, the thickness T208b, and the thickness T208c. Note that the thicknesses T108a, T108b, T108c, T208a, T208b, and T208c are not limited to the above-mentioned ranges.

[0345] It is more preferable that the semiconductor layers 108a, 108b, and 108c each have crystallinity. When the semiconductor layer 108a has crystallinity, the crystallinity of the semiconductor layer 108b formed thereon can be increased. Similarly, when the semiconductor layer 108b has crystallinity, the crystallinity of the semiconductor layer 108c formed thereon can be increased.

[0346] The band gap of the first metal oxide and the band gap of the third metal oxide can be different. The band gap of the third metal oxide is preferably larger than the band gap of the first metal oxide. By using a material with a large band gap for the semiconductor layer 108c located on the conductive layer 104 side functioning as a gate electrode, carriers are prevented from being generated and induced in the semiconductor layer 108c and at the interface between the semiconductor layer 108c and the gate insulating layer (the insulating layer 106 here), thereby making the transistor highly reliable. For example, carriers are prevented from being generated and induced in the semiconductor layer 108c and at the interface thereof by light incident on the transistor, thereby making it possible to suppress fluctuations in the electrical characteristics of the transistor due to light.

[0347] Note that by making the band gap of the first metal oxide in the semiconductor layer 208a smaller than the band gap of the third metal oxide in the semiconductor layer 208c, the contact resistance between the semiconductor layer 208a and the conductive layer 212a and the contact resistance between the semiconductor layer 208a and the conductive layer 212b can be reduced. Therefore, the transistor 200 can have a large on-state current.

[0348] The difference between the band gap of the first metal oxide and the band gap of the third metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more. The conduction band minimum of the third metal oxide is preferably closer to the vacuum level than the conduction band minimum of the first metal oxide. In other words, the electron affinity of the third metal oxide is preferably smaller than the electron affinity of the first metal oxide.

[0349] The content of element M in the third metal oxide is preferably higher than the content of element M in the first metal oxide, thereby making it possible to make the band gap of the third metal oxide larger than the band gap of the first metal oxide.

[0350] When the first metal oxide, the second metal oxide, and the third metal oxide are In-M-Zn oxides, for example, the first metal oxide can have a composition of In:M:Zn=1:1:1 (atomic ratio) or thereabout, the second metal oxide can have a composition of In:M:Zn=40:1:10 (atomic ratio) or thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn=1:1:1 (atomic ratio) or thereabout, the second metal oxide can have a composition of In:M:Zn=10:1:10 (atomic ratio) or thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 (atomic ratio) or thereabout.

[0351] More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=40:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=10:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition.

[0352] The second metal oxide may be configured to not contain the element M. For example, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=4:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout. Alternatively, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=1:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout.

[0353] Although Figure 20A and other figures illustrate an example in which the semiconductor layer 108 and the semiconductor layer 208 each have a three-layer structure, one embodiment of the present invention is not limited thereto. For example, the semiconductor layer 108 may have a structure in which one or both of the semiconductor layer 108a and the semiconductor layer 108c are absent, and the semiconductor layer 208 may have a structure in which one or both of the semiconductor layer 208a and the semiconductor layer 208c are absent. For example, as shown in Figure 22A, the semiconductor layer 108 may have a two-layer structure of the semiconductor layer 108b and the semiconductor layer 108c, and the semiconductor layer 208 may have a two-layer structure of the semiconductor layer 208b and the semiconductor layer 208c. Alternatively, as shown in Figure 22B, the semiconductor layer 108 may have a two-layer structure of the semiconductor layer 108a and the semiconductor layer 108b, and the semiconductor layer 208 may have a two-layer structure of the semiconductor layer 208a and the semiconductor layer 208b. Alternatively, the semiconductor layer 108 and the semiconductor layer 208 may each have a stacked structure of four or more layers.

[0354] The structures of the semiconductor layer 108 and the semiconductor layer 208 shown in Structure Example 7 can also be applied to other structure examples.

[0355] Although the structure examples of the semiconductor device including two transistors are described in Structure Example 1 to Structure Example 7, one embodiment of the present invention is not limited thereto. The number of transistors included in the semiconductor device is not particularly limited.

[0356] 23 is a top view of a semiconductor device 10J according to one embodiment of the present invention. FIG. 24A shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 23, and FIG. 24B shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0357] The semiconductor device 10J includes a transistor 100H, a transistor 200H, a transistor 300, an insulating layer 110, an insulating layer 107, and an insulating layer 120. The semiconductor device 10J differs from the semiconductor device 10 shown in FIG. 1B and the like mainly in that the semiconductor device 10J includes the transistor 300 and the insulating layer 120.

[0358] 25A to 25C are enlarged views of the transistor 100H, the transistor 200H, and the transistor 300 shown in FIG. 24A . The transistor 300 includes a conductive layer 304, an insulating layer 106, a semiconductor layer 308, a conductive layer 312a, and a conductive layer 312b. In the transistor 300, the conductive layer 304 functions as a gate electrode, the insulating layer 106 functions as a gate insulating layer, the conductive layer 312a functions as one of a source electrode and a drain electrode, and the conductive layer 312b functions as the other of the source electrode and the drain electrode. The semiconductor layer 308 includes a channel formation region of the transistor 300. For the transistor 100H, the description of the transistor 100 can be referred to. For the transistor 200H, the description of the transistor 200 can be referred to.

[0359] The insulating layer 120 is located between the substrate 102 and the conductive layer 212a, and the conductive layer 312a is located between the substrates 102 and 102. The conductive layer 312a is provided over the substrate 102, the insulating layer 120 is provided over the conductive layer 312a, the conductive layer 212a is provided over the insulating layer 120, the insulating layer 107 is provided over the conductive layer 212a, and the conductive layer 112a is provided over the insulating layer 107. The insulating layer 120 has a region in contact with the top surface and side surfaces of the conductive layer 312a and the top surface of the substrate 102. The surface on which the conductive layer 312a is to be formed (here, the top surface of the substrate 102), the surface on which the conductive layer 212a is to be formed (here, the top surface of the insulating layer 120), and the surface on which the conductive layer 112a is to be formed (here, the top surface of the insulating layer 107) are different from each other. Furthermore, the conductive layer 312a, the conductive layer 212a, and the conductive layer 112a can be formed in different processes. By forming the conductive layer 312a, the conductive layer 212a, and the conductive layer 112a in different processes, the distance between the conductive layer 112a and the conductive layer 212a, the distance between the conductive layer 112a and the conductive layer 312a, and the distance between the conductive layer 212a and the conductive layer 312a can be reduced. Furthermore, a structure can be achieved in which two or more of the conductive layer 112a, the conductive layer 212a, and the conductive layer 312a overlap with each other. This allows the area occupied by the semiconductor device to be further reduced.

[0360] Note that the configuration of the transistor 300 and the insulating layer 120 described in Structural Example 8 can also be applied to other structural examples.

[0361] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0362] 26A to 30B , a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and formation methods of elements, descriptions of parts similar to those described in Embodiment 1 may be omitted.

[0363] Thin films (e.g., insulating films and conductive films) constituting semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, or the like. CVD methods include a PECVD method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0364] Thin films (e.g., insulating films and conductive films) that constitute semiconductor devices can be formed by wet film-forming methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0365] When processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film can be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film can be directly formed by a film formation method using a shielding mask such as a metal mask.

[0366] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0367] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0368] The thin film can be etched by one or more of dry etching, wet etching, and sandblasting.

[0369] Here, an example of a method for manufacturing the semiconductor device 10A shown in Fig. 6A to Fig. 6C will be described with reference to Fig. 26A to Fig. 30B, which show cross-sectional views taken along dashed line A1-A2 shown in Fig. 6A.

[0370] First, a conductive film is formed over the substrate 102 and then processed to form the conductive layer 212a. The conductive film can be preferably formed by a sputtering method.

[0371] Subsequently, an insulating film 107f to be the insulating layer 107 is formed over the conductive layer 212a and the substrate 102 (FIG. 26A). The insulating film 107f can be preferably formed by sputtering or PECVD.

[0372] Subsequently, a conductive layer 112a is formed on the insulating film 107f (FIG. 26B).

[0373] Subsequently, an insulating film 110af to be the insulating layer 110a is formed over the conductive layer 112a and the insulating film 107f (FIG. 26C). The insulating film 110af can be preferably formed by sputtering or PECVD.

[0374] Next, a conductive layer 103A is formed on the insulating film 110af (FIG. 26D). The conductive film that becomes the conductive layer 103A can be preferably formed by sputtering or PECVD. The conductive layer 103A will later become the conductive layer 103.

[0375] Next, a layer 105A is formed on the surface of the conductive layer 103A (FIG. 26E). For example, the conductive layer 103A can be subjected to oxidation treatment or nitridation treatment to form the layer 105A on the top surface and side surfaces of the conductive layer 103A. Plasma treatment can be suitably used for the oxidation treatment or nitridation treatment.

[0376] Next, an insulating film 110bf, which will become the insulating layer 110b, is formed on the layer 105A and the insulating film 110af (FIG. 26F). The insulating film 110bf can be preferably formed by sputtering or PECVD.

[0377] When a PECVD apparatus is used to form the insulating film 110bf, the layer 105A can be formed in the PECVD apparatus. For example, after forming the conductive layer 103A, a plasma treatment can be performed in the PECVD apparatus to form the layer 105A on the surface of the conductive layer 103A, and the insulating film 110bf can be formed continuously. For example, the plasma treatment can be performed using a N ２ O plasma treatment can be used. By using the same equipment for forming the layer 105A and the insulating film 110bf, productivity can be improved.

[0378] The substrate temperature during the formation of the insulating films 110af and 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature within the above-described range during the formation of the insulating films 110af and 110bf, the amount of impurities (e.g., water and hydrogen) released from the insulating films can be reduced, and the diffusion of impurities into the semiconductor layer 108 and the semiconductor layer 208 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0379] Since the insulating films 110af and 110bf are formed before the semiconductor layers 108 and 208, there is no need to worry about oxygen being desorbed from the semiconductor layers 108 and 208 due to the heat applied during the formation of the insulating films 110af and 110bf.

[0380] After the insulating films 110af and 110bf are formed, heat treatment can be performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110af and the insulating films 110bf and from their surfaces.

[0381] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. For example, ion implantation or plasma treatment can be used as a method for supplying oxygen. Oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied by ion implantation or plasma treatment to the insulating film 110bf. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of apparatus that convert gas into plasma using high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The ion implantation or plasma treatment is preferably performed in an atmosphere containing oxygen. For example, the atmosphere can be oxygen (O ２ ), nitrous oxide (N ２O), nitrogen dioxide (NO ２ An atmosphere containing one or more of carbon monoxide, carbon dioxide, and / or nitric acid can be preferably used. Alternatively, oxygen can be supplied by generating oxygen plasma by irradiating high-frequency electromagnetic waves in an oxygen-containing atmosphere. For example, oxygen can be supplied by performing microwave treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating film 110bf through a film that suppresses oxygen desorption formed on the insulating film 110bf. The film is preferably removed after oxygen is supplied. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0382] In this specification, microwaves refer to electromagnetic waves with a frequency of 300 MHz or more and 300 GHz or less. A typical example of microwaves is electromagnetic waves with a frequency of 2.45 GHz. Microwave processing refers to processing using a device with a power source that generates high-density plasma using microwaves. Microwave processing can also be called microwave-excited high-density plasma processing.

[0383] After the insulating film 110bf is formed, oxygen can be supplied by performing a plasma treatment without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, N ２ O plasma treatment can be performed.

[0384] A film 137 is preferably formed over the insulating film 110bf (FIG. 27A). The film 137 preferably contains oxygen. By forming the film 137, oxygen can be supplied to the insulating film 110bf.

[0385] The conductivity of the film 137 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 137. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 137.

[0386] The film 137 is preferably made of an oxide material containing one or more of the same elements as those of the semiconductor layers 108 and 208. In particular, it is preferable to use a metal oxide applicable to the semiconductor layers 108 and 208. Furthermore, by using the same material as those of the semiconductor layers 108 and 208 for the film 137, a common device can be used to form the film 137 and the films that will become the semiconductor layers 108 and 208, thereby increasing productivity and reducing manufacturing costs.

[0387] When forming the film 137, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the oxygen flow rate of the film formation gas introduced into the treatment chamber of the film formation apparatus or the oxygen partial pressure in the treatment chamber. The oxygen flow rate or oxygen partial pressure is, for example, 50% to 100%, preferably 65% ​​to 100%, more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate to 100% and the oxygen partial pressure as close to 100% as possible.

[0388] By forming the film 137 in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf during the formation of the film 137, and oxygen can be prevented from being released from the insulating film 110bf. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 and the semiconductor layer 208 by subsequent heat treatment. As a result, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0389] Heat treatment can be performed after the film 137 is formed. By performing heat treatment after the film 137 is formed, oxygen can be effectively supplied from the film 137 to the insulating film 110bf.

[0390] The temperature of the heat treatment is preferably 150° C. or higher, 200° C. or higher, 230° C. or higher, or 250° C. or higher, but lower than the strain point of the substrate, i.e., 450° C. or lower, 400° C. or lower, 350° C. or lower, or 300° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere with as low a content of hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being taken into the insulating films 110af and 110bf as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) apparatus, or the like. By using an RTA device, the heat treatment time can be shortened.

[0391] After the film 137 is formed or after the above-described heat treatment, oxygen can be further supplied to the insulating film 110bf through the film 137. The above description can be referred to for the method of supplying oxygen, and therefore detailed description thereof will be omitted.

[0392] Next, the film 137 is removed. There is no particular limitation on the method for removing the film 137, but wet etching can be suitably used. By using wet etching, etching of the insulating film 110bf can be suppressed when removing the film 137. This can suppress the thickness of the insulating film 110bf from becoming thin, and can make the thickness of the insulating layer 110b uniform.

[0393] After removing the film 137, oxygen can be further supplied to the insulating film 110bf. The above description can be referred to for the method of supplying oxygen. For example, as shown in FIG. 27B , a film 139 can be formed on the insulating film 110bf, and oxygen can be supplied to the insulating film 110bf through the film 139. For this treatment, plasma treatment in an atmosphere containing oxygen can be used. In FIG. 27B , arrows are used to schematically show how oxygen is supplied to the insulating film 110bf.

[0394] A conductive film or a semiconductor film is preferably used as the film 139. A metal oxide, a metal, or an alloy can be used for the film 139. When a metal oxide is used for the film 139 and the film 139 is formed by a sputtering method or the like in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf even during the formation of the film 139.

[0395] Because oxygen is supplied to the insulating film 110bf through the film 139, the thickness of the film 139 is preferably small. Specifically, the thickness of the film 139 is preferably 1 nm to 20 nm, more preferably 2 nm to 15 nm, and even more preferably 3 nm to 10 nm. Typically, the thickness can be about 5 nm.

[0396] The substrate temperature during the formation of the film 139 is preferably 350° C. or less, more preferably 340° C. or less, further preferably 330° C. or less, and further preferably 300° C. or less, thereby increasing the amount of oxygen supplied to the insulating film 110bf.

[0397] By providing the film 139, when a bias voltage is applied between the pair of electrodes when oxygen is supplied, the film 139 tends to attract ionized oxygen, thereby increasing the amount of oxygen supplied to the insulating film 110bf.

[0398] A dry etching apparatus, an ashing apparatus, or a PECVD apparatus can be suitably used as the processing apparatus for supplying oxygen. In particular, it is preferable to use an ashing apparatus. When a bias voltage is applied between a pair of electrodes of the processing apparatus, the bias voltage can be set to, for example, 10 V or more and 1 kV or less. Alternatively, the bias power density can be set to, for example, 1 W / cm.２ More than 5W / cm ２ It can be as follows:

[0399] Next, the film 139 is removed (FIG. 27C). The film 139 can be preferably removed by wet etching.

[0400] By supplying oxygen to the insulating film 110bf that becomes the insulating layer 110b, the amount of oxygen contained in the insulating layer 110b increases, and the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 and the semiconductor layer 208 can be increased, so that even a transistor with a short channel length can exhibit good electrical characteristics.

[0401] Next, an insulating film 110cf, which will become the insulating layer 110c, is formed on the insulating film 110bf (FIG. 27D). The description of the formation of the insulating film 110cf can be referred to, and therefore a detailed description thereof will be omitted.

[0402] Next, a conductive film 112f to be the conductive layer 112b and the conductive layer 212b is formed over the insulating film 110cf (FIG. 27E). The conductive film 112f can be preferably formed by sputtering.

[0403] Next, the conductive film 112f is processed to form a conductive layer 112B and a conductive layer 212B ( FIG. 28A ). The conductive layer 112B has a region overlapping with the conductive layer 112a and will later become the conductive layer 112b. The conductive layer 212B has a region overlapping with the conductive layer 212a and will later become the conductive layer 212b. The conductive layer 112B and the conductive layer 212B can be formed by either or both of a dry etching method and a wet etching method.

[0404] Next, the conductive layer 112B, the insulating film 110cf, the insulating film 110bf, the layer 105A, and the conductive layer 103A are partially removed to form the conductive layer 112b having the opening 143, and the insulating layer 110C, the insulating layer 110B, the layer 105, and the conductive layer 103 having the opening 141A ( FIG. 28B ). The formation of the opening 141A exposes the insulating film 110af. The opening 143 and the opening 141A are provided in a region overlapping with the conductive layer 112a. Note that a portion of the insulating film 110af overlapping with the opening 141A may be removed, resulting in a thinner insulating film 110af in that region. The conductive layer 112b can be formed by, for example, wet etching. The insulating layer 110C, the insulating layer 110B, the layer 105, and the conductive layer 103 can be formed by, for example, dry etching.

[0405] By using the same resist mask for forming the opening 141A and the opening 143, productivity can be improved. Furthermore, the top surface shapes of the opening 141A and the opening 143 can be made to match or approximately match. Note that different resist masks can also be used for forming the opening 141A and the opening 143.

[0406] Next, the layer 105 is formed on the side surface of the conductive layer 103 on the opening 141A side (FIG. 28C). The above description can be referred to for the formation of the layer 105.

[0407] Subsequently, an insulating film 116f that will become the insulating layer 116 is formed so as to cover the openings 143 and 141A (FIG. 28D). The insulating film 116f can be preferably formed by sputtering or PECVD.

[0408] When a PECVD apparatus is used to form the insulating film 116f, the layer 105 can be formed in the PECVD apparatus. For example, after forming the opening 141A, a plasma treatment is performed in the PECVD apparatus to form the layer 105 on the side surface of the conductive layer 103 on the opening 141A side, and the insulating film 116f can be formed continuously. For example, the plasma treatment can be performed using a N ２O plasma treatment can be used. By using the same equipment for forming the layer 105 and the insulating film 116f, productivity can be improved.

[0409] Next, a portion of the insulating film 116f is removed to form the insulating layer 116 ( FIG. 29A ). By forming the insulating layer 116, the conductive layer 112a, the conductive layer 112b, and the conductive layer 212B are exposed. At this time, the insulating film 116f and the insulating film 110af are removed from the region provided along the upper surface of the conductive layer 112a in the opening 141A, thereby forming the opening 141. For example, a dry etching method can be suitably used to form the insulating layer 116. In particular, an anisotropic etching method is preferably used to form the insulating layer 116.

[0410] Note that when or after forming the opening 141, a part of the conductive layer 112a overlapping with the opening 141 can be removed. As a result, the thickness of the region of the conductive layer 112a in contact with the bottom surface of the semiconductor layer 108 becomes thinner than the thickness of the region not in contact with the semiconductor layer 108. This makes it possible to strengthen the electric field of the gate electrode applied to the channel formation region near the conductive layer 112a, thereby increasing the on-state current of the transistor.

[0411] Next, the conductive layer 212B, the insulating layer 110C, the insulating layer 110B, the insulating layer 110A, and the insulating layer 107f are partially removed to form the conductive layer 212b having an opening 243, and the insulating layer 110c, the insulating layer 110b, the insulating layer 110a, and the insulating layer 107 having an opening 241 ( FIG. 29B ). The opening 243 and the opening 241 are provided in a region overlapping the conductive layer 212a. The formation of the opening 243 and the opening 241 exposes the conductive layer 212a. The conductive layer 212b can be preferably formed by, for example, wet etching. The insulating layer 110c, the insulating layer 110b, the insulating layer 110a, and the insulating layer 107 can be preferably formed by, for example, dry etching.

[0412] By using the same resist mask for forming the openings 241 and 243, productivity can be improved. Furthermore, the top surface shapes of the openings 241 and 243 can be made to match or approximately match. Note that different resist masks can also be used for forming the openings 241 and 243.

[0413] Note that when or after forming the opening 241, a part of the conductive layer 212a in a region overlapping with the opening 241 can be removed. As a result, the thickness of the region of the conductive layer 212a in contact with the bottom surface of the semiconductor layer 208 becomes thinner than the thickness of the region not in contact with the semiconductor layer 208. This makes it possible to strengthen the electric field of the gate electrode applied to the channel formation region in the vicinity of the conductive layer 212a, and increase the on-current of the transistor.

[0414] Subsequently, a film 108f to be the semiconductor layer 108 and the semiconductor layer 208 is formed so as to cover the openings 141, 143, 241, and 243 ( FIG. 29C ). The film 108f is provided in contact with the top surface and side surfaces of the insulating layer 110, the top surface and side surfaces of the insulating layer 116, the top surface of the conductive layer 112a, the top surface and side surfaces of the conductive layer 112b, the top surface of the conductive layer 212a, and the top surface and side surfaces of the conductive layer 212b.

[0415] The film 108f is preferably formed by a sputtering method using a metal oxide target. Alternatively, the film 108f is preferably formed by an ALD method. Because the ALD method has high coverage, it can be suitably used to form the film 108f that covers the openings 141, 143, 241, and 243. By using the ALD method, the film 108f can be formed with high coverage on the side surfaces of the insulating layer 110 and the top and side surfaces of the insulating layer 116. Furthermore, the ALD method makes it easy to control the film formation rate, so a thin film can be formed with a high yield. Therefore, the ALD method can be suitably used when the film 108f is thin. Thermal ALD or PEALD can be used as the ALD method. PECVD can also be used to form the film 108f. When a metal oxide is used for the film 108f, the film 108f can be referred to as a metal oxide film.

[0416] The film 108f is preferably a dense film with as few defects as possible. Furthermore, the film 108f is preferably a high-purity film in which impurities including hydrogen elements are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the film 108f.

[0417] When the metal oxide film is formed, oxygen gas is preferably used. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110 and the insulating layer 116. For example, when an oxide or an oxynitride is used for the insulating layer 110b and the insulating layer 116, oxygen can be suitably supplied to the insulating layer 110b and the insulating layer 116.

[0418] By supplying oxygen to the insulating layer 116, oxygen can be supplied from the insulating layer 116 to the semiconductor layer 108 in a later step. By supplying oxygen to the insulating layer 110b, oxygen can be supplied from the insulating layer 110b to the semiconductor layer 208 and from the insulating layer 110b to the semiconductor layer 108 via the insulating layer 116. As a result, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0419] A mixture of oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used to form a metal oxide film. Note that the higher the oxygen flow rate or oxygen partial pressure when forming the metal oxide film, the higher the crystallinity of the metal oxide film, resulting in a highly reliable transistor. On the other hand, the lower the oxygen flow rate or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, resulting in a transistor with a large on-state current.

[0420] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may become polycrystalline. In the case of a polycrystalline metal oxide film, the grain boundaries become recombination centers, and carriers are captured, which may reduce the on-current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the metal oxide film does not become polycrystalline. Since the ease with which the metal oxide film becomes polycrystalline varies depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure depending on the composition of the metal oxide film.

[0421] The higher the substrate temperature during formation of the metal oxide film, the higher the crystallinity and density of the metal oxide film, which leads to a highly reliable transistor. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film, which leads to a transistor with a large on-state current.

[0422] The substrate temperature during the formation of the metal oxide film is preferably from room temperature to 250° C., more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to 140° C. is preferable because it increases productivity. Furthermore, by forming the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0423] If the substrate temperature is too high, the metal oxide film may have a polycrystalline structure, so it is preferable to vary the substrate temperature depending on the composition of the material used for the metal oxide film.

[0424] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0425] For example, when forming an In—Ga—Zn oxide, three precursors, namely, a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, namely, a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0426] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]-indium.

[0427] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0428] Precursors containing aluminum include, for example, aluminum chloride and trimethylaluminum.

[0429] Tin-containing precursors include, for example, tin(IV) chloride and tetrakis(dimethylamido)tin.

[0430] Precursors containing zinc include, for example, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0431] Oxidizing agents include, for example, ozone, oxygen, and water.

[0432] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the flow time of the source gases, and the order in which the source gases are flowed. By adjusting these, the composition of the metal oxide film can be controlled. Furthermore, by adjusting these, it is also possible to form a metal oxide film whose composition changes continuously.

[0433] Before forming the metal oxide film, it is preferable to perform at least one of a treatment for removing impurities (e.g., water, hydrogen, and organic substances) adsorbed on the surfaces of the insulating layer 110 and the insulating layer 116 and a treatment for supplying oxygen into the insulating layer 110 and the insulating layer 116. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layer 110 and the insulating layer 116. By performing plasma treatment containing nitrous oxide gas, oxygen can be supplied while suitably removing organic substances from the surfaces of the insulating layer 110 and the insulating layer 116. After such treatment, it is preferable to form a metal oxide film in succession without exposing the surfaces of the insulating layer 110 and the insulating layer 116 to the air.

[0434] When the semiconductor layer 108 and the semiconductor layer 208 have a stacked structure, it is preferable to form a metal oxide film first and then form a subsequent metal oxide film without exposing the surface of the first metal oxide film to the air.

[0435] When the semiconductor layer 108 and the semiconductor layer 208 each have a stacked structure, all of the layers constituting the semiconductor layer 108 and the semiconductor layer 208 can be formed by the same film formation method (for example, sputtering or ALD). Alternatively, different film formation methods can be used for each layer. For example, when the semiconductor layer 108 and the semiconductor layer 208 each have a two-layer structure of a first metal oxide layer and a second metal oxide layer on the first metal oxide layer, the first metal oxide layer can be formed by sputtering, and the second metal oxide layer can be formed by ALD.

[0436] Subsequently, the film 108f is processed into an island shape to form the semiconductor layer 108 and the semiconductor layer 208 (FIG. 29D).

[0437] The semiconductor layer 108 and the semiconductor layer 208 can be preferably formed by wet etching. At this time, a part of the conductive layer 112b and a part of the conductive layer 212b in a region that does not overlap with either the semiconductor layer 108 or the semiconductor layer 208 may be etched and thinned. Furthermore, a part of the insulating layer 110 in a region that does not overlap with either the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112b, or the conductive layer 212b may be etched and thinned. For example, in a region of the insulating layer 110 that does not overlap with either the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112b, or the conductive layer 212b, a part of the insulating layer 110c may be removed by etching, forming a recess in the insulating layer 110c. Note that, in etching the film 108f, using a material with a high selectivity for the insulating layer 110c can prevent the insulating layer 110c from becoming thin.

[0438] Heat treatment is preferably performed after the film 108f is formed or after the film 108f is processed into the semiconductor layer 108 and the semiconductor layer 208. The heat treatment can remove impurities (e.g., hydrogen and water) contained in or adsorbed to the surface of the film 108f or the semiconductor layer 108 and the semiconductor layer 208. Furthermore, the heat treatment may improve the film quality of the film 108f or the semiconductor layer 108 and the semiconductor layer 208 (e.g., reduce defects or improve crystallinity).

[0439] By the heat treatment, oxygen can also be supplied from the insulating layer 110b and the insulating layer 116 to the film 108f or the semiconductor layer 108 and the semiconductor layer 208. In this case, it is more preferable to perform the heat treatment before processing into the semiconductor layer 108 and the semiconductor layer 208. The above description can be referred to for the heat treatment, and therefore detailed description thereof will be omitted.

[0440] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, a later step in which heat is applied (e.g., a film formation step) may also serve as this heat treatment.

[0441] After the film 108f is formed or after the film 108f is processed into the semiconductor layer 108 and the semiconductor layer 208, oxygen can be supplied to the film 108f or the semiconductor layer 108 and the semiconductor layer 208. As a result, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. The above description can be referred to for the oxygen supply method. For example, microwave treatment can be performed in an oxygen-containing atmosphere. Furthermore, by supplying oxygen while heating the substrate, the crystallinity of the film 108f or the semiconductor layer 108 and the semiconductor layer 208 can be improved, and impurities (e.g., hydrogen and water) contained in or adsorbed on the surface of the film 108f or the semiconductor layer 108 and the semiconductor layer 208 can be removed. The substrate temperature during heating is preferably higher than room temperature (e.g., 25°C) and not higher than 600°C, more preferably 100°C to 600°C, and even more preferably 300°C to 450°C. The substrate temperature is preferably 100°C to 700°C, and even more preferably 300°C to 450°C. This can further improve the crystallinity of the film 108f or the semiconductor layer 108 and the semiconductor layer 208. When the substrate temperature increases with the oxygen supply treatment, the treatment may improve the crystallinity and remove impurities.

[0442] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112b, the conductive layer 212b, and the insulating layer 110 (FIG. 30A). The insulating layer 106 can be formed by, for example, a PECVD method, a sputtering method, or an ALD method.

[0443] When an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 208, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 106 suppresses oxygen diffusion, thereby suppressing oxygen desorption from the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies (V ＯIn addition, oxygen contained in the semiconductor layer 108 and the semiconductor layer 208 is prevented from diffusing into the conductive layer 104 and the conductive layer 204 through the insulating layer 106, thereby preventing the conductive layer 104 and the conductive layer 204 from being oxidized. As a result, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0444] By increasing the temperature during the formation of the insulating layer 106 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during the formation of the insulating layer 106 is high, oxygen is released from the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies (V Ｏ ) and V Ｏ H may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108 and the semiconductor layer 208. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0445] Before forming the insulating layer 106, plasma treatment can be performed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. The plasma treatment can reduce impurities such as water adsorbed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. Therefore, impurities at the interfaces between the semiconductor layer 108 and the insulating layer 106 and the semiconductor layer 208 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the air between the formation of the semiconductor layer 108 and the semiconductor layer 208 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere containing oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. Furthermore, the plasma treatment and the formation of the insulating layer 106 are preferably performed successively without exposure to the air.

[0446] After the insulating layer 106 is formed, oxygen can be supplied to the insulating layer 106. The above description can be referred to for the method of supplying oxygen. For example, microwave treatment can be performed in an atmosphere containing oxygen. The oxygen supplied to the insulating layer 106 is further supplied to the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained. Furthermore, by supplying oxygen while heating the substrate, impurities (e.g., hydrogen and water) contained in or adsorbed on the surface of the insulating layer 106 can be removed, and defects in the insulating layer 106 can also be reduced. By reducing defects in the insulating layer 106 that functions as a gate insulating layer of the transistor, a transistor exhibiting good electrical characteristics can be obtained. For the substrate temperature during heating, the description of the heat treatment described above can be referred to. Note that when the substrate temperature increases due to the treatment of supplying oxygen, the treatment can sometimes remove impurities and reduce defects.

[0447] Subsequently, a conductive film is formed over the insulating layer 106 and processed to form the conductive layers 104 and 204 ( FIG. 30B ). The conductive film can be formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.

[0448] Subsequently, an insulating layer 195 is formed (FIG. 6B). The insulating layer 195 can be preferably formed by PECVD.

[0449] Through the above steps, the semiconductor device 10A of one embodiment of the present invention can be manufactured.

[0450] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS. 31A to 60F.

[0451] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit for electronic devices having relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0452] The display device of the present embodiment can be a high-definition display device, and therefore can be used, for example, as a display unit of a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit of a wearable device that can be worn on the head, such as a VR device such as a head-mounted display (HMD) or an AR device such as a glasses-type device.

[0453] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0454] The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0455] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0456] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0457] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel has a configuration in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element (also called a display device) and an opposing substrate.

[0458] <Configuration Example 1 of Display Device> FIG. 31A shows a perspective view of a display device 50A.

[0459] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 31A, the substrate 152 is indicated by a dashed line.

[0460] The display device 50A includes a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, and the like. Fig. 31A shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 31A can also be said to be a display module including the display device 50A, an IC, and an FPC. Note that the number of ICs and FPCs mounted on the display device is not particularly limited, and a configuration in which multiple ICs and FPCs are mounted can be used.

[0461] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 31A shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 electrically connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0462] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0463] The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside through the FPC 172 or are input to the conductive layer 165 from the IC 173.

[0464] 31A shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like. The IC 173 may be, for example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit. The display device 50A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method, or the like.

[0465] The semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 162 and the circuit portion 164 of the display device 50A, for example.

[0466] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0467] The display section 162 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 210. Fig. 31A shows an enlarged view of one pixel 210.

[0468] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0469] The pixel 210 shown in FIG. 31A includes a pixel 230R that emits red light, a pixel 230G that emits green light, and a pixel 230B that emits blue light. A full-color display can be achieved by configuring one pixel 210 with the pixels 230R, 230G, and 230B. The pixels 230R, 230G, and 230B each function as subpixels. The display device 50A shown in FIG. 31A also illustrates an example in which the pixels 230 functioning as subpixels are arranged in a stripe array. The number of subpixels constituting one pixel 210 is not limited to three and may be four or more. For example, the pixel 210 may have four subpixels that emit R, G, B, and white (W) light. Alternatively, the pixel 210 may have four subpixels that emit R, G, B, and Y light.

[0470] Each of the pixel 230R, the pixel 230G, and the pixel 230B includes a display element and a circuit that controls the driving of the display element.

[0471] Various elements can be used as the display element, including, for example, a liquid crystal element (also called a liquid crystal device) and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements using microcapsules, electrophoresis, electrowetting, or electronic liquid powder (registered trademark) methods, etc. Furthermore, a QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot materials may also be used.

[0472] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0473] Examples of modes that can be used in display devices using liquid crystal elements include vertical alignment (VA) mode, Fringe Field Switching (FFS) mode, In-Plane-Switching (IPS) mode, Twisted Nematic (TN) mode, Axially Symmetric Aligned Micro-cell (ASM) mode, Optically Compensated Birefringence (OCB) mode, Ferroelectric Liquid Crystal (FLC) mode, Anti-Ferroelectric Liquid Crystal (AFLC) mode, and Electrically Compensated Birefringence (ECB) mode. Examples of the VA mode include a Multi-Domain Vertical Alignment (MVA) mode, a Patterned Vertical Alignment (PVA) mode, and an Advanced Super View (ASV) mode.

[0474] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, and the like, depending on the conditions. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material, and the type can be selected depending on the mode or design to be applied.

[0475] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0476] Examples of light-emitting substances that the light-emitting element has include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials), and inorganic compounds (quantum dot materials, etc.).

[0477] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0478] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0479] Note that the display device of one embodiment of the present invention may be any of a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type that emits light toward a substrate on which a light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0480] 31B is a block diagram illustrating a display device 50A. The display device 50A has a display unit 162 and a circuit unit 164. The d...

Claims

a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer; the first transistor has a first conductive layer, a second conductive layer, a first semiconductor layer, a gate insulating layer, and a first gate electrode; the second transistor has a third conductive layer, a fourth conductive layer, a second semiconductor layer, the gate insulating layer, and a second gate electrode; the first insulating layer overlies the third conductive layer; the first conductive layer is located on the first insulating layer; the second insulating layer overlies the first conductive layer and the first insulating layer; the third insulating layer is located on the second insulating layer; the second conductive layer and the fourth conductive layer are located on the third insulating layer; the second conductive layer, the third insulating layer, and the second insulating layer have a first opening reaching the first conductive layer; the first semiconductor layer has a region in contact with an upper surface of the first conductive layer, a side surface of the second insulating layer, a side surface of the third insulating layer, and a side surface of the second conductive layer in the first opening; the fourth conductive layer, the third insulating layer, the second insulating layer and the first insulating layer have a second opening reaching the third conductive layer; the second semiconductor layer has a region in contact with a top surface of the third conductive layer, a side surface of the first insulating layer, a side surface of the second insulating layer, a side surface of the third insulating layer, and a side surface of the fourth conductive layer in the second opening; the gate insulating layer is located on the first semiconductor layer and the second semiconductor layer; the first semiconductor layer has a region overlapping with the first gate electrode through the gate insulating layer in the first opening; the second semiconductor layer has a region that overlaps with the second gate electrode through the gate insulating layer in the second opening. 　 a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer; the first transistor has a first conductive layer, a second conductive layer, a first semiconductor layer, a first gate insulating layer, a first gate electrode, a second gate insulating layer, and a second gate electrode; the second transistor has a third conductive layer, a fourth conductive layer, a second semiconductor layer, the first gate insulating layer, and a third gate electrode; the first insulating layer overlies the third conductive layer; the first conductive layer is located on the first insulating layer; the second insulating layer overlies the first conductive layer and the first insulating layer; the second gate electrode is located on the second insulating layer; the third insulating layer is located on the second gate electrode and the second insulating layer; the second conductive layer and the fourth conductive layer are located on the third insulating layer; the second conductive layer, the third insulating layer, the second gate electrode, and the second insulating layer have a first opening reaching the first conductive layer; the second gate insulating layer is provided along a sidewall of the first opening, the first semiconductor layer has a region in contact with an upper surface of the first conductive layer, an upper surface and a side surface of the second gate insulating layer, and a side surface of the second conductive layer in the first opening; the fourth conductive layer, the third insulating layer, the second insulating layer and the first insulating layer have a second opening reaching the third conductive layer; the second semiconductor layer has a region in contact with a top surface of the third conductive layer, a side surface of the first insulating layer, a side surface of the second insulating layer, a side surface of the third insulating layer, and a side surface of the fourth conductive layer in the second opening; the first gate insulating layer is located on the first semiconductor layer and the second semiconductor layer; the first semiconductor layer has, in the first opening, a region overlapping with the first gate electrode via the first gate insulating layer and a region overlapping with the second gate electrode via the second gate insulating layer; the second semiconductor layer has a region that overlaps with the third gate electrode through the first gate insulating layer in the second opening. 　 In claim 2, the second insulating layer has a portion located between the second gate insulating layer and the first conductive layer. 　 In claim 2 or 3, the second transistor having a layer; the layer contacts an upper surface and a side surface of the second gate electrode; the layer includes the element contained in the second gate electrode and oxygen. In claim 2 or 3, the second transistor having a layer; the layer contacts an upper surface and a side surface of the second gate electrode; the second gate electrode comprises aluminum; The layer comprises aluminum and oxygen. 　 In any one of claims 1 to 3, The first conductive layer has a region overlapping with the third conductive layer. 　 In any one of claims 1 to 3, the first semiconductor layer and the second semiconductor layer each include a metal oxide; The first insulating layer has a region having a higher hydrogen concentration than the second insulating layer. 　 In any one of claims 1 to 3, the first semiconductor layer and the second semiconductor layer each include a metal oxide; the first insulating layer comprises silicon, nitrogen, and hydrogen; the second insulating layer comprises silicon and nitrogen; The third insulating layer comprises silicon and oxygen. 　 In claim 8, A fourth insulating layer is provided. the fourth insulating layer is located between the second conductive layer, the fourth conductive layer, and the third insulating layer; The fourth insulating layer comprises silicon and nitrogen. 　 In claim 8, A fourth insulating layer is provided. the fourth insulating layer is located between the second conductive layer, the fourth conductive layer, and the third insulating layer; The fourth insulating layer comprises one or both of aluminum and hafnium, and oxygen.

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