Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device having small-size transistors. This semiconductor device includes: first and second transistors; and first and second insulating layers. The two transistors are both vertical transistors, and the second transistor is provided so as to be superimposed on the first transistor. The following are provided in order given and have overlapping regions: one (first conductive layer) of a source electrode and a drain electrode of the first transistor; the first insulating layer; and the other (second conductive layer) of the source electrode and the drain electrode of the first transistor. An opening reaching the first conductive layer is provided in the second conductive layer and the first insulating layer. A semiconductor layer, a gate insulating layer, and a gate electrode are provided in that order and in contact with a lateral wall and the bottom surface of the opening. The second insulating layer is provided so that a recess of the gate electrode of the first transistor is embedded in the second insulating layer. One of a source electrode and a drain electrode of the second transistor is provided in contact with the top of the gate electrode.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a transistor, a semiconductor device, a display device, a display module, and an electronic device. 1. Field of the Invention One embodiment of the present invention relates to a method for manufacturing a transistor, a method for manufacturing a semiconductor device, and a method for manufacturing a display device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), an electronic device including any of these devices, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices having transistors are widely used in display devices and electronic devices, and there is a demand for semiconductor devices with higher integration and faster speeds. For example, when semiconductor devices are applied to high-resolution display devices, semiconductor devices with higher integration levels are required. As one means for increasing the integration level of transistors, development of fine-sized transistors is underway.

[0005] In recent years, there has been a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). Display devices for XR are desired to have high resolution and high color reproducibility in order to enhance the sense of realism and immersion. Examples of display devices applicable to such devices include liquid crystal display devices, organic electroluminescence (EL) devices, and light-emitting devices including light-emitting devices (also referred to as light-emitting elements) such as light-emitting diodes (LEDs).

[0006] Patent Document 1 discloses a display device for VR that uses an organic EL device (also called an organic EL element).

[0007] International Publication No. 2018 / 087625

[0008] An object of one embodiment of the present invention is to provide a semiconductor device including a micro-sized transistor and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a small-sized semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a manufacturing method of a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a novel semiconductor device and a manufacturing method thereof.

[0009] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0010] To further increase the integration density of semiconductor devices, it is effective to miniaturize transistors included in the semiconductor device and to devise a layout for the transistors. For example, it is effective to arrange multiple transistors included in a semiconductor device by stacking them vertically with respect to a substrate surface rather than arranging them on the same plane. This allows for increased integration of semiconductor devices without increasing the area occupied by the transistors within the substrate surface. On the other hand, when transistors are stacked, if the top surface of a lower transistor has large irregularities, the surface on which the transistor to be formed thereon is formed also has irregularities, making it difficult to form fine transistors by stacking them. Therefore, it is preferable that the surface on which the transistor is formed is as flat as possible. Therefore, one embodiment of the present invention provides a semiconductor device including transistors whose top surface irregularities are planarized by an insulating layer, and a manufacturing method thereof.

[0011] One embodiment of the present invention provides a transistor including a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer. The first transistor includes a first semiconductor layer, a first conductive layer, a second conductive layer, a gate insulating layer, and a gate electrode. The second transistor includes a second semiconductor layer, a third conductive layer, and a fourth conductive layer. The first insulating layer is provided over the first conductive layer, and the second conductive layer is provided over the first insulating layer. The first insulating layer and the second conductive layer each have a first opening reaching the first conductive layer. In the first opening, the first semiconductor layer is provided in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer. a gate electrode is provided in contact with the upper surface of the gate insulating layer so as to have a region overlapping with the first opening; a second insulating layer is provided on the gate electrode so as to fill the first opening; a third conductive layer is provided in contact with the second insulating layer and the gate electrode; the third insulating layer is provided on the third conductive layer; a fourth conductive layer is provided on the third insulating layer; the third insulating layer and the fourth conductive layer each have a second opening reaching the third conductive layer; within the second opening, the second semiconductor layer is provided in contact with the upper surface of the third conductive layer, a side surface of the third insulating layer, and a side surface of the fourth conductive layer; and the second insulating layer is made of an organic insulating material.

[0012] In the above, it is preferable that a fourth insulating layer is provided in an area on the gate insulating layer that does not overlap with the first opening, the third insulating layer is provided on the fourth insulating layer, and the fourth insulating layer has the same material as the second insulating layer.

[0013] In addition, in the above, it is preferable that the second insulating layer contains one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of these resins.

[0014] In the above, it is preferable that the first transistor has a back gate electrode, and that the back gate electrode is provided between the first conductive layer and the second conductive layer so as to have an area overlapping with each of the first conductive layer and the second conductive layer, and that in the first opening, one surface of the first semiconductor layer faces the gate electrode and the other surface of the first semiconductor layer faces the back gate electrode.

[0015] In the above, it is preferable that at least one of the first semiconductor layer and the second semiconductor layer contains a metal oxide, the metal oxide contains two or three selected from indium, an element M, and zinc, the element M contains one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium, and that at least one of the first insulating layer and the third insulating layer contains silicon oxide or silicon oxynitride.

[0016] Furthermore, in the above, it is preferable that the first insulating layer has a fifth insulating layer, a sixth insulating layer on the fifth insulating layer, and a seventh insulating layer on the sixth insulating layer, the third insulating layer has an eighth insulating layer, a ninth insulating layer on the eighth insulating layer, and a tenth insulating layer on the ninth insulating layer, and that the fifth insulating layer, the seventh insulating layer, the eighth insulating layer, and the tenth insulating layer each have silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and that the sixth insulating layer and the ninth insulating layer each have silicon oxide or silicon oxynitride.

[0017] Another embodiment of the present invention includes forming a first conductive layer, a first insulating film, and the first conductive film in this order; removing portions of the first insulating film and the first conductive film to form a first opening reaching the first conductive layer; forming the first insulating layer and a second conductive layer; forming a first semiconductor layer in contact with a side surface of the second conductive layer, a side surface of the first insulating layer, and an upper surface of the first conductive layer in the first opening; forming a second insulating layer and a second conductive film in this order to contact the upper surface of the first semiconductor layer; forming a second insulating film on the second conductive film to fill the first opening; removing a portion of the second insulating film to form a third insulating layer filled in the first opening; a third insulating film and a fourth conductive film are formed in this order on the fourth conductive layer; a portion of the third insulating film and a portion of the fourth conductive film are removed to form a second opening reaching the fourth conductive layer; and a fourth insulating layer and a fifth conductive layer are formed; and a second semiconductor layer is formed in contact with a side surface of the fifth conductive layer, a side surface of the fourth insulating layer, and an upper surface of the fourth conductive layer in the second opening, respectively.

[0018] Furthermore, in the above, after forming the third conductive layer and the fourth conductive layer, and before forming the third insulating film and the fourth conductive film, it is preferable to form a fourth insulating film and a fifth insulating film in this order on the fourth conductive layer and the second insulating layer, remove a portion of the fifth insulating film to form the fifth insulating layer, and expose a portion of the upper surface of the fourth insulating film, and then form a third insulating film and a fourth conductive film in this order on the fifth insulating layer and the fourth insulating film.

[0019] According to one embodiment of the present invention, a semiconductor device including a transistor whose top surface is flat and has little unevenness, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a small-sized semiconductor device, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device, and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a manufacturing method of a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a novel semiconductor device, and a manufacturing method thereof can be provided.

[0020] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0021] FIG. 1A is a plan view showing an example of a semiconductor device. FIG. 1B is a cross-sectional view showing an example of a semiconductor device. FIG. 2 is a cross-sectional view showing an example of a semiconductor device. FIG. 3 is a cross-sectional view showing an example of a semiconductor device. FIG. 4 is a cross-sectional view showing an example of a semiconductor device. FIG. 5 is a cross-sectional view showing an example of a semiconductor device. FIG. 6A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 6B and 6C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 7A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 7B and 7C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 8A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 8B and 8C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 9A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 9B and 9C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 10A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 10B and 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 11A is a plan view showing an example of a method for manufacturing a semiconductor device. 11B and 11C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 12A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 12B and 12C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 13A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 13B and 13C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 14A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 14B and 14C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 15A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 15B and 15C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 16A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 16B and 16C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 17A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 17B and 17C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 18A is a plan view illustrating an example of a manufacturing method of a semiconductor device. 18B and 18C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.FIG. 19A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 19B and 19C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 20A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 20B and 20C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 21A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 21B and 21C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 22A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 22B and 22C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 23A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 23B and 23C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 24A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 24B and 24C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 25A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 25B and 25C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 26A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 26B and 26C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 27A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 27B and 27C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 28A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 28B and 28C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 29 is a block diagram of a display device. FIGS. 30A to 30D are circuit diagrams of pixel circuits. FIG. 31 is a plan view illustrating an example of a semiconductor device. FIG. 32 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 33 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 34 is a perspective view illustrating an example of a display device. FIG. 35 is a cross-sectional view illustrating an example of a display device. FIG. 36 is a cross-sectional view illustrating an example of a display device. FIG. 37 is a cross-sectional view illustrating an example of a display device. FIG. 38 is a cross-sectional view illustrating an example of a display device. FIGS. 39A to 39D are diagrams illustrating examples of electronic devices. FIGS. 40A to 40F are diagrams illustrating examples of electronic devices. 41A to 41G are diagrams showing an example of an electronic device.

[0022] The following description of the preferred embodiments will be given in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the preferred embodiments shown below.

[0023] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0024] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0025] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0026] A transistor is a type of semiconductor element that can realize functions such as amplifying current or voltage, and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0027] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. Note that the names of the source and drain of a transistor may be appropriately changed to the source terminal and drain terminal, or the source electrode and drain electrode, etc., depending on the situation.

[0028] The terms "gate" and "back gate" can be interchanged. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0029] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0030] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no exchange of an electric signal or an interaction of electric potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B.

[0031] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0032] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0033] In this specification and the like, a structure in which at least light-emitting layers are separately fabricated for light-emitting devices with different emission wavelengths may be referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting device, increasing the degree of freedom in the selection of materials and configurations, and facilitating improvements in brightness and reliability.

[0034] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other in terms of cross-sectional shape, characteristics, or the like. Furthermore, one layer may have two or three functions of the carrier injection layer, carrier transport layer, and carrier block layer.

[0035] In this specification and the like, a light-emitting device has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer).

[0036] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it refers to a shape having a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface on which the structure is to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface on which the structure is to be formed do not necessarily have to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0037] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0038] In this specification, the phrase "top surface shapes generally match" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0039] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. Furthermore, a plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0040] Furthermore, in this specification and the like, "approximately the same height" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are approximately the same in a cross-sectional view. For example, when a planarization process (typically, a chemical mechanical polishing (CMP) process) is performed, the heights of the processed surfaces are approximately the same. However, even when a planarization process is performed, the heights may not strictly match depending on the film material, etc., but in this specification and the like, this case is also considered to be "approximately the same height."

[0041] Embodiment 1 In this embodiment, a transistor of one embodiment of the present invention, a manufacturing method of the transistor, and the like will be described.

[0042] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer.

[0043] The first transistor and the second transistor are both vertical transistors in which the source electrode and the drain electrode are provided overlapping each other at different heights relative to the substrate surface, and the drain current flows in the height direction (vertical direction). Therefore, they can be miniaturized and occupy a smaller area than planar transistors in which the source electrode and the drain electrode are provided on the same plane. The first transistor and the second transistor have the above-mentioned structure, which allows miniaturization and high integration of the semiconductor device.

[0044] Furthermore, by using a structure in which the first transistor and the second transistor are stacked, miniaturization and higher integration of the semiconductor device can be achieved.

[0045] However, since a vertical transistor has a structure in which the source electrode, the channel formation region, and the drain electrode are provided at different heights, the vertical transistor is more likely to have large steps or unevenness in the height direction than a planar transistor. Therefore, stacking a vertical transistor on a vertical transistor is much more difficult to fabricate than stacking a planar transistor on a planar transistor.

[0046] In the vertical transistor of one embodiment of the present invention, steps or unevenness occurring in the height direction are filled with a layer having a planarization function, which allows stacking of multiple vertical transistors, thereby enabling miniaturization and high integration of semiconductor devices.

[0047] In the semiconductor device of one embodiment of the present invention, the first transistor and the second transistor are provided overlapping with each other in this order.

[0048] The first insulating layer is provided above one of the source electrode and the drain electrode of the first transistor, and the other of the source electrode and the drain electrode of the first transistor is provided on the first insulating layer. That is, the first insulating layer has a region sandwiched between the source electrode and the drain electrode of the first transistor.

[0049] The first insulating layer and the other of the source electrode or drain electrode of the first transistor each have a first opening reaching one of the source electrode or drain electrode of the first transistor. A semiconductor layer of the first transistor is provided in contact with a side surface of the first insulating layer within the first opening, a side surface of the other of the source electrode or drain electrode of the first transistor within the first opening, and an upper surface of one of the source electrode or drain electrode of the first transistor within the first opening. A gate insulating layer of the first transistor is provided in contact with the upper surface of the semiconductor layer. A gate electrode of the first transistor is provided in contact with the upper surface of the gate insulating layer so as to have a region overlapping with the first opening. The gate electrode has a shape that follows the shape of the first opening. That is, the gate electrode has a recess on its upper surface that corresponds to the shape of the first opening.

[0050] The second insulating layer is a layer having the aforementioned planarizing function. The second insulating layer is provided so as to fill a recess formed in the gate electrode of the first transistor. The upper surface of the second insulating layer has a generally flat shape. The upper surface of the second insulating layer and the upper surface of the highest region of the gate electrode of the first transistor as viewed from the substrate surface are generally the same height.

[0051] One of a source electrode and a drain electrode of a second transistor is provided in contact with a part of the top surface of the gate electrode of the first transistor.

[0052] The third insulating layer is provided above one of the source electrode and the drain electrode of the second transistor, and the other of the source electrode and the drain electrode of the second transistor is provided on the third insulating layer. That is, the third insulating layer has a region sandwiched between the source electrode and the drain electrode of the second transistor.

[0053] The third insulating layer and the other of the source electrode or drain electrode of the second transistor each have a second opening reaching one of the source electrode or drain electrode of the second transistor. A semiconductor layer of the second transistor is provided in contact with a side surface of the third insulating layer in the second opening, a side surface of the other of the source electrode or drain electrode of the second transistor in the second opening, and an upper surface of one of the source electrode or drain electrode of the second transistor in the second opening. A gate insulating layer of the second transistor is provided in contact with the upper surface of the semiconductor layer. A gate electrode of the second transistor is provided in contact with the upper surface of the gate insulating layer and has a region overlapping with the second opening.

[0054] As described above, the semiconductor device of one embodiment of the present invention has two vertical transistors, and at least one of the vertical transistors has a structure in which steps or unevenness occurring in the height direction are filled with a layer having a planarizing function. Therefore, it is easy to form another vertical transistor overlaying the vertical transistor. For example, when the semiconductor device of one embodiment of the present invention is used in a pixel circuit of a display device using an organic EL device, vertical transistors can be used for both the selection transistor and the driving transistor, and these transistors can be stacked. Therefore, the density of the pixel portion can be increased.

[0055] Below, specific structural examples of the semiconductor device of one embodiment of the present invention will be described with reference to the drawings.

[0056] <Configuration Example 1 of Semiconductor Device> Fig. 1A shows a plan view (also referred to as a top view) of a semiconductor device 100. Fig. 1B shows a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 1A, and Fig. 2 shows a cross-sectional view taken along dashed dotted line B1-B2 shown in Fig. 1A. Note that Fig. 1A omits some of the components of the semiconductor device 100 (insulating layers, etc.). As with Fig. 1A , some of the components will also be omitted in the plan views of semiconductor devices and the like in the following drawings.

[0057] The semiconductor device 100 is provided over a substrate 102. Although not shown in FIG. 1B and other drawings, an insulating layer functioning as a base film may be provided between the substrate 102 and the semiconductor device 100. The semiconductor device 100 includes a transistor 10_1, a transistor 10_2, an insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1), an insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2), an insulating layer 192, an insulating layer 193, and an insulating layer 194. The transistor 10_1 and the transistor 10_2 are provided overlapping each other in this order.

[0058] The transistor 10_1 includes a conductive layer 104_1, an insulating layer 106_1, a semiconductor layer 108_1, a conductive layer 112a1, and a conductive layer 112b1. The conductive layer 104_1 functions as a gate electrode. A part of the insulating layer 106_1 functions as a gate insulating layer. The conductive layer 112a1 functions as one of a source electrode and a drain electrode. The conductive layer 112b1 functions as the other of the source electrode and the drain electrode. An entire region of the semiconductor layer 108_1 that overlaps with the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. A region of the semiconductor layer 108_1 that is in contact with the source electrode functions as a source region, and a region that is in contact with the drain electrode functions as a drain region.

[0059] The above description of transistor 10_1 can be applied to transistor 10_2 by replacing the conductive layer 104_1, the insulating layer 106_1, the semiconductor layer 108_1, the conductive layer 112a1, and the conductive layer 112b1 with the conductive layer 104_2, the insulating layer 106_2, the semiconductor layer 108_2, the conductive layer 112a2, and the conductive layer 112b2, respectively.

[0060] The detailed configuration of the semiconductor device 100 will be described.

[0061] A conductive layer 112a1 is provided over the substrate 102. An insulating layer 110a1 is provided over the conductive layer 112a1 and the substrate 102. An insulating layer 110b1 is provided over the insulating layer 110a1. An insulating layer 110c1 is provided over the insulating layer 110b1. A conductive layer 112b1 is provided over the insulating layer 110c1. Note that the insulating layer 110a1, the insulating layer 110b1, and the insulating layer 110c1 may be collectively referred to as the insulating layer 110_1.

[0062] The conductive layer 112a1, the insulating layer 110_1, and the conductive layer 112b1 overlap with each other in a region where the insulating layer 110_1 is sandwiched between the conductive layer 112a1 and the conductive layer 112b1.

[0063] The insulating layer 110_1 and the conductive layer 112b1 have an opening 143 that reaches the conductive layer 112a1.

[0064] The top surface shape of the opening 143 can be, for example, circular or elliptical. The top surface shape of the opening 143 may be a polygon such as a triangle, a quadrangle (including a rectangle, a rhombus, and a square), or a pentagon, or a polygon with rounded corners. As shown in FIG. 1A , the top surface shape of the opening 143 is preferably circular. By making the top surface shape of the opening 143 circular, the processing accuracy when forming the opening 143 can be improved, and the opening 143 can be formed with a fine size. Note that in this specification and the like, a circle is not limited to a perfect circle.

[0065] 1B and 2 show a configuration in which the thickness of the conductive layer 112a1 in the region overlapping with the opening 143 is approximately equal to the thickness of the region not overlapping with the opening 143, but this is not limited thereto. The thickness of the conductive layer 112a1 in the region overlapping with the opening 143 may be thinner than the thickness of the region not overlapping with the opening 143. In this case, the electric field from the conductive layer 104_1 (i.e., the gate electric field of the transistor 10_1) can be applied up to the channel formation region near the conductive layer 112a1. Therefore, the effect of the gate electric field on carriers in the channel formation region can be strengthened in some cases compared to when the conductive layer 112a1 has a uniform thickness.

[0066] The semiconductor layer 108_1 is provided in contact with the top surface of the conductive layer 112a1 in the opening 143, the side surface of the insulating layer 110_1 in the opening 143, the side surface of the conductive layer 112b1 in the opening 143, and the top surface of the conductive layer 112b1.

[0067] 1B and 2 show a structure in which the semiconductor layer 108_1 has a region in contact with the top surface of the conductive layer 112b1, but this is not limiting. The semiconductor layer 108_1 only needs to have a region in contact with the side surface of the conductive layer 112b1 in at least the opening 143.

[0068] For example, by configuring the entire region of the semiconductor layer 108_1 to be located within the opening 143 and the end portion of the semiconductor layer 108_1 to be in contact only with the side surface of the conductive layer 112b1 within the opening 143, it is possible to prevent the end portion of the semiconductor layer 108_1 from causing a step on the conductive layer 112b1. This can improve the coverage of a film on the top surface of the conductive layer 112b1 as a formation surface.

[0069] 1B and 2, by configuring the semiconductor layer 108_1 so that the end portion of the semiconductor layer 108_1 extends to the outside of the opening 143 and the semiconductor layer 108_1 is in contact with not only the side surface of the conductive layer 112b1 in the opening 143 but also the top surface of the conductive layer 112b1, the contact area between the semiconductor layer 108_1 and the conductive layer 112b1 can be increased. This can prevent the semiconductor layer 108_1 from peeling off. Furthermore, the contact resistance between the semiconductor layer 108_1 and the conductive layer 112b1 can be reduced, which can increase the on-state current of the transistor 10_1 in some cases.

[0070] Here, the insulating layer 110b1 of the insulating layer 110_1 is preferably an insulating layer containing oxygen. Furthermore, it is preferably an insulating layer that releases oxygen by heating. Thus, for example, when a metal oxide is used for the semiconductor layer 108_1, oxygen contained in the insulating layer 110b1 can be supplied to the metal oxide. This can repair oxygen vacancies in the metal oxide, thereby improving the electrical characteristics and reliability of the transistor 10_1.

[0071] On the other hand, the insulating layer 110a1 and the insulating layer 110c1 of the insulating layer 110_1 preferably have a blocking property against gases such as oxygen and hydrogen. This can prevent oxygen contained in the insulating layer 110b1 from being released to the outside through the insulating layer 110a1 or the insulating layer 110c1. Furthermore, it can prevent hydrogen from diffusing from the outside of the insulating layer 110_1 into the insulating layer 110b1 through the insulating layer 110a1 or the insulating layer 110c1 and then diffusing into the semiconductor layer 108_1. For example, when a metal oxide is used for the semiconductor layer 108_1, hydrogen in the semiconductor layer 108_1 can cause deterioration of the electrical characteristics and reliability of the transistor 10_1.

[0072] An insulating layer 106_1 is provided over the semiconductor layer 108_1. The insulating layer 106_1 has a region in contact with the top surface and side surfaces of the semiconductor layer 108_1, the top surface of the conductive layer 112b1, and the top surface of the insulating layer 110c1.

[0073] The conductive layer 104_1 is provided over the insulating layer 106_1. The conductive layer 104_1 is provided to have a region overlapping with the opening 143 in a plan view. The conductive layer 104_1 has a shape that conforms to the shapes of the semiconductor layer 108_1 and the insulating layer 106_1 in the opening 143. That is, the conductive layer 104_1 has a recess in its upper surface that corresponds to the shape of the opening 143. The conductive layer 104_1 has a region that faces the semiconductor layer 108_1 with the insulating layer 106_1 interposed therebetween in the opening 143.

[0074] An insulating layer 192 is provided over the conductive layer 104_1 so as to fill the opening 143. The top surface of the insulating layer 192 has a substantially flat shape. For example, an organic insulating material is preferably used as the insulating layer 192. This allows recesses formed in the conductive layer 104_1 to be easily planarized with good productivity. The top surface of the insulating layer 192 and the top surface of the highest region of the conductive layer 104_1 as viewed from the substrate surface are preferably substantially the same height. This allows the formation surfaces of layers (e.g., the conductive layer 112a2) provided over the insulating layer 192 and the conductive layer 104_1 to be substantially flat, thereby improving the coverage of the layers.

[0075] A conductive layer 112a2 is provided over the insulating layer 192 and the conductive layer 104_1. The conductive layer 112a2 is provided to have a region overlapping with the opening 143. Ends of the conductive layer 112a2 and the conductive layer 104_1 are approximately aligned in plan view. The conductive layer 112a2 has regions in contact with the top surface of the insulating layer 192 and parts of the top surface of the conductive layer 104_1.

[0076] An insulating layer 193 is provided over the transistor 10_1 and the conductive layer 112a2 so as to cover them. The insulating layer 193 is preferably made of the same material as the insulating layers 110a1 and 110c1. This can prevent impurities such as hydrogen from diffusing into the transistor 10_1 from the outside of the transistor 10_1 through the insulating layer 193.

[0077] An insulating layer 194 is provided in a region of the insulating layer 193 that does not overlap with the opening 143. The insulating layer 194 has a function of filling in and planarizing steps or unevenness caused by the transistor 10_1. Therefore, the insulating layer 194 is preferably made of the same material as the insulating layer 192 described above. For example, an organic insulating material is preferably used. This allows the steps or unevenness caused by the transistor 10_1 to be easily planarized with good productivity. The heights of the top surface of the insulating layer 194 and part of the top surface of the insulating layer 193 (specifically, the top surface of the region overlapping with the conductive layer 112a2) are preferably approximately the same. This allows the formation surfaces of layers (e.g., the insulating layer 110_2) provided on the insulating layer 194 and the insulating layer 193 to be approximately flat, thereby improving the coverage of the layers.

[0078] An insulating layer 110a2 is provided over the insulating layer 194 and the insulating layer 193. An insulating layer 110b2 is provided over the insulating layer 110a2. An insulating layer 110c2 is provided over the insulating layer 110b2. A conductive layer 112b2 is provided over the insulating layer 110c2. Note that the insulating layer 110a2, the insulating layer 110b2, and the insulating layer 110c2 may be collectively referred to as insulating layer 110_2.

[0079] The insulating layers 110a2, 110b2, and 110c2 are preferably made of the same materials as the insulating layers 110a1, 110b1, and 110c1, respectively. As a result, for example, when a metal oxide is used for the semiconductor layer 108_2, oxygen contained in the insulating layer 110b2 can be supplied to the metal oxide. Furthermore, release of oxygen contained in the insulating layer 110b2 to the outside through the insulating layer 110a2 or the insulating layer 110c2 can be suppressed. Furthermore, diffusion of hydrogen from the outside of the insulating layer 110_2 into the insulating layer 110b2 through the insulating layer 110a2 or the insulating layer 110c2 to the semiconductor layer 108_2 can be suppressed.

[0080] The conductive layer 112a2, the insulating layer 193, the insulating layer 110_2, and the conductive layer 112b2 overlap with each other in a region where the insulating layer 193 and the insulating layer 110_2 are sandwiched between the conductive layer 112a2 and the conductive layer 112b2.

[0081] The insulating layer 193, the insulating layer 110_2, and the conductive layer 112b2 each have an opening 144 that reaches the conductive layer 112a2.

[0082] For the top surface shape of the opening 144, please refer to the description of the top surface shape of the opening 143. As shown in Fig. 1A, the top surface shape of the opening 144 is preferably circular.

[0083] 1B and 2 show a configuration in which the film thickness of the conductive layer 112a2 in the region overlapping with the opening 144 is approximately equal to the film thickness of the region not overlapping with the opening 144, but this is not limited to this. As with the above description regarding the conductive layer 112a1 and the opening 143, the film thickness of the conductive layer 112a2 in the region overlapping with the opening 144 may also be thinner than the film thickness of the region not overlapping with the opening 144.

[0084] The semiconductor layer 108_2 is provided in contact with the top surface of the conductive layer 112a2 in the opening 144, the side surface of the insulating layer 193 in the opening 144, the side surface of the insulating layer 110_2 in the opening 144, the side surface of the conductive layer 112b2 in the opening 144, and the top surface of the conductive layer 112b2.

[0085] 1B and 2 show a configuration in which the semiconductor layer 108_2 has a region in contact with the top surface of the conductive layer 112b2, but this is not limited thereto. As with the above description of the semiconductor layer 108_1 and the conductive layer 112b1, the semiconductor layer 108_2 may also have at least a region in contact with the side surface of the conductive layer 112b2 in the opening 144.

[0086] An insulating layer 106_2 is provided over the semiconductor layer 108_2. The insulating layer 106_2 has a region in contact with the top surface and side surfaces of the semiconductor layer 108_2, the top surface of the conductive layer 112b2, and the top surface of the insulating layer 110c2.

[0087] The conductive layer 104_2 is provided over the insulating layer 106_2. The conductive layer 104_2 is provided to have a region overlapping with the opening 144 in a plan view. The conductive layer 104_2 has a shape that conforms to the shapes of the semiconductor layer 108_2 and the insulating layer 106_2 within the opening 144. That is, the conductive layer 104_2 has a recessed portion on its top surface that corresponds to the shape of the opening 144. The conductive layer 104_2 has a region that faces the semiconductor layer 108_2 with the insulating layer 106_2 interposed therebetween within the opening 144.

[0088] Note that the conductive layer 104_2 can also be formed to fill the opening 144. For example, depending on the diameter of the opening 144 in a plan view, the conductive layer 104_2 may be formed to fill the opening 144. In this case, a step or unevenness formed on the top surface of the conductive layer 104_2 in a region overlapping with the opening 144 is reduced, which is preferable because coverage of a layer formed thereon can be improved.

[0089] In the transistor 10_1, the source electrode and the drain electrode are located at different heights with respect to the surface of the substrate 102, which is a surface where the transistor is formed, and a drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the substrate 102. Similarly, in the transistor 10_2, the source electrode and the drain electrode are located at different heights with respect to the surface of the insulating layer 192, etc., which is a surface where the transistor is formed, and a drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the insulating layer 192, etc. That is, in the transistors 10_1 and 10_2, the drain current flows in the vertical direction or approximately vertically. Therefore, the transistor of one embodiment of the present invention can be called a vertical transistor, a vertical channel transistor, or a VFET (Vertical Field Effect Transistor).

[0090] Since the source electrode and the drain electrode of each of the transistors 10_1 and 10_2 can be overlapped, the transistors can be made smaller than a so-called planar transistor in which the source electrode and the drain electrode are arranged on the same plane, and the area occupied by the transistor within the substrate surface can be significantly reduced.

[0091] Furthermore, in the semiconductor device 100 of one embodiment of the present invention, the transistor 10_2 is provided so as to overlap the transistor 10_1, whose gate electrode is formed with a recess formed by the insulating layer 192 and the insulating layer 194 and is substantially planarized. Therefore, the area occupied by the transistors in the substrate surface can be significantly reduced compared to a configuration in which these two transistors are arranged on the same plane, thereby enabling miniaturization and high integration of the semiconductor device. For example, by using the semiconductor device of one embodiment of the present invention in a pixel circuit of a display device using an organic EL device, vertical transistors can be used for both the selection transistor and the driving transistor, and these transistors can be stacked, thereby enabling a display device with extremely high definition to be realized.

[0092] The channel lengths and channel widths of the transistors 10_1 and 10_2 will be described below. Note that although the channel length and channel width will be described below using the transistor 10_2, the same description can be applied to the transistor 10_1, which is also a vertical transistor, by replacing each component of the transistor (for example, by replacing the number "2" at the end of each reference numeral with "1").

[0093] In the semiconductor layer 108_2, a region in contact with the conductive layer 112a2 functions as one of a source region and a drain region, a region in contact with the conductive layer 112b2 functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region.

[0094] The channel length of the transistor 10_2 is the distance between the source region and the drain region. In FIG. 2, the channel length L10_2 of the transistor 10_2 is indicated by a dashed double-headed arrow. In FIG. 2, the distance along the semiconductor layer 108_2 in the region between the conductive layer 112a2 and the conductive layer 112b2 is indicated as the channel length L10_2 of the transistor 10_2.

[0095] Note that the sum of the thickness of the insulating layer 193 and the thickness of the insulating layer 110_2 in a region sandwiched between the top surface of the conductive layer 112a2 and the bottom surface of the conductive layer 112b2 (the thickness of the insulating layer 110_1 in the case of the channel length of the transistor 10_1) may be used as the channel length L10_2 of the transistor 10_2. Alternatively, the thickness of the insulating layer 110b2 (the thickness of the insulating layer 110b1 in the case of the channel length of the transistor 10_1) may be used as the channel length L10_2 of the transistor 10_2. Alternatively, the sum of the thickness of the insulating layer 193, the thickness of the insulating layer 110_2, and the thickness of the conductive layer 112b2 (the sum of the thickness of the insulating layer 110_1 and the thickness of the conductive layer 112b1 in the case of the channel length of the transistor 10_1) may be used as the channel length L10_2 of the transistor 10_2.

[0096] Here, the channel length L10_2 of the transistor 10_2 is determined by the thickness of the insulating layer 193, the thickness of the insulating layer 110_2, the thickness of the conductive layer 112b2, the angle θ110_2 between the surface where the semiconductor layer 108_2 is to be formed in the opening 144 (here, the side surface of the insulating layer 193, the side surface of the insulating layer 110_2, and the side surface of the conductive layer 112b2) and the surface where the insulating layer 193 is to be formed (here, the top surface of the conductive layer 112a2), and the like, and is not affected by the performance of the exposure apparatus used to manufacture the transistor. Therefore, the channel length L10_2 can be set to a value smaller than the limit resolution of the exposure apparatus, and a transistor with a microscopic size can be realized.

[0097] The channel length L10_2 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm. For example, the channel length L10_2 can be 100 nm or more and less than 1 μm. By shortening the channel length L10_2, the on-state current of the transistor 10_2 can be increased.

[0098] The thickness of the insulating layer 110_2 (or the sum of the thickness of the insulating layer 193 and the thickness of the insulating layer 110_2) can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm.

[0099] The angle θ110_2 can be, for example, 30 degrees or more and less than 90 degrees, 35 degrees or more and less than 85 degrees, 40 degrees or more and less than 80 degrees, 45 degrees or more and less than 80 degrees, 50 degrees or more and less than 80 degrees, 55 degrees or more and less than 80 degrees, 60 degrees or more and less than 80 degrees, 65 degrees or more and less than 80 degrees, or 70 degrees or more and less than 80 degrees. Note that the angle θ110_2 can also be 90 degrees. The smaller the angle θ110_2, the better the coverage of the layer (such as the semiconductor layer 108_2) formed along the sidewall of the opening 144 can be. On the other hand, the closer the angle θ110_2 is to 90 degrees, the better the area occupied by the transistor on the substrate surface can be reduced.

[0100] The channel width of the transistor 10_2 is the length of the source region or the length of the drain region in a plan view ( FIG. 1A ). That is, the channel width of the transistor 10_2 is the length of the region where the semiconductor layer 108_2 and the conductive layer 112a2 are in contact with each other in a plan view or the length of the region where the semiconductor layer 108_2 and the conductive layer 112b2 are in contact with each other in a plan view. Alternatively, the channel width of the transistor 10_2 may be an intermediate value between the length of the region where the semiconductor layer 108_2 and the conductive layer 112a2 are in contact with each other in a plan view and the length of the region where the semiconductor layer 108_2 and the conductive layer 112b2 are in contact with each other in a plan view.

[0101] Here, the channel width of the transistor 10_2 is described as the perimeter of a region where the semiconductor layer 108_2 is in contact with the side surface of the conductive layer 112b2 on the opening 144 side. In Figures 1A and 2, the channel width W10_2 of the transistor 10_2 is indicated by a solid double-headed arrow. The channel width W10_2 can also be referred to as the perimeter of the opening 144 in a plan view (in the case of the channel width of the transistor 10_1, the perimeter of the opening 143 in a plan view).

[0102] The channel width W10_2 is determined by the top surface shape of the opening 144, etc. In FIGS. 1A and 2, the width D144 of the opening 144 is indicated by a two-dot chain line with a double arrow. The width D144 refers to the short side of the smallest rectangle circumscribing the opening 144 in a plan view. When the opening 144 is formed using photolithography, the width D144 of the opening 144 is equal to or greater than the resolution limit of the exposure tool. The width D144 is, for example, equal to or greater than 0.20 μm and less than 5.0 μm. Note that when the top surface shape of the opening 144 is circular, the width D144 corresponds to the diameter of the opening 144, and the channel width W10_2 can be calculated as "D144 × π."

[0103] [Semiconductor Layer 108_1, Semiconductor Layer 108_2] The semiconductor material that can be used for the semiconductor layer 108_1 and the semiconductor layer 108_2 is not particularly limited. For example, an elemental semiconductor or a compound semiconductor can be used. As the elemental semiconductor, for example, silicon or germanium can be used. As the compound semiconductor, for example, gallium arsenide and silicon germanium can be used. As the compound semiconductor, an organic substance having semiconductor properties or a metal oxide having semiconductor properties (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials may contain impurities that function as dopants (for example, when silicon is used as the semiconductor material, typical examples include elements such as phosphorus and boron).

[0104] The crystallinity of the semiconductor material used for the semiconductor layer 108_1 and the semiconductor layer 108_2 is not particularly limited, and any of an amorphous semiconductor and a crystalline semiconductor (a single-crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0105] The semiconductor layer 108_1 and the semiconductor layer 108_2 can be formed using silicon. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0106] A transistor using amorphous silicon for the semiconductor layers 108_1 and 108_2 can be formed over a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layers 108_1 and 108_2 has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for the semiconductor layers 108_1 and 108_2 has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0107] The semiconductor layer 108_1 and the semiconductor layer 108_2 preferably contain a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer 108_1 and the semiconductor layer 108_2 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin. Gallium is more preferred as the element M.

[0108] For the semiconductor layer 108_1 and the semiconductor layer 108_2, for example, indium oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO), or the like can be used. Alternatively, indium tin oxide containing silicon can be used.

[0109] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target.

[0110] When the semiconductor layers 108_1 and 108_2 are formed by the ALD method, it is preferable to use a film formation method such as a thermal ALD method or a PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0111] The compositions of the metal oxides in the semiconductor layers 108_1 and 108_2 greatly affect the electrical characteristics and reliability of the transistors 10_1 and 10_2, respectively.

[0112] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized. Furthermore, by using a metal oxide that does not contain gallium or has a low content of gallium in the semiconductor layers 108_1 and 108_2, for example, a transistor with high reliability against application of a positive bias can be obtained. Furthermore, by using a metal oxide with a low content of element M in the semiconductor layers 108_1 and 108_2, for example, a transistor with high reliability against application of a positive bias can be obtained. Furthermore, by increasing the content of element M in the metal oxide, for example, a transistor with high reliability against light can be obtained.

[0113] The composition of the metal oxide contained in the semiconductor layer 108_1 and the semiconductor layer 108_2 will be described in detail later.

[0114] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 108_1 and the semiconductor layer 108_2. For example, a metal oxide layer having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline (poly-crystal) structure, a nanocrystalline (nc: nano-crystal) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 108_1 and the semiconductor layer 108_2, the defect state density in the semiconductor layer 108_1 and the semiconductor layer 108_2 can be reduced, and a highly reliable transistor can be realized. Note that the CAAC structure is a crystal structure in which multiple microcrystals (typically, multiple IGZO microcrystals) have c-axis orientation and are connected without being oriented in the a-b plane. In the CAAC structure, crystal grain boundaries (grains) are less clearly visible in the a-b plane than in the polycrystalline structure, and therefore a highly reliable transistor can be realized.

[0115] The higher the crystallinity of the metal oxide layers used for the semiconductor layers 108_1 and 108_2, the more the density of defect states in the semiconductor layers 108_1 and 108_2 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0116] The semiconductor layer 108_1 and the semiconductor layer 108_2 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer can be used, and the second metal oxide layer can have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer can have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer 108_1 and the semiconductor layer 108_2 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs. For example, a stacked structure of two or more metal oxide layers with different crystallinity can be formed by using the same sputtering target and varying the ratio of the flow rate of oxygen gas to the total deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio). Note that the two or more metal oxide layers included in the semiconductor layer 108_1 and the semiconductor layer 108_2 may have different compositions.

[0117] The thickness of each of the semiconductor layer 108_1 and the semiconductor layer 108_2 (film thickness relative to the surface on which it is formed) is preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, further preferably 10 nm or more and 100 nm or less, further preferably 10 nm or more and 70 nm or less, further preferably 15 nm or more and 70 nm or less, further preferably 15 nm or more and 50 nm or less, further preferably 20 nm or more and 50 nm or less, further preferably 20 nm or more and 40 nm or less, further preferably 25 nm or more and 40 nm or less.

[0118] Here, oxygen vacancies that can be formed in the semiconductor layer 108_1 and the semiconductor layer 108_2 will be described.

[0119] When an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, and oxygen vacancies (V ＯFurthermore, defects in which hydrogen enters an oxygen vacancy (hereinafter referred to as V Ｏ H.) functions as a donor and generates electrons as carriers. Furthermore, some of the hydrogen atoms may bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stresses such as heat and an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0120] V Ｏ H can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation is sometimes performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration."

[0121] From the above, when an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain an oxide semiconductor in which H is sufficiently reduced, impurities such as water and hydrogen are removed from the oxide semiconductor (this may be referred to as dehydration or dehydrogenation treatment), and oxygen vacancies (V Ｏ It is important to repair the Ｏ By using an oxide semiconductor in which defects such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0122] When an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ Note that the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably 1×10 −９ cm −３ It can be said that:

[0123] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, by using an OS transistor in a semiconductor device, the power consumption of the semiconductor device can be reduced.

[0124] OS transistors can be applied to display devices. To increase the light-emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since OS transistors have a higher source-drain breakdown voltage than transistors using silicon (hereinafter referred to as Si transistors), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as a driving transistor in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the light-emission luminance of the light-emitting device.

[0125] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a greater number of gray levels to be displayed in the pixel circuit.

[0126] In terms of saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed through a light-emitting device, even when the current-voltage characteristics of the light-emitting device vary. In other words, when an OS transistor operates in a saturation region, the source-drain current of the OS transistor remains almost unchanged even when the source-drain voltage increases, thereby stabilizing the light-emitting luminance of the light-emitting device.

[0127] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of variations in light-emitting devices," and the like.

[0128] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays).

[0129] In the transistor of one embodiment of the present invention, and in a semiconductor device, a display device, or the like to which the transistor of one embodiment of the present invention is applied, an inorganic insulating material or an organic insulating material can be used for the insulating layer (the insulating layer 110_1, the insulating layer 110_2, the insulating layer 106_1, the insulating layer 106_2, the insulating layer 192, the insulating layer 193, and the insulating layer 194). Alternatively, the insulating layer may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0130] As the inorganic insulating material, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride can be used.

[0131] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0132] For example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS) can be used to analyze the oxygen and nitrogen contents. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing the element contents, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0133] Furthermore, for evaluating the film density of an insulating layer or the like, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR) can be used. Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscopy (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a pale (bright) transmission electron (TE) image. Even when the same material is used for the insulating layer, if the film densities are different, the boundary between these may be observed as a difference in contrast in a cross-sectional TEM image.

[0134] The nitrogen content of the insulating layer can be confirmed, for example, by energy dispersive X-ray spectrometry (EDX). For example, when silicon nitride, silicon oxynitride, or the like is used for the insulating layer, the nitrogen content can be evaluated using the ratio of the nitrogen peak height to the silicon peak height. In EDX, the peak of a certain element refers to the point at which the count number of the element reaches a maximum in a spectrum where the horizontal axis shows the energy of characteristic X-rays and the vertical axis shows the count number (detection value) of characteristic X-rays. Alternatively, the count number at the energy of characteristic X-rays specific to the element may be used to confirm the difference in nitrogen content by the ratio of the nitrogen count number to the silicon count number. For example, the count number at 1.739 keV (Si-Kα) can be used for silicon, and the count number at 0.392 keV (N-Kα) can be used for nitrogen.

[0135] The hydrogen concentration of the insulating layer can be evaluated by, for example, SIMS.

[0136] When hydrogen diffuses into the semiconductor layer 108_1 and the semiconductor layer 108_2, it reacts with oxygen atoms contained in the oxide semiconductor to form water, and oxygen vacancies (V Ｏ ) may be formed in the semiconductor layer 108_1 and the semiconductor layer 108_2. Ｏ When a blocking film that suppresses hydrogen diffusion is used as an insulating layer in contact with the semiconductor layer 108_1 or the semiconductor layer 108_2 or as an insulating layer located around the semiconductor layer 108_1 or the semiconductor layer 108_2, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0137] Oxygen vacancies (V Ｏ ) and V ＯIn particular, when the channel length is short, oxygen vacancies (V Ｏ ) and V Ｏ For example, when VH flows from the source region or drain region to the channel formation region, the influence of VH on the electrical characteristics and reliability of the transistors 10_1 and 10_2 increases. Ｏ The diffusion of H increases the carrier concentration in the channel formation region, which may cause fluctuations in the threshold voltages of the transistors 10_1 and 10_2 or reduce the reliability. Ｏ The influence of the diffusion of H on the electrical characteristics and reliability of the transistors 10_1 and 10_2 increases as the channel length decreases. Ｏ ) and V Ｏ By reducing H, it is possible to realize a transistor with a short channel length, which has good electrical characteristics and high reliability.

[0138] By using an insulating layer that releases oxygen as an insulating layer in contact with the semiconductor layer 108_1 and the semiconductor layer 108_2 (for example, the insulating layer 106_1, the insulating layer 106_2, the insulating layer 110b1, and the insulating layer 110b2), oxygen can be supplied from the insulating layer to the semiconductor layer 108_1 and the semiconductor layer 108_2. By supplying oxygen to the channel formation regions of the semiconductor layer 108_1 and the semiconductor layer 108_2, oxygen vacancies (V Ｏ ) and V Ｏ The H can be reduced, and a highly reliable transistor can be obtained, which has favorable electrical characteristics. Note that other treatments for supplying oxygen to the semiconductor layers 108_1 and 108_2 include heat treatment in an atmosphere containing oxygen, plasma treatment in an atmosphere containing oxygen, and the like.

[0139] It is preferable that an insulating layer in contact with the semiconductor layer 108_1 or 108_2, or an insulating layer located around the semiconductor layer 108_1 or 108_2, emits little impurities (for example, water and hydrogen) from itself. Note that the impurities referred to here are impurities that diffuse into the semiconductor layer 108_1 or 108_2 and cause oxygen vacancies (V Ｏ ) and V Ｏ Impurities refer to substances that can adversely affect the electrical characteristics of a transistor by, for example, generating H. Reducing the release of impurities can suppress the diffusion of the impurities into the semiconductor layers 108_1 and 108_2, thereby enabling a highly reliable transistor to exhibit favorable electrical characteristics.

[0140] Oxygen may be released from the semiconductor layers 108_1 and 108_2 due to heat applied in a process after the formation of the semiconductor layers 108_1 and 108_2. However, oxygen is supplied to the semiconductor layers 108_1 and 108_2 from an insulating layer in contact with the semiconductor layers 108_1 and 108_2, which can cause oxygen vacancies (V Ｏ ) and V Ｏ An increase in H can be suppressed. Furthermore, the degree of freedom in the process temperature can be increased in the processes after the formation of the semiconductor layers 108_1 and 108_2. Specifically, the process temperature can be increased in the processes after the formation of the semiconductor layers 108_1 and 108_2. Therefore, a transistor having good electrical characteristics and high reliability can be formed.

[0141] [Insulating Layer 110_1 and Insulating Layer 110_2] The insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) and the insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2) can be formed using an inorganic insulating material or an organic insulating material. The insulating layer 110_1 and the insulating layer 110_2 may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0142] An inorganic insulating material can be suitably used for the insulating layer 110_1 and the insulating layer 110_2. Examples of the inorganic insulating material that can be used include one or more of oxide, oxynitride, nitride oxide, and nitride. Examples of the insulating layer 110_1 and the insulating layer 110_2 that can be used include one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride.

[0143] The insulating layer 110_1 and the insulating layer 110_2 may have a stacked structure of two or more layers. In FIG. 1B and other drawings, the insulating layer 110_1 has a stacked structure of an insulating layer 110a1, an insulating layer 110b1 on the insulating layer 110a1, and an insulating layer 110c1 on the insulating layer 110b1, and the insulating layer 110_2 has a stacked structure of an insulating layer 110a2, an insulating layer 110b2 on the insulating layer 110a2, and an insulating layer 110c2 on the insulating layer 110b2. The insulating layers 110a1, 110b1, 110c1, 110a2, 110b2, and 110c2 may be made of the same material or different materials.

[0144] The insulating layers 110_1 and 110_2 preferably release little impurities (for example, water and hydrogen) from themselves.

[0145] The insulating layers 110b1 and 110b2 can be thicker than the insulating layers 110a1 and 110a2 and the insulating layers 110c1 and 110c2. As described above, the insulating layers 110b1 and 110b2 are insulating layers containing oxygen to be supplied to the semiconductor layers 108_1 and 108_2, respectively. Therefore, by making the insulating layers 110b1 and 110b2 thickest among the three insulating layers constituting the insulating layer 110_1 (the insulating layer 110a1, the insulating layer 110b1, and the insulating layer 110c1) and the three insulating layers constituting the insulating layer 110_2 (the insulating layer 110a2, the insulating layer 110b2, and the insulating layer 110c2), respectively, the amount of oxygen that can be contained in the entire insulating layer 110_1 and the entire insulating layer 110_2 can be increased. The deposition rate of the insulating layers 110b1 and 110b2 is preferably faster than the deposition rate of the insulating layers 110a1 and 110a2 and the deposition rate of the insulating layers 110c1 and 110c2. By increasing the deposition rate of a thick film, productivity can be improved.

[0146] The insulating layers 110a1 and 110c1, as well as the insulating layers 110a2 and 110c2, function as blocking films that suppress gas desorption from the insulating layers 110b1 and 110b2, respectively. The insulating layers 110a1 and 110c1, as well as the insulating layers 110a2 and 110c2, are preferably made of materials that are difficult for gas to diffuse through. The insulating layers 110a1 and 110c1, as well as the insulating layers 110a2 and 110c2, preferably have regions with higher film density than the insulating layers 110b1 and 110b2, respectively. Increasing the film density of the insulating layers can improve their blocking properties against gas. Slowing the film formation rate of the insulating layers increases the film density, thereby improving their blocking properties against gas.

[0147] The insulating layers 110b1 and 110b2 are preferably formed using an oxide or an oxynitride. The insulating layers 110b1 and 110b2 are preferably formed using a film that releases oxygen when heated. The insulating layers 110b1 and 110b2 are preferably formed using, for example, silicon oxide or silicon oxynitride.

[0148] When the insulating layers 110b1 and 110b2 release oxygen, oxygen can be supplied from the insulating layer 110b1 to the semiconductor layer 108_1 and from the insulating layer 110b2 to the semiconductor layer 108_2. The insulating layers 110b1 and 110b2 preferably have a high oxygen diffusion coefficient. A high oxygen diffusion coefficient facilitates diffusion of oxygen in the insulating layers 110b1 and 110b2, allowing oxygen to be efficiently supplied to the semiconductor layers 108_1 and 108_2, respectively. Furthermore, as described above, by configuring the insulating layers 110b1 and 110b2 to be thicker than the insulating layers 110a1 and 110c1 and the insulating layers 110a2 and 110c2, respectively, more oxygen can be supplied to the semiconductor layers 108_1 and 108_2.

[0149] The insulating layers 110_1 and 110_2 are preferably formed by a film formation method such as a sputtering method, an ALD method, or a plasma CVD method.

[0150] In particular, by using a sputtering method without using a gas containing hydrogen in the deposition gas, a film with an extremely low hydrogen content can be obtained. Therefore, hydrogen supply to the semiconductor layer 108_1 and the semiconductor layer 108_2 can be suppressed, and the electrical characteristics of the transistors 10_1 and 10_2 can be stabilized. When silicon oxide is deposited by sputtering, it can be deposited using a silicon target in an atmosphere containing an oxygen gas, for example. When silicon nitride is deposited by sputtering, it can be deposited using a silicon target in an atmosphere containing nitrogen gas, for example. When aluminum oxide is deposited by sputtering, it can be deposited using an aluminum target in an atmosphere containing an oxidizing gas, for example.

[0151] Silicon oxide and silicon nitride can be formed by, for example, the PEALD method. Aluminum oxide and hafnium oxide can be formed by, for example, the thermal ALD method. By forming an insulating layer by the PEALD method and the thermal ALD method, a dense insulating film can be formed, and thus the blocking property against oxygen and hydrogen can be improved.

[0152] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 can be made of a material having a higher nitrogen content than the insulating layers 110b1 and 110b2, respectively. Increasing the nitrogen content of the insulating layers can improve the blocking properties against oxygen and hydrogen.

[0153] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 may each have a region with a lower hydrogen concentration than the insulating layers 110b1 and 110b2.

[0154] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 are preferably impermeable to oxygen. Furthermore, the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 are preferably impermeable to hydrogen. The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 function as blocking films that suppress diffusion of hydrogen from the outside of the transistor to the semiconductor layer 108_1 and the semiconductor layer 108_2 through the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, respectively. The film densities of the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 are preferably higher than those of the insulating layers 110b1 and 110b2, respectively. Increasing the film density of the insulating layers can improve the blocking properties of oxygen and hydrogen. When silicon oxide or silicon oxynitride is used for the insulating layers 110b1 and 110b2, silicon nitride or silicon nitride oxide can be used for the insulating layers 110a1, 110c1, 110a2, and 110c2, respectively. Furthermore, hafnium oxide or aluminum oxide can be suitably used for the insulating layers 110a1, 110c1, 110a2, and 110c2.

[0155] Furthermore, the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2 can each have a structure in which two or more materials selected from silicon nitride, silicon nitride oxide, hafnium oxide, and aluminum oxide are stacked.

[0156] If oxygen contained in the insulating layers 110b1 and 110b2 diffuses downward (toward the substrate 102) from the insulating layers 110b1 and 110b2, the amounts of oxygen supplied from the insulating layers 110b1 and 110b2 to the semiconductor layers 108_1 and 108_2, respectively, may decrease. By providing the insulating layers 110a1 and 110a2 below the insulating layers 110b1 and 110b2, respectively, it is possible to prevent the oxygen contained in the insulating layers 110b1 and 110b2 from diffusing downward from the insulating layers 110b1 and 110b2. Furthermore, by providing the insulating layers 110c1 and 110c2 on the insulating layers 110b1 and 110b2, respectively, it is possible to suppress the oxygen contained in the insulating layers 110b1 and 110b2 from diffusing upward from the insulating layers 110b1 and 110b2. Therefore, the amount of oxygen supplied from the insulating layers 110b1 and 110b2 to the semiconductor layers 108_1 and 108_2 increases, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0157] Furthermore, by providing the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, diffusion of hydrogen into the semiconductor layers 108_1 and 108_2 is suppressed, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0158] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 preferably have a thickness that functions as a blocking film for oxygen and hydrogen. If the insulating layers are too thin, the blocking film function may be impaired. On the other hand, if the insulating layers are too thick, the regions of the semiconductor layers 108_1 and 108_2 that are in contact with the insulating layers 110b1 and 110b2, respectively, may become narrower, and the amount of oxygen supplied to the semiconductor layers 108_1 and 108_2 may become smaller. The film thickness (film thickness relative to the surface on which the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2 are preferably 1 nm or more and 200 nm or less, 1 nm or more and 100 nm or less, 1 nm or more and 60 nm or less, 1 nm or more and 50 nm or less, 1 nm or more and 40 nm or less, 1 nm or more and 30 nm or less, 1 nm or more and 20 nm or less, 1 nm or more and 10 nm or less, 1 nm or more and 5 nm or less, or 2 nm or more and 5 nm or less, respectively.

[0159] [Insulating Layer 106_1 and Insulating Layer 106_2] The insulating layers 106_1 and 106_2, which function as gate insulating layers, preferably have a low defect density. The low defect density of the insulating layers 106_1 and 106_2 enables a transistor to exhibit favorable electrical characteristics. Furthermore, the insulating layers 106_1 and 106_2 preferably have a high withstand voltage. The high withstand voltage of the insulating layers 106_1 and 106_2 enables a highly reliable transistor.

[0160] The insulating layers 106_1 and 106_2 are preferably insulating layers containing oxygen. Furthermore, they are preferably insulating layers that release oxygen when heated. For example, when a metal oxide is used for the semiconductor layers 108_1 and 108_2, oxygen contained in the insulating layers 106_1 and 106_2 can be supplied to the metal oxide. This can repair oxygen vacancies in the metal oxide, thereby improving the electrical characteristics and reliability of the transistors 10_1 and 10_2.

[0161] The insulating layers 106_1 and 106_2 can include, for example, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride having insulating properties. The insulating layers 106_1 and 106_2 can include, for example, one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide. The insulating layers 106_1 and 106_2 can be single layers or stacked layers. The insulating layers 106_1 and 106_2 can have, for example, a stacked structure of an oxide and a nitride.

[0162] In a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0163] The insulating layers 106_1 and 106_2 preferably release little impurities (for example, water and hydrogen) from themselves. The small amount of impurity release from the insulating layers 106_1 and 106_2 suppresses the diffusion of the impurities into the semiconductor layers 108_1 and 108_2, respectively, and thus the transistors can have favorable electrical characteristics and high reliability.

[0164] The insulating layers 106_1 and 106_2 are preferably formed under conditions that cause little damage to the semiconductor layers 108_1 and 108_2 because they are formed over the semiconductor layers 108_1 and 108_2, respectively. For example, they are preferably formed under conditions that cause little damage to the semiconductor layers 108_1 and 108_2. For example, when the insulating layers 106_1 and 106_2 are formed by a plasma CVD method, low power consumption can reduce damage to the semiconductor layers 108_1 and 108_2.

[0165] Here, the insulating layers 106_1 and 106_2 will be specifically described using an example in which metal oxide is used for the semiconductor layers 108_1 and 108_2.

[0166] In order to improve interface characteristics with the semiconductor layer 108_1 and the semiconductor layer 108_2, it is preferable to use one or more of oxide and oxynitride on at least the side of the insulating layer 106_1 that is in contact with the semiconductor layer 108_1 and on at least the side of the insulating layer 106_2 that is in contact with the semiconductor layer 108_2. For example, one or more of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 106_1 and the insulating layer 106_2. It is more preferable to use a film that releases oxygen by heating for the insulating layer 106_1 and the insulating layer 106_2.

[0167] The insulating layers 106_1 and 106_2 may have a stacked structure. The insulating layers 106_1 and 106_2 can have a stacked structure of an oxide film or oxynitride film in contact with the semiconductor layer 108_1 and the semiconductor layer 108_2, respectively, and a nitride film in contact with the conductive layer 104_1 and the conductive layer 104_2, respectively. As the oxide film or the oxynitride film, for example, one or more of silicon oxide and silicon oxynitride can be preferably used. As the nitride film, for example, silicon nitride can be preferably used.

[0168] The thickness of the insulating layer 106_1 and the insulating layer 106_2 (thickness relative to the surface where the insulating layer 106_1 and the insulating layer 106_2 are formed) is more preferably 1 nm to 100 nm. At least a part of the insulating layer 106_1 and the insulating layer 106_2 may have a region with the above thickness.

[0169] [Conductive Layer 112a1, Conductive Layer 112b1, Conductive Layer 112a2, and Conductive Layer 112b2] The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2, which function as a source electrode and a drain electrode, respectively, can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the above metals. The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2 can be formed using a low-resistance conductive material containing one or more of copper, silver, gold, and aluminum. Copper and aluminum are particularly preferred because of their excellent mass productivity.

[0170] The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2 can each be formed using a metal oxide film (also referred to as an oxide conductor). Examples of oxide conductors (OC) include In—Sn oxide (ITO), In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Zn oxide, In—Sn—Si oxide (ITSO), and In—Ga—Zn oxide.

[0171] Here, oxide conductors (OC) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0172] The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2 may each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0173] The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2 may each be a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, it is possible to process the film by wet etching, thereby reducing manufacturing costs.

[0174] Note that the conductive layers 112a1 and 112b1 may be formed using the same material or different materials. The same applies to the conductive layers 112a2 and 112b2.

[0175] Here, the conductive layers 112a1, 112b1, 112a2, and 112b2 will be specifically described using a structure in which metal oxide is used for the semiconductor layers 108_1 and 108_2 as an example.

[0176] When an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, the conductive layer 112a1 and the conductive layer 112b1 and the conductive layer 112a2 and the conductive layer 112b2 are oxidized by oxygen contained in the semiconductor layer 108_1 and the semiconductor layer 108_2, which may result in an increase in resistance. The conductive layer 112a1 and the conductive layer 112b1 and the conductive layer 112a2 and the conductive layer 112b2 are oxidized by oxygen contained in the insulating layer 110_1 and the insulating layer 110_2, which may result in an increase in resistance. Furthermore, the conductive layer 112a1 and the conductive layer 112b1 and the conductive layer 112a2 and the conductive layer 112b2 are oxidized by oxygen contained in the semiconductor layer 108_1 and the semiconductor layer 108_2, which may result in an oxygen deficiency (V ＯWhen the conductive layers 112a1 and 112b1 and the conductive layers 112a2 and 112b2 are oxidized by oxygen contained in the insulating layers 110_1 and 110_2, the amounts of oxygen supplied from the insulating layers 110_1 and 110_2 to the semiconductor layers 108_1 and 108_2, respectively, may decrease.

[0177] The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2, are preferably made of a material that is resistant to oxidation. The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2, are preferably made of an oxide conductor. For example, In—Sn oxide (ITO) or In—Sn—Si oxide (ITSO) can be suitably used. The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2, may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2 may each have a stacked structure of the above-mentioned materials.

[0178] By using a material that is difficult to oxidize for the conductive layers 112a1 and 112b1 and the conductive layers 112a2 and 112b2, it is possible to prevent oxidation due to oxygen contained in the semiconductor layer 108_1 or 108_2 or oxygen contained in the insulating layer 110_1 or 110_2, which can prevent an increase in resistance. Ｏ ) can be suppressed, and the amounts of oxygen supplied from the insulating layers 110_1 and 110_2 to the semiconductor layers 108_1 and 108_2, respectively, can be increased.

[0179] The conductive layers 104_1 and 104_2, which function as gate electrodes, can be formed using, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above metals. Furthermore, the conductive layers 104_1 and 104_2 can be formed using the same materials as those used for the conductive layers 112a1 and 112b1 and the conductive layers 112a2 and 112b2.

[0180] 1B and the like, the conductive layers 104_1 and 104_2 are shown as single-layer structures, but this is not limited thereto. For example, the conductive layers 104_1 and 104_2 may have a stacked structure of two or more layers. For example, when the conductive layers 104_1 and 104_2 have a two-layer stacked structure, a nitride or an oxide can be used as the first conductive layer (the conductive layer on the insulating layer 106_1 side and the conductive layer on the insulating layer 106_2 side, respectively), and a second conductive layer can be used as one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above metals. Furthermore, for example, when the conductive layer 104_1 and the conductive layer 104_2 have a three-layer stacked structure, the first conductive layer (the conductive layer on the insulating layer 106_1 side and the conductive layer 106_2 side, respectively) can be an alloy containing one or more of the above-mentioned metals as components, or a nitride of the metal or the alloy; the second conductive layer can be an alloy containing one or more of the above-mentioned metals as components; and the third conductive layer can be an alloy containing one or more of the above-mentioned metals as components, or a nitride of the metal or the alloy.

[0181] [Insulating Layer 192, Insulating Layer 194] The insulating layer 192 filling the opening 143 and the insulating layer 194 planarizing the top surface of the transistor 10_1 can each be made of an organic insulating material or an inorganic insulating material, or both. An organic insulating material is preferably used for the insulating layer 192 and the insulating layer 194. For example, by using an organic insulating material for the insulating layer 192 and the insulating layer 194, a film with excellent planarity can be easily formed at a relatively low temperature on a formation surface having steps.

[0182] Specific examples of organic insulating materials that can be used for the insulating layers 192 and 194 include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimideamide resins, siloxane resins, benzocyclobutene-based resins, phenolic resins, and precursors of these resins. Photosensitive materials may also be used as the organic insulating material. Here, photosensitivity refers to the property of being sensitive to ultraviolet light, far ultraviolet light, electron beams, X-rays, and the like. This property is utilized to form a resist pattern by exposure. For exposure of silicon-containing resists, ultraviolet light, and more preferably far ultraviolet light, is primarily used. The raw material monomer used here may be aromatic, but to increase sensitivity, it is more desirable for the structure to be free of aromatic rings. For example, polyimide resins are preferably used for the insulating layers 192 and 194.

[0183] An inorganic insulating material can also be used for the insulating layer 192 and the insulating layer 194. Specific examples of the inorganic insulating material that can be used for the insulating layer 192 and the insulating layer 194 include the inorganic insulating materials that can be used for the insulating layer 110_1 and the insulating layer 110_2. For example, the insulating layer 192 and the insulating layer 194 are preferably made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.

[0184] [Insulating Layer 193] The insulating layer 193 covering the transistor 10_1 is preferably made of an insulating material that does not easily diffuse impurities. Providing the insulating layer 193 can effectively prevent external impurities from diffusing into the transistor 10_1, thereby improving the reliability of the transistor 10_1. Examples of impurities include water and hydrogen. The insulating layer 193 can be an insulating layer containing an inorganic insulating material or an insulating layer containing an organic insulating material. The insulating layer 193 is preferably made of an inorganic insulating material. Specific examples of inorganic insulating materials that can be used for the insulating layer 193 include the inorganic insulating materials that can be used for the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2. For example, the insulating layer 193 is preferably made of silicon nitride, silicon nitride oxide, hafnium oxide, aluminum oxide, or the like.

[0185] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material has at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 102. The shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0186] A flexible substrate may be used as the substrate 102, and the semiconductor device 100 or the like may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the semiconductor device 100 or the like. The peeling layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate 102 and transfer the semiconductor device 100 or the like to another substrate. In this case, the semiconductor device 100 or the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0187] [Composition of Metal Oxide in Semiconductor Layer 108_1 and Semiconductor Layer 108_2] The composition of metal oxide in the semiconductor layer 108_1 and the semiconductor layer 108_2 will be described below.

[0188] The compositions of the metal oxides in the semiconductor layers 108_1 and 108_2 greatly affect the electrical characteristics and reliability of the transistors 10_1 and 10_2, respectively.

[0189] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized.

[0190] When an In—Zn oxide is used for the semiconductor layers 108_1 and 108_2, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or a metal oxide in a range of these values, can be used.

[0191] When an In—Sn oxide is used for the semiconductor layers 108_1 and 108_2, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a ratio close to these, can be used.

[0192] When the semiconductor layer 108_1 and the semiconductor layer 108_2 are made of In-M-Zn oxide, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer 108_1 and the semiconductor layer 108_2 may be made of metal oxides in which the atomic ratio of metal elements is In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=5:1:9, In:M:Zn=5:1:10, In:M:Zn=5:1:11, In:M:Zn=5:1:12, In:M:Zn=5:1:13, In:M:Zn=5:1:14, In:M:Zn=5:1:15, In:M:Zn=5:1:16, In:M:Zn=5:1:17, In:M:Zn=5:1:18, In:M:Zn=5:1:19 ... Metal oxides having a ratio of In:M:Zn=6:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides having a ratio close to these can be used.

[0193] In addition, when the element M has a plurality of metal elements, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range. For example, in the case of an In-Ga-Sn-Zn oxide having gallium and tin as the element M, the sum of the atomic ratio of gallium and the atomic ratio of tin can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range.

[0194] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the number of atoms of metal elements contained in the metal oxide is 30 atomic % to 100 atomic %, preferably 30 atomic % to 95 atomic %, more preferably 35 atomic % to 95 atomic %, more preferably 35 atomic % to 90 atomic %, more preferably 40 atomic % to 90 atomic %, more preferably 45 atomic % to 90 atomic %, more preferably 50 atomic % to 80 atomic %, more preferably 60 atomic % to 80 atomic %, and more preferably 70 atomic % to 80 atomic %. For example, when an In—Ga—Zn oxide is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, the ratio of the number of indium atoms to the total number of indium, gallium, and zinc atoms is preferably in the above-mentioned range.

[0195] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0196] By increasing the indium content of the metal oxide, a transistor with a large on-state current can be obtained. By applying the transistor to a transistor that requires a large on-state current, a semiconductor device with excellent electrical characteristics can be obtained.

[0197] The composition of a metal oxide can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, or quantification may be difficult, or element M may not be detected.

[0198] In this specification, a "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio is described as In:M:Zn = 4:2:3 or a composition near there, this includes a case where, when the atomic ratio of indium is 4, the atomic ratio of M is 1 to 3 and the atomic ratio of zinc is 2 to 4. Furthermore, when an atomic ratio is described as In:M:Zn = 5:1:6 or a composition near there, this includes a case where, when the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 5 and less than 7. Furthermore, when an atomic ratio is described as In:M:Zn = 1:1:1 or a composition near there, this includes a case where, when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 0.1 and less than 2.

[0199] Here, the reliability of a transistor will be described. One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which a transistor is held at a high temperature while an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate relative to the source potential and the drain potential while the transistor is held at a high temperature is called a Positive Bias Temperature (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate while the transistor is held at a high temperature is called a Negative Bias Temperature (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and an NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0200] In an n-channel transistor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows). Therefore, the amount of change in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0201] By using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer 108_1 and the semiconductor layer 108_2, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of fluctuation in threshold voltage in a PBTS test can be obtained. Furthermore, when a metal oxide containing gallium is used, it is preferable to make the gallium content lower than the indium content. This makes it possible to realize a highly reliable transistor.

[0202] One factor that causes the threshold voltage to fluctuate in the PBTS test is carrier trapping into defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect level density, the greater the number of carriers trapped in the defect levels, resulting in significant degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0203] The following is a possible reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in the metal oxide has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the gallium-rich metal oxide and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage.

[0204] More specifically, when In—Ga—Zn oxide is used for the semiconductor layers 108_1 and 108_2, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layers 108_1 and 108_2. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for the semiconductor layers 108_1 and 108_2.

[0205] For the semiconductor layer 108_1 and the semiconductor layer 108_2, it is preferable to use a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is more than 0 atomic % and 50 atomic % or less, preferably 0.1 atomic % to 40 atomic % or less, more preferably 0.1 atomic % to 35 atomic % or less, more preferably 0.1 atomic % to 30 atomic % or less, more preferably 0.1 atomic % to 25 atomic % or less, more preferably 0.1 atomic % to 20 atomic % or less, more preferably 0.1 atomic % to 15 atomic % or less, and more preferably 0.1 atomic % to 10 atomic % or less. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be obtained. Note that by including gallium in the metal oxide, oxygen deficiency (V Ｏ ) is less likely to occur.

[0206] A metal oxide that does not contain gallium may be used for the semiconductor layer 108_1 and the semiconductor layer 108_2. For example, In—Zn oxide may be used for the semiconductor layer 108_1 and the semiconductor layer 108_2. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can improve the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide can result in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Furthermore, a metal oxide that does not contain gallium or zinc, such as indium oxide, may be used for the semiconductor layer 108_1 and the semiconductor layer 108_2. Using a metal oxide that does not contain gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0207] For example, an oxide containing indium and zinc can be used for the semiconductor layer 108_1 and the semiconductor layer 108_2. In this case, a metal oxide having an atomic ratio of metal elements of In:Zn=2:3 or a ratio close thereto can be used.

[0208] Although gallium has been used as a representative example, the present invention can also be applied to a case where the element M is used instead of gallium. For the semiconductor layers 108_1 and 108_2, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of the element M is preferably used. Also, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M is preferably used.

[0209] By using a metal oxide having a low content of the element M for the semiconductor layers 108_1 and 108_2, a transistor having high reliability against application of a positive bias can be obtained. By using the transistor as a transistor that is required to have high reliability against application of a positive bias, a highly reliable semiconductor device can be obtained.

[0210] Next, the reliability of the transistor against light will be described.

[0211] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0212] Increasing the content of the element M in the metal oxide can provide a transistor with high reliability against light. That is, a transistor with a small variation in threshold voltage in an NBTIS test can be provided. Specifically, a metal oxide in which the atomic ratio of the element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in an NBTIS test. The band gap of the metal oxide included in the semiconductor layer 108_1 and the semiconductor layer 108_2 is preferably 2.0 eV or more, more preferably 2.5 eV or more, further preferably 3.0 eV or more, further preferably 3.2 eV or more, further preferably 3.3 eV or more, further preferably 3.4 eV or more, and further preferably 3.5 eV or more.

[0213] For example, the semiconductor layer 108_1 and the semiconductor layer 108_2 can be made of metal oxides having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, or In:M:Zn=1:3:4, or metal oxides having an atomic ratio of these metal elements.

[0214] For the semiconductor layer 108_1 and the semiconductor layer 108_2, a metal oxide in which the ratio of the number of atoms of the element M to the number of atoms of the contained metal element is 20 atomic % to 70 atomic %, preferably 30 atomic % to 70 atomic %, more preferably 30 atomic % to 60 atomic %, more preferably 40 atomic % to 60 atomic %, and more preferably 50 atomic % to 60 atomic % can be suitably used.

[0215] When the semiconductor layer 108_1 and the semiconductor layer 108_2 are made of In—Ga—Zn oxide, a metal oxide having an atomic ratio of indium to gallium equal to or less than that of gallium can be used. For example, a metal oxide having an atomic ratio of metal elements of In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, or In:Ga:Zn=1:3:4, or a ratio thereof close to these, can be used.

[0216] For the semiconductor layer 108_1 and the semiconductor layer 108_2, a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is 20 atomic % or more and 60 atomic % or less, preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0217] By using a metal oxide having a high content of element M for the semiconductor layers 108_1 and 108_2, a transistor with high reliability against light can be obtained. By using the transistor as a transistor that is required to have high reliability against light, a highly reliable semiconductor device can be obtained.

[0218] As described above, the electrical characteristics and reliability of a transistor differ depending on the composition of the metal oxide used for the semiconductor layer 108_1 and the semiconductor layer 108_2. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0219] The semiconductor layer 108_1 and the semiconductor layer 108_2 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 108_1 and the semiconductor layer 108_2 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0220] The two or more metal oxide layers included in the semiconductor layer 108_1 and the semiconductor layer 108_2 may have different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a composition similar thereto and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition similar thereto provided on the first metal oxide layer can be preferably used. Furthermore, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0221] <Configuration Example 2 of Semiconductor Device> Fig. 3 shows a configuration example of a semiconductor device 100A having a different configuration from the semiconductor device 100 shown in Fig. 1A to Fig. 2. Fig. 3 is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in Fig. 1A.

[0222] The semiconductor device 100A shown in FIG. 3 is different from the semiconductor device 100 shown in FIGS. 1A to 2 mainly in that the transistor 10_1 includes a conductive layer 114_1 that functions as a second gate electrode (also referred to as a back gate electrode) and an insulating layer 110s1 that functions as a second gate insulating layer (also referred to as a back gate insulating layer), and that the insulating layer 110_1 is composed of six layers: an insulating layer 110d1, an insulating layer 110e1, an insulating layer 110f1, an insulating layer 110g1, an insulating layer 110h1, and an insulating layer 110i1.

[0223] In the semiconductor device 100A, the insulating layer 110_1 is composed of six layers: an insulating layer 110d1 on the conductive layer 112a1 and the substrate 102, an insulating layer 110e1 on the insulating layer 110d1, an insulating layer 110f1 on the insulating layer 110e1, an insulating layer 110g1 on the insulating layer 110f1, an insulating layer 110h1 on the insulating layer 110g1, and an insulating layer 110i1 on the insulating layer 110h1. A conductive layer 114_1 is provided between the insulating layer 110f1 and the insulating layer 110g1. The conductive layer 112a1, the insulating layer 110d1, the insulating layer 110e1, the insulating layer 110f1, the conductive layer 114_1, the insulating layer 110g1, the insulating layer 110h1, the insulating layer 110i1, and the insulating layer 112b1 have overlapping regions.

[0224] In the semiconductor device 100A, openings 143 reaching the conductive layer 112a1 are provided in the insulating layers 110d1, 110e1, 110f1, the conductive layer 114_1, 110g1, 110h1, 110i1, and 112b1.

[0225] An insulating layer 110s1 is provided in contact with the top surface of the conductive layer 112a1, the side surfaces of the insulating layers 110d1, 110e1, 110f1, the conductive layer 114_1, 110g1, 110h1, 110i1, and the conductive layer 112b1 within the opening 143. The upper end of the insulating layer 110s1 has a curved shape.

[0226] The semiconductor layer 108_1 is provided in contact with the top surface of the conductive layer 112a1 in the opening 143, the side surface of the insulating layer 110s1 in the opening 143, the curved portion of the insulating layer 110s1, and the top surface of the conductive layer 112b1.

[0227] In the transistor 10_1 included in the semiconductor device 100A, one surface of the semiconductor layer 108_1 in the opening 143 faces the conductive layer 104_1 with the insulating layer 106_1 interposed therebetween, and the other surface of the semiconductor layer 108_1 in the opening 143 faces the conductive layer 114_1 with the insulating layer 110s1 interposed therebetween. As described above, the conductive layer 114_1 functions as the second gate electrode of the transistor 10_1. The insulating layer 110s1 also functions as the second gate insulating layer of the transistor 10_1.

[0228] The transistor 10_1 of the semiconductor device 100A has two gate electrodes sandwiching the semiconductor layer 108_1, so that a gate electric field can be applied to carriers in the channel formation region from both sides of the semiconductor layer 108_1. Therefore, the transistor 10_1 can achieve a larger on-state current and a smaller off-state current than the transistor 10_1 of the semiconductor device 100 having only one gate electrode (conductive layer 104_1). The threshold voltage can be shifted toward the normally-off state. Furthermore, the saturation characteristics of the current flowing when the semiconductor device 100A operates in the saturation region can be improved (i.e., the magnitude of the drain current hardly changes with an increase in the drain voltage).

[0229] For example, when the semiconductor device 100A is used in a pixel circuit of a display device using an organic EL device, a high-performance pixel circuit capable of high-speed operation and excellent saturation characteristics can be realized by using the transistor 10_1 as a drive transistor and the transistor 10_2 as a selection transistor.

[0230] The insulating layer 110s1, which functions as the second gate insulating layer of the transistor 10_1, is preferably formed using a material that contains oxygen and releases oxygen by heat treatment or the like. For example, the insulating layer 110s1 can be formed using the same material as that used for the insulating layers 110b1 and 110b2. As a result, when a metal oxide is used for the semiconductor layer 108_1, for example, oxygen contained in the insulating layer 110s1 can be supplied to the metal oxide. As a result, oxygen vacancies in the metal oxide can be repaired, thereby improving the electrical characteristics and reliability of the transistor 10_1.

[0231] The conductive layer 114_1 which functions as the second gate electrode of the transistor 10_1 can be formed using the same material as that which can be used for the conductive layer 104_1 and the conductive layer 104_2.

[0232] Of the six insulating layers constituting the insulating layer 110_1, the insulating layer 110d1, the insulating layer 110f1, the insulating layer 110g1, and the insulating layer 110i1 can be made of the same materials as those used for the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2. The insulating layer 110e1 and the insulating layer 110h1 can be made of the same materials as those used for the insulating layer 110b1 and the insulating layer 110b2.

[0233] As a result, for example, when a metal oxide is used for the semiconductor layer 108_1, oxygen contained in the insulating layers 110e1 and 110h1 can be supplied to the semiconductor layer 108_1 through the insulating layer 110s1. This can repair oxygen vacancies in the metal oxide, thereby improving the electrical characteristics and reliability of the transistor 10_1. Furthermore, oxygen contained in the insulating layer 110e1 can be prevented from diffusing to the conductive layer 112a1 through the insulating layer 110d1 and to the conductive layer 114_1 through the insulating layer 110f1. Similarly, oxygen contained in the insulating layer 110h1 can be prevented from diffusing to the conductive layer 114_1 through the insulating layer 110g1 and to the conductive layer 112b1 through the insulating layer 110i1.

[0234] Regarding the semiconductor device 100A, the contents described in the semiconductor device 100 can be referred to for the points other than those described above.

[0235] <Configuration Example 3 of Semiconductor Device> Fig. 4 shows a configuration example of a semiconductor device 100B having a different configuration from the semiconductor device 100A shown in Fig. 3. Fig. 4 is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in Fig. 1A.

[0236] 4 is different from the semiconductor device 100A shown in Fig. 3 mainly in that the transistor 10_1 includes an insulating layer 116 that covers the conductive layer 114_1 and functions as a blocking film for oxygen and hydrogen, and that the insulating layer 110_1 is composed of three layers, namely, an insulating layer 110a1, an insulating layer 110b1, and an insulating layer 110c1. Also, the shape of the insulating layer 110a1 is different from that of the semiconductor device 100 shown in Fig. 1B.

[0237] In the transistor 10_1 of the semiconductor device 100B, the end portion of the insulating layer 110a1 on the opening 143 side has a shape that protrudes further than the side surface of the insulating layer 110b1 on the opening 143 side, the side surface of the insulating layer 110c1 on the opening 143 side, and the side surface of the conductive layer 112b1 on the opening 143 side.

[0238] Furthermore, a conductive layer 114_1 is provided over the insulating layer 110a1 so as to overlap with the insulating layer 110b1, the insulating layer 110c1, and the conductive layer 112b1. An insulating layer 116 is provided in contact with the top surface and side surface of the conductive layer 114_1. An insulating layer 110s1 is provided in contact with the top surface of the insulating layer 110a1 in the opening 143, the side surface of the insulating layer 116 on the opening 143 side, the side surface of the insulating layer 110b1 on the opening 143 side, the side surface of the insulating layer 110c1 on the opening 143 side, and the side surface of the conductive layer 112b1 on the opening 143 side. The upper end of the insulating layer 110s1 has a curved shape.

[0239] The transistor 10_1 included in the semiconductor device 100B is different from the transistor 10_1 included in the semiconductor device 100A in that the insulating layer 110s1 is not in contact with the conductive layer 112a1. Therefore, it is possible to prevent problems such as a decrease in on-state current of the transistor 10_1 caused by oxygen in the insulating layer 110s1 diffusing toward the conductive layer 112a1 and oxidizing the conductive layer 112a1 to increase its resistance.

[0240] The semiconductor layer 108_1 is provided in contact with the top surface of the conductive layer 112a1 in the opening 143, the side surface of the insulating layer 110a1 on the opening 143 side, the side surface of the insulating layer 110s1 on the opening 143 side, the curved portion of the insulating layer 110s1, and the top surface of the conductive layer 112b1.

[0241] In the transistor 10_1 included in the semiconductor device 100B, one surface of the semiconductor layer 108_1 in the opening 143 faces the conductive layer 104_1 with the insulating layer 106_1 interposed therebetween, and the other surface of the semiconductor layer 108_1 in the opening 143 faces the conductive layer 114_1 with the insulating layer 110s1 and the insulating layer 116 interposed therebetween. As described above, the conductive layer 114_1 functions as a second gate electrode. The insulating layer 110s1 functions as a second gate insulating layer. The insulating layer 116 in a region sandwiched between the conductive layer 114_1 and the insulating layer 110s1 can also function as a second gate insulating layer.

[0242] The insulating layer 116 is preferably formed of a material that functions as a blocking film for oxygen and hydrogen. For example, the insulating layer 116 can be formed using the material that can be used for the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2. By covering the top surface and side surface of the conductive layer 114_1 with the insulating layer 116 formed of such a material as shown in FIG. 4, it is possible to prevent problems, such as a decrease in the conductivity of the conductive layer 114_1 due to diffusion of oxygen contained in the insulating layer 110s1 and the insulating layer 110b1 into the conductive layer 114_1.

[0243] Here, the insulating layer 116 can be formed by a deposition method such as plasma CVD or sputtering. Alternatively, for example, the surface of the conductive layer 114_1 can be oxidized by plasma treatment or the like in an oxygen atmosphere to form the insulating layer 116 covering the top and side surfaces of the conductive layer 114_1. In this case, the insulating layer 116 having the same function as the insulating layer 110a1 and the insulating layer 110c1 can be formed without using a deposition method such as plasma CVD or sputtering. This reduces the number of times the above deposition method is applied, and may improve productivity. For example, productivity can be improved compared to the semiconductor device 100A having six insulating layers that constitute the insulating layer 110_1. In this case, it is preferable to use a material that is easily oxidized by plasma treatment or the like in an oxygen atmosphere for the conductive layer 114_1. For example, aluminum is preferable. In this case, the insulating layer 116 is an insulating layer made of an oxide of an element contained in the conductive layer 114_1. For example, when aluminum is used as the material of the conductive layer 114_1, the insulating layer 116 becomes aluminum oxide.

[0244] With respect to the semiconductor device 100B, the contents described for the semiconductor device 100 and the semiconductor device 100A can be referred to for the points other than those described above.

[0245] Although the semiconductor device 100B and the semiconductor device 100A shown in <Configuration Example 2 of Semiconductor Device> each have a configuration in which the transistor 10_1 has two gate electrodes and the transistor 10_2 has only one gate electrode, this is not limiting. For example, the transistor 10_1 may have only one gate electrode and the transistor 10_2 may have two gate electrodes.

[0246] <Configuration Example 4 of Semiconductor Device> Fig. 5 shows a configuration example of a semiconductor device 100C having a different configuration from the semiconductor device 100 shown in Fig. 1A to Fig. 2. Fig. 5 is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in Fig. 1A.

[0247] The semiconductor device 100C shown in FIG. 5 differs from the semiconductor device 100 shown in FIGS. 1A to 2 mainly in that it has a conductive layer 114_2 instead of the conductive layer 104_2 as a conductive layer that functions as the gate electrode of the transistor 10_2, that it has an insulating layer 110s2 that functions as a gate insulating layer, and that the insulating layer 110_2 is composed of six layers, namely, an insulating layer 110d2, an insulating layer 110e2, an insulating layer 110f2, an insulating layer 110g2, an insulating layer 110h2, and an insulating layer 110i2.

[0248] In the semiconductor device 100C, the insulating layer 110_2 is composed of six layers: an insulating layer 110d2 on the insulating layer 193 and the insulating layer 194; an insulating layer 110e2 on the insulating layer 110d2; an insulating layer 110f2 on the insulating layer 110e2; an insulating layer 110g2 on the insulating layer 110f2; an insulating layer 110h2 on the insulating layer 110g2; and an insulating layer 110i2 on the insulating layer 110h2. A conductive layer 114_2 is provided between the insulating layer 110f2 and the insulating layer 110g2. The conductive layer 112a2, the insulating layer 110d2, the insulating layer 110e2, the insulating layer 110f2, the conductive layer 114_2, the insulating layer 110g2, the insulating layer 110h2, the insulating layer 110i2, and the insulating layer 112b2 have overlapping regions.

[0249] In the semiconductor device 100C, openings 144 reaching the conductive layer 112a2 are provided in the insulating layer 193, the insulating layer 110d2, the insulating layer 110e2, the insulating layer 110f2, the conductive layer 114_2, the insulating layer 110g2, the insulating layer 110h2, the insulating layer 110i2, and the insulating layer 112b2.

[0250] An insulating layer 110s2 is provided in contact with the top surface of the conductive layer 112a2, the side surface of the insulating layer 193, the side surface of the insulating layer 110d2, the side surface of the insulating layer 110e2, the side surface of the insulating layer 110f2, the side surface of the conductive layer 114_2, the side surface of the insulating layer 110g2, the side surface of the insulating layer 110h2, the side surface of the insulating layer 110i2, and the side surface of the conductive layer 112b2, respectively, within the opening 144. The upper end of the insulating layer 110s2 has a curved shape.

[0251] The semiconductor layer 108_2 is provided in contact with the top surface of the conductive layer 112a2 in the opening 144, the side surface of the insulating layer 110s2 in the opening 144, the curved portion of the insulating layer 110s2, and the top surface of the conductive layer 112b2.

[0252] In the transistor 10_2 included in the semiconductor device 100C, the semiconductor layer 108_2 faces the conductive layer 114_2 in the opening 144 with the insulating layer 110s2 interposed therebetween.

[0253] For materials that can be used for the insulating layer 110s2 and the conductive layer 114_2, the descriptions of the insulating layer 110s1 and the conductive layer 114_1 in the semiconductor device 100A in <Configuration Example 2 of Semiconductor Device> can be referred to. For materials that can be used for the insulating layer 110d2, the insulating layer 110e2, the insulating layer 110f2, the insulating layer 110g2, the insulating layer 110h2, and the insulating layer 110i2, the descriptions of the insulating layer 110d1, the insulating layer 110e1, the insulating layer 110f1, the insulating layer 110g1, the insulating layer 110h1, and the insulating layer 110i1 in the semiconductor device 100A in <Configuration Example 2 of Semiconductor Device> can be referred to.

[0254] Here, in the semiconductor device 100 shown in Figures 1A to 2, the semiconductor layer 108_2 of the transistor 10_2 surrounds the gate electrode (conductive layer 104_2) in a planar view, whereas in the semiconductor device 100C shown in Figure 5, the gate electrode (conductive layer 114_2) of the transistor 10_2 surrounds the semiconductor layer 108_2 in a planar view.

[0255] In the transistor 10_2 included in the semiconductor device 100C, the surface on which a channel of the semiconductor layer 108_2 is formed faces the conductive layer 114_2, which can prevent the surface from being directly affected by damage caused by deposition of a layer (e.g., the insulating layer 106_2) formed over the semiconductor layer 108_2. Therefore, the semiconductor device 100 may have a semiconductor layer 108_2 (especially a channel formation region) with fewer defects than the transistor 10_2 included in the semiconductor device 100. On the other hand, in the semiconductor device 100, the gate electrode (conductive layer 104_2) of the transistor 10_2 is provided to cover the opening 144, which can preferably reduce the step or unevenness of the transistor 10_2 compared to the transistor 10_2 included in the semiconductor device 100C.

[0256] Note that in each of the semiconductor devices (semiconductor device 100, semiconductor device 100A, semiconductor device 100B, and semiconductor device 100C) illustrated in FIGS. 1A to 5, the transistor 10_2 has only one gate electrode, but this is not limited thereto. Like the transistor 10_1 included in the semiconductor device 100A illustrated in FIG. 3 and the transistor 10_1 included in the semiconductor device 100B illustrated in FIG. 4, the transistor 10_2 may have two gate electrodes. The transistor 10_2 having two gate electrodes can achieve a larger on-state current than a transistor having only one gate electrode. It can also achieve a smaller off-state current. Furthermore, the threshold voltage can be shifted toward the normally-off state. Furthermore, the saturation characteristics of the current flowing when the transistor operates in the saturation region can be improved.

[0257] With respect to the semiconductor device 100C, the contents described in connection with the semiconductor device 100 can be referred to for the points other than those described above.

[0258] <Example of Manufacturing Method of Semiconductor Device> An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. Here, the semiconductor device 100 shown in FIGS. 1A to 2 is used as an example.

[0259] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0260] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used when film formation is performed using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when forming films of compounds such as oxides, nitrides, and carbides by reactive sputtering.

[0261] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, photo-CVD (photo-CVD) methods that utilize light, etc. Furthermore, CVD methods can be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0262] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0263] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0264] The CVD and ALD methods differ from sputtering methods in that particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0265] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film whose composition changes continuously by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0266] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0267] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0268] When processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0269] There are two typical photolithography methods: one is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed; the other is a method in which a photosensitive thin film is formed, and then the thin film is exposed to light and developed to be processed into a desired shape.

[0270] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0271] For etching the thin film, for example, dry etching, wet etching, or sandblasting can be used.

[0272] Typically, a polishing method such as CMP can be suitably used as the planarization treatment of the thin film. Alternatively, a reflow method, in which the conductive layer is subjected to a heat treatment to fluidize it, can be suitably used. Alternatively, a combination of the reflow method and CMP can be used.

[0273] Alternatively, a process may be used in which a planarizing film is formed on an uneven film surface and then highly anisotropically etched (e.g., dry etching) on ​​the planarizing film to form a film with a flat upper surface, or a process may be used in which a planarizing film and a photoresist are formed in that order on the uneven film surface and then highly anisotropically etched on the planarizing film and the photoresist to fill the recesses with only the planarizing film and flatten the entire upper surface (these processes are sometimes referred to as etch-back processes). The etch-back process does not require a high-temperature (e.g., about 800°C) heating process as in the reflow process, and therefore there is no need to worry about damage to elements during fabrication due to the heating process. Furthermore, the etch-back process is suitable because it can be applied to elements on large substrates that are difficult to process using CMP due to the effects of warping, etc.

[0274] Other examples of the planarization treatment for a thin film include dry etching and plasma treatment. The polishing, dry etching, and plasma treatment may be performed multiple times, or a combination of these may be performed. When a combination of these treatments is performed, the order of the steps is not particularly limited, and may be appropriately determined according to the unevenness of the surface to be treated.

[0275] To precisely process a thin film to a desired thickness, for example, a CMP method is used. In this method, the thin film is first polished at a constant processing speed until a portion of the top surface thereof is exposed. Then, the thin film is polished at a slower processing speed until the thin film reaches the desired thickness, thereby enabling highly precise processing.

[0276] Methods for detecting the end point of polishing include an optical method in which light is irradiated onto the surface of the surface to be treated and changes in the reflected light are detected, a physical method in which changes in the polishing resistance that the processing device receives from the surface to be treated are detected, and a method in which magnetic field lines are applied to the surface to be treated and changes in the magnetic field lines due to the eddy currents that are generated are used.

[0277] After the upper surface of the thin film is exposed, the thickness of the thin film can be controlled with high precision by performing a polishing process at a slow processing speed while monitoring the thickness of the thin film by an optical method such as a laser interferometer. If necessary, the polishing process may be performed multiple times until the thin film reaches the desired thickness.

[0278] 6A to 28C are diagrams illustrating a method for manufacturing the semiconductor device 100. In each figure, A shows a plan view corresponding to FIG. 1A. In each figure, B shows a cross-sectional view taken along dashed line A1-A2 in the plan view shown in FIG. 1A. In each figure, C shows a cross-sectional view taken along dashed line B1-B2 in the plan view shown in FIG. 1A.

[0279] First, a conductive film to be the conductive layer 112a1 is formed over the substrate 102, and then part of the conductive film is removed to form the conductive layer 112a1 (FIGS. 6A to 6C). The conductive film can be formed by, for example, a sputtering method. The conductive film can be processed by one or both of a wet etching method and a dry etching method.

[0280] Subsequently, an insulating film 110a1f, an insulating film 110b1f, and an insulating film 110c1f are formed in this order on the conductive layer 112a1 and the substrate 102.

[0281] The insulating film 110a1f can be made of any of the materials that can be used for the insulating layer 110a1 described above.

[0282] The insulating film 110a1f can be formed using, for example, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide.

[0283] Specifically, the insulating film 110a1f can be formed by, for example, a silicon nitride film by a sputtering method, a PEALD method, or an aluminum oxide film by a sputtering method.

[0284] Alternatively, for example, a structure in which aluminum oxide and silicon nitride are stacked can be used, for example, a structure in which aluminum oxide formed by sputtering and silicon nitride formed by PEALD are stacked.

[0285] The insulating film 110b1f can be made of any of the materials that can be used for the insulating layer 110b1 described above.

[0286] For example, silicon oxide, silicon oxynitride, or the like can be suitably used as the insulating film 110b1f.

[0287] Specifically, the insulating film 110b1f can be formed by, for example, a silicon oxide film by a sputtering method, a silicon oxide film by a PECVD method, or a silicon oxynitride film by a PECVD method.

[0288] Alternatively, for example, a silicon oxide film formed by sputtering and a silicon oxide or silicon oxynitride film formed by PECVD can be stacked and used.

[0289] After the insulating film 110b1f is formed, heat treatment may be performed. By performing the heat treatment, water and hydrogen can be released from the surface and the interior of the insulating film 110b1f.

[0290] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) may be used. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, or the like as possible can prevent hydrogen, water, or the like from being taken into the insulating film 110b1f as much as possible. The heat treatment can be performed using, for example, an oven or a rapid thermal annealing (RTA) device. By using an RTA device, the heat treatment time can be shortened.

[0291] After the heat treatment, a step of supplying oxygen to the insulating film 110b1f may be performed. For example, after the insulating film 110b1f is formed, a metal oxide layer may be formed over the insulating film 110b1f to supply oxygen to the insulating film 110b1f. Alternatively, heat treatment may be performed after the metal oxide layer is formed. By performing heat treatment after the metal oxide layer is formed, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110b1f, and oxygen can be contained in the insulating film 110b1f. In a later step, the oxygen supplied to the insulating film 110b1f is supplied to the semiconductor layer 108_1, thereby reducing oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0292] After the metal oxide layer is formed or after the heat treatment, oxygen may be supplied to the insulating film 110b1f through the metal oxide layer. Examples of a method for supplying oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be preferably used. Examples of apparatus that convert gas into plasma using high-frequency power include a plasma etching apparatus and a plasma ashing apparatus.

[0293] The metal oxide layer may be an insulating layer or a conductive layer, and may be, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0294] For the metal oxide layer, it is preferable to use an oxide material containing one or more of the same elements as those of the semiconductor layer 108_1. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108_1. This allows the metal oxide layer to be formed using the same sputtering target as that of the semiconductor layer 108_1, thereby reducing manufacturing costs.

[0295] When a metal oxide material containing indium and gallium is used for the metal oxide layer, a material having a higher gallium content than the semiconductor layer 108_1 can be used. By using a material having a higher gallium content for the metal oxide layer, the blocking property against oxygen can be further improved. This is preferable because oxygen contained in the insulating film 110b1f can be prevented from being released to the outside.

[0296] The metal oxide layer is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. This allows oxygen to be suitably supplied to the insulating film 110b1f during the formation of the metal oxide layer.

[0297] Next, the metal oxide layer is removed, for example, by wet etching.

[0298] The process of supplying oxygen to the insulating film 110b1f is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, or the like may be supplied to the insulating film 110b1f by ion doping, ion implantation, plasma treatment, or the like. Alternatively, a film that suppresses oxygen desorption may be formed over the insulating film 110b1f, and then oxygen may be supplied to the insulating film 110b1f through the film. The film is preferably removed after supplying oxygen. The film that suppresses oxygen desorption may be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten.

[0299] The insulating film 110c1f can be made of any of the materials that can be used for the insulating layer 110c1 described above.

[0300] For the material and the deposition method that can be used for the insulating film 110c1f, the above description of the material and the deposition method that can be used for the insulating film 110a1f can be referred to.

[0301] Next, a conductive film 112b1f is formed over the insulating film 110c1f (FIGS. 7A to 7C). The conductive film 112b1f can be formed using any of the materials that can be used for the conductive layer 112b1 described above. The conductive film 112b1f can be formed by, for example, a sputtering method.

[0302] Next, a part of the conductive film 112b1f is removed to form a conductive layer 112b1e (FIGS. 8A to 8C). The conductive layer 112b1e may be formed by wet etching or dry etching, or both. The conductive layer 112b1e is formed to have a region overlapping with the conductive layer 112a1.

[0303] Next, a process is performed to remove parts of the conductive layer 112b1e, the insulating film 110c1f, the insulating film 110b1f, and the insulating film 110a1f to form an opening 143 that reaches the conductive layer 112a1. For example, dry etching can be suitably used for this process. By this process, the conductive layer 112b1, the insulating layer 110c1, the insulating layer 110b1, and the insulating layer 110a1 each have an opening (FIGS. 9A to 9C).

[0304] Next, a semiconductor film to be the semiconductor layer 108_1 is formed in contact with the top surface of the conductive layer 112a1 in the opening 143, the side surfaces of the insulating layer 110_1 (insulating layers 110a1, 110b1, and 110c1) in the opening 143, the side surfaces of the conductive layer 112b1 in the opening 143, and the top surface of the conductive layer 112b1. Then, a portion of the semiconductor film is removed by etching to form the semiconductor layer 108_1 ( FIGS. 10A to 10C ). The semiconductor layer 108_1 is provided to have a region overlapping with the opening 143. Furthermore, the semiconductor layer 108_1 is provided so that an end portion thereof has a region in contact with the conductive layer 112b1.

[0305] For the semiconductor film to be the semiconductor layer 108_1, any of the above-described materials that can be used for the semiconductor layer 108_1 can be used as appropriate.

[0306] The semiconductor film to be the semiconductor layer 108_1 can be formed by, for example, a sputtering method. For example, when a metal oxide is used for the semiconductor layer 108_1, the semiconductor layer 108_1 can be formed by a sputtering method using a metal oxide target. The sputtering method is preferable because a film with a low hydrogen content can be formed relatively easily.

[0307] When a metal oxide is used for the semiconductor layer 108_1, the semiconductor layer 108_1 can be formed by an ALD method using a precursor containing a constituent metal element and an oxidizing agent.

[0308] For example, when forming an In—Ga—Zn oxide, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0309] As the precursor containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and the like can be used.

[0310] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0311] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0312] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0313] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form films with different compositions successively.

[0314] The ALD method is preferably used to form the semiconductor film to be the semiconductor layer 108_1 because the semiconductor layer 108_1 can be formed with a uniform thickness on the side surface of the insulating layer 110_1.

[0315] After the semiconductor film to be the semiconductor layer 108_1 is formed, heat treatment may be performed. The heat treatment can reduce water and hydrogen contained in the semiconductor film and supply oxygen from the insulating layer 110_1 to the semiconductor film. Note that the heat treatment may be performed after the semiconductor film is processed.

[0316] The substrate temperature (stage temperature) during the formation of the semiconductor layer 108_1 is preferably from room temperature (25° C.) to 200° C., more preferably from room temperature to 130° C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when a large-area glass substrate is used.

[0317] The higher the substrate temperature during the formation of the metal oxide layer, the higher the crystallinity of the metal oxide layer that can be formed.Furthermore, the higher the oxygen flow rate ratio, the higher the crystallinity of the metal oxide layer that can be formed.

[0318] Subsequently, the insulating layer 106_1 is formed to cover the semiconductor layer 108_1, the conductive layer 112b1, and the insulating layer 110c1 (FIGS. 11A to 11C). The insulating layer 106_1 has regions in contact with the top and side surfaces of the semiconductor layer 108_1, the top and side surfaces of the conductive layer 112b1, and the top surface of the insulating layer 110c1.

[0319] The insulating layer 106_1 can be formed using any of the above-described materials as appropriate.

[0320] The insulating layer 106_1 can be formed by, for example, an ALD method. The ALD method is preferable because the insulating layer 106_1 can be formed with good coverage over the semiconductor layer 108_1 formed to cover the opening 143. Note that, if the semiconductor layer 108_1 can be sufficiently covered, a method other than the ALD method may be used to form the insulating layer 106_1. For example, a PECVD method, a sputtering method, or the like can be used. This allows the insulating layer 106_1 to be formed at a higher rate than when the ALD method is used, thereby increasing productivity.

[0321] Next, a conductive film 104_1f is formed over the insulating layer 106_1 (FIGS. 12A to 12C). The conductive film 104_1f can be formed using any of the materials that can be used for the conductive layer 104_1 described above. The conductive film 104_1f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate. The conductive film 104_1f is preferably formed in contact with the insulating layer 106_1 that faces the side surface of the insulating layer 110_1 in the opening 143. Therefore, the conductive film 104_1f is preferably formed by a method that has good coverage or embedding properties, and more preferably by a CVD method, an ALD method, or the like.

[0322] Subsequently, an insulating film 192f is formed over the conductive film 104_1f. The insulating film 192f can be formed using any of the materials that can be used for the insulating layer 192 described above. The insulating film 192f is formed so as to fill the opening 143. The insulating film 192f is formed so that the height of its top surface is higher than the height of the top surface of any region of the conductive film 104_1f. For example, when an organic insulating material such as polyimide resin is used for the insulating film 192f, the insulating film 192f having a substantially flat top surface can be easily formed by a method such as spin coating.

[0323] Next, light 139 (for example, visible light or ultraviolet light) is irradiated onto the insulating film 192f through the mask 136 to expose the region of the insulating film 192f that does not overlap with the mask 136 (FIGS. 13A to 13C). Here, when a positive photosensitive resin composition such as polyimide resin is used for the insulating film 192f, the light 139 is irradiated via the mask 136 onto the region where the insulating layer 192 will not be formed in a later step.

[0324] Subsequently, the exposed region of the insulating film 192f is removed by development, thereby forming an insulating layer 192e (FIGS. 14A to 14C). The insulating layer 192e is formed in a region overlapping with the opening 143. In addition, the upper surface of the conductive film 104_1f is exposed in the region from which the insulating film 192f is removed by development. Here, when a polyimide resin is used for the insulating film 192f, it is preferable to use an alkaline solution as the developer, such as a tetramethylammonium hydroxide (TMAH) aqueous solution.

[0325] After the development, a step of removing the residue (so-called scum) remaining after the development may be carried out. For example, the residue can be removed by ashing using oxygen plasma. A step of removing the residue may also be carried out after each of the development steps described below.

[0326] Subsequently, the insulating layer 192e is subjected to an etch-back process, which forms an insulating layer 192 having a flat upper surface and filling the entire opening 143 (FIGS. 15A to 15C).

[0327] 13A to 15C , the method of using etch-back treatment to form the insulating layer 192 is described, but this is not limited to this. In one embodiment of the present invention, the insulating layer 192 can also be formed without using etch-back treatment.

[0328] 12A to 12C, the insulating film 192f is formed over the conductive film 104_1f. Note that the thickness of the insulating film 192f is smaller than that in the case where the etch-back treatment is performed.

[0329] Next, as described above, the insulating film 192f is irradiated with light 139 through the mask 136, and the regions of the insulating film 192f that do not overlap with the mask 136 are exposed to light (FIGS. 16A to 16C).

[0330] Subsequently, development is performed to remove the exposed regions of the insulating film 192f, thereby forming the insulating layer 192 only in the region overlapping the opening 143 and exposing the top surface of the conductive film 104_1f in other regions (FIGS. 17A to 17C). In this way, depending on the film thickness of the insulating film 192f when it is formed, it is possible to form the insulating layer 192 without using an etch-back process, thereby reducing the number of steps. However, when this method is used, a gently convex shape is likely to be formed on the top surface of the insulating layer 192, as shown in FIGS. 17B and 17C. Therefore, if it is desired to further improve the flatness of the top surface of the insulating layer 192, it may be preferable to use the etch-back process described above.

[0331] Next, a conductive film 112a2f is formed over the insulating layer 192 and the conductive film 104_1f (FIGS. 18A to 18C). The conductive film 112a2f can be formed using any of the materials that can be used for the conductive layer 112a2 described above. The conductive film 112a2f can be formed by a sputtering method, for example.

[0332] Next, the conductive layer 112a2 and the conductive layer 104_1 are formed by removing parts of the conductive film 112a2f and the conductive film 104_1f ( FIGS. 19A to 19C ). The conductive layer 112a2 and the conductive layer 104_1 are formed to have regions overlapping with the opening 143. The ends of the conductive layer 112a2 and the conductive layer 104_1 are formed to approximately coincide with each other in a plan view. Furthermore, the top surface of the insulating layer 106_1 is exposed in the regions from which the conductive films 112a2f and 104_1f are removed. The conductive layer 112a2 and the conductive layer 104_1 may be formed by wet etching or dry etching, or both.

[0333] As a result, the transistor 10_1 is formed.

[0334] Subsequently, an insulating film 193f is formed over the conductive layer 112a2 and the insulating layer 106_1. The insulating film 193f is provided in contact with the top surface and side surfaces of the conductive layer 112a2, the side surfaces of the conductive layer 104_1, and the top surface of the insulating layer 106_1. The insulating film 193f can be formed using any of the materials that can be used for the insulating layer 193 described above. The insulating film 193f can be formed by, for example, an ALD method, a PECVD method, a sputtering method, or the like.

[0335] Next, an insulating film 194f is formed on the insulating film 193f (FIGS. 20A to 20C). The insulating film 194f can be formed using any of the materials that can be used for the insulating layer 194 described above. The insulating film 194f is formed so that its upper surface is higher than the upper surface of any region of the insulating film 193f. For example, when an organic insulating material such as polyimide resin is used for the insulating film 194f, the insulating film 194f can be easily formed with a substantially flat upper surface by a method such as spin coating.

[0336] Next, an etch-back process is performed on the insulating film 194f. The etch-back process is performed until the highest region of the insulating film 193f seen from the substrate surface (the region overlapping the conductive layer 112a2) is exposed. This process forms an insulating layer 194 having a flat upper surface and a height that is approximately the same as the upper surface of the highest region of the insulating film 193f seen from the substrate surface (FIGS. 21A to 21C).

[0337] 20A to 21C, the method of using etch-back treatment to form the insulating layer 194 is described, but this is not limited to this. In one embodiment of the present invention, the insulating layer 194 can also be formed without using etch-back treatment.

[0338] 20A to 20C, the insulating film 193f is formed, and then the insulating film 194f is formed on the insulating film 193f. However, at this time, the insulating film 194f is formed to have a thickness thinner than that in the case where the etch-back process is performed.

[0339] Next, light 139 is irradiated onto the insulating film 194f through the mask 138, and the regions of the insulating film 194f that do not overlap with the mask 138 are exposed to light (FIGS. 22A to 22C).

[0340] Subsequently, development is performed to remove the exposed areas of the insulating film 194f, thereby forming the insulating layer 194 only in the areas that do not overlap the opening 143 and exposing the top surface of the insulating film 193f in other areas (FIGS. 23A to 23C). In this way, depending on the thickness of the insulating film 194f when it is formed, it is possible to form the insulating layer 194 without using an etch-back process, thereby reducing the number of steps. However, when using this method, a gently convex shape is likely to form on the top surface of the insulating layer 194, as shown in FIGS. 23B and 23C. Therefore, if it is desired to further increase the flatness of the top surface of the insulating layer 194, it may be preferable to use the etch-back process described above.

[0341] Next, the insulating film 110a2f, the insulating film 110b2f, the insulating film 110c2f, and the conductive film 112b2f are formed in this order over the insulating layer 194 and the insulating film 193f (FIGS. 24A to 24C). For materials that can be used for the insulating film 110a2f, the insulating film 110b2f, the insulating film 110c2f, and the conductive film 112b2f, as well as their formation methods, the descriptions of the insulating film 110a1f, the insulating film 110b1f, the insulating film 110c1f, and the conductive film 112b1f can be referred to, respectively.

[0342] Next, a part of the conductive film 112b2f is removed to form a conductive layer 112b2e (FIGS. 25A to 25C). The conductive layer 112b2e may be formed by wet etching or dry etching, or both. The conductive layer 112b2e is formed to have a region overlapping with the conductive layer 112a2.

[0343] Next, a process is performed to remove parts of the conductive layer 112b2e, the insulating film 110c2f, the insulating film 110b2f, the insulating film 110a2f, and the insulating film 193f, thereby forming an opening 144 that reaches the conductive layer 112a2. For example, dry etching can be suitably used for this process. By this process, the conductive layer 112b2, the insulating layer 110c2, the insulating layer 110b2, the insulating layer 110a2, and the insulating layer 193, each having an opening, are formed ( FIGS. 26A to 26C ).

[0344] Next, a semiconductor film to be the semiconductor layer 108_2 is formed in contact with the top surface of the conductive layer 112a2 in the opening 144, the side surfaces of the insulating layer 193 in the opening 144, the side surfaces of the insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2) in the opening 144, the side surfaces of the conductive layer 112b2 in the opening 144, and the top surface of the conductive layer 112b2. Then, a portion of the semiconductor film is removed by etching to form the semiconductor layer 108_2 ( FIGS. 27A to 27C ). The semiconductor layer 108_2 is provided to have a region overlapping with the opening 144. The semiconductor layer 108_2 is also provided so that an end portion thereof is in contact with the conductive layer 112b2.

[0345] For materials, formation methods, and the like that can be used for the semiconductor film to be the semiconductor layer 108_2, the above description of materials, formation methods, and the like that can be used for the semiconductor film to be the semiconductor layer 108_1 can be referred to.

[0346] Next, the insulating layer 106_2 is formed to cover the semiconductor layer 108_2, the conductive layer 112b2, and the insulating layer 110c2 ( FIGS. 28A to 28C ). The insulating layer 106_2 has a region in contact with the top surface and side surfaces of the semiconductor layer 108_2, the top surface and side surfaces of the conductive layer 112b2, and the top surface of the insulating layer 110c2. For materials that can be used for the insulating layer 106_2, a formation method, and the like, the above description of materials that can be used for the insulating layer 106_1, a formation method, and the like can be referred to.

[0347] Next, a conductive film to be the conductive layer 104_2 is formed over the insulating layer 106_2. For materials, formation methods, and the like that can be used for the conductive film, the above description of materials, formation methods, and the like that can be used for the conductive film 104_1f can be referred to.

[0348] Next, a part of the conductive film to be the conductive layer 104_2 is removed to form the conductive layer 104_2. The conductive layer 104_2 is formed to have a region overlapping with the opening 144. In addition, the top surface of the insulating layer 106_2 is exposed in the region where the conductive film to be the conductive layer 104_2 is removed. The conductive layer 104_2 may be formed by one or both of a wet etching method and a dry etching method.

[0349] As a result, the transistor 10_2 is formed.

[0350] Through the above steps, the semiconductor device 100 can be manufactured (FIGS. 1A to 2).

[0351] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0352] Embodiment 2 A semiconductor device according to one embodiment of the present invention can be applied to, for example, a display device. In this embodiment, circuits, layouts, and the like that can be applied to the display device will be described.

[0353] 29 is a block diagram illustrating a display device 300 to which the semiconductor device of one embodiment of the present invention can be applied. The display device 300 includes a display portion 435, a first driver circuit portion 431, and a second driver circuit portion 432.

[0354] The display unit 435 has a plurality of pixels 230 arranged in a matrix of m rows (m is an integer of 1 or more) and n columns (n ​​is an integer of 1 or more).

[0355] The display unit 435 corresponds to, for example, the display unit 168 in FIG. 34 described in embodiment 3, and the pixel 230 corresponds to, for example, the sub-pixels 11R, 11G, 11B, and pixel 210 in FIG. 34 described in embodiment 3.

[0356] 29, the pixel 230 in the first row and nth column is indicated as pixel 230[1,n], the pixel 230 in the mth row and first column is indicated as pixel 230[m,1], and the pixel 230 in the mth row and nth column is indicated as pixel 230[m,n]. Also, any pixel 230 included in the display unit 435 may be indicated as pixel 230[r,s]. r is an integer greater than or equal to 1 and less than or equal to m, and s is an integer greater than or equal to 1 and less than or equal to n.

[0357] The circuit included in the first drive circuit unit 431 functions as, for example, a scanning line drive circuit. The circuit included in the second drive circuit unit 432 functions as, for example, a signal line drive circuit. Note that some kind of circuit may be provided at a position facing the first drive circuit unit 431 across the display unit 435. Note that some kind of circuit may be provided at a position facing the second drive circuit unit 432 across the display unit 435. Note that the circuits included in the first drive circuit unit 431 and the second drive circuit unit 432 are collectively referred to as a peripheral drive circuit 433.

[0358] The peripheral driver circuit 433 can include various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a multiplexer circuit, a demultiplexer circuit, and a logic circuit. The semiconductor device 100 according to one embodiment of the present invention or the like can be used for the peripheral driver circuit 433. Note that the transistors included in the peripheral driver circuit and the transistors included in the pixel 230 may be formed in the same process.

[0359] The display device 300 also has m wires 436 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the first drive circuit unit 431, and n wires 437 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the second drive circuit unit 432.

[0360] 29 shows an example in which the wiring 436 and the wiring 437 are connected to the pixel 230. However, the wiring 436 and the wiring 437 are just an example, and the wirings connected to the pixel 230 are not limited to the wiring 436 and the wiring 437.

[0361] 30A to 30D show configuration examples of the pixel 230. The pixel 230 includes a pixel circuit 51 (a pixel circuit 51A, a pixel circuit 51B, a pixel circuit 51C, or a pixel circuit 51D) and a light-emitting element 61.

[0362] The light-emitting element described in the present embodiment and the like refers to a self-luminous display element such as an organic EL element (also called an OLED (Organic LED)). Note that the light-emitting element connected to the pixel circuit can be a self-luminous light-emitting element such as an LED, a micro LED, a QLED (Quantum-dot LED), or a semiconductor laser.

[0363] A pixel circuit 51A shown in FIG. 30A is a 2Tr1C type pixel circuit having a transistor 52A, a transistor 52B, and a capacitor 53.

[0364] One of the source and drain of the transistor 52A is connected to the wiring SL, and the gate of the transistor 52A is connected to the wiring GL. The other of the source and drain of the transistor 52A is connected to the gate of the transistor 52B and one terminal of the capacitor 53. One of the source and drain of the transistor 52B is connected to the wiring ANO. The other of the source and drain of the transistor 52B is connected to the other terminal of the capacitor 53 and the anode of the light-emitting element 61. The cathode of the light-emitting element 61 is connected to the wiring VCOM. A region where the other of the source and drain of the transistor 52A, the gate of the transistor 52B, and one terminal of the capacitor 53 are connected functions as a node ND.

[0365] The wiring GL corresponds to the wiring 436, and the wiring SL corresponds to the wiring 437. The wiring VCOM is a wiring that applies a potential for supplying a current to the light-emitting element 61. The transistor 52A has a function of controlling the conduction state (a state in which a current can flow) or the non-conduction state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM. The transistor 52A can also be called a selection transistor because it functions as a switch for controlling the selection and non-selection of the pixel 230.

[0366] By turning on the transistor 52A, an image signal is supplied from the wiring SL to the node ND. Then, by turning off the transistor 52A, the image signal is held in the node ND. In order to reliably hold the image signal supplied to the node ND, it is preferable to use a transistor with low off-state current as the transistor 52A. For example, it is preferable to use an OS transistor as the transistor 52A.

[0367] The transistor 52B has a function of controlling the amount of current flowing through the light-emitting element 61. The transistor 52B can also be called a driving transistor. The capacitor 53 has a function of holding the gate potential of the transistor 52B. The intensity of light emitted by the light-emitting element 61 is controlled in accordance with an image signal supplied to the gate (node ​​ND) of the transistor 52B.

[0368] The pixel circuit 51B shown in Fig. 30B is a 3Tr1C type pixel circuit having a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The pixel circuit 51B shown in Fig. 30B has a configuration in which a transistor 52C is added to the pixel circuit 51A shown in Fig. 30A.

[0369] The source or the drain of the transistor 52C is connected to the other of the source or the drain of the transistor 52B. The other of the source or the drain of the transistor 52C is connected to a wiring V0. For example, a reference potential is supplied to the wiring V0. The gate of the transistor 52C is connected to a wiring GL.

[0370] The transistor 52C has a function of controlling conduction or non-conduction between the other of the source and the drain of the transistor 52B and the wiring V0 based on the potential of the wiring GL. The wiring V0 is a wiring for applying a reference potential. When an n-channel transistor is used as the transistor 52B, the reference potential of the wiring V0 applied via the transistor 52C can suppress variations in the gate-source voltage of the transistor 52B.

[0371] Furthermore, the wiring V0 can be used to acquire a current value that can be used to set pixel parameters. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the outside.

[0372] 30C has a configuration in which the transistor 52B in the pixel circuit 51A in FIG. 30A has a back gate. The back gate of the transistor 52B is connected to the other of the source or the drain of the transistor 52B, the other terminal of the capacitor 53, and the anode of the light-emitting element 61. Connecting the back gate of the transistor 52B to the other of the source or the drain of the transistor 52B can make the operation of the transistor 52B more stable.

[0373] The pixel circuit 51D shown in Figure 30D is configured such that, in the pixel circuit 51B shown in Figure 30B, the transistor 52B has a back gate, and the wiring connected to the gate of the transistor 52A and the wiring connected to the gate of the transistor 52C are independent of each other.

[0374] The back gate of the transistor 52B is connected to the other of the source and the drain of the transistor 52B, one of the source and the drain of the transistor 52C, the other terminal of the capacitor 53, and the anode of the light-emitting element 61. As described above in the pixel circuit 51C shown in Figure 30C, connecting the back gate of the transistor 52B to the other of the source and the drain of the transistor 52B can make the operation of the transistor 52B more stable.

[0375] 30B , the pixel circuit 51B includes a wiring connected to the gate of the transistor 52A and a wiring connected to the gate of the transistor 52C. The wiring connected to the gate of the transistor 52A and the wiring connected to the gate of the transistor 52C are separately provided, which allows different potentials to be applied to the gates of the two transistors, thereby allowing the two transistors to operate independently.

[0376] 31 and 32 show a configuration example of a pixel 230 having the pixel circuit 51D shown in Fig. 30D. Fig. 31 is a plan view of the pixel 230 having the pixel circuit 51D. Fig. 31 shows a plan view of two rows of pixel circuits 51D. Fig. 32 is a cross-sectional view taken along dashed dotted line C1-C2 shown in Fig. 31.

[0377] Of the three transistors (transistor 52A, transistor 52B, and transistor 52C) shown in Figure 32, transistor 52A and transistor 52B correspond to the two transistors that constitute the semiconductor device 100A shown in Figure 3, and specifically, transistor 52B corresponds to transistor 10_1 and transistor 52A corresponds to transistor 10_2, respectively.

[0378] For details of the structures of the transistors 10_1 and 10_2, the description of the above embodiments can be referred to.

[0379] The transistor 52C includes a conductive layer 104_3, an insulating layer 106_1, a semiconductor layer 108_3, a conductive layer 112a4, and a conductive layer 112b1. The conductive layer 104_3 functions as a gate electrode. A part of the insulating layer 106_1 functions as a gate insulating layer. The conductive layer 112a4 functions as one of a source electrode and a drain electrode. The conductive layer 112b1 functions as the other of the source electrode and the drain electrode (as described above, the conductive layer 112b1 also functions as the other of the source electrode and the drain electrode of the transistor 52B). An entire region of the semiconductor layer 108_3 that overlaps with the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. A region of the semiconductor layer 108_3 that is in contact with the source electrode functions as a source region, and a region that is in contact with the drain electrode functions as a drain region.

[0380] A conductive layer 112a3 overlapping with the transistors 52A, 52B, and 52C and extending in a direction parallel to the conductive layer 112b1 in a plan view is provided over the substrate 102. An insulating layer 197 having an opening in a region overlapping with the transistor 52C is provided over the conductive layer 112a3. A portion of the conductive layer 112a4 of the transistor 52C fills the opening and is in contact with a portion of the top surface of the conductive layer 112a3 through the opening. On the other hand, the insulating layer 197 is provided under (on the substrate 102 side of) the conductive layer 112a1 of the transistor 52B and is not in contact with the conductive layer 112a3.

[0381] An insulating layer 196 is provided over the conductive layer 104_3 so as to fill a recess formed in the conductive layer 104_3. The insulating layer 196 has a substantially flat top surface. The insulating layer 196 can be made of the same material as the insulating layer 192.

[0382] A conductive layer 112a5 is provided over the insulating layer 196 and the conductive layer 104_3. Ends of the conductive layer 112a5 and those of the conductive layer 104_3 are generally aligned in a plan view. The conductive layer 112a5 can be formed using the same material as the conductive layer 112a2.

[0383] An insulating layer 193 is provided to cover the transistor 52B and the transistor 52C, and an insulating layer 194 having a substantially planarized top surface is provided to fill steps or unevenness on the insulating layer 193. The insulating layer 110_2 and the transistor 52A are provided in a region on the insulating layer 194 that overlaps with the transistor 52B, and the insulating layer 110_2, the conductive layer 112b2, and the insulating layer 106_2 are provided in this order in a region on the insulating layer 194 that overlaps with the transistor 52C.

[0384] 32 shows the conductive layer 112b2 as being divided on either side of the opening 137, but as shown in Fig. 31, the conductive layer 112b2 is provided so as to bypass the opening 137 in plan view. Therefore, the conductive layer 112b2 is not divided by the opening 137 and extends as a single wiring.

[0385] An insulating layer 195 is provided over the conductive layer 104_2 and the insulating layer 106_2. The insulating layer 195 preferably functions as a protective layer for the transistor. The insulating layer 195 is preferably formed using a material through which impurities such as water and hydrogen are less likely to diffuse. This allows the insulating layer 195 to function as a barrier layer. With such a structure, diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the display device.

[0386] An insulating layer 235 is provided over the insulating layer 195. The insulating layer 235 preferably functions as a planarization layer that fills in steps or unevenness formed on the transistor 52A or the like and planarizes the top surface.

[0387] An opening 137 reaching the conductive layer 114_1 is provided in the insulating layer 110_1, the conductive layer 112b1, the insulating layer 106_1, the insulating layer 193, the insulating layer 194, the insulating layer 110_2, the insulating layer 106_2, the insulating layer 195, and the insulating layer 235 located over the conductive layer 114_1. The sidewalls and bottom surfaces of the opening 137 (the upper surface of the conductive layer 114_1 in the opening 137, the side surface of the insulating layer 110_1 in the opening 137, the The conductive layer 111 is provided in contact with the following: a side surface of the conductive layer 112b1 in the opening 137, a side surface of the insulating layer 106_1 in the opening 137, a side surface of the insulating layer 193 in the opening 137, a side surface of the insulating layer 194 in the opening 137, a side surface of the insulating layer 110_2 in the opening 137, a side surface of the insulating layer 106_2 in the opening 137, a side surface of the insulating layer 195 in the opening 137, and a side surface of the insulating layer 235 in the opening 137. The conductive layer 111 functions as a pixel electrode. The conductive layer 111 is in contact with the conductive layer 112b1 and the conductive layer 114_1 through the opening 137. That is, the conductive layer 111, the conductive layer 112b1, and the conductive layer 114_1 are connected to each other.

[0388] In the case of the pixel circuit 51D shown in Figure 30D, the conductive layer 111 corresponds to the anode of the light-emitting element 61, the conductive layer 112b1 corresponds to one of the source or drain of the transistor 52C and the other of the source or drain of the transistor 52B, and the conductive layer 114_1 corresponds to the back gate of the transistor 52B.

[0389] Fig. 33 shows a cross-sectional view of a configuration example of a pixel 230 including a pixel circuit 51D, which is different from the configuration example shown in Fig. 32. The configuration example shown in Fig. 33 differs from the configuration example shown in Fig. 32 in that a transistor 52C does not include a conductive layer 112a4, the configuration of the pixel electrode, and the like.

[0390] 33 , the transistor 52C does not include the conductive layer 112a4, and part of the bottom surface of the semiconductor layer 108_3 is in direct contact with part of the top surface of the conductive layer 112a3 through an opening in the insulating layer 197. In this case, the conductive layer 112a3 can function as one of the source electrode and the drain electrode of the transistor 52C and as a wiring. Therefore, the number of steps can be reduced because the conductive layer 112a4 does not need to be provided.

[0391] In addition, in the example structure shown in Figure 33, conductive layers that function as pixel electrodes are separately provided in two openings that are provided for connection to the conductive layer 114_1 etc., and are connected to each other. Specifically, an opening 147 reaching the conductive layer 114_1 is provided in the first layer of the insulating layer 110_1, the conductive layer 112b1, the insulating layer 106_1, the insulating layer 193, the insulating layer 194, and the insulating layer 110_2 on the conductive layer 114_1, and a conductive layer 111_1 is provided in contact with the sidewall and bottom surface of the opening 147 (the top surface of the conductive layer 114_1 in the opening 147, the side surface of the insulating layer 110_1 in the opening 147, the side surface of the conductive layer 112b1 in the opening 147, the side surface of the insulating layer 106_1 in the opening 147, the side surface of the insulating layer 193 in the opening 147, the side surface of the insulating layer 194 in the opening 147, and the side surface of the first layer of the insulating layer 110_2 in the opening 147), and a part of the top surface of the first layer of the insulating layer 110_2. In addition, an opening 157 reaching the top surface of the conductive layer 111_1 is provided in the second and third layers of the insulating layer 110_2, the insulating layer 106_2, the insulating layer 195, and the insulating layer 235, and a conductive layer 111_2 is provided in contact with the sidewalls and bottom surface of the opening 157 (the top surface of the conductive layer 111_1 in the opening 157, the side surfaces of the second and third layers of the insulating layer 110_2 in the opening 157, the side surfaces of the insulating layer 106_2 in the opening 157, the side surfaces of the insulating layer 195 in the opening 157, and the side surfaces of the insulating layer 235 in the opening 157).

[0392] In this way, by forming two openings for connection to the conductive layer 114_1 etc., each opening can be formed shallower, which allows finer openings to be formed with a higher yield than when only one opening is formed.

[0393] By using the semiconductor device of one embodiment of the present invention in a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced. Therefore, the resolution of the display device can be improved. For example, a display device having a resolution of 1,000 ppi to 10,000 ppi, preferably 2,000 ppi to 9,000 ppi, more preferably 3,000 ppi to 8,000 ppi, further preferably 4,000 ppi to 8,000 ppi, further preferably 5,000 ppi to 8,000 ppi, and further preferably 6,000 ppi to 8,000 ppi can be realized.

[0394] Furthermore, by reducing the area occupied by the pixel circuit, it is possible to increase the number of pixels (resolution) of the display device, and it is possible to realize a display device with extremely high resolution, such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K2K (3840 x 2160 pixels), or 8K4K (7680 x 4320 pixels).

[0395] Therefore, by using the semiconductor device of one embodiment of the present invention in a pixel circuit of a display device, the display quality of the display device can be improved. Furthermore, in a bottom-emission display device using an EL element, the aperture ratio of the pixel can be increased. A pixel with a high aperture ratio can emit light with the same luminance as a pixel with a low aperture ratio, but with a lower current density than a pixel with a low aperture ratio. Therefore, the reliability of the display device can be improved.

[0396] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0397] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0398] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used in electronic devices having relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproducing devices.

[0399] The display device of the present embodiment can be a high-definition display device, and can therefore be used as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and eyeglass-type AR devices.

[0400] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0401] [Display Device 50A] FIG. 34 shows a perspective view of the display device 50A.

[0402] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 34, the substrate 152 is indicated by a dashed line.

[0403] The display device 50A has a display unit 168, a connection unit 140, a circuit unit 164, wiring 165, etc. Fig. 34 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 34 can also be said to be a display module having the display device 50A, an IC, and an FPC.

[0404] The connection portion 140 is provided on the outside of the display portion 168. The connection portion 140 can be provided along one side or multiple sides of the display portion 168. There may be one or multiple connection portions 140. FIG. 34 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion. The connection portion 140 connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0405] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0406] The wiring 165 has a function of supplying signals and power to the display portion 168 and the circuit portion 164. The signals and power are input to the wiring 165 from the outside via the FPC 172 or input to the wiring 165 from the IC 173.

[0407] 34 shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like. For example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173. The display device 50A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method, or the like.

[0408] The semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 168 and the circuit portion 164 of the display device 50A.

[0409] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0410] The display section 168 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 210. Fig. 34 shows an enlarged view of one pixel 210.

[0411] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0412] The pixel 210 shown in FIG. 34 has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light.

[0413] Each of the sub-pixels 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0414] Various elements can be used as the display element, for example, a liquid crystal element and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements using microcapsules, electrophoresis, electrowetting, or electronic liquid powder (registered trademark) methods, etc. Furthermore, a QLED using a light source and color conversion technology using quantum dot materials may also be used.

[0415] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0416] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs, OLEDs, semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0417] Examples of the light-emitting substance contained in the light-emitting element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material), and an inorganic compound (quantum dot material, etc.).

[0418] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0419] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0420] In this embodiment, a case where a light-emitting element is used as a display element will be mainly described as an example.

[0421] Note that the display device of one embodiment of the present invention may be any of a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type that emits light toward a substrate on which a light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0422] Figure 35 shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 168, a portion of the connection section 140, and a portion of the area including the end portion are cut away.

[0423] 35 includes transistors 205D, 205R, 205G, 205B, 206R, 206G, and 206B, as well as light-emitting elements 130R, 130G, and 130B, between substrates 151 and 152. The light-emitting element 130R is a display element included in the sub-pixel 11R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 11B that emits blue light.

[0424] The display device 50A employs an SBS structure, which allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in the selection of materials and configurations, and facilitating improvements in brightness and reliability.

[0425] The display device 50A is a top-emission type, which allows transistors and the like to be arranged overlapping the light-emitting region of the light-emitting element, thereby enabling a higher pixel aperture ratio than a bottom-emission type.

[0426] The transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are all formed over a substrate 151. These transistors can be manufactured using the same material and the same process.

[0427] In this embodiment, OS transistors are used as the transistors 205D, 205R, 205G, 205B, 206R, 206G, and 206B. The transistor 10_1 of one embodiment of the present invention can be used as the transistors 205D, 205R, 205G, and 205B, for example. The transistor 10_2 of one embodiment of the present invention can be used as the transistors 206R, 206G, and 206B, for example. The transistor 10_2 of one embodiment of the present invention can also be used as the transistor 205D. That is, the display device 50A includes either or both of the transistor 10_1 and the transistor 10_2 of one embodiment of the present invention in both the display portion 168 and the circuit portion 164. By using a semiconductor device of one embodiment of the present invention in which the transistor 10_1 and the transistor 10_2 are provided so as to overlap each other in the display portion 168 (the semiconductor device 100A shown in FIG. 3 is illustrated in FIG. 35 ), the pixel size can be reduced, and high definition can be achieved. Furthermore, by using the transistor 10_1 or the transistor 10_2 of one embodiment of the present invention for the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, and a narrower frame can be achieved. For the transistors 10_1 and 10_2 of one embodiment of the present invention, the description of the above embodiment can be referred to.

[0428] Specifically, the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B each include a conductive layer 104_1 functioning as a gate electrode, an insulating layer 106_1 functioning as a gate insulating layer, a conductive layer 112a1 functioning as one of a source electrode and a drain electrode, a conductive layer 112b1 functioning as the other of the source electrode and the drain electrode, and a semiconductor layer 108_1 having a metal oxide. The transistor 205R, the transistor 205G, and the transistor 205B each include a conductive layer 114_1 functioning as a back gate electrode and an insulating layer 110s1 functioning as a back gate insulating layer.

[0429] The transistor 206R, the transistor 206G, and the transistor 206B each include a conductive layer 104_2 functioning as a gate electrode, an insulating layer 106_2 functioning as a gate insulating layer, a conductive layer 112a2 functioning as one of a source electrode and a drain electrode, a conductive layer 112b2 functioning as the other of the source electrode and the drain electrode, and a semiconductor layer 108_2 having a metal oxide.

[0430] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention. For example, the display device may include a combination of the transistor of one embodiment of the present invention and a transistor having another structure.

[0431] The display device of this embodiment may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistor included in the display device of this embodiment may be either a top-gate transistor or a bottom-gate transistor. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0432] The display device of this embodiment mode may also include a transistor using silicon for a channel formation region (Si transistor).

[0433] Examples of silicon include single-crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, a transistor having an LTPS semiconductor layer (hereinafter also referred to as an LTPS transistor) can be used. The LTPS transistor has high field-effect mobility and favorable frequency characteristics.

[0434] To increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher source-drain breakdown voltage than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0435] Furthermore, when a transistor operates in a saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing to a light-emitting element. This allows a pixel circuit to have a larger number of gray levels.

[0436] Furthermore, in terms of saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to a light-emitting element, even when the current-voltage characteristics of the light-emitting element vary. In other words, when an OS transistor operates in a saturation region, the source-drain current of the OS transistor remains almost unchanged even when the source-drain voltage is changed, thereby stabilizing the light-emitting luminance of the light-emitting element.

[0437] The transistors included in the circuit portion 164 and the transistors included in the display portion 168 may have the same structure or different structures. The transistors included in the circuit portion 164 may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 168 may all have the same structure or may have two or more types.

[0438] All the transistors included in the display portion 168 may be OS transistors, all the transistors included in the display portion 168 may be Si transistors, or some of the transistors included in the display portion 168 may be OS transistors and the rest may be Si transistors.

[0439] For example, by using both an LTPS transistor and an OS transistor in the display portion 168, a display device with low power consumption and high driving capability can be realized. A structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. Note that a more preferable example is a structure in which an OS transistor is used as a transistor that functions as a switch for controlling conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

[0440] For example, one of the transistors included in the display unit 168 (transistor 205R, transistor 205G, and transistor 205B in the display device 50A shown in FIG. 35) functions as a transistor for controlling a current flowing to a light-emitting element and can also be called a driving transistor. One of the source and drain of the driving transistor is connected to a pixel electrode of the light-emitting element. An LTPS transistor is preferably used as the driving transistor. This can increase the current flowing to the light-emitting element in the pixel circuit.

[0441] On the other hand, the other transistors included in the display portion 168 (transistors 206R, 206G, and 206B in the display device 50A shown in FIG. 35 ) function as switches for controlling pixel selection and non-selection and can also be referred to as selection transistors. The gate of the selection transistor is connected to a gate line, and one of the source and drain is connected to a source line (signal line). It is preferable to use an OS transistor as the selection transistor. This allows the gradation of a pixel to be maintained even when the frame frequency is significantly reduced (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

[0442] An insulating layer 195 is provided to cover the transistor 206R, the transistor 206G, and the transistor 206B.

[0443] The insulating layer 195 preferably functions as a protective layer for the transistor. The insulating layer 195 is preferably made of a material through which impurities such as water and hydrogen are less likely to diffuse. This allows the insulating layer 195 to function as a barrier layer. With such a structure, diffusion of impurities from the outside into the transistor can be effectively suppressed, and the reliability of the display device can be improved.

[0444] An insulating layer 235 is provided over the insulating layer 195. The insulating layer 235 preferably functions as a planarization layer that fills in steps or unevenness formed over the transistors 205R, 205G, and 205B and planarizes the top surfaces of the transistors.

[0445] Furthermore, it is preferable that the outermost layer of the insulating layer 235 functions as an etching protection layer, which can prevent recesses from being formed in the insulating layer 235 when processing the pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses may be formed in the insulating layer 235 when processing the pixel electrodes 111R, 111G, 111B, etc.

[0446] On the insulating layer 235, the light emitting elements 130R, 130G, and 130B are provided.

[0447] The light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 135 on the EL layer 113R. The light-emitting element 130R shown in Fig. 35 emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0448] The light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 135 on the EL layer 113G. The light-emitting element 130G shown in Fig. 35 emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0449] The light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 135 on the EL layer 113B. The light-emitting element 130B shown in Fig. 35 emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0450] 35, the EL layers 113R, 113G, and 113B are all shown with the same film thickness, but this is not limited to this. The film thicknesses of the EL layers 113R, 113G, and 113B may be different. For example, it is preferable to set the film thicknesses of the EL layers 113R, 113G, and 113B to thicknesses corresponding to the optical path lengths that intensify the light emitted by each layer. This realizes a microcavity structure and can increase the color purity of the light emitted from each light-emitting element.

[0451] The pixel electrode 111R is connected to the conductive layer 114_1 of the transistor 205R through openings provided in the insulating layer 110_1, the insulating layer 106_1, the insulating layer 193, the insulating layer 194, the insulating layer 110_2, the insulating layer 195, and the insulating layer 235, which are located over the conductive layer 114_1. Similarly, the pixel electrode 111G is connected to the conductive layer 114_1 of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 114_1 of the transistor 205B.

[0452] 35, the pixel electrode of each light-emitting element is shown as being connected only to the conductive layer 114_1 of the transistor (transistor 205R, transistor 205G, or transistor 205B) in the first layer located directly below it, and not to the conductive layer 112b1, but in reality, the pixel electrode of each light-emitting element is connected to both the conductive layer 114_1 and the conductive layer 112b1 of the transistor in the first layer located directly below it (see FIGS. 31 and 32, etc.). The same applies to the display devices shown in FIGS. 36, 37, and 38.

[0453] Ends of the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B are covered with an insulating layer 237. The insulating layer 237 functions as a partition wall (also referred to as a bank, spacer, or bank). The insulating layer 237 can be formed to have a single-layer structure or a stacked-layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the material that can be used for the insulating layer 235 can be used for the insulating layer 237. The insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

[0454] The common electrode 135 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 135 shared by the plurality of light-emitting elements is connected to a conductive layer 123 provided in the connection portion 140. For the conductive layer 123, it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

[0455] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is preferably used for the pixel electrode and the common electrode, which are electrodes from which light is extracted, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0456] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. That is, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0457] Materials for forming the pair of electrodes of a light-emitting element can include metals, alloys, electrically conductive compounds, and mixtures thereof. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these metals in combination. Examples of such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Examples of such materials include aluminum alloys (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and silver alloys, such as an alloy of silver and magnesium and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not exemplified above, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.

[0458] The light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode). By having the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0459] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. Furthermore, the resistivity of these electrodes is 1×10 −２ Preferably, it is Ωcm or less.

[0460] The EL layer 113R, the EL layer 113G, and the EL layer 113B are each provided in an island shape. In FIG. 35 , the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap. When forming island-shaped EL layers using a fine metal mask, the ends of adjacent EL layers may overlap as shown in FIG. 35 , but this is not limited to this. In other words, adjacent EL layers may not overlap but may be spaced apart. Furthermore, the display device may have both overlapping portions between adjacent EL layers and portions between adjacent EL layers that do not overlap but are spaced apart.

[0461] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer includes one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0462] Examples of the light-emitting material include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0463] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transport properties (hole-transport material) and a substance with high electron-transport properties (electron-transport material) can be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron-transport properties and high hole-transport properties) or a TADF material may be used.

[0464] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex. This configuration allows efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, the energy transfer becomes smooth, allowing efficient emission. This configuration allows the light-emitting element to simultaneously achieve high efficiency, low-voltage operation, and a long life.

[0465] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer).In addition, the EL layer may include one or both of a bipolar material and a TADF material.

[0466] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. Each of the layers constituting the light-emitting element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an ink-jet method, or a coating method.

[0467] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure allows the light-emitting element to emit light with high brightness. Furthermore, compared to a single structure, the tandem structure can reduce the current required to achieve the same brightness, thereby improving reliability. The tandem structure may also be called a stack structure.

[0468] In Figure 35, when light-emitting elements with a tandem structure are used, it is preferable that EL layer 113R has a structure having multiple light-emitting units that emit red light, EL layer 113G has a structure having multiple light-emitting units that emit green light, and EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0469] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 149. A light-shielding layer 117 is provided on the substrate 152. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 35 , the space between the substrates 152 and 151 is filled with the adhesive layer 149, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 149 may be provided so as not to overlap with the light-emitting elements. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 149.

[0470] The protective layer 131 is preferably provided in at least the display portion 168, and is preferably provided so as to cover the entire display portion 168. The protective layer 131 is preferably provided so as to cover not only the display portion 168, but also the connection portion 140 and the circuit portion 164. The protective layer 131 is preferably provided up to the edge of the display device 50A. On the other hand, in the connection portion 204, the FPC 172 and the conductive layer 167 are connected to each other, so that a portion where the protective layer 131 is not provided is generated.

[0471] By providing the protective layer 131 on the light emitting elements 130R, 130G, and 130B, the reliability of the light emitting elements can be improved.

[0472] The protective layer 131 may have a single layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 131 does not matter. The protective layer 131 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film.

[0473] The protective layer 131 has an inorganic film, which prevents oxidation of the common electrode 135 and prevents impurities (e.g., water, oxygen, etc.) that cause deterioration of the light-emitting element from entering, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0474] For the protective layer 131, for example, an inorganic insulating film such as an insulating oxide film, an insulating nitride film, an insulating oxynitride film, or an insulating nitride oxide film can be used. Specific examples of these inorganic insulating films are as described above. In particular, the protective layer 131 preferably includes an insulating nitride film or an insulating nitride oxide film, and more preferably includes an insulating nitride film.

[0475] Alternatively, an inorganic film containing ITO, In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, IGZO, or the like may be used for the protective layer 131. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 135. The inorganic film may further contain nitrogen.

[0476] When light emitted from the light-emitting element is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0477] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. By using such a stacked structure, impurities (for example, water, oxygen, etc.) that may cause deterioration of the light-emitting element can be prevented from entering the EL layer side.

[0478] Furthermore, the protective layer 131 may include an organic film. For example, the protective layer 131 may include both an organic film and an inorganic film.

[0479] A connection portion 204 is provided in a region of the substrate 151 where the substrate 152 does not overlap. In the connection portion 204, a wiring 165 is connected to the FPC 172 via a conductive layer 166, a conductive layer 167, and a connection layer 242. The wiring 165 is an example of a conductive layer having a single-layer structure obtained by processing the same conductive film as the conductive layer 112a1. The conductive layer 166 is an example of a conductive layer having a single-layer structure obtained by processing the same conductive film as the conductive layer 112b2. The conductive layer 167 is an example of a conductive layer having a single-layer structure obtained by processing the same conductive film as the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B. The conductive layer 167 is exposed on the top surface of the connection portion 204. This allows the connection portion 204 and the FPC 172 to be connected via the connection layer 242.

[0480] The display device 50A is a top-emission type. Light emitted by the light-emitting elements is emitted toward the substrate 152. The substrate 152 is preferably made of a material that is highly transparent to visible light. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 135) contains a material that transmits visible light.

[0481] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, the circuit section 164, and the like.

[0482] Furthermore, a colored layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When a color filter is provided over the light-emitting element, the color purity of light emitted from the pixel can be increased.

[0483] Various optical members can be disposed on the outer side of the substrate 152 (the surface opposite to the substrate 151). Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. Furthermore, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be disposed on the outer side of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ ), polyester-based materials, or polycarbonate-based materials may also be used. Note that it is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0484] The substrate 151 and the substrate 152 can each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. When a flexible material is used for the substrate 151 and the substrate 152, the flexibility of the display device can be increased, and a flexible display can be realized. Furthermore, a polarizing plate may be used for at least one of the substrates 151 and 152.

[0485] Substrates 151 and 152 may each be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrates 151 and 152 may be made of glass having a thickness sufficient to provide flexibility.

[0486] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has low birefringence (it can also be said that the amount of birefringence is small). Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.

[0487] The adhesive layer 149 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. Alternatively, a two-component resin may be used. Alternatively, an adhesive sheet or the like may be used.

[0488] The connection layer 242 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0489] 36 is different from the display device 50A mainly in that a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter) are used for each color subpixel. Note that in the following description of the display device, descriptions of parts that are the same as those of the display devices described above may be omitted.

[0490] The display device 50B shown in Figure 36 has, between the substrate 151 and the substrate 152, a transistor 205D, a transistor 205R, a transistor 205G, a transistor 205B, a transistor 206R, a transistor 206G, a transistor 206B, a light-emitting element 130R, a light-emitting element 130G, a light-emitting element 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, a colored layer 132B that transmits blue light, and the like.

[0491] The light emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 135 on the EL layer 113. The light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0492] The light emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 135 on the EL layer 113. Light emitted from the light emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0493] The light emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 135 on the EL layer 113. Light emitted from the light emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0494] The light-emitting elements 130R, 130G, and 130B each have a common EL layer 113 and a common electrode 135. The configuration in which the common EL layer 113 is provided for the subpixels of each color can reduce the number of manufacturing steps compared to the configuration in which different EL layers are provided for the subpixels of each color.

[0495] 36 emit white light. The white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, respectively, to obtain light of a desired color.

[0496] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, light-emitting layers may be selected such that the emission colors of the two light-emitting layers have a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer have a complementary color relationship, a configuration in which the light-emitting element as a whole emits white light can be obtained. Furthermore, when three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers may be combined to form a configuration in which the light-emitting element as a whole emits white light.

[0497] The EL layer 113 preferably includes, for example, a light-emitting layer having a light-emitting substance that emits blue light and a light-emitting layer having a light-emitting substance that emits visible light with a wavelength longer than blue. The EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0498] A tandem structure is preferably used for the light-emitting element emitting white light. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light, in this order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and red light, and a light-emitting unit that emits blue light, in this order, or the like can be applied. For example, the number of layers of the light-emitting units and the order of the colors can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, and the number of layers of the light-emitting layers in light-emitting unit X and the order of the colors can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. Furthermore, another layer can be provided between the two light-emitting layers.

[0499] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in FIG. 36 emit blue light. In this case, the EL layer 113 includes one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, a color conversion layer can be provided between the light-emitting element 130R or 130G and the substrate 152 to convert the blue light emitted by the light-emitting element 130R or 130G into light with a longer wavelength, thereby extracting red or green light. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. A portion of the light emitted by the light-emitting element may be transmitted directly without being converted by the color conversion layer. By extracting the light transmitted through the color conversion layer via the colored layer, light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light emitted by the sub-pixel.

[0500] [Display Device 50C] A display device 50C shown in FIG. 37 differs from the display device 50B mainly in that it is a bottom-emission display device.

[0501] Light emitted from the light-emitting element is emitted toward the substrate 151. A material that is highly transparent to visible light is preferably used for the substrate 151. On the other hand, the light-transmitting property of a material used for the substrate 152 does not matter.

[0502] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistor. Fig. 37 shows an example in which the light-shielding layer 117 is provided over the substrate 151, the insulating layer 153 is provided over the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, and 205B are provided over the insulating layer 153. In addition, the coloring layer 132R (not shown), the coloring layer 132G, and the coloring layer 132B are provided over the insulating layer 195, and the insulating layer 235 is provided over the coloring layer 132R (not shown), the coloring layer 132G, and the coloring layer 132B.

[0503] The light emitting element 130G overlapping the colored layer 132G includes a pixel electrode 111G, an EL layer 113, and a common electrode 135.

[0504] The light emitting element 130B overlapping the colored layer 132B has a pixel electrode 111B, an EL layer 113 and a common electrode 135.

[0505] The pixel electrodes 111G and 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 135. In a bottom-emission display device, a low-resistance metal or the like can be used for the common electrode 135, which can suppress voltage drops caused by the resistance of the common electrode 135 and achieve high display quality.

[0506] The transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced; therefore, in a bottom-emission display device, the aperture ratio of a pixel can be increased or the pixel size can be reduced.

[0507] [Display Device 50D] The display device 50D shown in Figure 38 is an example of a display device that uses an MML (metal maskless) structure. That is, the display device 50D has light-emitting elements that are fabricated without using a fine metal mask. Note that the layered structure from the substrate 151 to the insulating layer 235 and the layered structure from the protective layer 131 to the substrate 152 are similar to those of the display device 50A, and therefore will not be described here.

[0508] In FIG. 38, a light emitting element 130R, a light emitting element 130G, and a light emitting element 130B are provided on an insulating layer 235.

[0509] The light-emitting element 130R includes a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 134 on the layer 133R, and a common electrode 135 on the common layer 134. The light-emitting element 130R shown in FIG. 38 emits red light (R). The layer 133R includes a light-emitting layer that emits red light. In the light-emitting element 130R, the layer 133R and the common layer 134 can be collectively referred to as an EL layer. Furthermore, one or both of the conductive layer 124R and the conductive layer 126R can be referred to as a pixel electrode.

[0510] The light-emitting element 130G includes a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 134 on the layer 133G, and a common electrode 135 on the common layer 134. The light-emitting element 130G shown in FIG. 38 emits green light (G). The layer 133G includes a light-emitting layer that emits green light. In the light-emitting element 130G, the layer 133G and the common layer 134 can be collectively referred to as an EL layer. Furthermore, one or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.

[0511] The light-emitting element 130B has a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 134 on the layer 133B, and a common electrode 135 on the common layer 134. The light-emitting element 130B shown in FIG. 38 emits blue light (B). The layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, the layer 133B and the common layer 134 can be collectively referred to as an EL layer. Furthermore, one or both of the conductive layer 124B and the conductive layer 126B can be referred to as a pixel electrode.

[0512] In this specification and the like, among the EL layers included in the light-emitting elements, layers provided in an island shape for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is referred to as a common layer 134. Note that in this specification and the like, the layers 133R, 133G, and 133B may be referred to as island-shaped EL layers, EL layers formed in an island shape, or the like, without including the common layer 134.

[0513] The layers 133R, 133G, and 133B are spaced apart from one another. By providing an island-shaped EL layer for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This makes it possible to prevent unintended light emission due to crosstalk, and realize a display device with extremely high contrast.

[0514] 38, the layers 133R, 133G, and 133B are all shown to have the same film thickness, but this is not limitative. The layers 133R, 133G, and 133B may have different film thicknesses.

[0515] The conductive layer 124R is connected to the conductive layer 114_1 included in the transistor 205R through openings provided in the insulating layer 110_1, the insulating layer 106_1, the insulating layer 193, the insulating layer 194, the insulating layer 110_2, the insulating layer 195, and the insulating layer 235, which are located over the conductive layer 114_1. Similarly, the conductive layer 124G is connected to the conductive layer 114_1 included in the transistor 205G, and the conductive layer 124B is connected to the conductive layer 114_1 included in the transistor 205B.

[0516] The conductive layers 124R, 124G, and 124B are formed so as to cover openings provided in the insulating layer 110_1, the insulating layer 106_1, the insulating layer 193, the insulating layer 194, the insulating layer 110_2, the insulating layer 195, and the insulating layer 235, which are located over the conductive layer 114_1, respectively. A layer 128 is buried in the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B, respectively.

[0517] The layer 128 has a function of planarizing the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B. The conductive layers 126R, 126G, and 126B, which are connected to the conductive layers 124R, 124G, and 124B, are provided on the conductive layers 124R, 124G, 124B, and the layer 128, respectively. Therefore, the regions overlapping with the recesses of the conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, thereby increasing the aperture ratio of the pixel. It is preferable to use a conductive layer that functions as a reflective electrode for the conductive layers 124R and 126R.

[0518] The layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 128. In particular, the layer 128 is preferably formed using an insulating material, and more preferably using an organic insulating material. For example, the organic insulating material that can be used for the insulating layer 237 can be used for the layer 128.

[0519] 38 shows an example in which the top surface of layer 128 has a flat portion, but there are no particular limitations on the shape of layer 128. The top surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0520] Furthermore, the height of the upper surface of layer 128 and the height of the upper surface of conductive layer 124R may be the same or approximately the same, or may be different from each other. For example, the height of the upper surface of layer 128 may be lower or higher than the height of the upper surface of conductive layer 124R.

[0521] The end of the conductive layer 126R may be flush with the end of the conductive layer 124R, or may cover the side surface of the end of the conductive layer 124R. The end of each of the conductive layers 124R and 126R preferably has a tapered shape. Specifically, the end of each of the conductive layers 124R and 126R preferably has a tapered shape with a taper angle of less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode has an inclined portion. By tapering the side surface of the pixel electrode, the coverage of the EL layer provided along the side surface of the pixel electrode can be improved.

[0522] The conductive layers 124G, 126G, 124B, and 126B are similar to the conductive layers 124R and 126R, and therefore detailed description thereof will be omitted.

[0523] The top surface and side surfaces of the conductive layer 126R are covered with the layer 133R. Similarly, the top surface and side surfaces of the conductive layer 126G are covered with the layer 133G, and the top surface and side surfaces of the conductive layer 126B are covered with the layer 133B. Therefore, the entire regions where the conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting regions of the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B, respectively, thereby increasing the aperture ratio of the pixel.

[0524] Part of the top surface and side surfaces of each of the layers 133R, 133G, and 133B are covered with the insulating layer 125 and the insulating layer 127. A common layer 134 is provided on the layers 133R, 133G, and 133B and the insulating layer 125 and the insulating layer 127, and a common electrode 135 is provided on the common layer 134. The common layer 134 and the common electrode 135 are each a continuous film provided in common to a plurality of light-emitting elements.

[0525] 38, the insulating layer 237 shown in FIG. 35 and other figures is not provided between the conductive layer 126R and the layer 133R. In other words, the display device 50D does not have an insulating layer (also called a partition, bank, spacer, or the like) that contacts the pixel electrode and covers the upper edge of the pixel electrode. Therefore, the distance between adjacent light-emitting elements can be made extremely narrow. This allows a high-definition or high-resolution display device to be obtained. Furthermore, a mask for forming the insulating layer is not required, thereby reducing the manufacturing cost of the display device.

[0526] As described above, the layers 133R, 133G, and 133B each have a light-emitting layer. The layers 133R, 133G, and 133B each preferably have a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Alternatively, the layers 133R, 133G, and 133B each preferably have a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer. Alternatively, the layers 133R, 133G, and 133B each preferably have a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer. Because the surfaces of the layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, providing one or both of a carrier transport layer and a carrier block layer on the light-emitting layer can prevent the light-emitting layer from being exposed to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.

[0527] The common layer 134 includes, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 134 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The common layer 134 is shared by the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B.

[0528] The side surfaces of the layers 133R, 133G, and 133B are covered with the insulating layer 125. The insulating layer 127 covers the side surfaces of the layers 133R, 133G, and 133B with the insulating layer 125 interposed therebetween.

[0529] The side surfaces (and even part of the upper surfaces) of the layers 133R, 133G, and 133B are covered with at least one of the insulating layer 125 and the insulating layer 127, which prevents the common layer 134 (or the common electrode 135) from contacting the pixel electrodes and the side surfaces of the layers 133R, 133G, and 133B, thereby preventing short circuits in the light-emitting elements, thereby improving the reliability of the light-emitting elements.

[0530] The insulating layer 125 is preferably in contact with each side surface of the layer 133R, the layer 133G, and the layer 133B. The insulating layer 125 being in contact with the layer 133R, the layer 133G, and the layer 133B can prevent the layer 133R, the layer 133G, and the layer 133B from peeling off, thereby improving the reliability of the light-emitting element.

[0531] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses in the insulating layer 125. The insulating layer 127 preferably covers at least a part of the side surface of the insulating layer 125.

[0532] By providing the insulating layers 125 and 127, the gaps between adjacent island-shaped layers can be filled, which reduces large unevenness in height on the surface on which a layer (e.g., a carrier injection layer, a common electrode, etc.) is formed on the island-shaped layers, thereby making the surface flatter, thereby improving the coverage of the carrier injection layer, the common electrode, etc.

[0533] The common layer 134 and the common electrode 135 are provided over the layer 133R, the layer 133G, the layer 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, a step is generated between a region where the pixel electrode and the island-shaped EL layer are provided and a region where the pixel electrode and the island-shaped EL layer are not provided (a region between light-emitting elements). In the display device of one embodiment of the present invention, the insulating layer 125 and the insulating layer 127 can flatten the step, thereby improving the coverage of the common layer 134 and the common electrode 135. Therefore, poor connection due to a step disconnection of the common layer 134 or the common electrode 135 can be suppressed. Furthermore, an increase in electrical resistance caused by a local thinning of the common electrode 135 due to the step can be suppressed.

[0534] The upper surface of the insulating layer 127 preferably has a highly flat shape. The upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface. For example, the upper surface of the insulating layer 127 preferably has a highly flat, smooth convex curved surface shape.

[0535] The insulating layer 125 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulating layer 125. Specific examples of these inorganic insulating films are as described above. The insulating layer 125 may have a single-layer structure or a stacked-layer structure. Aluminum oxide is particularly preferable because it has a high etching selectivity with respect to the EL layer and protects the EL layer in the formation of the insulating layer 127 described later. In particular, by using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an ALD method for the insulating layer 125, the insulating layer 125 can be formed with few pinholes and excellent protection of the EL layer. Alternatively, the insulating layer 125 may have a stacked-layer structure of a film formed by an ALD method and a film formed by a sputtering method. For example, the insulating layer 125 may have a stacked-layer structure of an aluminum oxide film formed by an ALD method and a silicon nitride film formed by a sputtering method.

[0536] The insulating layer 125 preferably functions as a barrier insulating layer against at least one of water and oxygen. The insulating layer 125 preferably has a function of suppressing diffusion of at least one of water and oxygen. The insulating layer 125 preferably has a function of capturing or fixing (also referred to as gettering) at least one of water and oxygen.

[0537] Note that in this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. In addition, in this specification and the like, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing or fixing (also referred to as gettering) a corresponding substance.

[0538] The insulating layer 125 has a function as a barrier insulating layer or a gettering function, which can suppress the intrusion of impurities (substances that can induce deterioration of the light-emitting element, typically at least one of water and oxygen) that can diffuse from the outside into each light-emitting element. With this structure, a highly reliable light-emitting element and further a highly reliable display device can be provided.

[0539] The insulating layer 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer. Furthermore, a low impurity concentration in the insulating layer 125 can improve the barrier properties against at least one of water and oxygen. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, or preferably both of them.

[0540] The insulating layer 127 provided on the insulating layer 125 has a function of flattening large unevenness of the insulating layer 125 formed between adjacent light-emitting elements. In other words, the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 135 is formed.

[0541] An insulating layer containing an organic material can be suitably used as the insulating layer 127. As the organic material, a photosensitive organic resin is preferably used, for example, a photosensitive resin composition containing an acrylic resin is preferably used. Note that in this specification and the like, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0542] The insulating layer 127 may also be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, or precursors of these resins. The insulating layer 127 may also be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. The photosensitive resin may also be a photoresist. Either a positive-type material or a negative-type material may be used as the photosensitive organic resin.

[0543] The insulating layer 127 may be made of a material that absorbs visible light. The insulating layer 127 absorbs light emitted from the light-emitting element, thereby suppressing leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 127 (stray light). This can improve the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.

[0544] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used for color filters (color filter materials). In particular, using a resin material in which two or more color filter materials are laminated or mixed is preferable because it can enhance the visible light blocking effect. In particular, mixing three or more color filter materials makes it possible to form a black or nearly black resin layer.

[0545] This embodiment mode can be combined with other embodiment modes as appropriate.

[0546] Embodiment 4 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS. 39A to 41G.

[0547] The electronic devices of this embodiment include the display device of one embodiment of the present invention in their display portions. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device of one embodiment of the present invention can be used in the display portions of various electronic devices.

[0548] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0549] In particular, the display device of one embodiment of the present invention can be suitably used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.

[0550] The display device of one embodiment of the present invention preferably has an extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display device having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. Furthermore, the screen ratio (aspect ratio) of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0551] The electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0552] The electronic device of the present embodiment can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out programs or data recorded on a recording medium, etc.

[0553] 39A to 39D , examples of wearable devices that can be worn on the head are described. These wearable devices have at least one of the functions of displaying AR content, VR content, SR content, and MR content. By having an electronic device with the function of displaying at least one of AR, VR, SR, and MR content, it is possible to enhance the sense of immersion felt by the user.

[0554] The electronic device 700A shown in Figure 39A and the electronic device 700B shown in Figure 39B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0555] The display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can provide an extremely high-definition display.

[0556] The electronic device 700A and the electronic device 700B can each project an image displayed on the display panel 751 onto a display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.

[0557] Each of electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image in front of it as an imaging unit. Furthermore, each of electronic device 700A and electronic device 700B may be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

[0558] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0559] The electronic device 700A and the electronic device 700B are each provided with a battery (not shown), which can be charged wirelessly and / or wired.

[0560] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. The touch sensor module can detect a tap operation, a slide operation, or the like by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can broaden the range of operations.

[0561] Various touch sensors can be used as the touch sensor module. For example, various types of touch sensors can be used, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, and an optical type. In particular, it is preferable to use a capacitance type or an optical type sensor in the touch sensor module.

[0562] When an optical touch sensor is used, a photoelectric conversion element can be used as the light receiving element. The active layer of the photoelectric conversion element can be made of either or both of an inorganic semiconductor and an organic semiconductor.

[0563] The electronic device 800A shown in Figure 39C and the electronic device 800B shown in Figure 39D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0564] The display device of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high definition can be provided. This allows a user to feel a high sense of immersion.

[0565] The display unit 820 is provided inside the housing 821 at a position where it can be viewed through the lens 832. Also, by displaying different images on the pair of display units 820, it is possible to perform three-dimensional display using parallax.

[0566] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view an image displayed on the display unit 820 through the lens 832.

[0567] It is preferable that the electronic device 800A and the electronic device 800B each have a mechanism for adjusting the left-right positions of the lens 832 and the display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that the electronic device 800A and the electronic device 800B each have a mechanism for adjusting the focus by changing the distance between the lens 832 and the display unit 820.

[0568] The mounting unit 823 allows the user to mount the electronic device 800A or the electronic device 800B on the head. Note that in Fig. 39C and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0569] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide-angle.

[0570] Although an example including the imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0571] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This allows a user to enjoy video and audio simply by wearing the electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0572] The electronic device 800A and the electronic device 800B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like, or power for charging a battery provided in the electronic device.

[0573] The electronic device of one embodiment of the present invention may have a function of wirelessly communicating with an earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, an electronic device 700A shown in FIG. 39A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, an electronic device 800A shown in FIG. 39C has a function of transmitting information to the earphone 750 through the wireless communication function.

[0574] The electronic device may have an earphone unit. Electronic device 700B shown in Fig. 39B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.

[0575] Similarly, electronic device 800B shown in Fig. 39D has earphone unit 827. For example, earphone unit 827 and control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or wearing unit 823. Furthermore, earphone unit 827 and wearing unit 823 may have magnets. This allows earphone unit 827 to be fixed to wearing unit 823 by magnetic force, which is preferable as it makes storage easier.

[0576] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0577] As described above, as electronic devices according to one embodiment of the present invention, both glasses-type devices (such as the electronic device 700A and the electronic device 700B) and goggle-type devices (such as the electronic device 800A and the electronic device 800B) are suitable.

[0578] An electronic device according to one embodiment of the present invention can transmit information to an earphone via a wired or wireless connection.

[0579] The electronic device 6500 shown in FIG. 40A is a portable information terminal that can be used as a smartphone.

[0580] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

[0581] The display device of one embodiment of the present invention can be applied to the display portion 6502 .

[0582] FIG. 40B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0583] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0584] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0585] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0586] The flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, the thickness of the electronic device can be reduced and a large-capacity battery 6518 can be mounted thereon. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the display portion 6502, an electronic device with a narrow frame can be realized.

[0587] 40C shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0588] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0589] 40C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0590] The television device 7100 is configured to include a receiver, a modem, and the like. Ordinary television broadcasts can be received using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it is also possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0591] 40D shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214. The housing 7211 includes a display portion 7000.

[0592] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0593] 40E and 40F show an example of digital signage.

[0594] 40E includes a housing 7301, a display portion 7000, a speaker 7303, and the like. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0595] 40F shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0596] 40E and 40F, the display device of one embodiment of the present invention can be applied to the display portion 7000.

[0597] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it attracts people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0598] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

[0599] 40E and 40F , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Furthermore, by operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0600] The digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0601] The electronic device shown in Figures 41A to 41G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, etc.

[0602] 41A to 41G, the display device of one embodiment of the present invention can be applied to the display portion 9001.

[0603] The electronic devices shown in Figures 41A to 41G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read a...

Claims

a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer; the first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a gate insulating layer, and a gate electrode; the second transistor has a second semiconductor layer, a third conductive layer, and a fourth conductive layer; the first insulating layer is provided on the first conductive layer; the second conductive layer is provided on the first insulating layer; the first insulating layer and the second conductive layer each have a first opening reaching the first conductive layer; In the first opening, the first semiconductor layer is provided in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer; the gate insulating layer is provided in contact with an upper surface of the first semiconductor layer, the gate electrode is provided in contact with an upper surface of the gate insulating layer so as to have a region overlapping with the first opening; the second insulating layer is provided on the gate electrode so as to fill the first opening; the third conductive layer is provided on and in contact with the second insulating layer and the gate electrode; the third insulating layer is provided on the third conductive layer; the fourth conductive layer is provided on the third insulating layer; the third insulating layer and the fourth conductive layer each have a second opening reaching the third conductive layer; In the second opening, the second semiconductor layer is provided in contact with an upper surface of the third conductive layer, a side surface of the third insulating layer, and a side surface of the fourth conductive layer; the second insulating layer comprises an organic insulating material; Semiconductor device. 　 In claim 1, a fourth insulating layer is provided on the gate insulating layer in a region not overlapping with the first opening; the third insulating layer is provided on the fourth insulating layer; the fourth insulating layer has the same material as the second insulating layer; Semiconductor device. 　 In claim 1 or 2, The second insulating layer contains one or more selected from an acrylic resin, a polyimide resin, an epoxy resin, a polyamide resin, a polyimideamide resin, a siloxane resin, a benzocyclobutene-based resin, a phenolic resin, and precursors of these resins. Semiconductor device. 　 In claim 1 or 2, the first transistor has a back gate electrode; the back gate electrode is provided between the first conductive layer and the second conductive layer so as to have an area overlapping with each of the first conductive layer and the second conductive layer; In the first opening, one surface of the first semiconductor layer faces the gate electrode, and the other surface of the first semiconductor layer faces the back gate electrode. Semiconductor device. 　 In claim 1, At least one of the first semiconductor layer and the second semiconductor layer comprises a metal oxide; The metal oxide has two or three elements selected from indium, an element M, and zinc, The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium; At least one of the first insulating layer and the third insulating layer comprises silicon oxide or silicon oxynitride. Semiconductor device. 　 In claim 5, the first insulating layer includes a fifth insulating layer, a sixth insulating layer on the fifth insulating layer, and a seventh insulating layer on the sixth insulating layer; the third insulating layer includes an eighth insulating layer, a ninth insulating layer on the eighth insulating layer, and a tenth insulating layer on the ninth insulating layer; the fifth insulating layer, the seventh insulating layer, the eighth insulating layer, and the tenth insulating layer each include silicon nitride, silicon oxynitride, hafnium oxide, or aluminum oxide; The sixth insulating layer and the ninth insulating layer each include silicon oxide or silicon oxynitride. Semiconductor device. 　 forming a first conductive layer, a first insulating film, and a first conductive film in this order; removing a portion of each of the first insulating film and the first conductive film to form a first opening reaching the first conductive layer, and forming a first insulating layer and a second conductive layer; forming a first semiconductor layer in contact with a side surface of the second conductive layer, a side surface of the first insulating layer, and an upper surface of the first conductive layer, each in the first opening; forming a second insulating layer and a second conductive film in this order in contact with an upper surface of the first semiconductor layer; forming a second insulating film on the second conductive film so as to fill the first opening; removing a portion of the second insulating film to form a third insulating layer embedded in the first opening and to expose a portion of an upper surface of the second conductive film; forming a third conductive film in contact with an upper surface of the third insulating layer and an upper surface of the second conductive film; removing a portion of each of the second conductive film and the third conductive film to form a third conductive layer and a fourth conductive layer so as to have an area overlapping with the first opening; forming a third insulating film and a fourth conductive film in this order on the fourth conductive layer; removing a portion of each of the third insulating film and the fourth conductive film to form a second opening reaching the fourth conductive layer, and forming a fourth insulating layer and a fifth conductive layer; forming a second semiconductor layer in contact with a side surface of the fifth conductive layer, a side surface of the fourth insulating layer, and an upper surface of the fourth conductive layer, respectively, in the second opening; A method for manufacturing a semiconductor device. 　 In claim 7, forming a fourth insulating film and a fifth insulating film in this order on the fourth conductive layer and the second insulating layer after forming the third conductive layer and the fourth conductive layer and before forming the third insulating film and the fourth conductive film; removing a portion of the fifth insulating film to form a fifth insulating layer and to expose a portion of an upper surface of the fourth insulating film; forming the third insulating film and the fourth conductive film in this order on the fifth insulating layer and the fourth insulating film; A method for manufacturing a semiconductor device.

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