Semiconductor device and electronic apparatus

Abstract

Provided is a semiconductor device capable of reducing deviation between bonding pads for a first substrate and bonding pads for a second substrate. The first substrate is configured to include: a first insulating film that forms a first surface of the first substrate; and a first wiring layer that includes a plurality of first bonding pads which are arranged in a matrix shape in the first insulating film and are arranged in the first insulating film such that the surfaces are located in the same plane as the first surface. The second substrate is configured to include: a second insulating film that forms a second surface, on the first substrate side, of the second substrate and that is bonded to the first insulating film; and a second wiring layer that includes a plurality of second bonding pads which are bonded to the first bonding pads, are arranged in a matrix shape in the second insulating film, and are arranged in the second insulating film such that the surfaces are located in the same plane as the second surface. A second interval between adjacent first bonding pads in a second region, which is a region other than a first region of the first surface, is set constant, and a first interval between adjacent first bonding pads in the first region is set different from the second interval.

Description

Semiconductor devices and electronic devices

[0001] The present technology (technology according to the present disclosure) relates to a semiconductor device and an electronic device.

[0002] Conventionally, for example, a semiconductor device including a first substrate and a second substrate smaller than the first substrate and bonded to the first substrate has been proposed (see, for example, Patent Document 1). The semiconductor device described in Patent Document 1 is formed using a technique (chip-on-wafer) in which an individualized second substrate is pressed against a wafer on which a plurality of first substrates are formed, and then the wafer is divided. In addition, at this time, the second substrate is pressed against the wafer so that the surface of the second substrate facing the first substrate is convex, thereby allowing air to escape between the wafer and the second substrate.

[0003] Special Publication No. 2020-509578

[0004] However, in the semiconductor device described in Patent Document 1, when the second substrate is bonded to the first substrate, the second substrate is pressed against the first substrate so that its surface facing the first substrate becomes convex, which can cause the surface of the second substrate facing the first substrate to expand, potentially resulting in misalignment between the bonding pads on the wafer (first substrate) and the bonding pads on the second substrate.

[0005] An object of the present disclosure is to provide a semiconductor device and electronic device that can reduce misalignment between bonding pads on a first substrate and bonding pads on a second substrate.

[0006] A semiconductor device according to one aspect of the present technology includes: (a) a first substrate; and (b) a second substrate having a size in a planar view smaller than that of the first substrate and bonded to a first region of a first surface, which is one surface of the first substrate; (c) the first substrate includes: a first insulating film forming the first surface of the first substrate; and a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film such that a surface of the first bonding pad is located in the same plane as the first surface; and a first semiconductor layer stacked on a surface of the first wiring layer opposite to the first surface; and (d) the second substrate includes: a second insulating film forming the first surface, which is the surface of the second substrate facing the first substrate; and a second insulating film bonded to the first insulating film, a second wiring layer arranged in a matrix within the second insulating film, the second wiring layer including a plurality of second bonding pads disposed in the first insulating film so that the surface is located in the same plane as the second surface and bonded to the first bonding pads, and a second semiconductor layer stacked on the surface of the second wiring layer opposite the second surface, wherein (e) a second interval, which is the interval between adjacent first bonding pads in a second region other than the first region of the first surface, is constant, and the first interval, which is the interval between adjacent first bonding pads in the first region, is different from the second interval.

[0007] A semiconductor device according to another aspect of the present technology includes: (a) a first substrate; and (b) a second substrate having a size in a planar view smaller than that of the first substrate and bonded to a first region of a first surface, which is one surface of the first substrate; (c) the first substrate includes: a first insulating film forming the first surface of the first substrate; a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film so that the surface is located in the same plane as the first surface; and a first semiconductor layer stacked on a surface of the first wiring layer opposite the first surface; and (d) the second substrate includes: The second substrate has a second surface which is the surface facing the first substrate, a second insulating film bonded to the first insulating film, a second wiring layer arranged in a matrix within the second insulating film, arranged in the first insulating film so that its surface is located in the same plane as the second surface, and including a plurality of second bonding pads bonded to the first bonding pads, and a second semiconductor layer stacked on the surface of the second wiring layer opposite the second surface, wherein (e) when viewed in a plane, the size of the second bonding pads is different from the size of the first bonding pads in the second region which is a region other than the first region of the first surface.

[0008] A semiconductor device according to another aspect of the present technology includes: (a) a first substrate; and (b) a second substrate having a size in a planar view smaller than that of the first substrate and bonded to a first region of a first surface, which is one surface of the first substrate; (c) the first substrate includes: a first insulating film forming the first surface of the first substrate; and a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film so that the surface is located in the same plane as the first surface; and a first semiconductor layer stacked on a surface of the first wiring layer opposite to the first surface, d) The second substrate forms a second surface, which is the surface of the second substrate facing the first substrate, and has a second insulating film bonded to the first insulating film, a second wiring layer arranged in a matrix within the second insulating film, arranged in the first insulating film so that its surface is located in the same plane as the second surface, and including a plurality of second bonding pads bonded to the first bonding pads, and a second semiconductor layer stacked on the surface opposite the second surface of the second wiring layer; and (e) a correction film stacked on the surface of the second substrate opposite the second wiring layer side, and including a material different from that of the second semiconductor layer.

[0009] An electronic device according to one aspect of the present technology includes: (a) a first substrate; and (b) a second substrate having a size in a planar view smaller than that of the first substrate and bonded to a first region of a first surface, which is one surface of the first substrate; (c) the first substrate includes: a first insulating film forming the first surface of the first substrate; and a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film so that the surface is located in the same plane as the first surface; and a first semiconductor layer stacked on a surface of the first wiring layer opposite the first surface; and (d) the second substrate forms a second surface, which is the surface of the second substrate facing the first substrate; The gist of the present invention is that the semiconductor device includes: a second insulating film bonded to the first insulating film; a second wiring layer arranged in a matrix within the second insulating film, the second wiring layer including a plurality of second bonding pads arranged in the first insulating film so that the surface is located in the same plane as the second surface and bonded to the first bonding pads; and a second semiconductor layer stacked on the surface of the second wiring layer opposite the second surface, wherein (e) a second interval, which is the interval between adjacent first bonding pads in a second region other than the first region of the first surface, is constant, and a first interval, which is the interval between adjacent first bonding pads in the first region, is different from the second interval.

[0010] According to another aspect of the present technology, there is provided an electronic device including: (a) a first substrate; and (b) a second substrate having a size in a planar view smaller than that of the first substrate and bonded to a first region of a first surface, which is one surface of the first substrate; (c) the first substrate includes a first insulating film forming the first surface of the first substrate; and a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film such that the surface is located in the same plane as the first surface; and a first semiconductor layer stacked on a surface of the first wiring layer opposite to the first surface; and (d) the second substrate includes a first insulating film forming the first surface of the second substrate. The gist of the present invention is that the semiconductor device includes: a second insulating film that forms a second surface that is the surface facing the first substrate and is bonded to the first insulating film; a second wiring layer that is arranged in a matrix within the second insulating film, is arranged in the first insulating film so that its surface is located in the same plane as the second surface, and includes a plurality of second bonding pads bonded to the first bonding pads; and a second semiconductor layer that is stacked on the surface of the second wiring layer opposite the second surface, wherein (e) when viewed in a plane, the size of the second bonding pads is different from the size of the first bonding pads in a second region that is a region other than the first region of the first surface.

[0011] According to another aspect of the present technology, there is provided an electronic device including: (a) a first substrate; and (b) a second substrate having a size in a plan view smaller than that of the first substrate and bonded to a first region of a first surface, which is one surface of the first substrate; (c) the first substrate includes a first insulating film forming the first surface of the first substrate; and a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film such that the surface is located in the same plane as the first surface; and a first semiconductor layer stacked on a surface of the first wiring layer opposite the first surface; and (d) a second substrate including a first insulating film forming the first surface of the first substrate and a first bonding pad, which is arranged in a matrix within the first insulating film and has the first bonding pads arranged in the first insulating film such that the surface is located in the same plane as the first surface. The plate forms a second surface, which is the surface of the second substrate facing the first substrate, and has a second insulating film bonded to the first insulating film, a second wiring layer arranged in a matrix within the second insulating film, and arranged in the first insulating film so that its surface is located in the same plane as the second surface, and including a plurality of second bonding pads bonded to the first bonding pads, and a second semiconductor layer stacked on the surface opposite the second surface of the second wiring layer, and (e) a semiconductor device is provided which has a correction film stacked on the surface of the second substrate opposite the second wiring layer side and including a material different from that of the second semiconductor layer.

[0012] 10 is a diagram showing the overall configuration of an image sensor according to a first embodiment; FIG. 11 is a diagram showing the internal configuration of an image sensor; FIG. 12 is a diagram showing a cross-sectional configuration of a semiconductor device; FIG. 13 is a diagram showing the positional relationship between first bonding pads and second bonding pads, and is a diagram showing the cross-sectional configuration of the semiconductor device when cut along line A-A in FIG. 3; FIG. 14 is a diagram showing an enlarged view of a portion of the first wiring layer and the second wiring layer in FIG. 3; FIG. 15 is a diagram showing chip-on-wafer (CoW) technology; FIG. 16 is a diagram showing chip-on-wafer (CoW) technology; FIG. 17 is a diagram showing the cross-sectional configuration of a first substrate and a second substrate of a comparative example immediately before bonding; FIG. 18 is a diagram showing the positional relationship between the first bonding pads and the second bonding pads when cut along line D-D in FIG. 8; FIG. 19 is a diagram showing the cross-sectional configuration of a first substrate and a second substrate of a comparative example after bonding; FIG. 19 is a diagram showing the positional relationship between the first bonding pads and the second bonding pads when cut along line E-E in FIG. 20; FIG. 21 is a diagram showing the arrangement of the first bonding pads when pressing down on the center of the second substrate; FIG. 22 is a diagram showing cross-sections of the first substrate and the second substrate immediately before bonding when pressing down on the vicinity of the lower left corner of the second substrate. 16 is a diagram showing a cross-sectional configuration of the first substrate and the second substrate after bonding when pressing down near the bottom left corner of the second substrate. FIG. 17 is a diagram showing the arrangement of the first bonding pads. FIG. 18 is a diagram showing the first substrate and the second substrate as viewed obliquely. FIG. 19 is a diagram showing the first substrate of FIG. 16 as viewed in plan. FIG. 20 is a diagram showing the positional relationship between the first bonding pads and the second bonding pads of FIG. 16. FIG. 21 is an enlarged view of a portion of the first wiring layer and the second wiring layer of FIG. 3. FIG. 22 is an enlarged view of a portion of the first wiring layer and the second wiring layer of FIG. 3. FIG. 23 is a diagram showing the arrangement of the first bonding pads when pressing down the left edge of the second substrate. FIG. 24 is a diagram showing the first substrate and the second substrate as viewed obliquely just before bonding. FIG. 25 is a diagram showing various patterns of pressing lines. FIG. 26 is a diagram showing the positional relationship between the first bonding pads and the second bonding pads in a semiconductor device according to a second embodiment. FIG. 27 is a diagram showing the planar configuration of the first surface of the first substrate of the semiconductor device. FIG. 28 is a diagram showing the first bonding pads and the second bonding pads after bonding. FIG. 29 is a diagram showing a method for setting the positions of the first bonding pads. FIG. 29 is an enlarged view of a portion of the first wiring layer and the second wiring layer of FIG. 1A and 1B are diagrams illustrating the positional relationship between the first and second bonding pads, and the layout of the first bonding pads.FIG. 10 is a diagram showing the first bonding pad and the second bonding pad after bonding; FIG. 11 is a diagram showing a method for setting the positions of the first bonding pad; FIG. 12 is a diagram showing the positional relationship between the first bonding pad and the second bonding pad; FIG. 13 is a diagram showing the arrangement of the first bonding pad; FIG. 14 is a diagram showing the first bonding pad and the second bonding pad after bonding; FIG. 15 is a diagram showing a method for setting the positions of the first bonding pad; FIG. 16 is a diagram showing the positional relationship between the first bonding pad and the second bonding pad; FIG. 17 is a diagram showing a method for setting the positions of the first bonding pad; FIG. 18 is a diagram showing the positional relationship between the first bonding pad and the second bonding pad in a semiconductor device according to a third embodiment; FIG. 19 is a diagram showing a planar configuration of a second surface of a second substrate of a semiconductor device; FIG. 19 is a diagram showing a method for setting the positions of the second bonding pad; FIG. 19 is a diagram showing the positional relationship between the first bonding pad and the second bonding pad ... 64. A diagram showing the positional relationship between the first bonding pad and the second bonding pad when broken at cross section E-E in FIG. 50. A diagram showing the cross-sectional configuration of the first substrate and the second substrate immediately before bonding. A diagram showing a method for manufacturing a semiconductor device. A diagram showing a method for manufacturing a semiconductor device. A diagram showing a method for manufacturing a semiconductor device. A diagram showing a method for manufacturing a semiconductor device. A diagram showing a method for manufacturing a semiconductor device. A diagram showing a method for manufacturing a semiconductor device. A diagram showing a method for manufacturing a semiconductor device. A diagram showing a method for manufacturing a semiconductor device. A diagram showing a method for manufacturing a semiconductor device. A diagram showing a cross-sectional configuration of a semiconductor device. A diagram showing the first substrate and the second substrate as viewed from an oblique direction. A diagram showing the positional relationship between the first bonding pad and the second bonding pad in FIG. 64. A diagram showing a schematic configuration of an electronic device according to a fourth embodiment. A block diagram showing an example of the schematic configuration of a vehicle control system. An explanatory diagram showing an example of the installation positions of an outside vehicle information detection unit and an imaging unit.

[0013] Examples of semiconductor devices and electronic devices according to embodiments of the present disclosure will be described below with reference to FIGS. 1 to 68. The embodiments of the present disclosure will be described in the following order. Note that the present disclosure is not limited to the following examples. Furthermore, the effects described in this specification are examples and are not limiting, and other effects may also be present.

[0014] 1. First Embodiment: Semiconductor Device 1-1 Overall Configuration of Semiconductor Device 1-2 Configuration of Main Parts 1-3 Modifications 2. Second Embodiment: Semiconductor Device 2-1 Configuration of Main Parts 2-2 Modifications 3. Third Embodiment: Semiconductor Device 3-1 Configuration of Main Parts 3-2 Modifications 4. Fourth Embodiment: Semiconductor Device 4-1 Configuration of Main Parts 4-2 Manufacturing Method of Semiconductor Device 4-3 Modifications 5. Fifth Embodiment: Application to Electronic Devices 6. Sixth Embodiment: Application to Mobile Objects

[0015] 1. First Embodiment [1-1 Overall Configuration of Semiconductor Device] In the first embodiment, an example in which the present technology is applied to a semiconductor device 1 will be described. The semiconductor device 1 of the first embodiment is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor. As shown in FIG. 66 , the semiconductor device 1 (solid-state imaging device 1002) captures incident light from a subject through a lens group 1001, converts the amount of incident light imaged on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal. As shown in FIG. 1 , the semiconductor device 1 includes a rectangular pixel region 2A disposed in the center of a two-dimensional plane including an X direction and a Y direction that intersect with each other, and a peripheral region 2B disposed outside the pixel region 2A so as to surround the pixel region 2A. In FIG. 1 , the X direction and the Y direction are orthogonal to each other, and the Z direction is a direction orthogonal to both the X direction and the Y direction.

[0016] The pixel region 2A is a light-receiving surface that receives light collected by the lens group 1001 (see FIG. 66 ). A plurality of pixels 3 are arranged in a matrix in the pixel region 2A. That is, the pixels 3 are repeatedly arranged in the X and Y directions, which intersect with each other, in a two-dimensional plane. Each pixel 3 also has a photoelectric conversion element. The photoelectric conversion element generates a signal charge according to the amount of received light. For example, a photodiode can be used as the photoelectric conversion element. A plurality of bonding pads 14 are also arranged in the peripheral region 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides of the semiconductor device 1 in the two-dimensional plane. Each of the plurality of bonding pads 14 is an input / output terminal used to electrically connect the semiconductor device 1 to an external device (not shown).

[0017] 2, the semiconductor device 1 includes a logic circuit 13 including a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The vertical drive circuit 4 is configured, for example, by a shift register, and sequentially selects each pixel 3 in the pixel region 2A row by row by, for example, sequentially outputting selection pulses to pixel drive wirings 9, and outputs pixel signals of the selected pixels 3 to the column signal processing circuit 5 through vertical signal lines 10. The pixel signals are signals obtained from charges (e.g., electrons) generated in the photoelectric conversion elements.

[0018] The column signal processing circuits 5 are arranged, for example, for each column of pixels 3, and perform signal processing such as noise removal on signals output from one row of pixels 3 for each pixel column. Examples of signal processing that can be used include correlated double sampling and AD (Analog-Digital) conversion to remove fixed pattern noise specific to pixels. The horizontal drive circuit 6 is configured, for example, with a shift register, and sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, selects the column signal processing circuits 5 in order, and causes the selected column signal processing circuit 5 to output the processed pixel signals to the horizontal signal line 12.

[0019] The output circuit 7 performs various signal processing operations on each pixel signal sequentially output from the column signal processing circuit 5 through the horizontal signal line 12. Examples of signal processing that can be used include various types of digital signal processing such as buffering, black level adjustment, and column variation correction. The control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock signal (not shown). The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0020] [1-2 Configuration of Main Parts] Next, the detailed structure of the semiconductor device 1 will be described. FIG. 3 is a diagram showing the cross-sectional configuration of the semiconductor device 1. FIG. 4 is a diagram showing the positional relationship between the first bonding pads 24 and the second bonding pads 34, and is a diagram showing the cross-sectional configuration of the semiconductor device 1 when broken along line A-A in FIG. 3. As shown in FIGS. 3 and 4, the semiconductor device 1 includes a first substrate 20 and a second substrate 30 that is smaller in size than the first substrate 20 in a plan view and is bonded to a first region B of one surface (hereinafter also referred to as the "first surface S1") of the first substrate 20. An example of a plan view is when the object is viewed from the thickness direction (Z direction) of the first substrate 20 and the second substrate 30. The first substrate 20 includes a first semiconductor layer 21 and a first wiring layer 22 stacked on one surface (hereinafter also referred to as the "surface S2") of the first semiconductor layer 21. In other words, the first semiconductor layer 21 is stacked on the surface opposite to the first surface S1 (described later) of the first wiring layer 22. The first semiconductor layer 21 is, for example, a semiconductor substrate made of silicon (Si) or the like, and has active elements such as transistors formed thereon. The first semiconductor layer 21 also has the pixel region 2A and photoelectric conversion elements described above formed thereon. The other surface (hereinafter also referred to as the "rear surface S3") of the first semiconductor layer 21 may further include, for example, a color filter, a microlens, etc. The color filter and the microlens are formed for each pixel 3 (see FIG. 2). In the semiconductor device 1 shown in FIGS. 3 and 4, incident light is captured from the rear surface S3 side of the first semiconductor layer 21.

[0021] The first wiring layer 22 includes a first insulating film 23 and a plurality of first bonding pads 24. The first insulating film 23 is composed of a multilayer insulating film. As shown in FIG. 5 , metal wiring 25 is disposed between the multiple insulating films, and a multilayer wiring layer is formed in which the multiple wirings 25 are stacked with the insulating films interposed therebetween. FIG. 5 illustrates a two-layer structure in which a first wiring 251 and a second wiring 252 are stacked from the first semiconductor layer 21 side. As shown in FIGS. 3 and 4 , the surface of the first insulating film 23 opposite the first semiconductor layer 21 side forms the first surface S1 (bonding surface) of the first substrate 20. The multiple first bonding pads 24 are arranged in a matrix within the first insulating film 23. Each of the first bonding pads 24 is arranged in the first insulating film 23 such that its surface S4 is located in the same plane as the first surface S1. 5, first vias 26 extending in the thickness direction of the first wiring layer 22 connect the first bonding pads 24 and the second wiring 25, the second wiring 25 and the first wiring 25, and the first wiring 25 and the first semiconductor layer 21. The first vias 26 electrically connect the first bonding pads 24, the second wiring 25, the first wiring 25, and the photoelectric conversion elements of the first semiconductor layer 21. FIG. 4 illustrates a case where the planar shape of the first bonding pads 24 is square. Note that some of the first bonding pads 24 may be dummy electrodes 24 that are not connected to the wiring 25. FIG. 5 illustrates a case where the first bonding pads 24 in a second region C (described below) on the first surface S1 include dummy electrodes 24 and electrode pads for external connection (e.g., bonding pads connected to the wiring 25).

[0022] The second substrate 30 includes a second semiconductor layer 31 and a second wiring layer 32 stacked on one surface (hereinafter also referred to as the "back surface S6") of the second semiconductor layer 31. In other words, the second semiconductor layer 31 is stacked on the surface of the second wiring layer 32 opposite to the second surface S7 (described later). The second semiconductor layer 31 is a semiconductor substrate made of, for example, silicon (Si), and includes active elements such as transistors. The active elements such as transistors form, for example, a logic circuit 13, a pixel signal readout circuit, a memory circuit such as a memory, a circuit for realizing artificial intelligence, etc. The second wiring layer 32 includes a second insulating film 33 and a plurality of second bonding pads 34. The second insulating film 33 is composed of a multilayer insulating film. As shown in FIG. 5, metal wiring 35 is arranged between the multilayer insulating films, and a multilayer wiring layer is formed in which the multiple wirings 35 are stacked via the insulating film. 5 illustrates a two-layer structure in which a first wiring 351 and a second wiring 352 are stacked from the second semiconductor layer 31 side. As shown in FIGS. 3 and 4 , the surface of the second insulating film 33 opposite the second semiconductor layer 31 side forms the surface of the second substrate 30 facing the first substrate 20 (hereinafter also referred to as the "second surface S7"). A plurality of second bonding pads 34 are arranged in a matrix within the second insulating film 33. Each of the second bonding pads 34 is arranged within the second insulating film 33 such that its surface S8 is located in the same plane as the second surface S7. The second bonding pads 34 are positioned so as to overlap with the first bonding pads 24 within the first region B when the second substrate 30 is bonded to the first region B. 5, second vias 36 extending in the thickness direction of the second wiring layer 32 connect the second bonding pad 34 and the second wiring 35, the second wiring 35 and the first wiring 35, and the first wiring 35 and the second semiconductor layer 31. The second vias 36 electrically connect the second bonding pad 34, the second wiring 35, the first wiring 35, and the logic circuit 13 of the second semiconductor layer 31. FIG. 4 illustrates an example in which the planar shape of the second bonding pad 34 is square.

[0023] Furthermore, the second substrate 30 has the second surface S7 of the second wiring layer 32 bonded to the first region B of the first surface S1 of the first substrate 20 (first wiring layer 22). Specifically, the first bonding pads 24 and the second bonding pads 34 in the first region B of the first wiring layer 22 and the second wiring layer 32 are bonded, and the first insulating film 23 and the second insulating film 33 in the first region B are bonded. This bonding can be performed by the following procedure. For example, first, the first surface S1 of the first wiring layer 22 and the second surface S7 of the second wiring layer 32 are activated by plasma, and the second substrate 30 is pressed against the first substrate 20, thereby temporarily bonding the second insulating film 33 to the first region B of the first insulating film 23 by hydrogen bonding. Thereafter, first substrate 20 and second substrate 30 are heated to form an alloy bond between first bonding pad 24 and second bonding pad 34, and also to convert the hydrogen bonds between first insulating film 23 and second insulating film 33 into covalent bonds (main bonds). Bonding first bonding pad 24 and second bonding pad 34 electrically connects first wiring layer 22 and second wiring layer 32, and electrically connects photoelectric conversion elements and the like of first semiconductor layer 21 to logic circuit 13 and the like of second semiconductor layer 31.

[0024] The first insulating film 23 and the second insulating film 33 may be made of insulating materials such as silicon oxide (SiO) or silicon nitride (SiN). The first bonding pads 24, the second bonding pads 34, and the wiring 25, 35 may be made of metals such as copper (Cu) or aluminum (Al). The first vias 26 and the second vias 36 may be made of metals such as copper (Cu), aluminum (Al), or tungsten (W).

[0025] Here, as a technique for bonding the second substrate 30 to the first substrate 20, for example, as shown in FIG. 6 , a technique (chip-on-wafer: CoW) may be used in which an individualized second substrate 30 is pressed against a wafer W on which a plurality of first substrates 20 are formed, and then the wafer W is divided. In this case, to release air between the wafer W and the second substrate 30, the second substrate 30 is pressed so that the second surface S7 becomes convex, as shown in FIG. 7 . Therefore, scaling, in which the second surface S7 of the second substrate 30 expands, may occur, and the positions of the second bonding pads 34 of the second substrate 30 may deviate from their original design positions. For example, in a configuration (hereinafter also referred to as a "comparative example") in which the first bonding pads 24 of the first substrate 20 and the second bonding pads 34 of the second substrate 30 are all equally spaced before bonding as shown in FIGS. 8 and 9 , the expansion of the second surface S7 of the second substrate 30 could potentially cause the positions of the second bonding pads 34 of the second substrate 30 to shift, as shown in FIGS. 10 and 11 . This could result in misalignment between the first bonding pads 24 of the wafer W (first substrate 20) and the second bonding pads 34 of the second substrate 30, potentially causing problems with the electrical connection between the photoelectric conversion elements, etc. of the first substrate 20 and the logic circuit 13, etc. of the second substrate 30. FIG. 8 is a diagram showing the cross-sectional configuration of the first substrate 20 and the second substrate 30 of the comparative example immediately before bonding. Also, FIG. 9 is a diagram showing the positional relationship between the first bonding pads 24 and the second bonding pads 34 when broken along line D-D in FIG. 8 . 10 is a diagram showing the cross-sectional configuration of the first substrate 20 and the second substrate 30 of the comparative example after bonding them together, and FIG. 11 is a diagram showing the positional relationship between the first bonding pad 24 and the second bonding pad 34 when cut along line E-E in FIG.

[0026] 4, in the first embodiment, the spacing between adjacent first bonding pads 24 in the first region B of the first surface S1 of the first substrate 20 (hereinafter also referred to as the "first spacing") is different from the spacing between adjacent first bonding pads 24 in a region other than the first region B of the first surface S1 (hereinafter also referred to as the "second region C") (hereinafter also referred to as the "second spacing"). Specifically, the spacing (second spacing) between adjacent first bonding pads 24 in the second region C is constant. That is, the spacing D in the X direction X2 and the distance D in the Y direction Y2 Both are set to the same constant value (D X2 =D Y2 On the other hand, the first spacing D X1 , D Y1 is the second interval D X2 , D Y2 In FIG. 4, the distance D in the X direction is X1 and the distance D in the Y direction Y1 Both of these are D X2 , D Y2 the same constant value (D X1 =D Y1 ) is illustrated. That is, on the first surface S1, the first bonding pads 24 in the first region B and the first bonding pads 24 in the second region C are arranged at equal intervals with different pad-to-pad distances. X1 , D Y1 >D X2 , D Y2 , D X1 =D Y1 , D X2 =D Y2 By setting the above, the position of the first bonding pad 24 in the first region B can be adjusted to the position of the second bonding pad 34 after bonding, i.e., the position of the second bonding pad 34 after movement. This reduces misalignment between the first bonding pad 24 of the first substrate 20 and the second bonding pad 34 of the second substrate 30, which occurs when the position of the second bonding pad 34 of the second substrate 30 moves when bonding the second substrate 30. This prevents the first bonding pad 24 from stepping off the second bonding pad 34.

[0027] As shown in FIG. 5 , the arrangement of the first bonding pads 24 in the first region B can be achieved by adjusting only the positions of the first bonding pads 24 while maintaining equal spacing between adjacent first vias 26 and wirings 25 (first wirings 25 1 and second wirings 25 2 ) in the first wiring layer 22. Furthermore, the spacing D between the first vias 26 connected to the first bonding pads 24 in the first region B is the same as the spacing D between the first vias 26 connected to the first bonding pads 24 in the second region C. As a result, the spacing in a plan view between the first bonding pads 24 and the first vias 26 connected to the first bonding pads 24 in the first region B is different from the spacing in a plan view between the first bonding pads 24 and the first vias 26 connected to the first bonding pads 24 in the second region C. For example, the spacing in a plan view between the first bonding pads 24 and the first vias 26 in the first region B increases with increasing distance from a specific position O (described later).

[0028] As an example of a method for setting the position of the first bonding pads 24, first, as shown in FIG. 12, a design position 37 is set for one of the first bonding pads 24 in the first region B. i and set the design position 37 i Center P i and a straight line 38 passing through the specific position O. i Set the design position 37 i For example, the distance D in the X direction and the Y direction in the first region B X1 , D Y1 The distance D in the X and Y directions of the second region C X2 , D Y2 The position of each first bonding pad 24 in the first region B can be adopted when it is assumed that the specific position O is the same as the position where the first bonding pads 24 are pressed when the substrate is bonded. i Above, design position 37 i Center P i A position far from the specific position O (center P i Move from specific position O to center P i Distance L to ' i is the distance from the specific position O to the center P iDistance r to i Then, the above procedure is performed for all the first bonding pads 24 in the first region B, and the design position 37 i The center of the destination P i Each of the positions L′ is used as the center position of the first bonding pad 24 in the first region B. i =r i × (1 + c) ... (1), where the coefficient c is a value greater than 0. For example, the ratio of the size in the X direction (or Y direction) of the second surface S7 after bonding to the size in the X direction (or Y direction) of the second surface S7 before bonding can be used. FIG. 12 is a diagram showing the arrangement of the first bonding pads 24 when pressing the center of the second substrate 30. By using this setting method, the positions of the first bonding pads 24 in the first region B can be made closer to the positions of the second bonding pads 34 after bonding, and the misalignment between the first bonding pads 24 and the second bonding pads 34 can be more appropriately reduced.

[0029] [1-3 Modifications] (1) In the first embodiment, the center of the second substrate 30 is pressed during bonding. However, other configurations may be employed. For example, as shown in FIGS. 13, 14, and 15, a configuration in which a portion other than the center is pressed may be used. FIGS. 13, 14, and 15 illustrate a case in which the lower left corner of the second substrate 30 is pressed. FIG. 13 is a diagram illustrating a cross section of the first substrate 20 and the second substrate 30 immediately before bonding when the vicinity of the lower left corner of the second substrate 30 is pressed. FIG. 14 is a diagram illustrating a cross section of the first substrate 20 and the second substrate 30 after bonding when the vicinity of the lower left corner of the second substrate 30 is pressed. FIG. 15 corresponds to FIG. 13 of the first embodiment and illustrates the arrangement of the first bonding pads 24.

[0030] (2) Although the first embodiment illustrates an example in which one second substrate 30 is bonded to one first substrate 20, other configurations may be employed. For example, as shown in FIGS. 16, 17, and 18, a configuration in which two or more second substrates 30 are bonded to one first substrate 20 (hereinafter also referred to as a "multi-chip configuration") may be employed. FIG. 16 illustrates the first substrate 20 and the second substrate 30 as viewed obliquely. FIG. 17 illustrates the first substrate 20 of FIG. 16 as viewed in plan. FIG. 18 illustrates the positional relationship between the first bonding pads 24 and the second bonding pads 34 of FIG. 16. In this case, two or more first regions B are formed on the first surface S1 of the first substrate 20, and the positions of the first bonding pads 24 are set for each first region B. FIG. 18 illustrates an example in which the positions of the first bonding pads 24 within the first region B are set for each first region B using the above formula (1). By setting the position of the first bonding pad 24 for each first region B, it is possible to reduce the misalignment between the second bonding pads 34 of two or more second substrates 30 and the first bonding pads 24 of the first substrate 20, which occurs when the positions of the second bonding pads 34 of each of the two or more second substrates 30 move when the second substrates 30 are bonded together.

[0031] (3) Although the first embodiment illustrates an example in which only the positions of the first bonding pads 24 are adjusted within the first region B, other configurations may also be employed. For example, as shown in FIG. 19 , a configuration may be adopted in which the positions of the first vias 26 as well as the first bonding pads 24 are adjusted. FIG. 19 illustrates an example in which the positions of the first vias 26 connecting the first bonding pads 24 to the second wiring 25 are shifted in a direction away from the specific position O. As a result, the distance D between the first vias 26 connected to the first bonding pads 24 within the first region B is different from the distance D between the first vias 26 connected to the first bonding pads 24 within the second region C. For example, as shown in FIG. 20 , a configuration may be adopted in which the positions of the wiring 25 as well as the first bonding pads 24 and the first vias 26 are adjusted. FIG. 20 illustrates an example in which the position of the second wiring 25 is shifted in a direction away from the specific position O. By adjusting the positions of the first vias 26 and the wiring 25, it is possible to more appropriately arrange the first bonding pads 24 compared to, for example, adjusting only the positions of the first bonding pads 24 (see FIG. 5 ). Note that although an example in which the positions of the first vias 26 and wiring 25 closest to the first surface S1 are adjusted is shown in FIGS. 19 and 20 , a configuration in which the positions of other first vias 26 and wiring 25 are adjusted may also be used.

[0032] (4) In the first embodiment, the spacing between the first bonding pads 24 in the row and column directions in the first region B is set to D X1 , D Y1 21, the distance between the first bonding pads 24 in the first region B (first distance) may be larger than the distance between the first bonding pads 24 in the second region C (second distance) in the direction perpendicular to the specific straight line O' set on the first surface S1 of the first substrate 20. In FIG. 21, the specific straight line O' extends along the Y direction, and the first distance is D. X1 , the second interval is D X2The example illustrates a case where the specific straight line O' overlaps, in plan view, a pressing line (described later) that is pressed during bonding. For example, as shown in FIG. 22 , if a method is adopted in which the second substrate 30 is pressed along a line (hereinafter referred to as a "pressing line 39") set on the second substrate 30 so that the second surface S7 becomes a cylindrical convex surface when bonding the substrates together, the second surface S7 of the second substrate 30 expands in a direction perpendicular to the pressing line 39. Therefore, as the second surface S7 of the second substrate 30 expands, the spacing between the second bonding pads 34 in the direction perpendicular to the pressing line (the spacing in the X direction in FIG. 22 ) expands. Therefore, by adopting the configuration of this modification (4), it is possible to reduce misalignment between the first bonding pads 24 of the first substrate 20 and the second bonding pads 34 of the second substrate 30, which occurs when the second substrates 30 are bonded together due to movement of the second bonding pads 34 of the second substrate 30. Fig. 21 is a diagram showing the arrangement of the first bonding pads 24 when the left edge of the second substrate 30 is pressed down. Fig. 22 is a diagram showing the first substrate 20 and the second substrate 30 viewed from an oblique direction immediately before bonding. Note that Fig. 21 shows the case where the pressing line 39 is located on the left edge side of the second substrate 30, while Fig. 22 shows the case where it is located at the center in the width direction of the second substrate 30. Furthermore, the position of the pressing line 39 is not limited to the position shown in Figs. 21 and 22, and it may be located on a diagonal line or in a corner of the second substrate 30 as shown in Fig. 23.

[0033] As an example of a method for setting the position of the first bonding pad 24, first, as shown in FIG. 21, a design position 37 is set for one of the first bonding pads 24 in the first region B. i and set the design position 37 i Center P i A straight line 38 that passes through the line 38 and extends in a direction perpendicular to the specific straight line O'. i Set the design position 37 i For example, the distance D in the X direction and the Y direction in the first region B X1 , D Y1 The distance D in the X and Y directions of the second region C X2 , D Y2The position of each first bonding pad 24 within the first region B can be adopted when the set straight line 38 is assumed to be the same as the i Above, design position 37 i Center P i The position far from the specific straight line O' (center P i ') from the specific line O' to the center P i Distance L to ' i is the distance from the specific straight line O' to the center P i Distance r to i Then, the above procedure is performed for all the first bonding pads 24 in the first region B, and the design position 37 i The center of the destination P i Each of the positions ' is used as the center position of the first bonding pad 24 in the first region B. By using this setting method, the position of the first bonding pad 24 in the first region B can be made closer to the position of the second bonding pad 34 after bonding, and the misalignment between the first bonding pad 24 and the second bonding pad 34 can be more appropriately reduced.

[0034] 2. Second Embodiment [2-1 Configuration of Main Parts] Next, a semiconductor device 1 according to a second embodiment of the present disclosure will be described. The overall configuration of the semiconductor device 1 according to the second embodiment is the same as that shown in FIGS. 1 and 2 , and is therefore not shown. FIG. 24 is a diagram corresponding to FIG. 4 of the first embodiment, illustrating the positional relationship between the first bonding pads 24 and the second bonding pads 34. FIG. 25 is a diagram corresponding to FIG. 12 of the first embodiment, illustrating the planar configuration of the first surface S1 of the first substrate 20 of the semiconductor device 1. In FIGS. 24 and 25 , parts corresponding to FIGS. 4 and 12 are denoted by the same reference numerals, and redundant description will be omitted. The semiconductor device 1 according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in that, as shown in FIGS. 24 and 25 , the size of the first bonding pads 24 in the first region B is different from the size of the first bonding pads 24 in the second region C when viewed in plan. Specifically, the size of the first bonding pads 24 in the first region B increases as the distance from the specific position O in the first region B increases. 24 and 25 illustrate an example in which the first bonding pads 24 are linear connection pads extending along the longitudinal direction of a line 39 extending radially from the specific position O in the first region B. That is, the first bonding pads 24 are shaped to extend in a direction away from the specific position O. In other words, the distance between the first bonding pads 24 decreases as the distance from the specific position O increases. As described above, the movement of the second bonding pads 34 (movement away from the pressing position) caused by scaling, in which the second substrate 30 expands during bonding, increases as the distance from the pressing position increases. For example, if the planar size of the second substrate 30 is 20 mm × 20 mm, the coefficient c is 100 ppm, and the pressing position is at a corner of the second substrate 30, the position of the second bonding pad 34 on the second substrate 30 will deviate from the designed position by a maximum of 20 mm × √2 × 10 ppm = 2.8 μm. In contrast, by giving the first bonding pad 24 the above-described shape, as shown in FIG. 26 , the position of the first bonding pad 24 in the first region B can be made closer to the position of the second bonding pad 34 after bonding, thereby more appropriately reducing the deviation between the first bonding pad 24 and the second bonding pad 34. This makes it possible to prevent the first bonding pad 24 from stepping off the second bonding pad 34.

[0035] As an example of a method for setting the position of the first bonding pad 24, first, as shown in FIGS. 25 and 27, a design position 37 is set for one of the first bonding pads 24 in the first region B. i and set the design position 37 i Center P i and a straight line 38 passing through the specific position O. i Set the design position 37 i For example, the distance D in the X direction and the Y direction in the first region B X1 , D Y1 The distance D in the X and Y directions of the second region C X2 , D Y2 The position of each first bonding pad 24 within the first region B can be adopted when the set straight line 38 is assumed to be the same as the i Along the design position 37 i From the center P i Distance r i Position P that is far from the specific position O by ×c i ' to the end point position, design position 37 i Extend from a specific position O to the center P i Distance L to ' i is the distance from the specific position O to the center P i Distance r to i Then, the above procedure is performed for all the first bonding pads 24 in the first region B, and the design position 37 after extension is calculated. i Each of these is used as the first bonding pad 24 in the first region B. By using this setting method, the first bonding pad 24 in the first region B can be extended to the position of the second bonding pad 34 after bonding, and the misalignment between the first bonding pad 24 and the second bonding pad 34 can be more appropriately reduced. Note that in FIG. 27, for convenience, the design position 37 is used as the first bonding pad 24. i The shape of the first bonding pad 24 is shown as a circle, but the position of the first bonding pad 24 is shown as a design position 37 i28 , the arrangement of the first bonding pads 24 in the first region B can be realized by adjusting only the shape of the first bonding pads 24 while maintaining equal intervals between adjacent first vias 26 and wirings 25 (first wiring 25 1 , second wiring 25 2 ) in the first wiring layer 22.

[0036] [2-2 Modifications] (1) In the second embodiment, the first bonding pads 24 are linear connection pads extending along the longitudinal direction of a line 39 extending radially from a specific position O within the first region B. However, other configurations may also be employed. For example, as shown in FIGS. 29 and 30 , the first bonding pads 24 may be arc-shaped connection pads extending along the circumferential direction of a circle 40 centered on the specific position O within the first region B. That is, the first bonding pads 24 are shaped to extend in the circumferential direction of a circle centered on the specific position O. Here, if the pressing position is a single point, there is a possibility that rotation, in which the second substrate 30 rotates around the pressing position, may occur during bonding. If such rotation occurs, the second bonding pads 34 of the second substrate 30 move in the rotational direction. Furthermore, the amount of movement in the rotational direction increases as the distance from the pressing position increases. Therefore, when the amount of rotation is θ [°], a deviation of a = 2 × r × sin(θ / 2) occurs in the circular direction depending on the distance r from the pressing position. For example, if the planar size of the second substrate 30 is 20 mm × 20 mm, the amount of rotation θ is 0.01°, and the pressing position is at a corner of the second substrate 30, the position of the second bonding pad 34 on the second substrate 30 will deviate from the designed position by a maximum of 20 mm × √2 × 2 × sin(θ / 2) = 4.9 μm. In contrast, by giving the first bonding pad 24 the above-described shape, as shown in FIG. 31 , the position of the first bonding pad 24 in the first region B can be made closer to the position of the second bonding pad 34 after bonding, i.e., the position of the second bonding pad 34 after rotation, thereby more appropriately reducing the deviation between the first bonding pad 24 and the second bonding pad 34.

[0037] As an example of a method for setting the position of the first bonding pads 24, first, as shown in FIGS. 30 and 32, a design position 37 is set for one of the first bonding pads 24 in the first region B. i and set the design position 37 i Center P i A circle 40 obtained by rotating around a specific position O i Set the design position 37 i For example, the distance D in the X direction and the Y direction in the first region B X1 , D Y1 The distance D in the X and Y directions of the second region C X2 , D Y2 The position of each first bonding pad 24 within the first region B can be adopted when the circle 40 is assumed to be the same as the circle 40. i Along the design position 37 i From the center P i Position P is a distance a = 2rsin(θ / 2) from i ' to the end point position, design position 37 i Then, the above procedure is performed for all the first bonding pads 24 in the first region B, and the designed positions 37 after the extension are i Each of these is used as the first bonding pad 24 in the first region B. By using this setting method, the first bonding pad 24 in the first region B can be positioned closer to the position of the second bonding pad 34 after bonding, that is, the position of the second bonding pad 34 after rotation, and the misalignment between the first bonding pad 24 and the second bonding pad 34 can be more appropriately reduced.

[0038] (2) For example, as shown in FIGS. 33 and 34 , the first bonding pads 24 may be fan-shaped bonding pads extending in both the circumferential and radial directions of a circle 40 centered on a specific position O in the first region B. That is, the first bonding pads 24 extend in directions away from the specific position O and in the circumferential direction of the circle centered on the specific position O. As described above, the movement of the second bonding pads 34 (movement away from the pressed position) caused by the expansion of the second substrate 30 during bonding increases with increasing distance from the pressed position. For example, a radial deviation of c×r occurs depending on the distance r from the pressed position. Furthermore, if the pressed position is a single point, the second substrate 30 may rotate around the pressed position during bonding, and the amount of movement in the rotational direction increases with increasing distance from the pressed position. For example, if the amount of rotation is θ [°], a circular deviation of a = 2×r×sin(θ / 2) occurs depending on the distance r from the pressed position. In contrast, by giving the first bonding pad 24 the above-described shape, as shown in FIG. 35, the position of the first bonding pad 24 in the first region B can be made closer to the position of the second bonding pad 34 after bonding (after enlargement and rotation), and the misalignment between the first bonding pad 24 and the second bonding pad 34 can be more appropriately reduced.

[0039] As an example of a method for setting the position of the first bonding pads 24, first, as shown in FIGS. 34 and 36, a design position 37 is set for one of the first bonding pads 24 in the first region B. i and set the design position 37 i Center P i and a straight line 38 passing through the specific position O. i Also, design position 37 i Center P i A circle 40 obtained by rotating around a specific position O i Set the design position 37 i For example, the distance D in the X direction and the Y direction in the first region B X1 , D Y1 The distance D in the X and Y directions of the second region C X2 , D Y2The position of each first bonding pad 24 within the first region B can be adopted when the set straight line 38 is assumed to be the same as the i Along the design position 37 i From the center P i Distance r i Position P that is far from the specific position O by ×c i ' to the end point position, design position 37 i Extend from a specific position O to the center P i Distance L to ' i is the distance from the specific position O to the center P i Distance r to i Then, the design position 37 after extension is calculated according to the above formula (1). i The above procedure is then performed for all of the first bonding pads 24 in the first region B, and the fan-shaped extended design positions 37 i Each of these is used as the first bonding pad 24 in the first region B. By using this setting method, the first bonding pad 24 in the first region B can be extended to the position of the second bonding pad 34 after bonding, that is, the position of the second bonding pad 34 after enlargement and rotation, and the misalignment between the first bonding pad 24 and the second bonding pad 34 can be more appropriately reduced.

[0040] (3) For example, as shown in FIGS. 37 and 38 , the first bonding pads 24 may be linear bonding pads extending in a direction perpendicular to the specific line O′ set in the first region B. That is, the first bonding pads 24 are shaped to extend in a direction away from the specific line O′. Here, as shown in FIG. 22 , for example, when bonding the second substrate 30, if a method is employed in which the second substrate 30 is pressed along a line (pressing line 39) set on the second substrate 30 so that the second surface S7 becomes a cylindrical convex surface, the second surface S7 of the second substrate 30 expands in a direction perpendicular to the pressing line 39. Therefore, as the second surface S7 of the second substrate 30 expands, the spacing between the second bonding pads 34 expands in a direction perpendicular to the pressing line 39. In contrast, by giving the first bonding pad 24 the above-mentioned shape, it is possible to reduce the misalignment between the first bonding pad 24 of the first substrate 20 and the second bonding pad 34 of the second substrate 30 that occurs when the position of the second bonding pad 34 of the second substrate 30 moves when the second substrate 30 is bonded.

[0041] As an example of a method for setting the position of the first bonding pads 24, first, as shown in FIGS. 38 and 39, a design position 37 is set for one of the first bonding pads 24 in the first region B. i and set the design position 37 i Center P i A straight line 38 passing through the line 38 and extending in a direction perpendicular to the specific straight line O'. i Set the design position 37 i For example, the distance D in the X direction and the Y direction in the first region B X1 , D Y1 The distance D in the X and Y directions of the second region C X2 , D Y2 The position of each first bonding pad 24 within the first region B can be adopted when the set straight line 38 is assumed to be the same as the i Along the design position 37 i From the center P i Distance r i ×c away from the specific straight line O' i ' to the end point position, design position 37 i Extend the specified straight line O' to the center Pi Distance L to ' i is the distance from the specific straight line O' to the center P i Distance r to i Then, the above procedure is performed for all the first bonding pads 24 in the first region B, and the design position 37 after extension is calculated. i Each of these is used as the first bonding pad 24 in the first region B. By using this setting method, the first bonding pad 24 in the first region B can be extended to the position of the second bonding pad 34 after bonding, and the misalignment between the first bonding pad 24 and the second bonding pad 34 can be more appropriately reduced.

[0042] 3. Third Embodiment [3-1 Configuration of Main Parts] Next, a semiconductor device 1 according to a third embodiment of the present disclosure will be described. The overall configuration of the semiconductor device 1 according to the third embodiment is the same as that shown in FIGS. 1 and 2 , and is therefore not shown. FIG. 40 is a diagram corresponding to FIG. 4 of the first embodiment, illustrating the positional relationship between the first bonding pads 24 and the second bonding pads 34. FIG. 41 is a diagram corresponding to FIG. 12 of the first embodiment, illustrating the planar configuration of the second surface S7 of the second substrate 30 of the semiconductor device 1. In FIGS. 40 and 41 , parts corresponding to those in FIGS. 4 and 12 are denoted by the same reference numerals, and redundant description will be omitted. The semiconductor device 1 according to the third embodiment differs from the semiconductor device 1 according to the first embodiment in that, as shown in FIGS. 40 and 41 , the size of the second bonding pads 34 on the second substrate 30 is different from the size of the first bonding pads 24 in the second region C of the first substrate 20 when viewed in plan. Specifically, the first bonding pads 24 within the first surface S1 (first region B, second region C) of the first substrate 20 are all the same size, and the second bonding pads 34 are larger in size as the distance from the specific position O2 within the second surface S7 increases. Figures 40 and 41 illustrate an example in which the second bonding pads 34 are linear connection pads extending along the longitudinal direction of a line 41 extending radially from the specific position O2 within the second surface S7. That is, the second bonding pads 34 are shaped to extend in the direction toward the specific position O2. In other words, the distance between the second bonding pads 34 decreases as the distance from the specific position O2 increases. As described above, the movement of the second bonding pads 34 (movement away from the pressing position) caused by the expansion of the second substrate 30 during bonding increases as the distance from the pressing position increases. In contrast, by forming the second bonding pad 34 in the above-described shape, the position of the second bonding pad 34 after bonding can be brought closer to the position of the first bonding pad 24, and misalignment between the first bonding pad 24 and the second bonding pad 34 can be more appropriately reduced. Therefore, misalignment between the first bonding pad 24 and the second bonding pad 34 can be prevented.

[0043] As an example of a method for setting the position of the second bonding pads 34, first, as shown in FIGS. 41 and 42, a design position 42 is set for one of the second bonding pads 34 on the second surface S7. i and set the design position 42 i Center P i and a straight line 43 passing through the specific position O2. i Set the design position 42 i For example, the position of each second bonding pad 34 on the second surface S7 can be adopted when it is assumed that the intervals in the X and Y directions on the second surface S7 are the same as the intervals in the X and Y directions on the first surface S1. i along the design position 42 i From the center P i Distance r i × c closer to the specific position O2 i ' to the end point position, and the design position 42 i Extend from the specific position O2 to the center P i Distance L to ' i is the distance from the specific position O2 to the center P i Distance r to i Then, the above procedure is performed for all the second bonding pads 34 on the second surface S7, and the design position 42 after extension is calculated. i Each of these is used as the second bonding pad 34 on the second surface S7. By using this setting method, the position of the second bonding pad 34 after bonding can be extended to the position of the first bonding pad 24, and the deviation between the first bonding pad 24 and the second bonding pad 34 can be more appropriately reduced. Note that in FIG. 42, for convenience, the design position 42 i The shape of the second bonding pad 34 is shown as a circle, but the position of the second bonding pad 34 is shown as a circle at the design position 42 i The same procedure can be used to set the shape of L in a rectangular shape. i =r i ×(1-c) ......(2)

[0044] [3-2 Modifications] (1) In the third embodiment, the second bonding pads 34 are linear connection pads extending along the longitudinal direction of the straight lines 41 extending radially from the specific position O2. However, other configurations may also be employed. For example, as shown in FIG. 43 , the second bonding pads 34 may be arc-shaped connection pads extending along the circumferential direction of a circle 44 centered on the specific position O2 on the second surface S7. That is, the second bonding pads 34 are shaped to extend in the circumferential direction of a circle centered on the specific position O2. In FIG. 43 , multiple circles 44 are set concentrically around the specific position O2. Here, if there is a single pressing position, there is a possibility that the second substrate 30 will rotate around the pressing position during bonding. If such rotation occurs, the second bonding pads 34 of the second substrate 30 will move in the rotational direction. Furthermore, the amount of movement in the rotational direction increases as the distance from the pressing position increases. In contrast, by giving the second bonding pad 34 the above-mentioned shape, the position of the second bonding pad 34 after bonding, i.e., the position of the second bonding pad 34 after rotation, can be made closer to the position of the first bonding pad 24, and the misalignment between the first bonding pad 24 and the second bonding pad 34 can be more appropriately reduced.

[0045] As an example of a method for setting the position of the second bonding pads 34, first, as shown in FIGS. 43 and 44, a design position 42 is set for one of the second bonding pads 34 on the second surface S7. i and set the design position 42 i Center P i A circle 44 obtained by rotating the circle 44 around the specific position O2 i Set the design position 42 i For example, the positions of the second bonding pads 34 on the second surface S7 can be adopted when it is assumed that the spacing in the X and Y directions on the second surface S7 is the same as the spacing in the X and Y directions on the first surface S1. i along the design position 42 i From the center P i Position P is a distance a = 2rsin(θ / 2) from i ' to the end point position, and the design position 42 iThen, the above procedure is performed for all the second bonding pads 34 on the second surface S7, and the design positions 42 after extension are i Each of these is used as the second bonding pad 34 on the second surface S7. By using this setting method, the positions of the second bonding pads 34 on the second surface S7 after bonding, that is, the positions of the second bonding pads 34 after rotation, can be made closer to the positions of the first bonding pads 24, and the misalignment between the first bonding pads 24 and the second bonding pads 34 can be more appropriately reduced.

[0046] (2) For example, as shown in FIG. 45 , the second bonding pads 34 may be fan-shaped bonding pads extending in both the circumferential and radial directions of a circle 44 centered on a specific position O2 on the second surface S7. That is, the second bonding pads 34 extend toward the specific position O2 and in the circumferential direction of the circle centered on the specific position O2. As described above, the movement of the second bonding pads 34 (movement away from the pressing position) caused by the expansion of the second substrate 30 during bonding increases with the distance from the pressing position. Furthermore, if the pressing position is a single point, the second substrate 30 may rotate around the pressing position during bonding, and the amount of movement in the rotational direction increases with the distance from the pressing position. In contrast, by giving the second bonding pad 34 the above-mentioned shape, the position of the second bonding pad 34 after bonding (after enlarging and rotating) can be made closer to the position of the first bonding pad 24, and the misalignment between the first bonding pad 24 and the second bonding pad 34 can be more appropriately reduced.

[0047] As an example of a method for setting the position of the second bonding pads 34, first, as shown in FIGS. 45 and 46, a design position 42 is set for one of the second bonding pads 34 on the second surface S7. i and set the design position 42 i Center P i and a straight line 43 passing through the specific position O2. i Also, the design position 42 i Center P i A circle 44 obtained by rotating the circle 44 around the specific position O2 iSet the design position 42 i For example, the position of each second bonding pad 34 on the second surface S7 can be adopted when it is assumed that the intervals in the X and Y directions on the second surface S7 are the same as the intervals in the X and Y directions on the first surface S1. i Along the design position 37 i From the center P i Distance r i × c closer to the specific position O2 i ' to the end point position, design position 37 i Extend from the specific position O2 to the center P i Distance L to ' i is the distance from the specific position O2 to the center P i Distance r to i Then, the design position 42 after extension is calculated according to the above formula (2). i The above procedure is then performed for all of the first bonding pads 24 in the first region B, and the fan-shaped extended design position 42 i Each of these is used as the second bonding pad 34 on the second surface S7. By using this setting method, the positions of the second bonding pads 34 on the second surface S7 after bonding, that is, the positions of the second bonding pads 34 after enlargement and rotation, can be made closer to the positions of the first bonding pads 24, and the misalignment between the first bonding pads 24 and the second bonding pads 34 can be more appropriately reduced.

[0048] (3) For example, as shown in FIG. 47 , the second bonding pads 34 may be linear bonding pads extending in a direction perpendicular to the specific line O′ defined on the second surface S7. That is, the second bonding pads 34 are elongated in a direction approaching the specific line O′. Here, as shown in FIG. 22 , for example, when bonding the second substrate 30, if a method is employed in which the second substrate 30 is pressed along a line (pressing line 39) defined on the second substrate 30 so that the second surface S7 becomes a cylindrical convex surface, the second surface S7 of the second substrate 30 expands in a direction perpendicular to the pressing line 39. Therefore, as the second surface S7 of the second substrate 30 expands, the spacing between the second bonding pads 34 expands in a direction perpendicular to the pressing line 39. In contrast, by giving the second bonding pad 34 the above-mentioned shape, it is possible to reduce the misalignment between the first bonding pad 24 of the first substrate 20 and the second bonding pad 34 of the second substrate 30 that occurs when the position of the second bonding pad 34 of the second substrate 30 moves when the second substrate 30 is bonded together.

[0049] As an example of a method for setting the position of the second bonding pads 34, first, as shown in FIGS. 47 and 48, the design position 42 is set for one of the second bonding pads 34 on the second surface S7. i and set the design position 42 i Center P i A straight line 43 passing through the line 43 and extending in a direction perpendicular to the specific straight line O2' i Set the design position 42 i For example, the position of each second bonding pad 34 on the second surface S7 can be adopted when it is assumed that the intervals in the X and Y directions on the second surface S7 are the same as the intervals in the X and Y directions on the first surface S1. i along the design position 42 i From the center P i Distance r i Position P that is closer to the specific straight line O2' by ×c i ' to the end point position, and the design position 42 i Extend the specific straight line O2' to the center P i Distance L to ' i is the distance from the specific straight line O2' to the center P i Distance r toi Then, the above procedure is performed for all the second bonding pads 34 on the second surface S7, and the design position 42 after extension is calculated. i Each of these is used as the second bonding pad 34 on the second surface S7. By using this setting method, the second bonding pad 34 on the second surface S7 after bonding can be extended to the position of the first bonding pad 24, and the misalignment between the first bonding pad 24 and the second bonding pad 34 can be more appropriately reduced.

[0050] (4) In the third embodiment, the first bonding pads 24 of the first substrate 20 are all the same size, and only the second bonding pads 34 of the second substrate 30 are adjusted in size. However, other configurations may be employed. For example, as shown in FIG. 49 , a configuration may be employed in which both the sizes of the first bonding pads 24 and the second bonding pads 34 are adjusted. That is, a configuration may be employed in which the size (shape) of the first bonding pads 24 shown in the embodiment and its modified example is combined with the size (shape) of the second bonding pads 34 shown in the third embodiment and its modified example. FIG. 49 illustrates, as a first configuration example, a case in which the second bonding pads 34 are arc-shaped along the concentric circles shown in FIG. 30 and the first bonding pads 24 are linearly shaped along the radial lines shown in FIG. 41 . This combination of configuration example 1 can suppress misalignment between the first bonding pads 24 and the second bonding pads 34 even when movement of the second bonding pads 34 due to expansion of the second substrate 30 and movement of the second bonding pads 34 due to rotation simultaneously occur during bonding. 49 illustrates, as a configuration example 2, a case in which the second bonding pads 34 are linear along the radial straight lines shown in Fig. 25, and the first bonding pads 24 are arc-shaped along the concentric circles shown in Fig. 43. Also, Fig. 49 illustrates, as a configuration example 3, a case in which the second bonding pads 34 and the first bonding pads 24 are fan-shaped as shown in Figs. 34 and 45.

[0051] 4. Fourth Embodiment [4-1 Configuration of Main Parts] Next, a semiconductor device 1 according to a fourth embodiment of the present disclosure will be described. The overall configuration of the semiconductor device 1 according to the fourth embodiment is the same as that shown in FIGS. 1 and 2 , and is therefore not shown. FIG. 50 is a diagram corresponding to FIG. 3 of the first embodiment, illustrating a cross-sectional configuration of the semiconductor device 1. FIG. 51 is a diagram corresponding to FIG. 4 of the first embodiment, illustrating the positional relationship between the first bonding pad 24 and the second bonding pad 34 when cut along cross section E-E in FIG. 50 . In FIGS. 50 and 51 , parts corresponding to FIGS. 3 and 4 are denoted by the same reference numerals, and redundant description will be omitted. As shown in FIG. 50 , the semiconductor device 1 according to the fourth embodiment differs from the semiconductor device 1 according to the first embodiment in that it includes a correction film 50 stacked on the surface of the second semiconductor layer 31 opposite the second wiring layer 32 side (hereinafter also referred to as “surface S9”) and containing a material different from that of the second semiconductor layer 31. Furthermore, in the semiconductor device 1 according to the fourth embodiment, the first bonding pads 24 on the first surface S1 and the second bonding pads 34 on the second surface S7 are all the same size.

[0052] As shown in FIG. 52 , the correction film 50 is a stress film that generates stress in the second substrate 30 in a direction that causes warpage of the second surface S7, forming an inverted dome-shaped concave surface. FIG. 52 is a diagram showing the cross-sectional configuration of the first substrate 20 and the second substrate 30 immediately before bonding. By providing such a stress film, when bonding the second surface S7 of the second wiring layer 32 to the first surface S1 of the first substrate 20 (first wiring layer 22), the four corners of the second surface S7 (second insulating film 33) of the second wiring layer 32 are first bonded to the first surface S1 (first insulating film 23) of the first wiring layer 22. Bonding of the second surface S7 to the first surface S1 is then carried out with the positional relationship between the four corners of the second surface S7 and the first surface S1 fixed. This prevents expansion of the second substrate 30 during bonding, reducing misalignment between the first bonding pads 24 of the first substrate 20 and the second bonding pads 34 of the second substrate 30. Therefore, it is possible to prevent the first bonding pad 24 from slipping off from the second bonding pad 34 .

[0053] For example, if the correction film 50 is not provided, the second substrate 30 tends to warp, forming a dome-shaped convex second surface S7. Therefore, during bonding, the four corners of the second surface S7 are not fixed, potentially causing the second substrate 30 to expand. Furthermore, if the configurations of the first to third embodiments in which the layout and shape of the first bonding pads 24 and the second bonding pads 34 are adjusted to reduce misalignment between the first bonding pads 24 and the second bonding pads 34 due to the expansion of the second substrate 30 were adopted, the inter-pad distance would be reduced in some locations, potentially making it difficult to ensure a sufficient short margin between the pads. In contrast, the fourth embodiment includes the correction film 50, eliminating the need to adjust the layout and shape of the first bonding pads 24 and the second bonding pads 34, thereby ensuring a sufficient short margin between the pads. The first substrate 20 and the second substrate 30 are bonded together in a vacuum to prevent air from remaining between the first substrate 20 and the second substrate 30. When bonding the first substrate 20 and the second substrate 30 in a vacuum (i.e., a space with a pressure sufficiently lower than atmospheric pressure), the small amount of air present between the first substrate 20 and the second substrate 30 escapes to the outside through gaps between the first surface S1 and each side between the four corners of the second surface S7.

[0054] The amount of misalignment of the second bonding pads 34 after bonding varies depending on the stress (film stress) and film thickness of the correction film 50. Therefore, the film stress and film thickness of the correction film 50 are set so that the second bonding pads 34 of the second substrate 30 overlap the first bonding pads 24 of the first substrate 20 after bonding, eliminating misalignment between the first bonding pads 24 and the second bonding pads 34. Examples of materials that can be used for the correction film 50 include silicon oxide (SiO), silicon nitride (SiN), titanium nitride (TiN), aluminum oxide (AlO), hafnium oxide (HfO), silicon nitride (SiN), and zirconium oxide (ZrO). Nitride films such as silicon nitride (SiN) are particularly preferred. A material with higher rigidity than the second semiconductor layer 31 is also preferred for the correction film 50. For example, when silicon (Si, elastic modulus 190 GPa) is used as the material of the second semiconductor layer 31, examples of the material of the correction film 50 include titanium nitride (TiN, elastic modulus 251 GPa), hafnium oxide (HfO, elastic modulus 284 GPa), silicon nitride (Si3N4, elastic modulus 280 to 300 GPa), zirconium oxide (ZrO2, elastic modulus 280 to 330 GPa), titanium oxide (TiO2, elastic modulus 300 GPa), and aluminum oxide (Al2O3, elastic modulus 350 to 392 GPa). By using a highly rigid material for the correction film 50, the correction film 50 can be made hard and resistant to stretching, and expansion of the second substrate 30 that occurs during bonding can be more appropriately suppressed.

[0055] Furthermore, the material for the correction film 50 preferably has a lower thermal expansion coefficient than the material for the second semiconductor layer 31. For example, if silicon (Si, elastic modulus 3.0-4.0 ppm / °C) is used as the material for the second semiconductor layer 31, the material for the correction film 50 can be hafnium oxide (HfO, thermal expansion coefficient 3.8-4.0 ppm / °C), zirconium oxide (ZrO2, 4.0-4.4 ppm / °C), titanium nitride (TiN, thermal expansion coefficient 5.0-7.0 ppm / °C), aluminum oxide (Al2O3, thermal expansion coefficient 5.9-7.0 ppm / °C), or titanium oxide (TiO2, thermal expansion coefficient 7.0-10.0 ppm / °C). By using a material with a low thermal expansion coefficient for the correction film 50, the correction film 50 can be made to be a film that is less likely to change in length due to temperature changes, and expansion of the second substrate 30 that occurs during bonding can be more appropriately suppressed.

[0056] [4-2 Manufacturing Method of Semiconductor Device] Next, a manufacturing method of the semiconductor device 1 according to the fourth embodiment will be described. While FIGS. 50 to 52 show a configuration in which one second substrate 30 is bonded to one first substrate 20 as the semiconductor device 1, a configuration in which two second substrates 30 are bonded together will be used here. As shown in FIG. 53 , first, a correction film 50 is formed on one surface S10 of the first wafer W1 using CVD (Chemical Vapor Deposition) technology or the like. Next, a second wafer W2 is bonded to the surface S11 of the correction film 50 opposite the first wafer W1 side to form a stacked wafer W3. The stacked wafer W3 is a wafer on which the second semiconductor layers 31 of multiple second substrates 30 are formed in a matrix. Next, the stacked wafer W3 is thinned from the second wafer W2 side using CMP (Chemical Mechanical Polishing) technology or the like. Next, chamfer grinding is performed on the outer periphery of the stacked wafer W3 to form a bevel on the stacked wafer W3. Next, the logic circuits 13 (see FIG. 2) of each of the plurality of second substrates 30 are formed on the laminated wafer W3.

[0057] Next, as shown in FIG. 54 , the second wiring layer 32 of each of the plurality of second substrates 30 is formed on the surface S12 of the laminated wafer W3 facing the second wafer W2, thereby forming the bonding surface (second surface S7) of the second substrate 30. Next, using BGR (Back Grinder) technology, the laminated wafer W3 is thinned from the first wafer W1 side. Next, the laminated wafer W3 is placed on a ring 51, and then the laminated wafer W3 is divided into a plurality of second substrates 30. Next, using a transfer device or the like, the divided second substrates 30 are transferred to another ring 52 (e.g., a 200 mm ring). Next, a cleaning process is performed to remove dust and the like from the surfaces of the second substrates 30.

[0058] Next, as shown in FIG. 55 , the second surface S7 of the second substrate 30 is subjected to surface treatment (chip activation) for bonding to the first substrate 20, followed by ring cleaning. Next, the second substrate 30 is removed from the ring 52 and bonded to the first substrate 20. Specifically, the individualized second substrate 30 is pressed against a wafer W on which a plurality of first substrates 20 are formed, thereby bonding the two substrates together. Due to the correction film 50, the second substrate 30 immediately prior to bonding is warped so that the second surface S7 forms an inverted dome-shaped concave surface, as shown in FIG. 52 . Therefore, when bonding the second substrate 30 to the first substrate 20, first, the four corners of the second surface S7 (second insulating film 33) of the second wiring layer 32 are bonded to the first surface S1 (first insulating film 23) of the first wiring layer 22. Then, bonding of the second surface S7 to the first surface S1 is carried out with the positional relationship between the four corners of the second surface S7 and the first surface S1 fixed. This prevents the second substrate 30 from expanding, reducing misalignment between the first bonding pads 24 of the first substrate 20 and the second bonding pads 34 of the second substrate 30. The bonding is performed in a vacuum to allow air to escape between the first substrate 20 and the second substrate 30.

[0059] Next, as shown in FIG. 56 , the second substrate 30 is thinned using CMP or the like from the surface opposite the second surface S7 (hereinafter also referred to as the “surface S13”). Thinning is continued until the portion of the second substrate 30 made of the first wafer W1 is removed and the correction film 50 is exposed. During this process, the correction film 50 acts as a stopper film, suppressing variations in the thickness of the second substrate 30. As a result, in a subsequent process, the bonding margin of the support substrate 54 (described below) can be expanded. Next, an insulating material 53 or the like is embedded in the surface of the wafer W to which the second substrate 30 is bonded (the first surface S1 of the first substrate 20) to flatten any irregularities, and then the support substrate 54 is bonded. Next, as shown in FIG. 57 , the first substrate 20 is thinned from the first semiconductor layer 21 side, and then an opening is formed in the back surface S3 of the first substrate 20 to expose the pad electrode 55 in the first wiring layer 22. Then, the probe 56 is used to measure the presence or absence of electrical continuity between the pad electrodes 55. By this procedure, the semiconductor device 1 shown in Figures 50 and 51 is manufactured.

[0060] Next, another method for forming the semiconductor device 1 will be described. As shown in FIG. 58, a first wafer W1 for forming multiple second substrates 30 is prepared. Next, the logic circuits 13 (see FIG. 2) and the like for each of the multiple second substrates 30 are formed on the first wafer W1. Next, the second wiring layer 32 for each of the multiple second substrates 30 is formed on one surface S10 of the first wafer W1 to form the bonding surface (second surface S7) of the second substrate 30. Next, using BGR technology, the first wafer W1 is thinned from the surface opposite the second wiring layer 32 (hereinafter also referred to as "surface S14"). Next, the first wafer W1 is placed on a ring 51 with the surface S14 facing upward. Next, using CVD technology or the like, a correction film 50 is formed on the surface S14 of the first wafer W1. 59, the surface S14 of the first wafer W1 is turned downward, and then the first wafer W1 is divided into a plurality of second substrates 30. Next, using a transfer device or the like, the divided second substrates 30 are transferred to another ring 52. Next, a cleaning process is performed to remove dust and the like from the surface of the second substrate 30.

[0061] Next, as shown in FIG. 60 , the second surface S7 of the second substrate 30 is subjected to surface treatment (chip activation) for bonding to the first substrate 20, followed by ring cleaning. Next, the second substrate 30 is removed from the ring 52, and the second substrate 30 is bonded to the first substrate 20. Specifically, the individualized second substrate 30 is pressed against a wafer W on which a plurality of first substrates 20 are formed, thereby bonding the two substrates together. Due to the correction film 50, the second substrate 30 immediately prior to bonding is warped so that the second surface S7 forms an inverted dome-shaped concave surface, as shown in FIG. 52 . Therefore, when bonding the second substrate 30 to the first substrate 20, first, the four corners of the second surface S7 (second insulating film 33) of the second wiring layer 32 are bonded to the first surface S1 (first insulating film 23) of the first wiring layer 22. Then, bonding of the second surface S7 to the first surface S1 is carried out with the positional relationship between the four corners of the second surface S7 and the first surface S1 fixed. This prevents the second substrate 30 from expanding, reducing misalignment between the first bonding pads 24 of the first substrate 20 and the second bonding pads 34 of the second substrate 30. The bonding is performed in a vacuum to allow air to escape between the first substrate 20 and the second substrate 30.

[0062] Next, as shown in FIG. 61 , the second substrate 30 is thinned from the surface (surface S13) opposite the second surface S7 using CMP or the like. Thinning is continued until the correction film 50 of the second substrate 30 is removed and the first wafer W1 (second semiconductor layer 31) is exposed. Next, an insulating material 53 or the like is embedded in the surface of the wafer W to which the second substrate 30 is bonded (first surface S1 of the first substrate 20) to flatten any irregularities, and then a support substrate 54 is bonded. Next, as shown in FIG. 62 , after thinning the first substrate 20 from the first semiconductor layer 21 side, openings are formed in the back surface S3 of the first substrate 20 to expose the pad electrodes 55 in the first wiring layer 22. Next, a probe 56 is used to measure the presence or absence of electrical continuity between the pad electrodes 55. Through this procedure, the semiconductor device 1 shown in FIGS. 50 and 51 is manufactured.

[0063] [4-3 Modifications] (1) In the fourth embodiment, an example was shown in which the four corners of the second substrate 30 were first joined to the first substrate 20 when bonding the second substrate 30, but other configurations may also be employed. For example, a configuration may be adopted in which the second substrate 30 is bent to reduce warpage, and the flat second substrate 30 is then bonded to the first substrate 20. In this case, by using, as the material for the correction film 50, a material with a higher rigidity than the second semiconductor layer 31 or a material with a lower thermal expansion coefficient than the material for the second semiconductor layer 31, the correction film 50 can suppress expansion of the second substrate 30 that occurs during bonding.

[0064] (2) Although the fourth embodiment illustrates an example in which the correction film 50 is laminated on the surface S9 of the second semiconductor layer 31, other configurations may also be employed. For example, as shown in FIG. 63 , the correction film 50 may be disposed between a portion of the second semiconductor layer 31 on the second wiring layer 32 side (hereinafter also referred to as the “first portion 57”) and a portion on the opposite side of the second wiring layer 32 (hereinafter also referred to as the “second portion 58”). FIG. 63 illustrates an example in which the second semiconductor layer 31 has a two-layer structure in which a flat first portion 57 and a flat second portion 58 are laminated, and the correction film 50 is formed between the first portion 57 and the second portion 58. In this case, in the manufacturing process illustrated in FIGS. 53 to 57 , the second substrate 30 is thinned in the thinning step illustrated in FIG. 56 so that the portion formed by the first wafer W1 (see FIG. 55 ) remains on the second substrate 30.

[0065] (3) Although the fourth embodiment illustrates an example in which one second substrate 30 is bonded to one first substrate 20, other configurations may also be employed. For example, as shown in FIGS. 64 and 65 , a configuration in which two or more second substrates 30 are bonded to one first substrate 20 (multi-chip configuration) may be employed. FIG. 64 illustrates the first substrate 20 and the second substrate 30 as viewed obliquely, as well as a cross-section of the second substrate 30. In FIG. 64 , the cross-section of the second substrate 30 illustrates the cross-section of the second substrate 30 immediately before bonding. FIG. 65 also illustrates a plan view of the positional relationship between the first bonding pads 24 and the second bonding pads 34. In this case, the correction film 50 is designed for each second substrate 30 so as to suppress expansion of the second substrate 30 during bonding. For example, the film stress and film thickness of the correction film 50 are adjusted. By designing the correction film 50 for each second substrate 30, the misalignment between the second bonding pads 34 of two or more second substrates 30 and the first bonding pads 24 of the first substrate 20 can be reduced when the second substrates 30 are bonded together.

[0066] (4) In the fourth embodiment, the first bonding pads 24 and the second bonding pads 34 are all the same size, but other configurations may be adopted. For example, a configuration may be adopted in which the correction film 50 is provided and the size, shape, arrangement, etc. of the first bonding pads 24 and the second bonding pads 34 are changed, as in the semiconductor device 1 according to the first to third embodiments.

[0067] (5) Furthermore, the present technology can be applied to semiconductor devices in general, in addition to the semiconductor device 1 as the image sensor shown in the first to fourth embodiments.

[0068] 5. Fifth Embodiment The technology according to the present disclosure (the present technology) may be applied to various electronic devices. Fig. 66 is a diagram showing an example of a schematic configuration of an imaging device (digital still camera, video camera, etc.) as an electronic device to which the present technology is applied. As shown in Fig. 66, the imaging device 1000 includes a lens group 1001, a solid-state imaging device 1002 (the semiconductor device 1 according to the first embodiment), a signal processing circuit 1003, a memory 1004, and a monitor 1005. The signal processing circuit 1003, the memory 1004, and the monitor 1005 are connected to each other via a bus line 1006.

[0069] The lens group 1001 guides incident light (image light) from a subject to the solid-state imaging device 1002, forming an image on the light-receiving surface (pixel region) of the solid-state imaging device 1002. The solid-state imaging device 1002 is composed of the CMOS image sensor of the first embodiment described above. The solid-state imaging device 1002 converts the amount of incident light imaged on the light-receiving surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies the pixel signal to the signal processing circuit 1003. The signal processing circuit 1003 then performs predetermined image processing on the pixel signal supplied from the solid-state imaging device 1002. The signal processing circuit 1003 then stores the processed image signal in a memory 1004 and displays an image of the subject on a monitor 1005 based on the image signal. The memory 1004 is composed of a flash memory or the like. The monitor 1005 is composed of a display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel.

[0070] Note that the electronic device to which the semiconductor device 1 can be applied is not limited to the imaging device 1000, but can also be applied to other electronic devices. Also, although the solid-state imaging device 1002 is configured to use the semiconductor device 1 according to the first embodiment, other configurations can also be adopted. For example, the solid-state imaging device 1002 may be configured to use other photodetector devices to which the present technology is applied, such as the semiconductor device 1 according to the second to fourth embodiments and modified examples of the first to fourth embodiments.

[0071] 6. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0072] FIG. 67 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0073] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 67, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0074] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0075] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0076] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0077] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0078] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0079] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0080] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0081] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0082] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 67, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0083] FIG. 68 is a diagram showing an example of the installation position of the imaging unit 12031.

[0084] In FIG. 68, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0085] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0086] 68 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0087] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0088] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0089] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0090] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0091] The above describes an example of a vehicle control system to which the technology disclosed herein can be applied. The technology disclosed herein can be applied to the imaging unit 12031 and other components of the above-described configuration. Specifically, the semiconductor device 1 (image sensor) of FIG. 2 can be applied to the imaging unit 12031. By applying the technology disclosed herein to the imaging unit 12031, it is possible to reduce misalignment between the first bonding pad 24 and the second bonding pad 34, thereby improving the reliability of the imaging unit 12031 and the reliability of the vehicle control system.

[0092] The present technology may also be configured as follows: (1) A semiconductor device comprising: a first substrate; and a second substrate having a size in a plan view smaller than that of the first substrate and bonded to a first region of a first surface that is one surface of the first substrate, wherein the first substrate comprises a first insulating film that forms the first surface of the first substrate, a first wiring layer including a plurality of first bonding pads arranged in the first insulating film in a matrix pattern and arranged in the first insulating film so that a surface thereof is located in the same plane as the first surface, and a first semiconductor layer stacked on a surface of the first wiring layer opposite the first surface, wherein the second substrate forms a second surface that is a surface of the second substrate facing the first substrate, and comprises a second insulating film bonded to the first insulating film, a second wiring layer arranged in the second insulating film in a matrix pattern and arranged in the second insulating film so that a surface thereof is located in the same plane as the second surface and arranged to the first bonding pads, and a second semiconductor layer stacked on a surface of the second wiring layer opposite the second surface, (2) The semiconductor device according to (1), wherein the second intervals between adjacent first bond pads in a second region other than the first region on the first surface are constant, and the first intervals between adjacent first bond pads in the first region are different from the second intervals. (2) The semiconductor device according to (1), wherein the first intervals are larger than the second intervals in both the row direction and the column direction of the matrix of the first bond pads. (3) The semiconductor device according to (1), wherein the first intervals are larger than the second intervals in a direction perpendicular to a specific straight line set on the first surface. (4) The semiconductor device according to (3), wherein the first wiring layer has wiring and first vias connecting the first bond pads to the wiring, and the second wiring layer has wiring and second vias connecting the second bond pads to the wiring, and the spacing between the first vias connected to the first bond pads in the first region is the same as the spacing between the first vias connected to the first bond pads in the second region.(5) The semiconductor device according to (3), wherein the first wiring layer has wiring and first vias connecting the first bond pads to the wiring, the second wiring layer has wiring and second vias connecting the second bond pads to the wiring, and the spacing between the first vias connected to the first bond pads in the first region is different from the spacing between the first vias connected to the first bond pads in the second region. (6) The semiconductor device according to any of (1) to (5), wherein some of the first bond pads are dummy electrodes. (7) The semiconductor device according to any of (1) to (6), wherein two or more second substrates are bonded to one first substrate. (8) The semiconductor device according to any of (1) to (7), wherein, in a plan view, the size of the first bond pads in the first region is different from the size of the first bond pads in the second region. (9) The semiconductor device according to (8), wherein the size of the first bond pads in the first region increases as the distance from a specific position in the first region increases. (10) The semiconductor device according to (8), wherein the first bond pad is a linear connection pad extending along the longitudinal direction of a straight line extending radially from a specific position in the first region. (11) The semiconductor device according to (8), wherein the first bond pad is an arc-shaped connection pad extending along the circumferential direction of a circle centered at the specific position in the first region. (12) The semiconductor device according to (11), wherein the first bond pad is a fan-shaped bond pad extending along both the circumferential direction and the radial direction of the circle. (13) The semiconductor device according to (8), wherein the first bond pad is a linear bond pad extending in a direction perpendicular to the specific straight line set in the first region.(14) A semiconductor device comprising: a first substrate; and a second substrate having a size in a planar view smaller than that of the first substrate and bonded to a first region of a first surface that is one surface of the first substrate, wherein the first substrate comprises a first insulating film that forms the first surface of the first substrate, a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film so that a surface thereof is located in the same plane as the first surface, and a first semiconductor layer stacked on a surface of the first wiring layer opposite the first surface; wherein the second substrate forms a second surface that is a surface of the second substrate facing the first substrate, and comprises a second insulating film bonded to the first insulating film, a second wiring layer arranged in a matrix within the second insulating film so that a surface thereof is located in the second insulating film so that a surface thereof is located in the same plane as the second surface, and arranged to the first bonding pads, and a second semiconductor layer stacked on a surface of the second wiring layer opposite the second surface; The semiconductor device according to (14), wherein, in a plan view, the size of the second bond pads is different from the size of the first bond pads in a second region other than the first region of the first surface. (15) The semiconductor device according to (14), wherein the size of the second bond pads increases as the distance from a specific position on the second surface increases. (16) The semiconductor device according to (14), wherein the second bond pads are linear bond pads extending along the longitudinal direction of a line extending radially from the specific position on the second surface. (17) The semiconductor device according to (14), wherein the second bond pads are arc-shaped bond pads extending along the circumferential direction of a circle centered at the specific position on the second surface. (18) The semiconductor device according to (17), wherein the second bond pads are fan-shaped bond pads extending along both the circumferential direction and the radial direction of the circle. (19) The semiconductor device according to (14), wherein the second bond pads are linear bond pads extending in a direction perpendicular to the specific line set on the second surface.(20) A semiconductor device comprising: a first substrate; and a second substrate having a size in a plan view smaller than that of the first substrate and bonded to a first region of a first surface that is one surface of the first substrate, wherein the first substrate comprises a first insulating film that forms the first surface of the first substrate, a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film so that a surface thereof is located in the same plane as the first surface, and a first semiconductor layer stacked on a surface of the first wiring layer opposite the first surface; wherein the second substrate forms a second surface that is a surface of the second substrate facing the first substrate, and comprises a second insulating film bonded to the first insulating film, a second wiring layer arranged in a matrix within the second insulating film so that a surface thereof is located in the second insulating film so that a surface thereof is located in the same plane as the second surface, and arranged to the first bonding pads, and a second semiconductor layer stacked on a surface of the second wiring layer opposite the second surface; A semiconductor device having a correction film stacked on a surface of the second semiconductor layer opposite to the second wiring layer side, or disposed between a portion of the second semiconductor layer on the second wiring layer side and a portion of the second semiconductor layer opposite to the second wiring layer, and containing a material different from the second semiconductor layer. (21) The semiconductor device according to (20), wherein the material of the correction film is a material with higher rigidity than the material of the second semiconductor layer. (22) The semiconductor device according to (20) or (21), wherein the material of the correction film is a material with a lower thermal expansion coefficient than the material of the second semiconductor layer. (23) The semiconductor device according to any of (20) to (22), wherein the correction film is a nitride film. (24) The semiconductor device according to any of (20) to (23), wherein the correction film is a stress film that generates stress in the second substrate in a direction that causes warpage such that the second surface becomes an inverted dome-shaped concave surface.(25) A semiconductor device comprising: a first substrate; and a second substrate having a size in a plan view smaller than that of the first substrate and bonded to a first region of a first surface that is one surface of the first substrate, wherein the first substrate comprises a first insulating film that forms the first surface of the first substrate; a first wiring layer including a plurality of first bonding pads that are arranged in a matrix within the first insulating film and that are arranged in the first insulating film so that their surfaces are located in the same plane as the first surface; and a first semiconductor layer that is stacked on a surface of the first wiring layer opposite to the first surface; wherein the second substrate forms a second surface that is a surface of the second substrate that faces the first substrate, and a first insulating film that is stacked on the first surface of the first substrate. a second insulating film bonded to the first surface, a second wiring layer including a plurality of second bonding pads arranged in a matrix within the second insulating film, the second wiring layer having a surface located in the second insulating film and bonded to the first bonding pads, the second wiring layer including a plurality of second bonding pads bonded to the first bonding pads, and a second semiconductor layer stacked on a surface of the second wiring layer opposite the second surface, wherein second intervals that are intervals between adjacent first bonding pads in a second region that is a region other than the first region on the first surface are constant, and first intervals that are intervals between adjacent first bonding pads in the first region are different from the second intervals.(26) A semiconductor device comprising: a first substrate; and a second substrate having a size in a plan view smaller than that of the first substrate and bonded to a first region of a first surface that is one surface of the first substrate, wherein the first substrate comprises a first insulating film that forms the first surface of the first substrate; a first wiring layer including a plurality of first bonding pads that are arranged in a matrix within the first insulating film and that are arranged in the first insulating film so that a surface of the first bonding pad is located in the same plane as the first surface; and a first semiconductor layer that is stacked on a surface of the first wiring layer opposite to the first surface, an insulating film forming a second surface and bonded to the first insulating film; a second wiring layer including a plurality of second bonding pads arranged in a matrix within the second insulating film, the second wiring layer having a surface in the second insulating film positioned in the same plane as the second surface and bonded to the first bonding pads; and a second semiconductor layer stacked on a surface of the second wiring layer opposite the second surface, wherein, in a plan view, the second bonding pads have a size different from the size of the first bonding pads in a second region that is a region other than the first region of the first surface. (27) A semiconductor device comprising: a first substrate; and a second substrate having a size in a plan view smaller than that of the first substrate and bonded to a first region of a first surface that is one surface of the first substrate, wherein the first substrate comprises a first insulating film that forms the first surface of the first substrate; a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film so that a surface thereof is located in the same plane as the first surface; and a first semiconductor layer stacked on a surface of the first wiring layer opposite the first surface; wherein the second substrate forms a second surface that is a surface of the second substrate facing the first substrate, and comprises a second insulating film bonded to the first insulating film; and a second wiring layer including a plurality of second bonding pads arranged in a matrix within the second insulating film and arranged in the second insulating film so that a surface thereof is located in the same plane as the second surface and joined to the first bonding pads; and a second semiconductor layer stacked on a surface of the second wiring layer opposite the second surface; electronic equipment.

[0093] REFERENCE SIGNS LIST 1...Semiconductor device, 2A...Pixel region, 2B...Peripheral region, 3...Pixel, 4...Vertical drive circuit, 5...Column signal processing circuit, 6...Horizontal drive circuit, 7...Output circuit, 8...Control circuit, 9...Pixel drive wiring, 10...Vertical signal line, 12...Horizontal signal line, 13...Logic circuit, 14...Bonding pad, 20...First substrate, 21...First semiconductor layer, 22...First wiring layer, 23...First insulating film, 24...First bonding pad, 241...Dummy electrode, 25...Wiring, 251...First wiring, 252...Second wiring, 26...First via, 30...Second substrate, 31...Second semiconductor layer, 32...Second wiring layer 32...Second insulating film, 34...Second bonding pad, 35...Wiring, 351...First wiring, 352...Second wiring, 36...Second via, 37 i ...Design position, 38 i ...straight line, 39...pressed straight line, 40, 40 i ...Circle, 41...Line, 42 i ...Design position, 43 i ...straight line, 44...circle, 44 i ...circle, 50...correction film, 51, 52...ring, 53...insulating material, 54...support substrate, 55...pad electrode, 56...probe, 57...first part, 58...second part, 1000...imaging device, 1001...lens group, 1002...solid-state imaging device, 1003...signal processing circuit, 1004...memory, 1005...monitor, 1006...bus line

Claims

1. A semiconductor device comprising: a first substrate; and a second substrate having a size in a plan view smaller than that of the first substrate and bonded to a first region of a first surface, which is one surface of the first substrate; the first substrate comprises a first insulating film forming the first surface of the first substrate, a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film such that a surface of the first wiring layer is located in the same plane as the first surface, and a first semiconductor layer laminated on a surface of the first wiring layer opposite to the first surface; the second substrate comprises a second insulating film forming a second surface, which is a surface of the second substrate facing the first substrate, bonded to the first insulating film, a second wiring layer including a plurality of second bonding pads arranged in a matrix within the second insulating film and arranged in the second insulating film such that a surface of the second wiring layer is located in the same plane as the second surface, and bonded to the first bonding pads, and a second semiconductor layer laminated on a surface of the second wiring layer opposite to the second surface; A semiconductor device, wherein a second interval, which is the interval between adjacent first bonding pads in a second region other than the first region of the first surface, is constant, and the first interval, which is the interval between adjacent first bonding pads in the first region, is different from the second interval.

2. The semiconductor device according to claim 1, wherein the first interval is greater than the second interval in both the row direction and the column direction of the matrix of the first bonding pads.

3. The semiconductor device according to claim 1, wherein the first interval is greater than the second interval in a direction perpendicular to the specific straight line set on the first surface.

4. The semiconductor device described in claim 3, wherein the first wiring layer has a wiring and a first via connecting the first bonding pad to the wiring, the second wiring layer has a wiring and a second via connecting the second bonding pad to the wiring, and the spacing between the first vias connected to the first bonding pads in the first region is the same as the spacing between the first vias connected to the first bonding pads in the second region.

5. The semiconductor device described in claim 3, wherein the first wiring layer has a wiring and a first via connecting the first bonding pad to the wiring, the second wiring layer has a wiring and a second via connecting the second bonding pad to the wiring, and the spacing between the first vias connected to the first bonding pads in the first region is different from the spacing between the first vias connected to the first bonding pads in the second region.

6. The semiconductor device according to claim 1, wherein some of the plurality of first bonding pads are dummy electrodes.

7. The semiconductor device according to claim 1, wherein two or more of the second substrates are bonded to one of the first substrates.

8. The semiconductor device according to claim 1, wherein, in a plan view, a size of the first bonding pad in the first region is different from a size of the first bonding pad in the second region.

9. The semiconductor device according to claim 8, wherein the size of the first bonding pad in the first region increases as the distance from a specific position in the first region increases.

10. The semiconductor device according to claim 8, wherein the first bonding pad is a linear connection pad extending along the longitudinal direction of a straight line extending radially from a specific position within the first region.

11. The semiconductor device according to claim 8, wherein the first bonding pad is an arc-shaped connection pad extending along the circumferential direction of a circle centered at a specific position within the first region.

12. The semiconductor device according to claim 11, wherein the first bonding pad is a fan-shaped bonding pad extending along both the circumferential direction and the radial direction of the circle.

13. The semiconductor device according to claim 8, wherein the first bonding pad is a linear bonding pad extending in a direction perpendicular to the specific straight line set in the first region.

14. A semiconductor device comprising: a first substrate; and a second substrate having a size in a plan view smaller than that of the first substrate and bonded to a first region of a first surface which is one surface of the first substrate; the first substrate comprises a first insulating film forming the first surface of the first substrate, a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film such that a surface of the first wiring layer is located in the same plane as the first surface, and a first semiconductor layer laminated on a surface of the first wiring layer opposite to the first surface; the second substrate comprises a second insulating film forming a second surface which is a surface of the second substrate facing the first substrate, bonded to the first insulating film, a second wiring layer including a plurality of second bonding pads arranged in a matrix within the second insulating film and arranged in the second insulating film such that a surface of the second wiring layer is located in the same plane as the second surface and joined to the first bonding pads, and a second semiconductor layer laminated on a surface of the second wiring layer opposite to the second surface; A semiconductor device, wherein, in a plan view, a size of the second bonding pad is different from a size of the first bonding pad in a second region that is a region other than the first region of the first surface.

15. The semiconductor device according to claim 14, wherein the size of said second bonding pad increases as the distance from the specific position on said second surface increases.

16. The semiconductor device according to claim 14, wherein the second bonding pad is a linear connection pad extending along the longitudinal direction of a straight line extending radially from a specific position within the second surface.

17. The semiconductor device according to claim 14, wherein the second bonding pad is an arc-shaped connection pad extending in the circumferential direction of a circle centered at a specific position on the second surface.

18. The semiconductor device according to claim 17, wherein the second bonding pad is a fan-shaped bonding pad extending along both the circumferential direction and the radial direction of the circle.

19. The semiconductor device according to claim 14, wherein the second bonding pad is a linear bonding pad extending in a direction perpendicular to the specific straight line set on the second surface.

20. A semiconductor device comprising: a first substrate; and a second substrate having a size in a plan view smaller than that of the first substrate and bonded to a first region of a first surface, which is one surface of the first substrate; the first substrate comprises a first insulating film forming the first surface of the first substrate, a first wiring layer arranged in a matrix within the first insulating film, the first wiring layer including a plurality of first bonding pads arranged in the first insulating film such that a surface of the first wiring layer is located in the same plane as the first surface, and a first semiconductor layer laminated on a surface of the first wiring layer opposite to the first surface; the second substrate comprises a second insulating film forming a second surface of the second substrate facing the first substrate, bonded to the first insulating film, a second wiring layer arranged in a matrix within the second insulating film, the second wiring layer including a plurality of second bonding pads arranged in the second insulating film such that a surface of the second wiring layer is located in the same plane as the second surface, and bonded to the first bonding pads, and a second semiconductor layer laminated on a surface of the second wiring layer opposite to the second surface; A semiconductor device having a correction film that is laminated on a surface of the second semiconductor layer opposite to the second wiring layer side, or is disposed between a portion of the second semiconductor layer on the second wiring layer side and a portion of the second semiconductor layer opposite to the second wiring layer, and includes a material different from that of the second semiconductor layer of the second semiconductor layer.

21. The semiconductor device according to claim 20, wherein the material of the correction film is a material having a higher rigidity than the material of the second semiconductor layer.

22. The semiconductor device according to claim 20, wherein the material of the correction film has a thermal expansion coefficient lower than that of the material of the second semiconductor layer.

23. The semiconductor device according to claim 20, wherein the correction film is a nitride film.

24. The semiconductor device according to claim 20, wherein the correction film is a stress film that generates stress in the second substrate in a direction that causes warping such that the second surface becomes an inverted dome-shaped concave surface.

25. A semiconductor device comprising: a first substrate; and a second substrate having a size in a plan view smaller than that of the first substrate and bonded to a first region of a first surface, which is one surface of the first substrate, the first substrate comprising: a first insulating film forming the first surface of the first substrate; a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film such that the surface is located in the same plane as the first surface; and a first semiconductor layer laminated on a surface of the first wiring layer opposite to the first surface; the second substrate forming a second surface, which is the surface of the second substrate facing the first substrate, and a first insulating film having a first bonding pad and a first semiconductor layer laminated on the first insulating film. an insulating film bonded to the first surface, a second wiring layer including a plurality of second bonding pads arranged in a matrix within the second insulating film, the second wiring layer including a plurality of second bonding pads arranged in the second insulating film such that the surface is located in the same plane as the second surface and bonded to the first bonding pads; and a second semiconductor layer stacked on a surface of the second wiring layer opposite the second surface, wherein a second interval, which is the interval between adjacent first bonding pads in a second region that is a region other than the first region on the first surface, is constant, and a first interval, which is the interval between adjacent first bonding pads in the first region, is different from the second interval.

26. A semiconductor device comprising: a first substrate; and a second substrate having a size in a plan view smaller than that of the first substrate and bonded to a first region of a first surface, which is one surface of the first substrate, the first substrate comprising: a first insulating film forming the first surface of the first substrate; a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film such that the surface is located in the same plane as the first surface; and a first semiconductor layer laminated on a surface of the first wiring layer opposite to the first surface, the second substrate comprising: a first insulating film forming the first surface of the first substrate; an insulating film forming a second surface and bonded to the first insulating film; a second wiring layer including a plurality of second bonding pads arranged in a matrix within the second insulating film, disposed in the second insulating film such that its surface is located in the same plane as the second surface and bonded to the first bonding pads; and a second semiconductor layer stacked on a surface of the second wiring layer opposite the second surface, wherein, when viewed in a plan view, a size of the second bonding pads is different from a size of the first bonding pads in a second region which is a region other than the first region of the first surface.

27. A semiconductor device comprising: a first substrate; and a second substrate having a size in a plan view smaller than that of the first substrate and bonded to a first region of a first surface, which is one surface of the first substrate; the first substrate comprising: a first insulating film forming the first surface of the first substrate; a first wiring layer including a plurality of first bonding pads arranged in a matrix within the first insulating film and arranged in the first insulating film such that a surface of the first wiring layer is located in the same plane as the first surface; and a first semiconductor layer laminated on a surface of the first wiring layer opposite to the first surface; the second substrate comprising: a second insulating film forming a second surface, which is a surface of the second substrate facing the first substrate, bonded to the first insulating film; a second wiring layer including a plurality of second bonding pads arranged in a matrix within the second insulating film and arranged in the second insulating film such that a surface of the second wiring layer is located in the same plane as the second surface and bonded to the first bonding pads; and a second semiconductor layer laminated on a surface of the second wiring layer opposite to the second surface; electronic equipment.

Images