LR bluetooth synchronization using phase compensation by PLL adjustments

Abstract

Various arrangements for synchronizing earbuds are described herein. The synchronizing can include generating, via a first phase-locked loop (PLL) circuit of a first earbud, a first timing signal that is used to perform one or more first operations associated with the first earbud, wherein the first PLL includes a first input coupled to an internal clock signal; generating, via a second PLL circuit of the first earbud, a second timing signal, wherein the second PLL includes a second input coupled to an external clock signal; determining a phase adjustment value to synchronize the states of internal audio processing circuitry with a second phase associated with the second timing signal; causing a phase shift of the second PLL circuit based on the phase adjustment value; and enabling the second PLL circuit to perform one or more second operations for the first earbud without interruption of audio operations while performing this adjustment.

Description

LR BLUETOOTH SYNCHRONIZATION USING PHASE COMPENSATION BY PLL ADJUSTMENTSBACKGROUND

[0001] True wireless earbuds (e.g., earbuds that do not have physical connections) have become increasingly popular in recent years. While the sound quality of true wireless earbuds is generally very good, in some cases there can be a time delay between when a left earbud outputs audio and when a right earbud outputs audio. In some cases, this lag can be noticed by a user if there is a sufficient mismatch between when the sound is produced by the left earbud and the right earbud. The ears are very sensitive to phase differences between signals because this property is used by the brain to sense direction. Thus, to obtain a good playback experience and to comply with recognized international wireless standards, there is a desire to ensure the playback delay in both earbuds is very close. Correcting this lag between earbuds, however, can be challenging because the two earbuds may not be powered on at the same time and may have different internal time references.SUMMARY

[0002] Various embodiments for left / right (LR) Bluetooth (BT) synchronization using phase adjustments by phase-locked loop (PLL) adjustments are described herein. Using the techniques described herein, the PLL adjustments are performed independently by each earbud. As such, the left earbud and the right earbud do not need to coordinate the PLL adjustments. Such PLL adjustments are transparent to the source device (e.g., the audio source) and the source device needs to take no action. The arrangements detailed does not require a direct link between the earbuds nor direct coordination. In addition, automatic noise cancellation (ANC) operations can continue to be performed even while these PLL adjustments are performed. The arrangement detailed herein further can include algorithms / techniques to cause the phase adjustment to be performed.

[0003] A system of one or more computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination of them installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions. One general aspect includes a method for synchronizing earbuds that communicate using a wireless protocol. In some examples, the method also includes generating, via a first phase-locked loop (PLL) circuit of a first earbud, a first timing signal that is used to perform one or more first operations associated with the first earbud, where the first PLL includesa first input coupled to an internal clock signal. In some examples, the method also includes generating, via a second PLL circuit of the first earbud, a second timing signal, where the second PLL includes a second input coupled to an external clock signal. In some examples, the method also includes determining a phase adjustment value to synchronize internal audio circuits, associated with a timing signal, with the phase associated with the second timing signal. In some examples, the method also includes causing a phase shift of the second PLL circuit based on the phase adjustment value. In some examples, the method also includes enabling the second PLL circuit to perform one or more second operations for the first earbud. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

[0004] Implementations may include one or more of the following features. The method where the one or more first operations include automatic noise cancelation (ANC) operations associated with the first earbud and where the one or more second operations include audio playback operations. Causing the phase shift may include changing a setting of a PLL divider circuit for a predetermined time period based on the phase adjustment value. Determining the phase adjustment value may include determining a value of a counter circuit of the first earbud at a sync event associated by a wireless circuit and provided by the wireless interface. The method may include: changing a setting of a PLL divider circuit associated with the second PLL from a first value to a second value; determining that a predetermined amount of time has elapsed; and changing the setting of the PLL divider circuit associated with the second PLL from the second value to the first value. In some examples, the method may include: changing a setting of a PLL divider circuit associated with the second PLL from a first value to a second value; periodically monitoring a phase difference by checking the value of an internal counter at synchronization events provided by a wireless circuit and; and changing the setting of the PLL divider circuit associated with the second PLL from the second value to the first value when a desired timing has been achieved. In some examples, a phase shift is performed using a fractional phase shifter as part of an interpolation chain while this filter chain is muted. The first earbud remains unmuted during the phase shift. Implementations of the described techniques may include hardware, a method or process, or computer software on a computer-accessible medium.

[0005] One general aspect includes a wireless earbud system that uses a wireless protocol. The wireless earbud system also includes a first earbud may include: a first wireless interface, a first speaker, a first processing system, a first PLL, a second PLL, an audio circuit, and a first microphone. The system also includes a second earbud may include: a second wireless interface, a second speaker, a second processing system, a third PLL, a fourth PLL, an audio circuit and asecond microphone, where: the first earbud is not physically connected with the second earbud; the first earbud is configured to: generate, via the first PLL, a first timing signal that is used to perform first operations associated with the first earbud, where the first PLL includes a first input coupled to a first internal clock signal; determine a phase adjustment value to synchronize the audio circuit with a second phase associated with a second timing signal; cause a first phase shift of the second PLL based on the phase adjustment value; and select the second PLL to perform one or more second operations. The system also includes the second earbud is configured to: generate, via the third PLL, a third timing signal that is used to perform third operations associated with the second earbud, where the third PLL includes a third input coupled to a second internal clock signal; determine a second phase adjustment value to synchronize a third phase associated with the third timing signal with a fourth phase associated with a fourth timing signal; cause a second phase shift of the fourth PLL based on the second phase adjustment value. The system also includes select the fourth PLL to perform one or more fourth operations. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

[0006] Implementations may include one or more of the following features. The wireless earbud system where one or more of the first earbud or the second earbud is further configured to perform automatic noise cancelation (ANC) operations during one or more of a first time to perform the phase adjustment or a second time to perform the second phase adjustment. Causing the first phase shift may include changing a setting of a PLL divider of the first earbud based, at least in part on a state of internal audio processing. Determining the phase adjustment value may include determining a value of a counter of the first earbud at a synchronization event provided by the wireless interface such as a falling edge event associated with an external word select I2S audio signal. The first internal clock signal is generated by an internal clock of the first earbud. The first earbud and the second earbud are true wireless stereo earbuds. The first earbud remains unmuted during the phase adjustment and the second earbud remains unmuted during the second phase adjustment. Implementations of the described techniques may include hardware, a method or process, or computer software on a computer-accessible medium.

[0007] One general aspect includes a wireless earbud that uses a wireless protocol. The wireless earbud also includes a wireless interface. The earbud also includes a microphone. The earbud also includes a speaker. The earbud also includes a first PLL. The earbud also includes a second PLL. The earbud also includes an audio circuit. The earbud also includes a processing system in communication with the wireless interface, the microphone, the speaker, the first PLL, and the second PLL, configured to perform operations may include: generating, via internal audioprocessing circuitry a first timing signal based on either an output from the first or second PLL, that is used to perform one or more first operations, where the first PLL includes a first input coupled to an internal clock signal; generating, via the second PLL, a second timing signal, where the second PLL includes a second input coupled to an external clock signal; determining a phase adjustment value to synchronize a first phase associated with the first timing signal from the audio processing circuitry with a second phase associated with the second timing signal; causing a phase shift of the second PLL based on the phase adjustment value; and enabling the second PLL to perform one or more second operations. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

[0008] Implementations may include one or more of the following features. The wireless earbud where the one or more first operations include automatic noise cancelation (ANC) operations.Causing the phase shift may include changing a setting of a PLL divider for a predetermined time period based on the phase adjustment value. Determining the phase adjustment value may include determining an internal state of audio processing circuitry of the wireless earbud at specific time determined by the wireless interface such as a falling edge event associated with an external word select from an I2S audio signal. The wireless earbud remains unmuted during the phase shift. Implementations of the described techniques may include hardware, a method or process, or computer software on a computer-accessible medium.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A further understanding of the nature and advantages of various embodiments may be realized by reference to the following figures. In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

[0010] FIG. 1 illustrates a system in which audio is transmitted between an audio source and earbuds and a wireless synchronization signal such as Bluetooth piconet is used to obtain a reference signal and this signal will be used for alignment between internal timing circuits and the external clock signal, according to some embodiments.

[0011] FIG. 2 illustrates a system in which phase adjustments are made to a PLL used for audio playback, according to some embodiments.

[0012] FIG. 3 illustrates an example process for performing LR synchronization of earbuds, according to some embodiments.

[0013] FIG. 4 illustrates an example process for using a phase difference to perform LR synchronization, according to some embodiments.

[0014] FIG. 5 illustrates an example system showing how to implement a fractional delay for synchronization of an internal timing signal with an I2S signal, according to some embodiments.

[0015] FIG. 6 illustrates an example ANC system in which LR synchronization is performed, according to some embodiments.

[0016] FIG. 7 illustrates an example process for using fractional delays to perform LR synchronization, according to some embodiments.DETAILED DESCRIPTION

[0017] Techniques are described herein that are directed to synchronizing the playback of audio in sink devices (e.g., true wireless stereo (TWS) earbuds that may be referred to herein as “earbuds”). The techniques are directed to reducing the lag / delay between the left-right (LR) earbuds audio output by performing LR synchronization alignment, reducing power consumption, and helping to ensure that sink devices output audio data transmitted by a source device within a predetermined time (e.g., + / - 25 is) of each other.

[0018] When using Bluetooth (BT) true wireless earbuds, it is desirable that both left and right ear receives the audio with the same, or similar, delay. While the BT protocol has built in mechanisms, such as piconet timing, to provide timing alignment, these mechanisms do not solve the problem of performing the actual timing alignment of the associated audio circuits. As such, prior to techniques described herein, a first sink device and a second sink device may not be synchronized resulting in a user’s spatial perception of audio being negatively affected.

[0019] Embodiments detailed herein can involve a sink device (e.g., a first / second earbud) performing phase shift operations to adjust for a phase difference detected between an internal timing signal generated by an earbud and an external clock signal. Such phase shift operations can be performed by each sink device that is transparent to the source, and the source needs to take no action. The arrangements detailed herein do not require a direct link between the earbuds nor direct coordination. The arrangement detailed herein further can include techniques / algorithms to cause a sink device to change from using a first PLL that is synced with an internal clock signal, to a second PLL that is synced with an external clock signal.

[0020] There are different techniques / algorithms which can be used in isolation, or in some combination, to perform the LR synchronization alignment. Modem audio circuits typically employ multiple decimator and interpolator sections, running at different sample frequencies to support low power operation and input from digital microphones and amplifiers that employ digital modulation techniques. Because of the use of multiple sample rates, incoming audio samples from an external wired connection may not be aligned with the internal processing of these samples. A simply way to ensure alignment of the multiple sample rates may be the use of a counter, but the value of this counter when a new incoming sample from wireless means arrives is unknown and thus there will normally be a discrepancy between earbuds in the left and right ear, because these are not turned on at the exact same moment and will have variations in manufacturing. A first technique for LR sync alignment that can be used in embodiments can slowly shift the phase of a PLL based on an external clock signal. During this first technique, when a wireless audio connection has been made to a sink device (e.g., an external BT I2S Word Sync, WS clock signal is detected by a wireless earbud and an internal PLL of the wireless earbud has achieved lock with this I2S WS clock signal), a phase adjustment value can be determined that is related to a phase difference between an internal timing signal generated by the earbud and an external clock signal. This phase adjustment value is used by the wireless earbud to determine how much to shift the phase of a PLL that is locked to the external clock signal as compared to the timing of the internal audio circuits.

[0021] In some examples, the internal clock frequency of the PLL is increased or decreased by a minute / small amount by changing a PLL feedback divider value slightly (e.g., 0.1% from a nominal value) to cause a frequency shift at the output of the PLL. This small frequency shift will result in the audio circuits being driven by a frequency reference that is slightly off from the external clock signal and therefore there will be a slow change in phase between these two sources. In some examples, the “minute / small” amount is a value that does not cause the PLL to lose phase lock with the external clock signal. Since, in some configurations, the internal audio circuits, microphone outputs, decimators, audio processing, interpolators, and output pulse duration modulation (PDM) amplifier rely on the same audio clock and the frequency change in the PLL is small during the adjustment, the phase shift is inaudible to a user wearing the wireless earbud. Using the techniques described herein, full ANC can continue to operate during the LR synchronization alignment operations. Stated another way, the volume of the earbuds can be maintained without having to mute the earbuds or turn the volume down (to avoid playing back a glitch). Thus, the user experience will be improved by this method.

[0022] Another technique that can be used to perform LR synchronization of the earbuds includes alignment of the interpolator chains associated with the different sources. The interpolator chains are configured to up sample a signal and increase its sample rate. In some examples, when there is a separate path for ANC and audio playback, it is possible to maintain ANC while the audio path is being reconfigured with respect to internal delays.

[0023] Yet another technique for LR synchronization is related to transmission from a pair of earbuds to a stereo receiver. This technique also addresses the problem of the alignment of the outgoing streams. In some examples, the technique changes the delays inside the decimator chains, but any such change will typically result in the formation of an audible glitch. Therefore, in some configurations, an extra decimation chain is used to perform this operation and slowly mix between two sets of decimators to slowly change the delay. In some configurations, this mixing can be performed after a second decimator is settled to a new fractional delay value.

[0024] In some examples, the earbuds are configured to perform bidirectional audio communication (e.g., during a phone call, video conference, audio conference, gaming session, . . .) where audio is received wirelessly by the earbuds from an audio source (e.g., smartphone, laptop, computer, . . .) for output via one or both speakers of the earbuds (referred to as downstream audio). Audio can also be captured using one or more microphones of the earbuds and wirelessly transmitted by the earbuds to the audio source (referred to as upstream audio). According to some examples, the earbuds use Bluetooth-based communications using Bluetooth LE Audio. While this document is focused on examples involving earbuds, embodiments are also applicable to situations where two or more wireless speakers are present (e.g., a wireless multi-speaker Dolby 7.1 surround system).

[0025] Further details regarding such embodiments and others is provided in relation to the figures. FIG. 1 illustrates a system 100 in which audio is transmitted between earbuds 120 and audio source 130. Downstream audio is transmitted from audio source 130 to earbuds 120 and upstream audio (e.g., voice captured via microphone) is transmitted from one of earbuds 120 to audio source 130. System 100 includes: earbud 120-1 (e.g., a right or left earbud of a pair of true wireless earbuds); earbud 120-2 (e.g., a true wireless earbud for the opposite ear from earbud 120- 1); and audio source 130. Communication between earbuds 120 and audio source 130 occurs via a low-power device-to-device communication protocol, such as Bluetooth Low Energy (LE) Audio, or some other wireless protocol.

[0026] Earbuds 120 can be TWS earbuds, which refer to a pair of earbuds that do not have any physical connection, such as a wire or band, connecting the two earbuds or with an audio source.True wireless earbuds can allow a user to use both earbuds 120 or use a single earbud (either earbud 120-1 or earbud 120-2) at any given time.

[0027] Some components of earbuds 120 are illustrated. Specifically, earbuds 120 include: wireless interfaces 122; microphones 124; processing systems 126; speakers 128, PLLs 130, counters 132, and clocks 134. All components of earbuds 120 can be housed by housings of the respective earbud, which can be made from a rigid or semi-rigid material. Earbuds 120 can be shaped to be at least partially inserted into a user’s ear so that it will stay in place during normal body movements.

[0028] Wireless interface 122 can be a short-range wireless interface that allows for a device-to- device exchange of data. For example, short-range refers to up to 1, 10, 15, or 20 meters. Wireless interface 122 can be a Bluetooth interface that allows for data to be exchanged according to a communication protocol from the Bluetooth family of communication protocols, such as Bluetooth basic rate or extended data rate (BR / EDR, which can also be referred to as “Bluetooth classic”), and Bluetooth Low Energy (BLE) protocol. Wireless interface 122 can communicate using the 2.4 GHz band, which for Bluetooth spans from 2.4 GHz to 2.4835 GHz. This frequency band can be divided up into a number of channels, such as 80 channels for Bluetooth BDR / EDR, each 1 MHz wide, or 40 channels for Bluetooth LE, which are each 2 MHz wide. Bluetooth communications can involve frequent channel changes within the 2.4 GHz band, such as up to 1600 channel changes per second.

[0029] Wireless interfaces 122 can be understood as Bluetooth wireless interfaces or other wireless protocol interfaces in that each of wireless interfaces 122 can communicate with other Bluetooth interfaces (e.g., wireless interface 142) that conform to the Bluetooth standard. For example, in FIG. 1, audio source 130 has a Bluetooth interface, referred to as wireless interface 132. Wireless interfaces 122 can exchange data using Bluetooth or other wireless protocols with wireless interface 132. For example, wireless interface 142 may be used to transmit downstream audio packets to wireless interfaces 122 while upstream audio packets constructed using audio captured using one or more of microphones 124 are transmitted by wireless interfaces 122 to wireless interface 142.

[0030] In earbud 120-1, processing system 126-1 can be in communication with wireless interface 122-1; speaker 128-1; microphone 124-1; PLL 130-1; counter 132-1; and clock 134-1. In earbud 120-2, processing system 126-2 can be in communication with wireless interface 122-2; speaker 128-2; microphone 124-2; PLL 130-2; counter 132-2; and clock 134-2. Processing systems 126 may include one or more special-purpose or general-purpose processors. Suchspecial-purpose processors may include processors that are specifically designed to perform the functions of the components detailed herein. Such special-purpose processors may be ASICs or FPGAs which are general-purpose components that are physically and electrically configured to perform the functions detailed herein. Such general-purpose processors may execute specialpurpose software that is stored using one or more non-transitory processor-readable mediums, such as flash memory or other forms of memory.

[0031] Speakers 128 are used for outputting audio to a user. Processing system 126 can control the volume of audio received via wireless interfaces 122, the gain of microphones 124, and perform other actions. Microphones 124 are present in each of earbuds 120. Microphones 124 can be used to capture audio in the vicinity of earbuds 120, such as speech of a user wearing at least one of earbuds 120 and transmit the captured audio as upstream audio packets via a wireless interface such as Bluetooth (e.g., supporting the Bluetooth LE Audio protocol) to audio source 130. Microphones 124 can also be used to capture background noise to perform automatic noise cancellation, ANC.

[0032] In the embodiments detailed herein, each of the earbuds 120 is configured to perform phase shift operations to adjust for a phase difference detected between an internal timing signal generated by the earbud (e.g., indirectly from a PLL 130) and an external clock signal such as a clock signal associated with a BT PS interface. Such phase shift operations can be performed by each sink device that is transparent to the source, and the source needs to take no action. The arrangements detailed herein do not require a direct link between the earbuds nor direct coordination. The arrangement detailed herein further can include techniques / algorithms to cause a sink device to change from using a first PLL that is synced with an internal clock signal, to a second PLL that is synced with an external clock signal.

[0033] The phase-locked loop (PLL) circuits 130 are configured to synchronize the phase of its internal audio circuits based on the on-board clock with a reference signal. In some examples, the reference signal may be an internal clock signal (e.g., a crystal oscillator timing signal, or a realtime clock (RTC) signal), or an external clock signal (e.g., a 1.536 MHz BT signal). . As used herein, an internal clock signal is a clock signal that is generated by one or more components within an earbud 120. An “external clock signal” is a clock signal that is generated by one or more components external from an earbud 120. Phase-lock looping is a synchronization method that allows multiple circuits / components to lock to a shared reference signal. As a result, these circuits / components can synchronize the phase of their sample clocks. Because the phase referenceof each sample clock is synchronized, each board can take a measurement at precisely the same instant.

[0034] As discussed above, there are different techniques / algorithms which can be used in isolation, or in some combination, to perform the LR synchronization alignment. A first technique for LR sync alignment that can be used in embodiments can slowly shift the phase of a PLL 130 based on a phase adjustment value determined by the detected phase difference between the input clock reference and the current phase of the audio processing circuitry. During this first technique, when a BT audio connection has been made to an earbud 130, such as earbud 1301-1, a phase adjustment value that can be used to synchronize a first phase of the internal timing signal generated by dividing the output from a PLL of the earbud and a second phase associated with the external clock signal is determined. This phase adjustment value is used by the wireless earbud to determine how much to shift the phase of the audio circuits that are normally locked to the external clock signal. The external clock signal may be at different frequencies, such as but not limited to 16 kHz, 32 kHz, 48 kHz, 96 kHz, 192 kHz, 384 kHz, and the like.

[0035] In some examples, the internal clock output frequency of the PLL 130-1 coupled to the external clock signal is increased or decreased by a minute amount by changing a PLL feedback divider value slightly (e.g., by 0.1% from a nominal value) to cause the phase shift. For example, changing the value of the PLL feedback divider from 7,680 (e.g., the nominal value) to 7,681 or 7,679, 7680 to 7,682 or 7,678, and the like. Minute changes in the feedback value is directed to avoiding affecting the quality of the current audio operation. Once the phase difference between the external clock signal and the internal timing signal aligns within a predetermined phase difference (e.g., + / - Ips, + / - 2ps, + / - 2.5 s, . . .), the PLL feedback divider value is returned to the original value (e.g., 7,680) such that the internal audio circuits and external clock signal are phase locked. Since, in some configurations, the internal audio circuits, microphone outputs, decimators, audio processing, interpolators, and output pulse density modulation (PDM) amplifier rely on the same audio clock and the frequency change in the PLL is small during the adjustment, the phase shift is inaudible to a user wearing the wireless earbud.

[0036] Using the techniques described herein, full ANC can continue to operate during the LR synchronization alignment operations. Stated another way, the volume of the earbuds can be maintained without having to mute the earbuds or turn the volume down (to avoid playing back a glitch which may happen with a quick phase adjustment). Thus, the user experience will be improved.

[0037] Another technique that can be used to perform LR synchronization of the earbuds includes alignment of the interpolator chains associated with the different source devices. The interpolator chains are configured to up sample a signal and increase its sample rate. In some configurations, this may be done by including selectable delay cells similar to shown in Fig. 5. The advantage of this is an instant delay update but the disadvantage of an audio glitch, regardless of whether IIR or FIR filters are used. Thus, in some examples, to perform this operation, an extra interpolator chain is used and change the output slowly from one interpolator chain to another after adjustment to avoid hearing any audio disturbance or have no audio playback in this direction. In some configurations, this adjustment aligns the delays in the direction from the wireless interface to the earbud, without aligning the delays in the direction from the earbud to the wireless interface.

[0038] Another technique that can be used to perform LR synchronization of the earbuds includes alignment of the decimator chains associated with the different sink devices. The decimator chains are configured to down sample a signal and reduce its sample rate. This may be done by including selectable delay cells similar to shown in Fig. 5 but with the signals going in the opposite direction. The advantage of this is an instant delay update but the disadvantage of a glitch, regardless of whether HR or FIR filters are used. Therefore, in some examples, to perform this operation, one or more extra decimator chains are used and the output is changed slowly from one decimator chain to another after adjustment to avoid hearing any audio disturbance. This adjustment aligns the delays in the direction from the earbud to the wireless interface, without aligning the delays in the direction from the wireless interface to the earbud.

[0039] According to another configuration, cycle-stealing from the decimator / interpolator chains can be performed to achieve the LR synchronization. Instead of making one single large change in phase, cycle-stealing operations can be performed (e.g., slowly over 10-20 ms) to gradually align the internal and external timing. As an example, two subsequent values from a digital microphone may be added together to form a single value and the decimator chain may receive this single value and skip one clock cycle. This may be repeated multiple times with some delay between these events to minimize the disturbance. Similarly, the interpolators may skip one clock cycle and hold the input value for one extra clock cycle.

[0040] As another alternative, the channel 4 decimator chain (see Fig. 6) can act as a replacement for channel 0-3 and it is possible to gradually do the change in phase by mixing between an un-delayed and delayed version of the decimator signals.

[0041] In some configurations, the LR sync alignment can be performed by aligning the internal phase of the decimator / ANC engine / interpolators when a BT connection has been made. Usingthis technique, the LR channels can be aligned in phase with a high precision (better than specified by the BT specification), but a small audible glitch may be detected that happens at the alignment event due to the transient response of the digital filters, because the phase is changed momentarily. Thus, while this technique is simple and quick, muting of audio temporarily may be needed to avoid playing back any glitch.

[0042] In some examples, a counter circuit 132 within each of the wireless earbuds is used to determine the phase difference used to perform PLL phase shift operations. According to some configurations, the lowest six bits of a binary counter 132 running at 3.072 MHz are used for the timing associated with the alignment of decimators, interpolators, digital memory access (DMA), Low Latency Engine (LLE, a custom DSP), and the like. By performing a phase alignment between the external clock signal and the internal timing signal each of the earbuds will be synchronized with each other, resulting in LR alignment.

[0043] PS is a serial bus interface specially designed for communicating digital audio data between integrated circuits (ICs). The PS protocol sends pulse-code modulation (PCM) audio data from a controller to a target. It has at least three lines: the bit clock, the word select (WS), and a data line. Word select is used to specify which of the stereo channel, left or right, the data should be sent to. Since the WS line indicated the arrival of a new sample, this may be used to align the internal audio circuits with the wireless interface. Normally, the first of two samples are transmitted after a negative edge on the WS line, therefore, this edge will normally be used for realignment, though both edges could be used with the end result of a different but still constant delay.

[0044] Audio source 140 includes wireless interface 142 and processing system 144. Examples of audio source 140 can include: a smartphone; a desktop, laptop, or tablet computer; a gaming device; a smart television; a digital music player device; a smartwatch; smart glasses; an augmented reality or a virtual reality headset; or any other device from which a user may desire to stream audio to earbuds 120 and, possibly, transmit upstream audio from earbuds 120 to audio source 140. Audio source 140 includes wireless interface 142, which can communicate with earbuds 120 using device-to-device communication protocols, such as a Bluetooth communication protocol (e.g., Bluetooth classic, Bluetooth LE, . . .), WiFi or the like. Therefore, audio source 140 can transmit a downstream audio stream to one or more of earbuds 120 via wireless interface 142 and can receive an upstream audio stream from one or more of earbuds 120.

[0045] Processing system 144 may include one or more special-purpose or general-purpose processors. Such special-purpose processors may include processors that are specifically designedto perform the functions of the components detailed herein, such as detailed in relation to processing systems 126.

[0046] FIG. 2 illustrates a system 200 in which phase adjustments are made to a PLL used for audio playback. System 200 includes multiplexor (MUX) 202A, MUX 202B, audio PLL 204A, audio PLL 204B, and phase shift manager 206. Both PLL’s contain an internal programmable clock divider from the internal VCO to the phase comparator (not shown). There is also an output audio clock divider 208 and an audio counter 210. In some configurations, the components illustrated in FIG. 2 are contained within an earbud 120, such as earbud 120-1 and earbud 120-2.

[0047] According to some examples, when an earbud 120 is turned on, MUX 202A selects the RC-OSC clock signal (RC-oscillator) as an input to audio PLL 204A. After the audio PLL 204A has stabilized with the RS-OSC signal as an input, the earbud 120 is booted. In some examples, after booting the earbud, the clock input to the PLL 204A is changed by the MUX 202A to an internal crystal reference signal, such as RTC signal (real time clock, often 32.768 kHz), that is more accurate compared to the RS-OSC signal, that may be trimmed but still has much larger tolerances. After the audio PLL 204A stabilizes using the RTC signal as an input, the earbud 120 may perform operations. In some examples, the operations may include a variety of different audio operations, such as ANC operations. For example, the earbud may perform ANC operations to cancel noise in the environment of the user before the earbud is connected to an external wireless source, such as a BT-connection. A BT clock reference signal may be detected by the earbud 120.

[0048] Upon the earbud 120 detecting a BT signal, audio PLL 204B generates a timing signal that is locked to the BT clock signal. As discussed above, the external clock signal may be a BT external I2S clock signal that can be received at some point after booting the earbud. As discussed above, a second PLL can be started and stabilized before transitioning from using a first PLL that uses an internal clock signal to a second PLL that uses an external clock signal. A special circuit may be employed to ensure a glitch-free transition when changing the clock source from PLL1 to PLL2 using MUX2, 202B (not shown).

[0049] In some configuration, the phase shift manager 206 is configured to execute phase shift operations for performing the LR phase alignment for earbuds 120. By performing a phase alignment, each of the earbuds will be synchronized with the wireless interface and thereby also to each other, resulting in LR alignment. As discussed above, the phase shift manager 206 may cause the internal clock frequency of the audio PLL 204B to be increased or decreased by a small amount by changing a PLL feedback divider value slightly (e.g., by 0.1% from a nominal value) to cause the phase shift. In some configurations, the phase difference will be determined by the phaseshift manager 206 to be aligned after the expiration of a predetermined time period. In other configurations, the phase shift manager 206 may perform one or more phase difference measurements / determinations to determine whether alignment has been achieved. Once PLL204B has achieved synchronization with the external clock signal (the wireless interface) the MUX202B will select this clock source and the realignment may begin.. As discussed above, the operations can include ANC operations, audio playback operations, as well as other types of operations that may be performed by an earbud.

[0050] Various methods may be performed using the systems, states, and arrangements detailed in relation to FIGS. 1-2, and 5-7. FIG. 3 illustrates an embodiment of a method 300 for LR synchronization of using a phase shift technique. Method 300 can be used by at least one or more two earbuds 120, to perform delay synchronization. The earbuds 120 can perform the phase shift technique at the same time, or different times. Thus, the alignment is not dependent on both earbuds being connected to the wireless interface at the same time.

[0051] At 305, an earbud 120 is turned on and digital logic is used to boot the earbud. As discussed above, an internal clock signal that is different from the external clock signal can be used before a BT clock reference is detected. In some examples, a first PLL 130 is started with an internal RC-OSC signal as a clock input. This has the advantage it is stable very quickly (e.g., 1 ps) but normally not stable enough for audio operations. It may be used to prepare the earbud for audio operations later by performing boot operations. In some examples, after booting the earbud 120, the clock input to the PLL 130 is changed to an internal crystal reference signal that is more accurate compared to the RS-OSC signal but takes much longer before it is stable (e.g., 100 ms). This clock reference is precise enough that audio operations such as ANC may be commenced.

[0052] At 310, the first PLL 130 can be used to perform first operations for the earbud 120. As discussed above, the first operations may include a variety of different operations, such as ANC operations. For example, the earbud 120 may perform ANC operations to cancel noise in the environment of the user before a BT clock reference signal is detected. There may also be use cases where there is no intention to connect to a wireless connection (e.g., for noise reduction in an airplane).

[0053] At block 315, a determination is made as to whether an external clock signal is detected. As discussed above, the external clock signal may be a BT external I2S clock signal that can be received at some point after booting the earbud 120. The external clock signal may be at different frequencies, such as but not limited to 16 kHz, 32 kHz, 48 kHz, 96 kHz, 192 kHz, 384 kHz, and the like. In some examples, if the external clock signal is not detected, the process may return to310 to continue to perform operations. When the external clock signal is detected, the process moves to 320.

[0054] At 320, the external clock signal is used as an input to a second PLL 130. As discussed above, a second PLL 130 can be started and stabilized before transitioning from using a first PLL 130 that is locked to an internal clock signal to a second PLL 130 that is locked to an external clock signal.

[0055] At 325, a determination is made as to whether the second PLL 130 has stabilized. When the second PLL 130 has not stabilized, the process may return to 320 to continue to perform operations. When the second PLL 130 has stabilized, the process moves to 330 where PLL2 will replace PLL1 as the clock source.

[0056] At 335, the phase adjustment value is determined, and phase shift operations are performed. As discussed above, a phase adjustment value indicates a phase difference between the state of internal audio processing circuits (e.g., determined by an audio counter and a second timing signal provided by the wireless interface). In some examples the phase difference can be determined based on a value of a counter 132 (e.g., running of a 3.072 MHz audio clock) that is included within the earbud 120. According to some examples, the counter 132 is used for the timing associated with the alignment of decimators, interpolators, digital memory access (DMA), Low Latency Engine (LLE, a custom DSP), and the like. By performing a phase alignment between the counter 132 and the external clock signal each of the earbuds will be synchronized with the wireless interface and therefore indirectly also with each other, resulting in LR alignment.

[0057] As discussed above, the internal clock frequency of the second PLL 130 is increased or decreased by a minute amount by changing a PLL feedback divider value slightly (e.g., + / - 2 least significant bits (LSBs) from a nominal value) to cause the phase shift. For example, changing the PLL feedback divider from 7,680 (e.g., the nominal value) to 7,681 or 7,679, 7680 to 7,682 or 7,678, and the like. Once the phase difference between the external clock signal and the internal timing signal aligns within a predetermined phase difference (e.g., + / - Ips, + / - 2ps, + / - 2.5ps, . . .), the PLL feedback divider value is returned to the original value such that the internal and external audio circuits are phase locked. In some configurations, the phase difference will be aligned after a predetermined period of time. In other configurations, one or more phase difference measurements / determinations can be performed.

[0058] At 340, the second PLL 130 is used when performing second operations for the earbud 120. As discussed above, the second operations can include ANC operations, audio playback operations, as well as other types of operations that may be performed by an earbud.

[0059] FIG. 4 illustrates an embodiment of a method 400 for detecting a phase difference and performing phase shift operations. Method 400 can be used by at least one or more earbuds, to perform LR synchronization. The earbuds can perform the phase shift technique at the same time, or different times.

[0060] At 405, an external clock signal is received by an earbud. As discussed above, the wireless device 122 and processing system 126 may use a PS (Inter-Integrated Circuit (IC) Sound) protocol to communicate Pulse-code modulation (PCM) audio data between ICs. The PS protocol defines a serial clock signal, a word select (WS) signal, and serial data signals. The clock frequency is based on the sample rate, the number of channels, and the number of bits per channel. According to some examples, the frequency of the word select clock is set to 32 kHz. Other frequencies can also be used. The word select signal indicates what channel (e.g., left channel or right channel) is currently being sent. For example, the left channel data is received after the falling edge and the right channel is received after a rising edge of the WS signal.

[0061] At 410, an LR sync event is detected. As discussed above, the earbud 120 may analyze the WS signal to identify the WS falling edge and / or the WS rising edge and use this timing event for LR alignment.

[0062] At 415, the counter 132 is read. As discussed above, in some examples, a counter circuit 132 within each of the wireless earbuds 120 is used to determine the difference between the input signal of the PLL (the BT clock reference) of the wireless earbud and a current value of a counter circuit 132 within the earbud. For example, in some configurations, if the counter is a value of 0, the phase difference may be determined to be 0. According to some configurations, the lowest six bits of the counter 132 are also used for the timing associated with the alignment of decimators, interpolators, digital memory access (DMA), Low Latency Engine (LLE), and the like and these will represent the phase difference.

[0063] At 420, the setting of the PLL divider is changed. As discussed above, the setting of the PLL divider may be increased or decreased by a small amount. Changing the setting of the PLL divider slightly increases or decreases the output frequency of the second PLL. In some examples, the value of the setting for the PLL divider is small enough such that the PLL stays in lock and the audio processing such as ANC is not affected so much as to be audible.

[0064] At 425, the phase shift is performed. As discussed above, different techniques can be used to perform the phase shift operations. In some examples, the earbud 120 may analyze the WS signal to identify the WS falling edge and / or the WS rising edge and read the counter at that timeto determine the phase difference. In other examples, a predetermined time may be used in which the PLL has the feedback divider set to a slightly offset value.

[0065] At block 430, a determination is made as to whether the phase is adjusted. When the phase is not adjusted, the process may return to 425. When the phase adjustment has been completed, the process moves to 435.

[0066] At 435, once the phase difference between the external clock signal and the internal timing signal aligns within a predetermined phase difference (e.g., + / - Ips, + / - 2ps, + / - 2.5ps, . . .), the PLL feedback divider value is returned to the original value such that the internal and external audio circuits are phase locked and will remain phase locked.

[0067] FIG. 5 illustrates an example system 500 showing synchronization of an internal timing signal with an I2S signal.

[0068] The Bluetooth standard specifies that the difference in delay between the left and right true wireless earbuds 120 be below 25us. In this example, I2S signals are received at each earbud 120. To achieve a good listening experience for a user, the earbuds 120 perform phase shifting operations to align / synchronize the signals between the earbuds 120, so the total delay from receiving a I2S sample until it is being played out is consistent.

[0069] Generally, there is a time difference between the arrival of a new I2S sample and the actual phase of the internal audio circuits (e.g., controlled by the value of a counter). As discussed above, this value is used when performing the slow PLL adjustment (e.g., ensures the audio counter has the same value at the arrival of a new I2S sample). In some configurations, another technique can be used that delays the time from the input of I2S samples in the interpolator chain and to the final output. This delay can be programmed and thus directly compensate for any changes in the difference between the audio counter and the arrival of a new I2S sample. This technique, in some examples, uses an extra interpolator chain if ANC operation is running at the same time since the adjustment will be audible if the interpolator chain that changes the delay is not muted for a while after the change (to ensure all transient conditions are settled), and this alignment will only realign samples from the wireless interface to the output speakers, not in the path from the microphones to the wireless interface.

[0070] For purposes of illustration, an example will now be described with reference to FIG. 5. Assume a full path delay of 63 samples and an audio counter value of 31 at an I2S sample trigger event. In this case, we could add an extra delay of 32 samples (at 3.072 MHz) to have a full path delay (ignoring the filter delay itself, that is stable) of 63 samples. If the audio counter value was 8,an extra delay of 55 samples (63-8= 55) at 3.072 MHz would be added to have a full path delay of 63 samples at 3.072 MHz. In some examples, the following formula can be used to directly compensate for the I2S misalignment without changing clocks: Delay Value = Full Path Delay (e.g., 63) - Audio Count value at occurrence of PS event. In other examples, different formulas can be used. Generally, as long as each path uses the same formula, LR synchronization can be performed. According to some examples, the delay value can be stored within a 6-bit register. As can be seen by referring to FIG. 5, time delays can be added at one or more time delays 502A- 502F. As illustrated, delays can be performed at different sample rates. There may be a difficulty when the observed delay is very close to zero or the ideal position. In this case, there could be one sample more or less in the receive buffer that captures the incoming samples. In some examples, to address this case, a short delay / wait is introduced (e.g., 1 is) and then redo the alignment, because the number of samples in the receive buffer will then be stable (since it is past the event where a sample is received) and then do the realignment based on this position (i.e. with an offset of e.g., two samples).

[0071] FIG. 6 illustrates an example system 600 in which LR synchronization is performed. The system 600 shows in more detail the components and processing that may be included within an earbud 120. This system 600 may provide ANC functionality with a low latency using multiple microphones as input and hybrid processing paths. At 602, acoustic signals are captured using one or more microphones, DMICO-DMIC-4. At 604, an input switch matrix enables dynamic routing of the acoustic signals and feedback signals AUX0 and AUX1. At 606, a fast-filtering process takes place based directly on the incoming PDM samples. This can serve as the fast path for ANC filtering. At 608 and 610, feedback signals are provided that are filtered in the PDM domain (i.e., based on samples with only two values, typically {-1, +1 }). At 612, an extra PDM filter allows dynamic changes of the filter coefficients without encountering glitches. This is done by letting this filter replace the output for any of the other PDM filters while these coefficients of one of these may be changed by programming. At 614, limiting functionality is included to avoid overflow. At 616, a mapping from the input values of {0, 1 } from the digital microphones to {-1, +1 } is performed. In 618, first stage decimators are configured to reduce the sample rate by a factor of eight. In 620, high pass filters can be used to remove any DC-component from the incoming audio signals and providing a gain adjustment. In 622, a second stage decimator reduces the sample rate to { 16, 48, 96, 192, 384 kHz}. In 624, a MUX allows monitoring of the final output final for test purposes. In 632, a timestamp module allows direct capture of the audio counter 132 by DMA transfers. In 634, an output MUX selects the samples to be transferred by DMA. In 636, a MUX selects what audio channel that will be used to provide a sidetone signal. In638, the actual sidetone signal level is decided and this signal is merged with the audio playback (e.g., from BT). In the large block 640, the audio processing at lower frequencies (16-384 kHz) occurs. This includes ANC processing, LLE (low latency engine) processing, inclusion of timestamp and LR synchronization, high quality audio and Bluetooth interface, UART and I2S interfaces. XPC path is for the inclusion of an external desired audio signal (transparency enablement). The PLL’s, main memory, registers and various other hardware blocks such as memory switch matrix (some not shown) are also situated in block 640. In 642, the sidetone signal, playback signal, and XPC signals are combined and optionally delayed by a fractional amount such as shown in Fig. 5. In 644, 646 and 648, PCM signals are converted to the PDM domain using digital delta sigma modulators. Block 648 can be used as an interface to an external PDM amplifier while 644 and 646 can be used to provide an interface to the fast PDM filters 608 and 610. The conversion of the PCM signals to the PDM domain to be filtered by 608 and 610 results in much lower power consumption that may be obtained by the PDM filters (the just two input values effectively result in a replacement of multiplications with addition or subtraction of a coefficient thereby lowering power consumption). In 630, a small delay allows gives extra margin for the processing in 640. In 650, there is included a volume control so the feedback signal will have the same variation as controlled by the main volume control, 652. In 654, a volume control for the combined fast PDM filter output and the value of the volume is passed on to the signed multiplier 656 that performs that actual volume change while limiter 658 ensures the output signal stays within a finite predefined range. In decimator 660, the sample rate is changed from 3.072 MHz to {48, 96, 192, 384} and provides a reference feedback signal of what is being played out (playback, XPC and sidetone). In 662, the playback reference is high pass filtered and in 664 there is a playback volume control that include the capability of turning down the volume in case the BT signal disappears without encountering any glitches in the process. In 666, there is provided an echo reference signal while multiplier 668 ensures an output volume aligned with the main volume control. In 670, the is a MUX that selects for an output feedback filtering from either before or after the final output gain control. In 672, an interpolator chain with adjustable fractional delays implemented similar to Fig. 5 is illustrated. This provides the slow path ANC signal as calculated by the LLE (low latency engine) based on audio signals (48-384 kHz) while the fast path is being processed by the PDM filters (606, 608 and 610). The fractional delays allow for alignment between the ANC signals and the PDM processed signals and independently of any delays in the playback chain (interpolator 642). In 674, the combined output signal is multiplied by the value provided by the main volume control, 652. In 676 there is included a post filter to reduce out-of- band noise from the PDM filters while MUX 678 allows to skip this stage. In 680, a programmable hard limiter = can set the maximum output level while 682 illustrates an independent output gaincontrol that can be included in case of system failure. In 684 the output sample rate is increased from 3.072 MHz to 6.144 MHz by the output interpolator and in 686 it is further increased to 12.288 MHz by this final interpolator. In 688 the actual output sample rate is determined and this is being feed to the output delta sigma modulator, 648.

[0072] In some configurations, two interpolators can be used in the interpolator chain. In these configurations, the left and right interpolators can include a fractional divider that can be used to realign the I2S signal without needing to adjust the clock. According to some examples, an audio counter is read at a word select WS event and is used to adjust the fractional divider accordingly. In some configurations, this can include the following steps of operation, see Fig. 7.

[0073] FIG. 7 illustrates an embodiment of a method 700 for LR synchronization of using a phase shift technique. Method 700 can be used by at least one or more two earbuds 120, to perform delay synchronization. The earbuds 120 can perform the phase shift technique at the same time, or different times. Thus, the alignment is not dependent on both earbuds being connected to a source by wireless means at the same time.

[0074] At 705, an earbud 120 is turned on and digital logic is used to boot the earbud. As discussed above, an internal clock signal that is different from the external BT clock signal can be used before a BT clock reference is detected. In some examples, a first PLL 130 is started with an internal RC-OSC signal as a clock input. This has the advantage it is stable very quickly (e.g., 1 ps) but normally not stable enough for audio operations. It may be used to prepare the earbud for audio operations later by performing boot operations. In some examples, after booting the earbud 120, the clock input to the PLL 130 is changed to an internal crystal reference signal that is more accurate compared to the RS-OSC signal but takes much longer before it is stable (e.g., 100 ms). This clock reference is precise enough that audio operations such as ANC may be commenced.

[0075] At 710, the first PLL 130 can be used to perform first operations for the earbud 120. As discussed above, the first operations may include a variety of different operations, such as ANC operations. For example, the earbud 120 may perform ANC operations to cancel noise in the environment of the user before a BT clock reference signal is detected. There may also be use cases where there is no intention to connect to a wireless connection (e.g., for noise reduction in an airplane).

[0076] At block 715, a determination is made as to whether an external clock signal is detected. As discussed above, the external clock signal may be a BT external I2S clock signal that can be received at some point after booting the earbud 120. The external clock signal may be at different frequencies, such as but not limited to 16 kHz, 32 kHz, 48 kHz, 96 kHz, 192 kHz, 384 kHz, andthe like. In some examples, the external clock signal is not detected, the process may return to 310 to continue to perform operations. When the external clock signal is detected, the process moves to 720.

[0077] At 720, the external clock signal is used as an input to a second PLL 130. As discussed above, a second PLL 130 can be started and stabilized before transitioning from using a first PLL 130 that is locked to an internal clock signal to a second PLL 130 that is locked to an external clock signal.

[0078] At 725, a determination is made as to whether the second PLL 130 has stabilized. When the second PLL 130 has not stabilized, the process may return to 720 to continue to perform operations. When the second PLL 130 has stabilized, the process moves to 730.

[0079] At 730, the second PLL 130 is used when performing second operations for the earbud 120. As discussed above, the second operations can include ANC operations, audio playback operations, ring tone operations, as well as other types of operations that may be performed by an earbud.

[0080] At 735, the phase adjustment value is determined. As discussed above, a phase adjustment value indicates a phase difference between the state of internal audio processing circuits (e.g., determined by an audio counter and a second timing signal provided by the wireless interface). In some examples the phase difference can be determined based on a value of a counter 132 (e.g., running of a 3.072 MHz audio clock) that is included within the earbud 120. According to some examples, the counter 132 is used for the timing associated with the alignment of decimators, interpolators, digital memory access (DMA), Low Latency Engine (LLE), and the like. By performing a phase alignment between the counter 132 and the external clock signal each of the earbuds will be synchronized with the wireless interface and therefore indirectly also with each other, resulting in LR alignment.

[0081] At 740, a determination is made as to whether the phase adjustment value is close to zero (e.g., within 2 of zero, so if the counter 132 is 6 bits, values {62, 63, 0, 1, 2} would all be considered close to zero). When the phase adjustment value is close to zero, the process 700 moves to 745. When the phase adjustment value is not close to zero, the process 700 moves to 750. This step can be used since the receive buffer size may be uncertain just when we receive a new sample.

[0082] At 745, the phase adjustment value can be determined again (e.g., after a few clock cycles).

[0083] At 750, phase shift operations can be performed. As discussed above, phase shift operations can include performing fractional delays and buffer updates as discussed above. In some configurations, the phase difference is aligned after a predetermined period of time.

[0084] It should be noted that the methods, systems, and devices discussed above are intended merely to be examples. It must be stressed that various embodiments may omit, substitute, or add various procedures or components as appropriate. For instance, it should be appreciated that, in alternative embodiments, the methods may be performed in an order different from that described, and that various steps may be added, omitted, or combined. Also, features described with respect to certain embodiments may be combined in various other embodiments. Different aspects and elements of the embodiments may be combined in a similar manner. Also, it should be emphasized that technology evolves and, thus, many of the elements are examples and should not be interpreted to limit the scope of the invention.

[0085] Specific details are given in the description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, well-known, processes, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring the embodiments. This description provides example embodiments only, and is not intended to limit the scope, applicability, or configuration of the invention. Rather, the preceding description of the embodiments will provide those skilled in the art with an enabling description for implementing embodiments of the invention. Various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the invention.

[0086] Also, it is noted that the embodiments may be described as a process which is depicted as a flow diagram or block diagram. Although each may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process may have additional steps not included in the figure.

[0087] Having described several example configurations, various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the disclosure. For example, the above elements may be components of a larger system, wherein other rules may take precedence over or otherwise modify the application of the invention. Also, a number of steps may be undertaken before, during, or after the above elements are considered.

Claims

WHAT IS CLAIMED IS:

1. A method for synchronizing earbuds that communicate using a wireless protocol, the method comprising: generating, via a first phase-locked loop (PLL) circuit of a first earbud, a first timing signal that is used to perform one or more first operations associated with the first earbud, wherein the first PLL includes a first input coupled to an internal clock signal; generating, via a second PLL circuit of the first earbud, a second timing signal, wherein the second PLL includes a second input coupled to an external clock signal; determining a phase adjustment value to synchronize internal audio circuits, associated with a timing signal, with the phase associated with the second timing signal; causing a phase shift of the second PLL circuit based on the phase adjustment value; and enabling the second PLL circuit to perform one or more second operations for the first earbud.

2. The method of claim 1, wherein the one or more first operations include automatic noise cancelation (ANC) operations associated with the first earbud and wherein the one or more second operations include audio playback operations.

3. The method of claim 1, wherein causing the phase shift comprises changing a setting of a PLL divider circuit for a predetermined time period based on the phase adjustment value.

4. The method of claim 1, wherein determining the phase adjustment value comprises determining a value of a counter circuit of the first earbud at a sync event associated by a wireless circuit and provided by the wireless interface.

5. The method of claim 4, further comprising: changing a setting of a PLL divider circuit associated with the second PLL from a first value to a second value; determining that a predetermined amount of time has elapsed; and changing the setting of the PLL divider circuit associated with the second PLL from the second value to the first value.

6. The method of claim 4, further comprising:changing a setting of a PLL divider circuit associated with the second PLL from a first value to a second value; periodically monitoring a phase difference by checking the value of an internal counter at synchronization events provided by a wireless circuit; and changing the setting of the PLL divider circuit associated with the second PLL from the second value to the first value when a desired timing has been achieved.

7. The method of claim 1, wherein a phase shift is performed using a fractional phase shifter as part of an interpolation chain while this filter chain is muted.

8. The method of claim 1, wherein the first earbud remains unmuted during the phase shift.

9. A wireless earbud system that uses a wireless protocol, comprising: a first earbud comprising: a first wireless interface, a first speaker, a first processing system, a first PLL, a second PLL, an audio circuit, and a first microphone; and a second earbud comprising: a second wireless interface, a second speaker, a second processing system, a third PLL, a fourth PLL, an audio circuit and a second microphone, wherein: the first earbud is not physically connected with the second earbud; the first earbud is configured to: generate, via the first PLL, a first timing signal that is used to perform first operations associated with the first earbud, wherein the first PLL includes a first input coupled to a first internal clock signal; determine a phase adjustment value to synchronize the audio circuit with a second phase associated with a second timing signal; cause a first phase shift of the second PLL based on the phase adjustment value; and select the second PLL to perform one or more second operations; and the second earbud is configured to: generate, via the third PLL, a third timing signal that is used to perform third operations associated with the second earbud, wherein the third PLL includes a third input coupled to a second internal clock signal;determine a second phase adjustment value to synchronize a third phase associated with the third timing signal with a fourth phase associated with a fourth timing signal; cause a second phase shift of the fourth PLL based on the second phase adjustment value; and select the fourth PLL to perform one or more fourth operations.

10. The wireless earbud system of claim 9, wherein one or more of the first earbud or the second earbud is further configured to perform automatic noise cancelation (ANC) operations during one or more of a first time to perform the phase adjustment or a second time to perform the second phase adjustment.

11. The wireless earbud system of claim 9, wherein causing the first phase shift comprises changing a setting of a PLL divider of the first earbud based, at least in part on a state of internal audio processing.

12. The wireless earbud system of claim 9, wherein determining the phase adjustment value comprises determining a value of a counter of the first earbud at a synchronization event provided by the wireless interface such as a falling edge event associated with an external word select I2S audio signal.

13. The wireless earbud system of claim 9, wherein the first internal clock signal is generated by an internal clock of the first earbud.

14. The wireless earbud system of claim 9, wherein the first earbud and the second earbud are true wireless stereo earbuds.

15. The wireless earbud system of claim 9, wherein the first earbud remains unmuted during the phase adjustment and the second earbud remains unmuted during the second phase adjustment.

16. A wireless earbud that uses a wireless protocol, comprising: a wireless interface; a microphone; a speaker; a first PLL; a second PLL; an audio circuit; anda processing system in communication with the wireless interface, the microphone, the speaker, the first PLL, and the second PLL, configured to perform operations comprising: generating, via internal audio processing circuitry a first timing signal based on either an output from the first or second PLL, that is used to perform one or more first operations, wherein the first PLL includes a first input coupled to an internal clock signal; generating, via the second PLL, a second timing signal, wherein the second PLL includes a second input coupled to an external clock signal; determining a phase adjustment value to synchronize a first phase associated with the first timing signal from the audio processing circuitry with a second phase associated with the second timing signal; causing a phase shift of the second PLL based on the phase adjustment value; and enabling the second PLL to perform one or more second operations.

17. The wireless earbud of claim 16, wherein the one or more first operations include automatic noise cancelation (ANC) operations.

18. The wireless earbud of claim 16, wherein causing the phase shift comprises changing a setting of a PLL divider for a predetermined time period based on the phase adjustment value.

19. The wireless earbud of claim 16, wherein determining the phase adjustment value comprises determining an internal state of audio processing circuitry of the wireless earbud at specific time determined by the wireless interface such as a falling edge event associated with an external word select from an I2S audio signal.

20. The wireless earbud of claim 16, wherein the wireless earbud remains unmuted during the phase shift.

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