Smooth-selective wet etching of n-polar GAN and making devices with the same

Abstract

Novel N-polar devices including smooth gate recesses and optionally one or more inclined surfaces. In one embodiment, a method of etching of N-polar III-nitride includes performing a first etch step, e.g., using citric acid; removing the citric acid; performing a second wet etch step using HCl, HNO3 and H2O; and removing the HCl, HNO33, and H2O. Devices (e.g., Schottky barrier HEMTs) manufactured using the method are also disclosed. Such HEMTs have reduced gate leakage and higher gain as compared to Schottky HEMTs manufactured by dry etching.

Description

[0001] SMOOTH-SELECTIVE WET ETCHING OF N-POLAR GAN AND MAKING DEVICES WITH THE SAME

[0002] CROSS REFERNCE TO RELATED APPLICATIONS This application claims the benefit under 35 U.S.C. Section 119(e) of U.S.

[0003] Provisional Application No. 63 / 588,193, filed October 5, 2023, entitled “SMOOTH- SELECTIVE WET ETCHING OF N-POLAR GAN AND MAKING DEVICES WITH THE SAME” by Emre Akso, Henry Thomas Collins, Emmanuel Kayede, Brian Romanczyk, and Umesh K. Mishra,” attorney’s docket no. 30794.0843USP2, which application is incorporated by reference herein.

[0004] This application is related to US. Patent Application Serial No. 17352139 entitled N-POLAR III-N SEMICONDUCTOR DEVICE STRUCTURES (2020-703), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. provisional patent application Serial Nos:

[0005] 63 / 040,705, filed on June 18, 2020, by Brian Romanczyk, Umesh K. Mishra, and Emmanuel Kayede, entitled “N-POLAR IILN SEMICONDUCTOR DEVICE STRUCTURES ENABLED BY WET CHEMISTRY,” Attorney Docket 30794.778USP1 (UC Ref. 2020-703); and

[0006] 63 / 040,674, filed on June 18, 2020, by Umesh K. Mishra, Wenjian Liu, Islam Sayed, and Brian Romanczyk, entitled “DEVICE STRUCTURES UTILIZING BARRIER ENHANCEMENT CONDUCTIVE MATERIALS ON N-POLAR III- NITRIDES,” Attorney Docket 30794.780USP1 (UC Ref. 2020-710), all of which applications are incorporated by reference herein.

[0007] STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT

[0008] This invention was made with Government support under Grant Nos. N00014- 23-1-2078 and N00014-23-1-2152 awarded by the Office of Naval Research (ONR). The Government has certain rights in the invention. BACKGROUND OF THE INVENTION

[0009] 1. Field of the Invention.

[0010] The present disclosure relates to methods of etching III-Nitride and devices manufactured using the same.

[0011] 2. Description of the Related Art.

[0012] Nitrogen Polar Gallium Nitride (N-Polar GaN) High Electron Mobility Transistors (HEMTs) have emerged as outstanding candidates for high-frequency power amplification, with demonstrated more than double output power with high efficiency compared to the traditional Gallium Polar GaN HEMTs. These devices have traditionally employed gate dielectrics, such as SisN4, to suppress the gate leakage current. Although dielectrics are beneficial for minimizing the gate leakage current, they introduce many undesired effects that limit both the device performance and reliability. The dielectrics contain traps that cause (1) threshold-voltage instability, and (2) DC-RF dispersion, which are detrimental to the large signal performance. Furthermore, the increased distance between the electrons in the channel and the gate metal due to the insertion of a dielectric degrades the gate control and results in lower gain and efficiency. Schottky HEMTs, on the other hand, are realized by direct deposition of the gate metal without a gate dielectric, which brings high-gain, high efficiency and more reliable operation with less threshold voltage instability. What is needed are N-polar Schottky barrier HEMTs with low gate leakage. The present disclosure satisfies this need.

[0013] SUMMARY OF THE INVENTION

[0014] The superior performance of N-polar HEMTs can be partially attributed to the inclusion of a GaN cap in the device structure, which reduces the channel access region resistance and improves the DC-RF dispersion significantly, both of which are essential to obtaining high power and efficiency at high frequencies. In the device fabrication process, however, the GaN cap needs to be selectively etched against Aluminum Gallium Nitride (Al GaN) cap both under the gate, and under the ohmic contacts for N+ regrowth. This process traditionally has been done using inductively- coupled-plasma etching. In this invention, the GaN cap recess etching has been demonstrated with a sequential two-step wet etch process, by doing an above room temperature citric acid etch as the first step, followed by HC1:HNO3:H2O etch as the second step. This method of etching N-Polar GaN offers high-selectivity against Al GaN while preserving the smoothness of the starting surface. Both selectivity and the smoothness of the etched surface are very attractive for the electrical performance of the devices to optimize the gate control and gate leakage current. Therefore, a reliable method of smooth-selective wet etching will enable the fabrication of high- performance N-Polar deep recess Schottky and MIS HEMTs in a much cheaper, repeatable, reliable, robust and higher throughput way than the plasma etching.

[0015] The remarkable selectivity and smoothness achievable with the surface treatment has been demonstrated for different GaN cap thicknesses, e.g., 14 nm and 43 nm , and for creation of gate recesses with sub- 100 nm features. The selectivity, surface smoothness and uniformity, and sidewall symmetry are further confirmed with cross-sectional TEM images in < 1120 > and < 1100 > direction, showing that the etched recess profile looks close to the ideal gate profile with no undercutting of the dielectric etch mask. This proposed technique will not only enable cheap, repeatable, reliable, robust and higher throughput way of fabricating HEMTs in the conventional gate recess orientation in < 1120 >, but also enable threshold voltage engineering and unleashing further potential performance improvements in the orthogonal < 1100 > direction gate profile. A Schottky -barrier gate N-Polar deep recess HEMT is fabricated using the proposed etch technique for the gate recess. The device demonstrates low gate leakage, high transconductance, record high-gain and high- efficiency, paving the way for not only cheap and reliable fabrication of N-polar deep recess HEMTs but also a superior performance than the traditional dry-recess-etched HEMTs with gate dielectrics. Illustrative embodiments of the present invention include, but are not limited to, the following.

[0016] 1. An N-polar III-N device, comprising: a III -Nitride backbarrier; a III-Nitride channel comprising a two dimensional electron gas (2DEG) confined in the channel by the backbarrier; an optional cap layer on the channel; at least one ohmic contact to the channel; a etched recess in the cap and / or into the channel; and a gate electrode in the recess forming a Schottky barrier such that when the device is operated: the gate leakage through the Schottky barrier is less than 0.5mA / mm for VDS of 0.5 V or less, and / or under forward bias at +1 VGS, the gate leakage is less than 0.5 mA / mm for the VDS is 0.5 V or less.

[0017] 2. The device of clause 1, wherein the etch results in a smooth surface of an etched surface 1850 of the recess with the root mean square (rms) surface roughness of the etched surface 1850 (e.g., comprising bottom surface of recess, or sidewall / inclined surface of recess, in contact with the channel or cap) is no more than (e.g., the larger of):

[0018] 2 times larger than the starting surface roughness, and / or

[0019] 3 nanometer rms roughness in a 10x10 pm region.

[0020] 3. The device of clause 1, wherein the cap layer comprises at least one of a GaN layer or an AlGaN layer .

[0021] 4. The device of clause 1 or 2, wherein the backbarrier comprises AlxGal-xN and the channel comprises GaN wherein 0.05^x^0.5.

[0022] 5. The device of any of the clauses 1-4, wherein the gate electrode comprises at least one of platinum, ruthenium, titanium nitride, palladium, nickel, or doped silicon.

[0023] 6. An N-polar III-N device comprising: a III -Nitride backbarrier; a III-Nitride channel comprising a 2DEG confined in the channel by the backbarrier; at least one ohmic contact to the channel; an optional cap; a recess having a varying thickness along a direction in the <1-100> direction, in the

[0024] <-l - 120> direction, or between the <1 - 100> direction and the <- 1 - 120> direction of the III-Nitride, such that the recess contains at least one bottom region with a slope inclined at an angle between 0.5 to 5 degrees with respect to an interface between the backbarrier and the channel.

[0025] 7. The device of any of the clauses 1-6, wherein the recess comprises a second bottom region having a second slope inclined at a second angle between 15 to 50 degrees with respect to the interface.

[0026] 8. The device of any of the clauses 1-7 comprising a gate electrode in the recess forming a Schottky barrier with the cap or the channel, wherein current flow between the source contact and the drain contact is along the direction of the varying thickness.

[0027] 9. The device of any of the clauses 1-8, wherein the current flow direction is within 10 degrees of the <l-100> direction.

[0028] 10. The device of any of the clauses 1-9, wherein the varying thickness of the recess is such that the cap and / or the channel has the varying thickness along the direction of current flow to obtain a threshold voltage varying over the gate width and / or gate length, with components in the gate width direction and the gate length direction

[0029] 11. The device of any of the clauses 1-10, wherein the varying thickness of the recess is such that the gate electrode to 2DEG distance varies along the direction within 10 degrees of perpendicular to current flow direction and such that the HEMT operation is linear, which is defined by the ratio of the third order derivative to the first order derivative of the drain current with respect to gate-to- source voltage ( gm3 / gml) of less than 0.05 (VA-2) over a drain current range covering a range >=10% of the maximum saturated drain current.

[0030] 12. The device of any of the clauses 1-11, wherein the varying thickness of the recess is such that the gate electrode to 2DEG distance varies along the direction within 10 degrees of current flow direction so that the threshold voltage at the drain and source are different

[0031] 13. The device of any of the clauses 1-12 wherein the device is a transistor wherein the gate electrode has a gate length of 5 nm-5000 nm.

[0032] 14. A method of etching of N-polar III-N, comprising:

[0033] (a) performing a first etch step on N-polar III-N using a first etchant to form etched N-polar III-Nitride;

[0034] (b) removing the first etchant from the etched N-polar III-N;

[0035] (c) performing a second etch step on the etched N-polar III-N using a wet etchant to form an etched surface; and

[0036] (d) removing the wet etchant from the etched surface.

[0037] 15. The method of clause 14 further comprising using the first etchant to remove at least Inm of the N-polar III-N and wherein the rms surface roughness of the etched surface is no more than (e.g., the larger of):

[0038] 2 times larger than the starting surface roughness, and / or

[0039] 3nm rms roughness over a 10x10 pm area of the etched surface.

[0040] 16. The method of any of the clauses 14-15, wherein the first etchant comprises an acid.

[0041] 17. The method of any of the clauses 14-16, the first etch step self terminates at an etch depth

[0042] 18. The method of clause 14 wherein the wet etchant comprises at least one ofHCl or HNO3 acid. 19. The method of any of the clauses 14-18 wherein the N-polar nitride comprises a top GaN layer that is only partially etched by using only step (a) and (b) or by timing a duration of steps (a)-(d).

[0043] 20. The method of any of the clauses 14-18 wherein: the N-polar Nitride comprises a top III-Nitride layer on top of an etch stop layer, steps (a)-(d) completely etch the top Nitride layer stopping on or in the etch stop layer; and in step (c), an etch rate of the etch stop layer is less than 1 / 10thof the etch rate of the top Nitride layer .

[0044] 21. The method of clause 20 wherein the top III-Nitride layer comprises less Al than the etch stop layer.

[0045] 22. The method of any of the clauses 14-21, wherein: the N-polar III-N comprises a top Nitride layer on an etch stop layer on a bottom III-Nitride layer , the method further comprising: performing steps (a)-(d) to remove the etch stop layer and etch into the bottom III-Nitride layer, and repeating step (a) so that the first etchant comprising citric acid etches the etch stop layer.

[0046] 23. A method of etching an N-polar structure comprising or consisting of a first GaN layer on an AlGaN layer on a second GaN layer , the method comprising using citric acid to etch through the first GaN layer, the AlGaN layer, and a portion of the second GaN layer. .

[0047] 24. The device of any of the clause 1-13 comprising a HEMT manufactured using the method clause 14 wherein the gate electrode comprises at least one of platinum, ruthenium, titanium nitride, palladium, nickel, or doped silicon. 25. The device of any of the clauses 1-13 comprising a transistor, wherein the cap on either the source side or drain side or both are thinned using citric acid to create equal or unequal thickness of the access region in the source and drain regions wholly or in part after depositing the gate electrode using gate metallization.

[0048] 26. The device of any of the clauses 1-13 manufactured using the method of clause 16 using the wet etchant comprising citric acid, wherein the etched surface is smoother and has less damage than the recess that has been completely dry etched.

[0049] 27. The method of clause 14, wherein the first etching step improves smoothness and reduces surface roughness of the etched surface as compared to wet etching comprising a single step using HC1, or HN03 or their mixture (HC1:HNO3 with or without H2O).

[0050] 28. A device manufactured using the method of any of clauses 14-23

[0051] 29. A method of etching of N-polar Ill-nitride, comprising: performing a first wet etch step on N-polar Ill-nitride using citric acid to form etched III-Nitride; removing the citric acid from the etched III-Nitride; performing a second wet etch step using HC1 and HNO3 and H2O to form an etched surface; and removing the HC1, HNO3, and the H2O from the etched surface.

[0052] 30. The method or device of any of the clauses 1-29 wherein the surface roughness of the etched surface of the recess is no more than 2 times larger than the starting surface roughness.

[0053] 31. The method or device of any of the clauses 1-29 wherein the surface roughness of the etched surface of the etched recess is no more than 3nm rms roughness over a 10x10 pm area of the etched surface.

[0054] BRIEF DESCRIPTION OF THE DRAWINGS The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee

[0055] Referring now to the drawings in which like reference numbers represent corresponding parts throughout:

[0056] Figure 1. (a) two dimensional (2D) (b) three dimensional (3D) Atomic Force Microscope AFM scans of 14 nanometer (nm) GaN cap deep recess wafer after HC1:HNO3:H2O etch, starting surface roughness: 0.5 nm rms and etched surface roughness: 1.6 nm rms. Etching conditions: The solution of

[0057] HC1: H2O: HN03(20 mL: 20 mL: 300 mL) is used to etch 14 nm GaN cap layer selectively against AIGaN cap without any prior surface treatment.

[0058] Figure 2. (a) 2D (b) 3D AFM scans of 14 nm GaN cap deep recess wafer after being subjected to first citric acid etch and then HCkHNCh EEO etch, starting surface roughness: 0.55 nm rms and etched surface roughness: 0.45 nm rms. Etching recipe: wafer first dipped in above room temperature citric acid solution ( 50 / 50w / w Citric Acid Monohydrate in water) for a period of time, then rinsed with water and dried, and finally dipped in HC1: H2O: HN03solution, which is followed by the same rinsing and drying steps as used for Fig. 1 results.

[0059] Figure 3. (a) 2D (b) 3D AFM scans of 43 nm GaN cap deep recess wafer after being subjected to first citric acid etch and then HCkHNCh EEO etch for a small (-100 nm) feature, starting surface roughness: 0.4 nm rms and etched surface roughness: 0.65 nm rms.

[0060] Figure 3 (c) Top-view (d) tilted-view of sub-100 nm features etched with the proposed etch technique on a 14 nm GaN cap deep recess HEMT epi

[0061] Figure 3. (e) Top-view (f) tilted-view of sub-100 nm features etched with the proposed etch technique on a 43 nm GaN cap deep recess HEMT epi

[0062] Figure 4. (a) 2D (b) 3D AFM scans of 14 nm GaN cap deep recess wafer after being subjected to first HCkHNCh EEO etch and then citric acid etch (reversed order). Starting surface roughness: 0.46 nm rms and etched surface roughness: 3.15 nm rms Figure 5. 2D AFM scans on UID N-Polar GaN wafers after citric etch for a duration of (a) 1 hour 30 min (b) 6 hours

[0063] Figure 6. The epitaxial structure of the wafers for wet-etched Schottky HEMTs fabricated on: (a) wafer 1, (b) wafer 2

[0064] Figure 7. (a) Cross-sectional schematic of the device at the gate recess etch step (b) Top-down image of the etched gate recess on “wafer 1” (20 nm GaN cap) (c) Top-down image of the etched gate recess on “wafer 2” (47 nm GaN cap)

[0065] Figure 8. Atomic Layer Deposition (ALD) Ru deposition after wet recess etch to form a Schottky -barrier gate

[0066] Figure 9. DC transfer characteristics of the wet-etched Schottky HEMTs on (a) “wafer 1” (b) “wafer 2.”

[0067] Figure 10. DC output characteristics of wet-etched Schottky HEMTs on (a) “wafer 1” (b) “wafer 2”

[0068] Figure 11. Small signal (RF) characterization of the wet-etched Schottky HEMTs for:

[0069] (a) peak fr bias on “wafer 1” for a device with LG of 77 nm, and LSD of 540 nm

[0070] (b) peak f\[ \.\' bias on “wafer 1” for a device with LG of 77 nm, and LSD of 540 nm

[0071] (c) peak fr bias on “wafer 1” for a device with LG of 50 nm, and LSD of 420 nm

[0072] (d) peak f\[ \.\' bias on “wafer 1” for a device with LG of 50 nm, and LSD of 420 nm

[0073] (e) peak fr bias on “wafer 2” for a device with LG of 62 nm, and LSD of 420 nm

[0074] (f) peak f iAx bias on “wafer 2” for a device with LG of 62 nm, and LSD of 420 nm

[0075] Figure 12. DC transfer characteristics of a wet-etched Schottky HEMT on “wafer 2” before and after large signal measurement stress Figure 13. Pulsed transfer characteristics under gate bias stress for the evaluation of threshold voltage shift (a) wet-etched Schottky HEMT (b) dry-etched MIS HEMT

[0076] Figure 14. Record 94 GHz load pull performance of the wet-etched Schottky HEMTs (a) device (LG of 77 nm, and LSD of 540 nm) on “wafer 1” measured at VDS.Q: 8 V and IDS.Q: 0.25 A / mm (b) device (LG of 77 nm, and LSD of 540 nm) on “wafer 1” measured at VDS.Q: 10 V and IDS.Q: 0.25 (c) device (LG of 62 nm, and LSD of 420 nm) on “wafer 2” measured at VDS.Q: 10 V and IDS.Q: 0.25 A / mm

[0077] Figure 15. Cross-sectional Transmission Electron Microscope (TEM) images of the gate recess profile oriented in <1120> direction (a) zoomed-out view (b) zoomedin view of the sidewall 1 (c) zoomed-in view of the sidewall 2. (e) The schematic of the etch test structure with the dielectric etch mask, with a profile oriented in < 1120 > direction (f) zoomed-in profile of the gate recess. These images confirm the following: (1) The etch stops effectively on the AlGaN cap (2) The etch reveals a smooth and uniform surface in c-plane (c-minus plane) (3) The GaN cap sidewalls are symmetrical with 51° angle with respect to the AlGaN cap ( cti = a2= 51° ) (4) No undercutting is observed under the etch mask (MOCVD SiN is the bottommost layer for the dielectric mask stack used). All the features mentioned above are highly desirable for the gate recess etching of the deep recess HEMT process. Given the fact that the conventional high-performance N- polar GaN HEMTs are designed with a gate recess profile oriented around the < 1120 > direction, the etch technique is very convenient for fabrication of these devices.

[0078] Figure 16. Cross-sectional TEM images of the gate recess profile oriented in <1100> direction (a) zoomed-out view (b) zoomed-in view of the sidewall 1 (c) zoomed-in view of the sidewall 2 (d) higher magnification view of the sidewall 2 close to the etch mask, (d) . The schematic of the etch test structure with the dielectric etch mask, with a profile oriented in < 1100 > direction (e) zoomed-in profile of the gate recess

[0079] Figure 17. Cross-sectional schematic of wet-etched HEMT with the gate profile oriented around in <1100> direction showing the slanted bottom recess. The devices can be oriented with either the source or drain edge of the recess bottom is raised compared to the opposite side.

[0080] Figure 18. Cross-sectional schematic of wet-etched HEMTs with the recess etch terminated at the different depths (a) The etch stops on AlGaN (the nominal case) (b) The GaN cap is partially etched (c) AlGaN cap is completely etched (d) Some portion of the channel is etched (e) diode structure.

[0081] Figure 19. Flowchart illustrating a method of making a device.

[0082] Figure 20 illustrates a process flow starting with (a) N-polar deep recess HEMT epi structure (b) GaN cap etch for the N + GaN regrowth for the ohmic contacts (c) GaN cap etch for the gate recess (d) Completed N-polar GaN HEMT structure

[0083] DETAILED DESCRIPTION OF THE INVENTION

[0084] In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0085] Technical Description

[0086] The challenge with the Schottky HEMTs is keeping the gate leakage low. The present disclosure describes a technique of wet etching of N-polar GaN that keeps the etched surface smooth and effectively stops etching on AlGaN. We then demonstrate a Schottky N-polar GaN HEMT implementation using this technique, where the gate recess profile (or the direction of current flow) is oriented around the <1120> crystal direction. These devices demonstrate a low gate leakage current thanks to the improved / good quality of the etched surface as characterized by (1) low roughness, and (2) no plasma damage (unlike for the case using the traditional method of plasma etching). Furthermore, these devices demonstrate record high gain and efficiency compared to the previous MIS (metal insulator semiconductor) devices with gate dielectrics. Embodiments of the present invention enable removal of two very costly processes from N-Polar HEMT fabrication: (1) Selective etching of N-Polar GaN against AlGaN with plasma etch (ICP) and (2) MOCVD gate dielectric deposition. Thus, embodiments of the present invention may enable a reliable method of smooth- selective wet etching for fabrication of high-performance N-Polar deep recess HEMTs (both Schottky and MIS) in a much cheaper, repeatable, reliable, robust and higher throughput way than using plasma etching.

[0087] First Example Method and Results

[0088] In one example, sequential smooth-selective wet etching of N-Polar GaN against AlGaN was performed as follows: (1) The wafer was first dipped in a citric acid solution (we used 50 / 50 w / w Citric Acid Monohydrate in water), where the temperature can be any temperature (we used 80 °C) .(2) The wafer was then rinsed with water and dried. (3) The wafer was then dipped in HCFHNC EhO solution, which we refer to as the etch solution. The fractional volume we used for the components was 1 : 15:1. However, the fractional volume can be any fraction of the individual chemicals, different from 1 : 15: 1. (4) The wafer was then rinsed with water and dried. The order of the etches is very important, as the reverse order will result in a significantly roughened surface and loss of selectivity.

[0089] The citric acid etch prior to the etch with HC1:HNO3:H2O solution plays a crucial role in keeping the etched surface smooth. To illustrate, the solution of HC1:HNO3:H2O (20 mL:20 mL:300 mL) was used to etch 14 nm GaN cap layer selectively against AlGaN cap without any prior surface treatment. The 14 nm deep recess HEMT wafer (with epitaxial layers same as in Fig. 6(b), but with a GaN cap thickness of 14 nm) was used solely for testing the etch. The 2D and 3D atomic force microscopy (AFM) scans of this etch are demonstrated in Fig. 1. The etch effectively stopped on the AlGaN . Nevertheless, the etched region surface roughness is 1.6 nm rms, which is more than three times as large as that of the starting surface with 0.5 nm rms roughness. On the other hand, for the case when the citric acid etch was performed prior to HCI HNO3 H2O etch, the etched region roughness turned out to be 0.45 nm rms while that of the starting surface was 0.55 nm rms, showing that the citric acid treatment keeps the roughness of the etched surface low after HCI HNO3 H2O etch, as shown in Fig. 2. To evaluate the selectivity, a wafer with unintentionally doped (UID) N-polar GaN with no AlGaN layer underneath GaN was used and was subjected to the exact same etch steps as the 14 nm GaN cap deep recess HEMT wafer. The etch depth on this UID N-polar GaN wafer turned out to be 40 nm. As the etch on the deep recess wafer stopped on the AlGaN after 14 nm, the GaN etch depth of 40 nm without going through AlGaN means that AlGaN was able to stop the etch on the deep recess epi for an equivalent time of etching 26 nm GaN (185% overetch), demonstrating a selectivity of at least 10. This method can be extended for N-polar GaN caps with larger thicknesses, i.e. 43 nm (tested on a wafer with epitaxial layers same as in Fig. 6(b), but with a GaN cap thickness of 43 nm).

[0090] Fig. 3 shows the AFM scans for a 43 nm GaN cap wafer (used solely for testing the etch) being subjected to the proposed etch method (citric etch first, and then HCFHNCUEEO etch), with starting surface roughness of 0.4 nm rms. The roughness of the etched surface was 0.65 nm rms, which shows that the smoothness was maintained to be low after such a deep etch. Fig 3c and 3d show the scanning electron microscopy (SEM) images after the etch with the S1O2hard mask in place. As it can be seen, sub-lOOnm gate lengths with smooth etched surface obtained, making this method very attractive for highly-scaled high-performance HEMTs. Fig. 3e and 3f show the SEM images of the 43 nm etched recess with smooth surface, which showcases the scalability of the method to the different GaN cap thicknesses for sub- 100 nm gate lengths.

[0091] The order of the etches is very important for the proposed method (citric etch first, and then HCFHNCUEEO etch). Reversing the order of the etches caused significant surface roughening and loss of selectivity. Fig 4. shows the AFM scans on the same 14 nm GaN cap wafer after doing first (1) HC1:HNO3:H2O etch, and then (2) citric acid etch. The starting surface roughness was 0.46 nm rms, and that of the etched region was 3.15 nm rms, which means more than 6.5 times rougher surface after the etch.

[0092] Additionally, the citric acid itself was evaluated without HC1:HNO3:H2O etch. For this experiment, two UID N-Polar GaN wafers were used. One of them was subjected to citric acid etch for 1 hour 30 min and the other one was subjected to the same for 6 hours. Fig 5. shows the AFM scans for these etches. For both cases, the etch depth was about 12 nm (-+3 nm). The etch depth could depend on temperature (we used 80 °C) and starting surface morphology. This shows that the GaN etch stops after a certain depth with citric-only etch. This feature of the citric-only etch can be used when an N-Polar GaN layer needs to be partially etched. In a device, this can be utilized for the recess etch as well as for thinning the cap on the access regions.

[0093] To make transistors, the etch method (citric acid etch first, and then HC1:HNO3:H2O etch ) was used to etch the gate recess of 20 nm and 47 nm GaN cap thickness deep recess HEMT wafers, where the gate recess profile was oriented around the <1120> crystal direction. The 20 nm GaN cap wafer had a 10 nm channel thickness (wafer 1), whereas the 47 nm GaN cap wafer had a 12 nm channel thickness (wafer 2), as shown in Fig.6. Fig.7 shows the etched gate recess fabricated with the etch method, showcasing smooth etched surface for 2 different GaN cap thicknesses and successful creation of sub-100 nm gate lengths. To form the Schottky-barrier gates, Atomic Layer Deposition (ALD) Ru was deposited at 300 °C, as shown in Fig. 8. The rest of the device process followed the traditional deep recess HEMT process with top-gate metal formation, and finally ohmic and pad metallization.

[0094] The devices were then characterized with DC, small signal, pulsed-IV and load pull measurements. Fig 9. shows the DC transfer characteristics of the Schottky HEMTs for both wafers. Table 1 below summarizes the performance. The devices demonstrate very low off-state (see Table 1) gate leakage current below 11 pA / mm and also low on-state (see Table 1) leakage current below 40 pA / mm at VD of 3 V. The low leakage current can be attributed in part to the (1) smooth wet etched surface with no plasma damage and (2) the choice of gate metal of Ru.

[0095] Wafer 1, which has a channel thickness of 10 nm, demonstrates a record-high transconductance of 917 mS / mm at VD of 3 V, which is significantly larger than what a device utilizing MIS gate (with gate insulator) can provide with equivalent material specifications, thanks to the vertical scaling enabled by the Schottky gate. The devices demonstrate a high on to off current ratio of more than 105, which is necessary to obtain both high efficiency and power.

[0096] Table 1 : DC transfer characteristics

[0097] Fig. 10 shows the DC output characteristics. Both wafers show low on-resistance (RON) and high-current (ID) as shown in Table 2 below:

[0098] Table 2: DC output characteristics

[0099] LG LSD RON (ohm.mm) ID ( / in in)

[0100] (nm) (nm)

[0101] Wafer 77 540 0.41 (at VG: +1.0V) 1.63 (at VG: + 1.5 V and VD: +2. 1 V )

[0102] 1

[0103] Wafer 62 420 0.43 (at VG: +1.0V) I .53 (at VG: + 1 ,0V and VD: +2.0V )

[0104] 2

[0105] Fig. 11 shows the small signal (RF) performance of the Schottky HEMTs with WG of 2x25 pm.

[0106] Wafer 1 : The device with LG of 77 nm, and LSD of 540 nm demonstrates peak fi iAx of 288 GHz and peak frof 139 GHz. The device with more scaled dimensions (LG of 50 nm, and LSD of 420 nm) demonstrates N-polar deep recess record peak frof 175.5 GHz and peak f\[ \x of 307 GHz.

[0107] Wafer 2: The device on wafer 2 exhibited high peak f\[ \x of 311 GHz with an associated fr of 94 GHz, and peak fr of 112 GHz with an associated 251 GHz fMAx.

[0108] 5 The devices have a very high maximum stable gain (MSG) of over 11.5 dB at the peak Ax bias. The table below summarizes the data:

[0109] Table 3 : Small signal (RF) performance

[0110] LG LSD f / fuAX fr / fMAX MSG (67 GHz) (nm) (nm) (peak fr condition) (peak I'MAX (peak fMAx condition) condition)

[0111] Wafer ! 540 139 GHz / 277 GHz 130 GHz / 288 GHz 12.35 dB

[0112] Wafer ! 420 176 GHz (record) / 162 GHz / 307 GHz 288

[0113] Wafer 2 62 420 1 I 2 GHz

[0114] Another advantage of the N-polar GaN Schottky HEMTs over the MIS0 HEMTs is the superior threshold voltage (VTH) stability. The transfer characteristics of the Schottky HEMT (LG: 62 nm, LSD: 420 nm, WG:2X25 pm) on “wafer 2” was measured before and after high-stress load pull measurements to evaluate VTH shift. After the first transfer characteristics measurement, the device was subjected sequentially to the following large signal measurements: 5 (1) Load pull and power sweep at VDS = 12 V and IDS = 0.25 A / mm

[0115] (2) Load pull and power sweep at VDS = 12 V and IDS = 0.30 A / mm

[0116] (3) Load pull and power sweep at VDS = 8 V and IDS = 0.25 A / mm

[0117] (4) Load pull and power sweep at VDS = 8 V and IDS = 0.30 A / mm

[0118] (5) Load pull and power sweep at VDS = 8 V and IDS = 0.35 A / mm0 (6) Load pull at VDS = 8 V and IDS = 0.4 A / mm

[0119] (7) Load pull at VDS = 8 V and IDS = 0.5 A / mm

[0120] (8) Load pull and power sweep at VDS = 10 V and IDS = 0.30 A / mm

[0121] (9) Load pull at VDS = 10 V and IDS = 0.35 A / mm

[0122] (10) Load pull at VDS = 10 V and IDS = 0.35 A / mm (11) Load pull and power sweep at VDS = 10 V and IDS = 0.60 A / mm

[0123] Fig. 12 shows the transfer characteristics for before and after the complete large signal measurement (load pull) stress (after step 11). The threshold voltage shift is very small (less than 25 mV), showcasing the robustness and reliability of these devices. Another way to evaluate the VTH shift would be through the pulsed transfer characteristics under VG stress. We compared wet-etched Schottky HEMTs (“wafer 2”) with dry-etched MIS HEMTs, which were fabricated on the exact same wafer as “wafer 2”.

[0124] Fig. 13 shows the VTH shift under gate bias (VG) stress for Schottky and MIS HEMTs in the pulsed measurements. Comparing pulsed transfer curves at the quiescent bias of (VGS.Q, VDS.Q) = (0 V, 0 V) to (-4 V, 0 V) for both wafers, dry-etched MIS HEMT demonstrated a threshold voltage difference of 0.49 V, whereas that of wet-etched Schottky HEMTs was only 0.18 V. It’s important to note that (-4 V, 0 V) condition is a very stressful condition for the wet-etched Schottky HEMT because the device is strongly turned-off at that bias. On the other hand, dry-etched MIS HEMT is still on for this bias condition. For a slightly on condition of (-2 V, 0 V), the wet- etched Schottky HEMT shows a threshold voltage shift of only 0.075 V. Another thing to note is that the sign of the threshold voltage shift could be different than what is reported here for dry-etched MIS HEMTs depending on the epitaxy, though the amount of shift will always be bigger than Schottky HEMTs.

[0125] Finally, the Schottky HEMTs (WG: 2X25 pm) on both wafers (“wafer 1” and “wafer 2”) were measured with load pull at 94 GHz for large signal performance evaluation, as shown in Fig. 14. When the load impedance is tuned for efficiency, a Schottky HEMT on “Wafer 1” demonstrates record gain (10.5 dB) and PAE (50.2%), and one on “Wafer 2” demonstrates record high PAE (47.5%). World-record high-gain and efficiency (PAE) were obtained with the wet-etched Schottky-barrier gate enabling increased gate control. “Wafer 1” load pull performance

[0126] (1) At VD.Q: 8 V and ID.Q: 250 mA / mm

[0127] • Linear gain: 9.9 dB

[0128] • Peak PAE condition: 50.3% PAE with an associated 2.1 W / mm POUT • Peak POUT condition: 42.9% PAE with an associated 2.6 W / mm POUT

[0129] (2) At VD.Q: 10 V and ID.Q: 250 mA / mm

[0130] • Linear gain: 10.5 dB

[0131] • Peak PAE condition: 50.2% PAE with an associated 2.8 W / mm POUT

[0132] • Peak POUT condition: 46.6% PAE with an associated 3.2 W / mm POUT

[0133] “Wafer 2” load pull performance

[0134] (1) At VD.Q: 10 V and ID.Q: 250 mA / mm

[0135] • Linear gain: 8.4 dB

[0136] • Peak PAE condition: 47.5% PAE with an associated 1.9 W / mm POUT

[0137] • Peak POUT condition: 41.6% PAE with an associated 2.5 W / mm POUT

[0138] Second Example: Novel Schottky and MIS HEMT structures enabled by the wet-etching technique described herein.

[0139] To evaluate the etch profile in the deep recess, cross sectional images of the etched regions are taken with TEM in 2 different perpendicular crystal directions, namely < 1120 > and < 1100 >, on the wafer with 43 nm GaN cap. The schematic of the etch test structure with the dielectric etch mask is shown in Fig. 15 for a profile in < 1120 > direction. The angle between the GaN cap sidewall and the AlGaN cap are denoted as a and a2for the respective sidewalls.

[0140] The demonstrated Schottky HEMTs’ gate recess profiles are oriented around the <1120> crystal direction. Fig. 15 shows the cross-sectional TEM images of the smooth- selective wet etch recess oriented around the <1120> crystal direction. In this direction, the GaN cap sidewalls are symmetrical.

[0141] In the orthogonal direction of <1100>, however, the sidewalls are asymmetrical, as shown in Fig. 16. These images in Fig. 16 demonstrate the following: (1) The etch stopped on the AlGaN cap (2) The etch reveals a smooth and uniform surface in c-plane (3) The sidewalls are asymmetrical: ?x= 23.5° and / 32= 3.7° (substrate miscut angle). (4) There is a distinct region on the GaN cap side wall where the GaN cap angle changes, which could be associated with the initial citric acid etch. The angle associated with the citric acid is nearly symmetric (0X= 36.8° and 02= 38.9°) (5) No undercutting is observed under the etch mask (MOCVD SiN is the bottommost layer for this dielectric mask stack). Although the gate recess profiles of the conventional HEMTs are designed around < 1120 > direction, doing this around the orthogonal < 1100 > direction using the etch technique allows for the potential of performance improvement for different applications.

[0142] As noted, one of the sidewalls has a very shallow angle of 3.7°. Fabricating devices with gate profiles around <1100> direction, the gates can be built directly on the sidewall with 3.7 ° angle, enabling threshold voltage variation and engineering between the source and drain due to varying distance between the gate metal and the electrons in the channel, and improving the degree of freedom in the HEMT design for breakdown voltage, saturation current and DC-RF dispersion. This etch profile is illustrated in Fig. 17. Although Fig. 17 illustrates the bottom of the recess is rising towards the drain, in another implementation the recess can be rising towards the source.

[0143] The recess etch can be terminated at different depths to be able to adjust the design for gain, breakdown voltage and leakage. The possible recess etch depth scenarios are illustrated in Fig. 18 and are as follows: (i) The etch stops on AlGaN (the nominal case) (ii) The GaN cap is partially etched (iii) AlGaN cap is completely etched (iv) Some portion of the channel is etched. These scenarios can be applied to both MIS and Schottky HEMTs and for gate recess profiles oriented around either of <1120> and <1100> directions.

[0144] Process Steps

[0145] Fig. 19 is a flowchart illustrating a method of etching N-polar III-Nitride. In one or more examples, the III-Nitride comprises a device structure for a HEMT. Although the present disclosure illustrates the methods and devices that transport electrons in a two dimensional electron gas (2DEG), devices using holes as the majority transport carrier in a two dimensional hole gas (2DHG) can also be fabricated using the methods described herein.

[0146] In typical embodiments, the 2DEG or 2DHG is confined in the channel layer by a barrier layer (e.g., backbarrier) because the barrier layer has a higher bandgap than the channel layer. Typical examples include, but are not limited to, GaN channel with AlGaN or AIN barrier, or an InGaN channel with InAlGaN barrier. A structure can further comprise one or more cap layers depending on the composition. For example, a first AlGaN cap layer can be provided on the GaN channel if the channel comprises no Al, and then a second cap can be provided on the AlGaN cap wherein the second cap layer has a lower Al content than the first AlGaN cap layer.

[0147] Block 1900 represents performing a first etch step with first etchant, e.g. wet etch with using citric acid or dry etch (e.g., reactive ion etching, RIE or inductively coupled plasma ICP, ).

[0148] Block 1902 represents removing the first etchant, e.g., citric acid from the etched III-Nitride (e.g., by rinsing with water and drying).

[0149] Block 1904 represents optionally performing a second wet etch step, e.g., using one or more wet etchants (e.g., HC1 and HNO3 and H2O).

[0150] Block 1906 represents removing the wet etchants, e.g., the HC1, the HNO3, and H2O from the etched III-Nitride (e.g., by rinsing with water and drying).

[0151] In one or more embodiments, the etching uses ratios of 1 : 15: 1 for HC1:HNO3:H2O and 50 / 50 w / w citric acid monohydrate in water.

[0152] Both the citric acid and the HC1:HNO3:H2O etch can be at room temperature or any temperature where the solution is still liquid). The timing and / or temperature of the first and second etch steps can be modified or optimized as needed.

[0153] Block 1908 represents optionally repeating the etching steps. In one or more embodiments, the steps 1900-1904 can be repeated or partially repeated. In one embodiment the N-polar nitride comprises GaN on AlGaN on GaN, and only partially etching the GaN, by using citric acid only (e.g., etches only 12 nm (+-3 nm) then it stops, where the etch depth could depend on temperature (we used 80 °C) and starting surface morphology) or timing the length of each of the steps 1400 and 1404 so that some GaN cap is left. In one embodiment, the timing uses an etch rate 0.3 nm per minute (at room temperature ) for the HCkHNC EhO etch.

[0154] Block 1910 represents optionally processing or fabricating the etched device structure into a device such as, but not limited to, a transistor (e.g., HEMT). Block 1912 illustrates the end result, an etched structure or device. In one or more embodiments, utilizing the specific sequential wet etch achieves a smooth surface with no plasma damage (unlike with dry plasma etch), resulting in superior gate control (e.g., increased threshold voltage stability), and low gate leakage Schottky HEMTs with higher gain. In addition, the high etch selectivity method reducing surface roughness enables high transconductance (as expected from superior Schottky HEMTs). Schottky barrier transistors can have superior properties to transistors with gate dielectrics which are more prone to threshold voltage instability.

[0155] The etching method described herein can also fabricate novel Schottky HEMTs with source and drain contacts oriented in the orthogonal direction (or other directions different from) the directions conventionally used. In one embodiment of the orthogonal direction, this sequential etch method creates a 3.7 degree sidewalls, which enables designs with varying threshold voltage between the source and drain.

[0156] Furthermore, making Schottky HEMTs using the etching technique enables more flexibility for tailoring the etch depth, e.g., (i) partially etching the GaN cap, or (ii) completely etching the GaN cap completely etched (nominal case) (iii) etching the AlGaN cap, or (iv) etching some portion of the GaN channel etched. Tailoring the etch depth can optimize trade-off's between gate leakage and breakdown with gain and efficiency for different applications.

[0157] Not only does the etch method presented herein enhance device performance, it can also fabricate devices more reliably (more repeatable results between devices) and more cost effectively.

[0158] Although the experimental results are illustrated using GaN / AlGaN / GaN structures on an AlGaN backbarrier, one skilled in the art understands that similar advantageous properties as described herein (smoother surfaces, larger selectivity, resulting in lower gate leakage and higher gain and transconductance) can be achieved for other Ill-nitride compositions (e.g., aluminum and gallium compositions such as AIN, InAlGaN or ScvGawAlxInyBzN where there is some Al content) that have a common quality to GaN and AlGaN compositions which make them adapted to being etched in a similar way.

[0159] In one or more embodiments, the second etchant in the second etch step of Block 1906 can be an etchant that etches (e.g., N-polar) AlxGai-xN faster than (e.g., bipolar) AlyGai-yN where x is less than y (e.g., preferentially etches N-polar GaN over N-polar AlGaN), or a selective etchant.

[0160] Although the method of selective wet etching of N-polar GaN is shown to be implemented in any epitaxial structure that involves an AlxGax-xN layer (0 < x < 1) under the GaN, the etching can be performed on other N-polar III -nitrides with common or similar N-polar etching qualities. However, one of the most attractive applications of this etch technique is the selective etching of the GaN cap for the N- polar GaN deep recess HEMT fabrication process. The deep recess HEMT epitaxial structure to test the selective N-Polar GaN etches is shown in Fig 19 (a), which involves a GaN cap on top and an AlGaN cap layer underneath it, grown on a 4° miscut substrate. In the deep recess HEMT process, the GaN cap is etched for both (1) N + GaN regrowth process for the ohmic contacts and (2) for the gate recess formation, as shown in Fig. 19 (b), and 19(c), respectively. Fig 19. (d) shows the final HEMT structure.

[0161] Illustrative embodiments of devices that can be fabricated include, but are not limited to, the following.

[0162] 1. An N-polar device 1800, e.g., a high electron mobility transistor (HEMT), comprising a III -Nitride backbarrier 1802; a III -Nitride channel 1804 comprising a 2DEG confined in the channel by the backbarrier; an optional cap layer 1805 on the channel; at least one ohmic contact 1806 (e.g., source and / or drain contact) to the channel; an (e.g., wet) etched recess 1808 in the cap and / or into the channel; and gate electrode 1810 in the recess 1808 forming a Schottky barrier (e.g., with the channel or the cap layer above the channel) such that when the device is operated: the gate leakage through the Schottky barrier is less than 0.5mA / mm for VDS of 0.5 V or less, and / or under forward bias at +1 VGS, the gate leakage is less than 0.5 mA / mm for the VDS is 0.5 V or less (or in a range of O.lmA / mm < gate leakage < 0.5 mA / mm).

[0163] 2. The HEMT of clause 1, wherein the cap layer comprises a GaN cap 1812 on an Al GaN cap 1814 and the recess extends to the channel, the GaN cap on the channel, or the AlGaN cap.

[0164] 3. The HEMT of clause 1 or 2, wherein the backbarrier comprises AlxGai-XN

[0165] (e.g., Alo.38Gao.62N) and the channel comprises GaN and wherein 0<x^l or 0.05 < x < 0.5) and wherein the backbarrier optionally comprises a thinner AIN layer on top of the thicker AlxGal-xN layer (so that the AIN is between the AlGaN and the GaN).

[0166] 4. The HEMT of any of the clauses 1-3, wherein the recess does not comprise an undercut.

[0167] 5. The HEMT of any of the clauses 1-4, wherein the gate electrode comprises platinum or ruthenium or titanium nitride, or palladium, or nickel, or doped silicon, or any conductive material that provides a barrier to produce the gate diode characteristics of clause 1.

[0168] 6. An N-polar device 1700 (e.g., HEMT) comprising: a III -Nitride backbarrier 1702; a III -Nitride channel 1704 comprising a 2DEG confined in the channel by the backbarrier; at least one ohmic contact 1706 (e.g., source contact and / or drain contact) to the channel; an optional cap 1708 (e.g., GaN); a recess 1710 having a varying thickness T along a direction 1712 between and including the <1 - 100> direction and the <-l - 120> direction of the III -Nitride such that the recess contains at least one region ( first region 1714a, optionally a second region 1714b) with a slope 1716 defined by an angle greater than 0 degrees with respect to the horizontal plane (or interface between the III-Nitride backbarrier and the III-Nitride channel) 1718 wherein the slope of the first region is at an angle 1720 between 0.5 to 5 degrees (e.g., 0.5 degrees < angle 1720 < 5 degrees), and the slope of the second region, when present, is at an angle between 15 to 50 degrees (e.g., 15 degrees < angle 1720 < 50 degrees), with respect to the horizontal plane; and optionally further comprising: a gate electrode 1722 in the recess forming a Schottky barrier with the cap or the channel, wherein current flow between the source contact and the drain contact is along / parallel to the direction 1712 of the varying thickness T.

[0169] 7. The N-polar HEMT of clause 6, wherein the current flow direction is within 10 degrees of the <l-100> direction.

[0170] 8. The N-polar HEMT of clause 6 or 7, wherein the cap has a thickness T2 varying along the direction of current flow 1724 to obtain a threshold voltage varying over the gate width (e.g., into page in Fig. 17) and / or gate length L, with components in the gate width direction and the gate length L direction having predetermined amounts, e.g., such as 6 nm thickness variation over 100 nm distance over gate length Lg, and / or 10 nm thickness variation over 10 pm distance over the gate width, or between 3 nm and 9 nm (e.g., 3 nm < AT2< 9nm) per lOOnm of gate length Lg and between 5 and 15nm (e.g., 5 nm < AT2< 15 nm) per 10 microns of gate width Wg.

[0171] 9. The N-polar HEMT of any of the clauses 6-8, wherein the gate electrode to 2DEG distance 1726 varies along the direction 1728 within 10 degrees of perpendicular to the direction 1724 of current flow such that the HEMT operation is linear, which is defined by the ratio of the third order derivative to the first order derivative of the drain current with respect to gate-to-source voltage (gm3 / gml) of less than 0.05 (V'2) over a drain current range of 0.15 to 0.5 A / mm (e.g., 0.15 A / mm < drain current < 0.5 A / mm)and / or covering a range > 10% of the maximum saturated drain current.

[0172] 10. The N-polar HEMT of any of the clauses 1-9, wherein gate electrode to 2DEG distance varies along the direction 1728 within 10 degrees of the current flow direction 1724 so that the threshold voltage at the drain contact and source contact are different, for example at least 5% or 100 mV threshold voltage difference.

[0173] 11. The N-polar HEMT of any of the clauses 1-10, wherein the channel comprises at least one of indium, gallium, aluminum, scandium and the backbarrier comprises at least aluminum.

[0174] 12. The HEMT of any of the clauses 1-11, wherein the Ill-nitride material comprises one or more layers of ScvGawAlxInyBzN where O^v^l, O^w^l, O^x^l, O^y^l, O^z^l, and v+w+x+y+z=l with compositions such that the 2DEG is confined in the channel.

[0175] 13. The HEMT of any of the clauses 1-12, wherein the transistor has a gate length L of 5 nm-5000 nm and a channel length Lsd of 10 nm- 5000 nm.

[0176] 14. A method of etching of N-polar Ill-nitride, comprising:

[0177] (a) performing a first wet etch step using citric acid;

[0178] (b) removing the citric acid;

[0179] (c) performing a second wet etch step using HC1 and HNO3 and H2O; and

[0180] (d) removing the HC1, HNO3, and H2O.

[0181] 15. The method of clause 14 wherein the N-polar nitride comprises GaN on AlGaN on GaN, and only partially etching the GaN, by using citric acid only (which in this example etches only 12 nm (+-3 nm) then it stops, where the etch depth could depend on temperature (we used 80 °C) and starting surface morphology) and / or timing length / duration of (a)-(d) so that some GaN cap is left (e.g., determining the timing using an etch rate 0.3 nm per minute (at room temperature ) for the HCI / HNO3 etch) 16. The method of clause 15, wherein the N-polar Nitride comprises GaN on AlGaN on GaN and the etching the top GaN completely by performing steps (a)- (d) to automatically stop on the AlGaN (AlGaN etch rate is less than one tenth of GaN etch rate), e.g., using 1 : 15: 1 for HCkHNCh ThO and (50 / 50 w / w citric acid monohydrate in water).

[0182] 17. The method of clause 14, wherein the N-polar Nitride comprises GaN on AlGaN on GaN, comprising etching to remove AlGaN to etch into the lower GaN, comprising performing steps (a)-(d) and then repeating step (a) so that the citric acid etches the AlGaN.

[0183] 18. AHEMT (e.g., of any of the clauses 1-13 or comprising a gate dielectric) manufactured using the method of any of the clauses 15-17 wherein the gate electrode comprises platinum or ruthenium or titanium nitride or any conductive material.

[0184] 19. A transistor (HEMT) of any of these clauses 1-18, wherein the cap on either the source side or drain side or both are thinned using citric acid after gate metallization to create equal or unequal thickness of the access region in the source and drain regions wholly or in part, e.g., after depositing the gate electrode using gate metallization. Citric acid is compatible with metals, so the GaN cap on the access regions (where there is channel but no gate) can be thinned using citric acid after gate metal is deposited.

[0185] 20. A transistor (HEMT) of any of these clauses 1-19, wherein the threshold voltage of the HEMT is stable with less than 200 mV change after power amplification at gain compression of greater than 1 dB and at a power density of greater than 1 W / mm.

[0186] 21. A transistor (e.g., HEMT) of any of these clauses 1-20, wherein the transition frequency x gate length product (frxLo) at peak fr bias is more than 6 THz. pm for the ratio of gate length to gate electrode-to-2DEG distance smaller than 10. 22. The transistor (e.g., HEMT) of any of the clauses 1-21, wherein the wet etched surfaces of the recess are smoother than, have the same roughness as, or have a roughness increased by no more than two times as compared to before the etching.

[0187] 23. The transistor (e.g. HEMT) of any of the clauses 1-22, wherein the wet etched surfaces are smoother and have less damage than the recess that has been dry etched.

[0188] 24. The HEMT of any of the clauses 1-23, wherein a base surface of the recess is inclined at around miscut angle, for example 3.7 degrees or within + / -3 degrees of 3.7 degrees (e.g., 0.7 degrees < 3.7 degrees < 6.7 degrees, with respect to the N-polar surface and in a direction away from the N-polar surface.

[0189] 25. The HEMT of any of the clauses 1-24, wherein sidewalls of the of the recess on either side of the base surface are inclined with an angle between 0.5-60 degrees so that the recess has increasing thickness moving away from the base surface.

[0190] 26. The HEMT of one or more of the clauses 1-25, comprising a Metalinsulator-semiconductor high-electron-mobility transistors (MIS-HEMTs).

[0191] 27. The HEMT of one or more of the clauses 1-26, wherein the HEMT is manufactured using the first wet etch step comprising citric acid and the second wet etch step using the etchants comprising hydrochloric acid (HC1), nitric acid (HNO3) and water (H2O).

[0192] 28. A method of etching of N-polar III-N, comprising:

[0193] (a) performing a first etch step on N-polar III-N using a first etchant;

[0194] (b) removing the first etchant to form etched N-polar III-N;

[0195] (c) performing a second etch step on the etched N-polar III-N using a (e.g., liquid) wet etchant; and

[0196] (d) removing the wet etchant.

[0197] 29. The method of clause 28 wherein the first etchant removes at least 1 nanometer of the N-polar III-N and following exposure to the wet etchant, the RMS surface roughness of an etched surface of the N-polar III-N is no more than (e.g., the larger of) :

[0198] 2 times larger than the starting surface roughness (prior to step (a)) and / or

[0199] 3 nm RMS (root mean square) roughness or 2nm rms or Inm rms in a 10x10 pm region.

[0200] (i.e., surface roughness is no more than 2 times larger than starting surface or no more than 3 nm RMS, whichever is larger)

[0201] 30. The method of clause 28 or 20 wherein the first etchant contains an acid such as citric acid.

[0202] 31. The method of any of the clauses 28-30 wherein the etch depth of the first etch step self terminates (e.g., because the first etch reaches an etch stop layer or because the etch forms a passivation layer after a particular depth).

[0203] 32. The method of any of the clauses 28-31 wherein the wet second etchant contains HC1 or HN03 acid.

[0204] 33. The method of any of the clauses 28-33 wherein the N-polar III-N comprises a top GaN layer that is only partially etched using only step (a) and (b) or timing duration of steps (a)-(d).

[0205] 34. The method of any of the clauses 28-33 wherein the N-polar Nitride comprises a top Nitride layer on top of an etch stop layer, steps (a)-(d) completely etch the top Nitride layer stopping on / in the etch stop layer and wherein the etch stop layer etch rate is less than 1 / 10ththe top Nitride layer etch rate in step (c) (e.g., by selection of etchant and / or composition of the nitride).

[0206] 35. The method of clause 34 wherein the top III-N layer contains less Al than the etch stop layer.

[0207] 36. The method of any of the clauses 28-35, wherein the N-polar Nitride comprises a top Nitride layer (e.g., GaN) on an etch stop layer (e.g., AlGaN) on a bottom Nitride layer (e.g., GaN), the method further comprising etching to remove the etch stop layer to etch into the bottom Nitride layer by performing steps (a)-(d) and then repeating step (a) so that the citric acid etches the etch stop layer. 37. The method of any of the clauses 28-37, wherein the N-polar III-N comprises a top Nitride layer such as GaN on an etch stop layer such as AlGaN on a bottom Nitride layer such as GaN, comprising etching to remove the etch stop layer to etch into the bottom Nitride layer, comprising performing only step (a) which etches through the top nitride layer (e.g., GaN), the etch stop layer (e.g., AlGaN), and some portion of the bottom nitride layer (e.g., GaN channel) by itself.

[0208] 38. The method or device of any of the clauses 1-37, wherein the etch results in a smooth surface with the rms surface roughness of the etched surface of the recess is no more than (e.g. the larger of):

[0209] 2 times larger than the starting surface roughness, and / or

[0210] 3 nanometer RMS roughness, 2 nm RMS roughness, 1 nm RMS roughness in a 10x10 pm region.

[0211] (i.e., surface roughness is no more than 2 times larger than starting surface or no more than 3 nm RMS, whichever is larger)

[0212] 39. The method or device of any of the clauses 1-38, wherein the etch results in a smooth surface with the rms surface roughness is in a range Inm < surface roughness < 3 nm.

[0213] 40. A device manufactured using the method of any of any of the clauses 14-17 or 28-39.

[0214] 41. The device of any of the clauses 1-13 or 18-27 manufactured using the method of any of the clauses 14-39.

[0215] 42. The method of any of the clauses 14-17 or 28-39, wherein the etching improves smoothness and reduces surface smoothness as compared to wet etching comprising a single step using HC1, or the HNO3 or their mixture (HCkHNCh with or without H2O).

[0216] 43. The method or device of any of the embodiments 1-41 without a gate dielectric between the gate electrode and the etched surface of the recess in contact with N-polar III-N or the channel. 44. The method or device of any of the clauses wherein the recess has an etched surface in contact with the III-N of the cap and / or channel with a smoothness / roughness characterized by a gate leakage through the Schottky barrier being less than 0.5mA / mm for VDS of 0.5 V or less, and / or under forward bias at +1 VGS, the gate leakage being less than 0.5 mA / mm for the VDS is 0.5 V or less (or in a range of O.lmA / mm < gate leakage < 0.5 mA / mm).

[0217] 45. The method or device of any of the clauses 1-44, wherein the surface roughness of the etched surface of the recess is no more than 2 times larger than the starting surface roughness.

[0218] 46. The method or device of any of the clauses 1-44, wherein the surface roughness of the etched surface of the recess is more than 3 nanometer RMS roughness, no more than 2 nm RMS roughness, or no more than 1 nm RMS roughness, in a 10x10 pm region.

[0219] Advantages and Improvements

[0220] Wireless transmission of electrical signals require power amplification to make sure that the transmitted signal is strong enough for the receiver to detect it after traveling long distances. As a result, any wireless communication or imaging application, such as radar and communication systems, require power amplification at high frequencies. The power of the transmitted signals is mainly limited by the transistor technology used in a power amplifier.

[0221] N-Polar GaN deep recess HEMTs have demonstrated world record power densities with high efficiency at W-band. One of the most critical fabrication steps of deep recess N-polar transistors is the selective etching of the GaN cap, which traditionally relies on the inductively-coupled-plasma etching (ICP). ICP tools are expensive, bulky and can only process a limited number of wafers at once. Additionally, ICP selective etches are sensitive to any drift in the conditions of the tool such as gas flow rates, temperature, pressure, plasma density and contamination, which could be detrimental to the device performance and thus cause very significant yield problems. On the other hand, achieving the same task by using wet chemistry is a very attractive and reliable solution for commercialization. Using wet chemistry does not require any complicated tools, it is very inexpensive, and it provides high throughput. Furthermore, the conditions of the etch could be very easily repeated, thereby increasing the process reliability and product yield significantly. Thus, the method of smooth and selective wet N-polar GaN etching described herein is a very promising and useful advancement for commercialization of N-Polar GaN technology.

[0222] Additionally, smooth wet etched recess surface with no plasma damage enables N-Polar GaN Schottky HEMTs with low gate leakage, high gain, high robustness (VT stability) and high efficiency, paving the way for not only inexpensive, reliable and high throughput manufacturing of the emerging N-Polar GaN HEMTs but also performance improvement over the existing dry-etched MIS HEMTs.

[0223] Nomenclature

[0224] The terms “Ill-nitride” as used herein (as well as the terms “Group-Ill nitride”, or “III-N”, or “nitride,” used generally) refer to any alloy composition of the (Sc,Ga,Al,In,B)N semiconductors having the formula ScvGawAlxInyBzN where O^v^l, O^w^l, O^x^l, O^y^l, O^z^l, and v+w+x+y+z=l. These terms are intended to be broadly construed to include respective nitrides of the single species, Sc, Ga, Al, In and B, as well as binary, ternary, quaternary and pentanary compositions of such Group III metal species. Accordingly, it will be appreciated that the discussion of the invention hereinafter in reference to GaN materials is applicable to the formation of various other (Sc,Ga,Al,In,B)N material species. Furthermore, (Sc,Ga,Al,In,B)N materials within the scope of the invention may include minor quantities of dopants and / or other impurity or inclusional materials. The term “N-polar” refers to the (000-1) plane of Ill-nitride materials, so that an N-polar device comprises layers of III-Nitride wherein a top surface, or interface between layers, on which subsequent layers would be grown, comprises the N-polar (000-1) plane.

[0225] Although typical embodiments use N-polar 000-1, e.g., because it is readily available at scale, other N-Polar planes in the GaN crystal or III-Nitride crystal which are applicable can also be used for the Ill-nitride layers of the devices and HEMTs described herein. Miscuts or off-cuts of these planes can also be used.

[0226] References

[0227] The following references are incorporated by reference herein.

[0228] [1] B. Romanczyk et al., "W-band power performance of SiN-passivated N- polar GaN deep recess HEMTs," IEEE Electron Device Lett., vol. 41, no. 3, pp. 349- 352, Mar. 2020, doi: 10.1109 / LED.2020.2967034.

[0229] [2] B. Romanczyk et al., "Demonstration of constant 8 W / mm power density at 10, 30, and 94 GHz in state-of-the-art millimeter- wave N-polar GaN MISHEMTs," IEEE Trans. Electron Devices, vol. 65, no. 1, pp. 45-50, Jan. 2018, doi:

[0230] 10.1109 / TED.2017.2770087.

[0231] [3] E. Akso et al., "First demonstration of four-finger N-polar GaN HEMT exhibiting record 712-mW output power with 31.7% PAE at 94 GHz ," IEEE Microw. Wireless Technol. Lett., early access, Feb. 1, 2023, doi:

[0232] 10.1109 / LMWT.2023.3239532.

[0233] [4] W. Li, et al., "Record RF power performance at 94 GHz from millimeterwave N-polar GaN-on-sapphire deep recess HEMTs," IEEE Trans. Electron Devices, vol. 70, no. 4, pp. 2075-2080, Apr. 2023, doi: 10.1109 / TED. 2023.3240683 .

[0234] [5] S. Wienecke et al., "N-polar GaN cap MISHEMT with record power density exceeding 6.5 W / mm at 94 GHz ," IEEE Electron Device Lett., vol. 38, no. 3, pp. 359-362, Mar. 2017, doi: 10.1109 / LED.2017.2653192. Conclusion

[0235] This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

WHAT IS CLAIMED IS:

1. An N-polar IILN device, comprising: a III -Nitride backbarrier; a III-Nitride channel comprising a 2DEG confined in the channel by the backbarrier; an optional cap layer on the channel; at least one ohmic contact to the channel; a etched recess in the cap and / or into the channel; and a gate electrode in the recess forming a Schottky barrier such that when the device is operated: the gate leakage through the Schottky barrier is less than 0.5mA / mm for VDS of 0.5 V or less, and / or under forward bias at +1 VGS, the gate leakage is less than 0.5 mA / mm for the VDS is 0.5 V or less.

2. The device of claim 1, wherein the etched recess has a smooth surface with the rms surface roughness of the etched surface of the recess is no more than the larger of:2 times larger than the starting surface roughness, and3 nanometer rms roughness in a 10x10 pm region.

3. The device of claim 1, wherein the cap layer comprises at least one of a GaN layer or an AlGaN layer .

4. The device of claim 2, wherein the backbarrier comprises AlxGal-xN and the channel comprises GaN wherein 0.05^x^0.5.

5. The device of claim 1, wherein the gate electrode comprises at least one of platinum, ruthenium, titanium nitride, palladium, nickel, or doped silicon.

6. The device of claim 1, wherein the recess has a varying thickness along a direction in the <1-100> direction, in the <-l - 120> direction, or between the <1 - 100> direction and the <- 1 -120> direction of the III -Nitride, such that the recess contains at least one bottom region with a slope inclined at an angle between 0.5 to 5 degrees with respect to an interface between the backbarrier and the channel.

7. An N-polar III-N device comprising: a III -Nitride backbarrier; a III-Nitride channel comprising a 2DEG confined in the channel by the backbarrier; at least one ohmic contact to the channel; an optional cap; a recess having a varying thickness along a direction in the <1-100> direction, in the<-l - 120> direction, or between the <1 - 100> direction and the <- 1 - 120> direction of the III-Nitride, such that the recess contains at least one bottom region with a slope inclined at an angle between 0.5 to 5 degrees with respect to an interface between the backbarrier and the channel.

8. The device of claim 6 or 7, wherein the recess comprises a second bottom region having a second slope inclined at a second angle between 15 to 50 degrees with respect to the interface.

9. The device of claim 6 or 7 comprising a gate electrode in the recess forming a Schottky barrier with the cap or the channel, wherein current flow between the source contact and the drain contact is along the direction of the varying thickness.

10. The device of claim 9, wherein the current flow direction is within 10 degrees of the <1 -100> direction.

11. The device of claim 9, wherein the varying thickness of the recess is such that the cap and / or the channel has the varying thickness along the direction of current flow to obtain a threshold voltage varying over the gate width and / or gate length, with components in the gate width direction and the gate length direction12. The device of claim 9, wherein the varying thickness of the recess is such that the gate electrode to 2DEG distance varies along the direction within 10 degrees of perpendicular to current flow direction and such that the HEMT operation is linear, which is defined by the ratio of the third order derivative to the first order derivative of the drain current with respect to gate-to-source voltage ( gm3 / gml) of less than 0.05 (VA-2) over a drain current range covering a range >=10% of the maximum saturated drain current.

13. The device of claim 9, wherein the varying thickness of the recess is such that the gate electrode to 2DEG distance varies along the direction within 10 degrees of current flow direction so that the threshold voltage at the drain and source are different14. The device of claim 1 or 7 wherein the device is a transistor wherein the gate electrode has a gate length of 5 nm-5000 nm.

15. A method of etching of N-polar III-N, comprising:(a) performing a first etch step on N-polar III-N using a first etchant to form etched N-polar III-Nitride;(b) removing the first etchant from the etched N-polar III-N;(c) performing a second etch step on the etched N-polar III-N using a wet etchant to form an etched surface; and(d) removing the wet etchant from the etched surface.

16. The method of claim 15 further comprising using the first etchant to remove at least Inm of the N-polar III-N and wherein the rms surface roughness of the etched surface is no more than the larger of2 times larger than the starting surface roughness, and 3nm rms roughness over a 10x10 pm area of the etched surface.

17. The method of claim 15, wherein the first etchant comprises an acid.

18. The method of claim 15, the first etch step self terminates at an etch depth19. The method of claim 15 wherein the wet etchant comprises at least one ofHCl or HNO3 acid.

20. The method of claim 15 wherein the N-polar nitride comprises a top GaN layer that is only partially etched by using only step (a) and (b) or by timing a duration of steps (a)-(d).

21. The method of claim 19 wherein: the N-polar Nitride comprises a top III-Nitride layer on top of an etch stop layer,steps (a)-(d) completely etch the top Nitride layer stopping on or in the etch stop layer; and in step (c), an etch rate of the etch stop layer is less than 1 / 10thof the etch rate of the top Nitride layer .

22. The method of claim 21 wherein the top III-Nitride layer comprises less Al than the etch stop layer.

23. The method of claim 15, wherein: the N-polar III-N comprises a top Nitride layer on an etch stop layer on a bottom III-Nitride layer , the method further comprising: performing steps (a)-(d) to remove the etch stop layer and etch into the bottom III-Nitride layer, and repeating step (a) so that the first etchant comprising citric acid etches the etch stop layer.

24. A method of etching an N-polar structure comprising or consisting of a first GaN layer on an AlGaN layer on a second GaN layer , the method comprising using citric acid to etch through the first GaN layer, the AlGaN layer, and a portion of the second GaN layer. .

25. The device of claim 1 comprising a HEMT manufactured using the method claim 14 wherein the gate electrode comprises at least one of platinum, ruthenium, titanium nitride, palladium, nickel, or doped silicon.

26. The device of claim 1 comprising a transistor, wherein the cap on either the source side or drain side or both are thinned using citric acid to create equal or unequal thickness of the access region in the source and drain regions wholly or in part after depositing the gate electrode using gate metallization.

27. The device of claim 1 manufactured using the method of claim 16 using the wet etchant comprising citric acid, wherein the etched surface is smoother and has less damage than the recess that has been completely dry etched.

28. The method of claim 15, wherein the first etching step improves smoothness and reduces surface roughness of the etched surface as compared to wet etching comprising a single step using HC1, or HN03 or their mixture (HC1:HNO3 with or without H2O).

29. A device manufactured using the method of claim 15.

30. A method of etching of N-polar Ill-nitride, comprising: performing a first wet etch step on N-polar Ill-nitride using citric acid to form etched III-Nitride; removing the citric acid from the etched III-Nitride; performing a second wet etch step using HC1 and HNO3 and H2O to form an etched surface; and removing the HC1, HNO3, and the H2O from the etched surface.

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