System and method for bootstrapping a double data rate (DDR) error control code (ECC) during system bootup

Abstract

A method for bootstrapping memory system initialization of error correction code (ECC) regions during system bootup is described. The method includes dividing a memory subsystem into subsystem memory fragments. The method also includes initializing, using a last-level-cache coprocessor (LCP), a first subsystem memory fragment of the subsystem memory fragments to provide a first ECC region. The method further includes booting a system with the first ECC region of the memory subsystem. The method also includes initializing, using the LCP, remaining ones of the subsystem memory fragments during the booting to enable a second ECC region of the memory subsystem.

Description

SYSTEM AND METHOD FOR BOOTSTRAPPING A DOUBLE DATA RATE (DDR) ERROR CONTROL CODE (ECC) DURING SYSTEM BOOTUPCROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application claims priority to India Patent Application No. 202341081563, filed on November 30, 2023, and titled “SYSTEM AND METHOD FOR BOOTSTRAPPING A DOUBLE DATA RATE (DDR) ERROR CONTROL CODE (ECC) DURING SYSTEM BOOTUP,” the disclosure of which is expressly incorporated by reference in its entirety.BACKGROUNDField

[0002] Aspects of the present disclosure relate to system bootup, and in particular, to a system and method for bootstrapping double data rate (DDR) error control codes (ECCs) during system bootup.Background

[0003] Vehicle or automotive control systems may be subject to more stringent electrical operational requirements. This is because errors in such vehicle or automotive control systems may result in severe injury or death to humans occupying associated vehicles, as well as humans, animals, and property that may collide with such vehicles. Such stringent electrical operational requirements may address system redundancy, greater resistance to electrical and software faults, and improved monitoring of such systems, to name a few issues. In particular, automotive control systems utilize error control codes (ECCs) for providing a critical layer of error detection and correction capability' within a memory subsystem. Once initialized, the ECCs operate by identify ing and rectifying single-bit errors, while also reporting the occurrence of double-bit errors. This emphasis on ECC initialization aligns with the automotive industry's commitment to safety and reliability.

[0004] In modem automotive chipsets, an amount of time consumed during a bootup process is of importance. A boot time may refer to an amount of time specified for a device to be operable for running applications after a power ON trigger. In particular,the amount of time consumed during the bootup process (e.g.. “boot time7’) is a key performance indicator (KPI) of these automotive chipsets. As a result, achieving a fast boot time for automotive chipsets has become a factor that directly impacts the abi 1 i ty to initiate early feature initializations. Unfortunately, ECC initialization during bootup of automotive chipsets has increased the boot time. As a result, a system and method for bootstrapping double data rate (DDR) error control codes (ECCs) during system bootup is desired.SUMMARY

[0005] A method for bootstrapping memory system initialization of error correction code (ECC) regions during system bootup is described. The method includes dividing a memory subsystem into subsystem memory fragments. The method also includes initializing, using a last-level-cache coprocessor (LCP), a first subsystem memory fragment of the subsystem memory' fragments to provide a first ECC region. The method further includes booting a system with the first ECC region of the memory subsystem. The method also includes initializing, using the LCP. remaining ones of the subsystem memory fragments during the booting to enable a second ECC region of the memory subsystem.

[0006] A non-transitory computer-readable medium having program code recorded thereon for bootstrapping memory system initialization of error correction code (ECC) regions during system bootup is described. The program code is executed by a processor. The non-transitory computer-readable medium includes program code to divide a memory subsystem into a plurality of subsystem memory fragments. The non- transitory computer-readable medium also includes program code to initialize, using a last-level-cache coprocessor (LCP), a first subsystem memory fragment of the plurality of subsystem memory fragments to provide a first ECC region. The non-transitory computer-readable medium further includes program code to boot the system with the first ECC region of the memory subsystem. The non-transitory computer-readable medium also includes program code to initialize, using the LCP, remaining ones of the plurality of subsystem memory' fragments during the booting to enable a second ECC region of the memory' subsystem.

[0007] This has outlined, broadly, the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood.Additional features and advantages of the present disclosure will be described below. It should be appreciated by those skilled in the art that this present disclosure may be readily utilized as a basis for modifying or designing other structures for conducting the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the present disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

[0009] FIGURE 1 illustrates an example implementation of a host system-on-chip (SoC), which is configured for bootstrapping memory subsystem initialization of error correction code (ECC) regions during system bootup, in accordance with various aspects of the present disclosure.

[0010] FIGURES 2A and 2B are block diagrams further illustrating the system-on-chip (SoC) of FIGURE 1, including a last-level-cache coprocessor (LCP) configured for bootstrapping an error correction code (ECC) initialization in a memory subsystem during system bootup, according to various aspects of the present disclosure.

[0011] FIGURE 3 is a block diagram further illustrating bootstrapping error correction code (ECC) initialization in a memory subsystem during system bootup of FIGURES 2A and 2B, according to various aspects of the present disclosure.

[0012] FIGURE 4 is a timing diagram further illustrating bootstrapping error correction code (ECC) initialization in a memory subsystem during system bootup, according to various aspects of the present disclosure.

[0013] FIGURES 5A and 5B illustrate a modification to bootstrapping error correction code (ECC) initialization in a memory subsystem during system bootup, according to various aspects of the present disclosure.

[0014] FIGURE 6 is a process flow diagram illustrating a method for bootstrapping memory subsystem initialization of error correction code (ECC) regions during system bootup, according to various aspects of the present disclosure.

[0015] FIGURE 7 is a block diagram showing an exemplary wireless communications system in which a configuration of the disclosure may be advantageously employed.

[0016] FIGURE 8 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component according to one configuration.DETAILED DESCRIPTION

[0017] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. It will be apparent, however, to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0018] As described herein, the use of the term “and / or” is intended to represent an “inclusive OR,” and the use of the term “or” is intended to represent an “exclusive OR.” As described herein, the term “exemplary” used throughout this description means “serving as an example, instance, or illustration.” and should not necessarily be construed as preferred or advantageous over other exemplary configurations. As described herein, the term “coupled” used throughout this description means “connected, whether directly or indirectly through interv ening connections (e.g., a switch), electrical, mechanical, or otherwise,” and is not necessarily limited to physical connections. Additionally, the connections can be such that the objects are permanently connected or releasably connected. The connections can be through switches. As described herein, the term “proximate” used throughout this description means“adjacent, very near, next to. or close tor’ As described herein, the term “on’7used throughout this description means '‘directly on” in some configurations, and ‘'indirectly on” in other configurations. It will be understood that the term “layer” includes film and is not construed as indicating a vertical or horizontal thickness unless otherwise stated. As described, the term “substrate” may refer to a substrate of a diced wafer or may refer to a substrate of a wafer that is not diced. Similarly, the terms “chip” and “die” may be used interchangeably.

[0019] Vehicle or automotive control systems may be subject to more stringent electrical operational requirements. This is because errors in such vehicle or automotive control systems may result in severe injury' or death to humans occupying associated vehicles, as well as humans, animals, and property that may collide with such vehicles. Such stringent electrical operational requirements may address system redundancy, greater resistance to electrical and software faults, and improved monitoring of such systems, to name a few issues. In particular, automotive control systems utilize error control codes (ECCs) for providing a critical layer of error detection and correction capability within a memory' subsystem. Once initialized, the ECCs operate by identifying and rectifying single-bit errors, while also reporting the occurrence of double-bit errors. This emphasis on ECC initialization aligns with the automotive industry’s commitment to safety and reliability.

[0020] Additionally, memory is a vital component for automotive control systems. For example, an automotive control system may integrate memory as part of an application processor, such as a system-on-chip (SoC) including a central processing unit (CPU) and a neural signal processing unit (NPU). Successful operation of some automotive control systems depends on the availability of higher-capacity and loyv-latency memory’ solutions for scalability of CPU / NPU workload. Cache memory is a chip-based computer component that operates as a temporary storage area for expediting data retrieval by the CPU / NPU. In particular, the cache memory' is typically integrated directly into the CPU / NPU chip or placed on a separate chip that has a separate bus interconnect with the CPU / NPU. In practice, double data rate (DDR) dynamic randomaccess memory (DRAM) may operate as cache memory, such as a last-level cache (LLC) of a memory subsystem.

[0021] These automotive control systems may be implemented using an automotive chipset. In modem automotive chipsets, an amount of time consumed during a bootup process is of importance. In particular, the amount of time consumed during the bootup process (‘‘boot time’') is a key performance indicator (KPI) of these automotive chipsets. As a result, achieving a fast boot time for automotive chipsets has become a factor that directly impacts the ability to initiate early feature initializations. Unfortunately, ECC initialization of the memory subsystem during bootup of automotive chipsets has increased the boot time. As a result, a system and method for bootstrapping memory subsystem initialization of error control code (ECC) regions during system bootup is desired.

[0022] Various aspects of the present disclosure are directed to a system and method for bootstrapping memory subsystem initialization of error control code (ECC) regions during system bootup. A method includes dividing a memory subsystem into multiple subsystem memory fragments. The method also includes initializing, using a last-level- cache coprocessor (LCP), a first subsystem memory' fragment of the multiple subsystem memory' fragments to provide a first ECC region. The method further includes booting a system using the first ECC region of the memory subsystem. Additionally, the method includes initializing, using the LCP, remaining ones of the subsystem memory fragments during the booting to enable a second ECC region of the memory subsystem.

[0023] FIGURE 1 illustrates an example implementation of a host system-on-chip (SoC) 100, which is configured for bootstrapping memory' subsystem initialization of error control code (ECC) regions during system bootup, in accordance with various aspects of the present disclosure. The host SoC 100 includes processing blocks tailored to specific functions, such as a connectivity block 110. The connectivity block 110 may include sixth generation (6G), connectivity fifth generation (5G) new radio (NR) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity7, USB connectivity7, Bluetooth® connectivity7, Secure Digital (SD) connectivity, and the like.

[0024] In this configuration, the host SoC 100 includes various processing units that support multi-threaded operation. For the configuration shown in FIGURE 1, the host SoC 100 includes a multi-core central processing unit (CPU) 102. a graphics processor unit (GPU) 104, a digital signal processor (DSP) 106, and a neural processor unit(NPU) / neural signal processor (NSP) 108. The host SoC 100 may also include a sensor processor 114, image signal processors (ISPs) 116, a navigation module 120, which may include a global positioning system, and a memory' 118. The multi-core CPU 102, the GPU 104, the DSP 106, the NPU / NSP 108, and the multimedia engine 112 support various functions such as video, audio, graphics, gaming, artificial networks, and the like. Each processor core of the multi-core CPU 102 may be a reduced instruction set computing (RISC) machine, an advanced RISC machine (ARM), a microprocessor, or some other type of processor. The NPU / NSP 108 may be based on an ARM instruction set.

[0025] The SoC 100 may include a set of subsystems (not shown) to perform various operations in accordance with the design specification for the SoC 100. For example, in the case of automotive control, the set of subsystems may include semi-autonomous or autonomous driving subsystems (e.g., advanced driver assistance systems (ADAS)), such as forward collision warning (FCW), lane departure warning (LDW), blind spot detection (BSD) subsystems (e.g., ADAS level “0” subsystems); adaptive cruise control (ACC) and lane keep assist (LKA) subsystems (e.g., ADAS level “1” subsystems); ACC with lane keeping and traffic jam assist subsystems (e.g., ADAS level '’2” subsystems); highway autopilot and traffic jam pilot subsystems (e.g., ADAS level “3” subsystems); full highway autopilot and full urban autopilot subsystems (e.g., ADAS level “4” subsystems); and robo-taxi / shuttles and autonomous delivery fleet subsystems (e.g., ADAS levelL‘5” subsystems).

[0026] In modem automotive chipsets, an amount of time consumed during a bootup process is of importance. In particular, the amount of time consumed during the bootup process ("‘boot time”) is a key performance indicator (KPI) of these automotive chipsets. As a result, achieving a fast boot time for automotive chipsets has become a factor that directly impacts the ability to initiate early feature initializations. Unfortunately, ECC initialization of the memory subsystem during bootup of automotive chipsets has increased the boot time. As a result, a system and method for bootstrapping memory subsystem initialization of error control code (ECC) regions during system bootup is desired.

[0027] FIGURES 2A and 2B are block diagrams further illustrating the system-on-chip(SoC) of FIGURE 1, including a last-level-cache coprocessor (LCP) configured forbootstrapping an error correction code (ECC) initialization in a memon' subsystem during system bootup, according to various aspects of the present disclosure. As shown in FIGURE 2A, an SoC 200 includes a processor 202 (e.g., the CPU 102 of FIGURE 1), a last-level cache controller (LLCC) 240 having a last-level-cache coprocessor (LCP) 250, a memory controller (MC) 230. and a memory subsystem 220 (e.g., double data rate (DDR) dynamic random-access memory (DRAM)). In this example, the SoC 200 is shown during a CPU bootup process 204. In various aspects of the present disclosure, the LCP 250 of the LLCC 240 operates in parallel with the CPU bootup process 204 to provide an ECC initialization path 206.

[0028] In various aspects of the present disclosure, the memory subsystem 220 is divided into multiple subsystem memory fragments (e.g., 222, 224, 226, and 228). Once the memory’ subsystem is divided, the CPU bootup process 204 is delayed until a first subsystem memory fragment 222 (e.g., FragO shown as ECC Imt) is initialized. Once the first subsystem memory fragment 222 is initialized, the CPU 202 uses the first subsystem memory’ fragment 222 to perform the CPU bootup process 204. In various aspects of the present disclosure, the LCP 250 performs a zero initialization by performing a zeroing operation on a memory range associated with a second subsystem memory fragment 224 (e.g., Fragl) in parallel with the CPU bootup process 204. In this example, the various subsystem memory’ fragments (e.g., 222, 224, 226, and 228) are defined based on memory’ ranges of the memory subsystem 220 from programming registers (not shown) of the LLCC 240. Additionally, zero initialization of the multiple subsystem memory fragments (e.g., 222. 224. 226, and 228) is performed using, for example, a direct memory access (DMA) controller (not shown) of the LLCC 240.

[0029] FIGURE 2B illustrates a next step 260 of the ECC initialization path 206. according to various aspects of the present disclosure. FIGURE 2B illustrates the ECC initialization path 206 follow ing zero initialization of the second subsystem memory fragment 224 (e.g., Fragl), which is added to the memory’ subsystem 220. In this example, the ECC initialization path 206 continues with the zero initialization of the third subsystem memory fragment 226 (e.g.. Frag2), and is completed following zero initialization of the fourth subsystem memory fragment 228 (e.g., Frag3), which is added to the memory’ subsystem 220. Zero initialization of a memory’ range associated with the subsystem memory fragments of the memory subsystem 220 through the ECCinitialization path 206. in parallel with the CPU bootup process 204, is further illustrated in FIGURE 3.

[0030] FIGURE 3 is a block diagram 300 further illustrating bootstrapping error correction code (ECC) initialization in a memory subsystem 320 during system bootup of FIGURES 2A and 2B, according to various aspects of the present disclosure. As shown in FIGURE 3, bootstrapping memory' subsystem initialization of ECC regions during system bootup begins with dividing the memory subsystem 320 into a first memory fragment 322. a second memory fragment 324. and a third memory fragment 326. Initially, at block 302, the CPU 202 is in a central processing unit (CPU) idle state because the CPU 202 needs initial memory to begin a bootup process.

[0031] At process block 310, the LCP 250 scrubs the first memory fragment 322, during which time the system and the CPU 202 are idle at block 302. Once the first memory fragment 322 is initialized, the CPU 202 is activated at process block 330. At process block 340, the CPU 202 begins the system bootup process using the initialized, first memory fragment 322. Additionally, at process block 342. the LCP 250 selects the second memory fragment 324 and performs zero initialization on the second memoryfragment 324 to scrub the second memory fragment 324. Once the zero initialization is completed at process block 342, at process block 350, the initialized, second memoryfragment 324 is added to the system memory-.

[0032] As shown in FIGURE 3, the LCP 250 uses an interrupt mechanism once zero initialization of a memory fragment is complete to communicate completion of the initialization to an operating system (OS) of the CPU 202. In response, the OS of the CPU 202 uses a hotplug operation to add the initialized memory- fragment (e.g., the initialized, first memory fragment 322 and the second memory fragment 324) into a growing memory- pool of the memory subsystem 320. Once added to the memory pool of the memory subsystem 320, at process block 350, the CPU 202 utilizes the initialized, first memory fragment 322 and the second memory fragment 324. Additionally, at process block 352, the LCP 250 selects the third memory fragment 326 and performs zero initialization on the third memory- fragment 326 to scrub the third memory- fragment 326. Once the zero initialization is completed at process block 352, at process block 360, the initialized, third memory fragment 326 is added to the systemmemory to complete ECC initialization of the memory subsystem 320, as further described in FIGURE 4.

[0033] FIGURE 4 is a timing diagram further illustrating bootstrapping error correction code (ECC) initialization in a memory subsystem during system bootup, according to various aspects of the present disclosure. As shown in FIGURE 4, a system activation timing diagram 400 begins at time TO with a pre- rimary bootloader (PBL) boot (PrePBLBoot) stage 402. The PrePBLBoot) stage 402 is followed by a reset and a primary’ bootloader (PBL) stage 404 at time Tl, during which a boot time 450 begins. Following the PBL stage 404, the system activation timing diagram 400 is modified to support bootstrapping memory subsystem initialization of error correction code (ECC) regions.

[0034] In various aspects of the present disclosure, bootstrapping of ECC region initialization is supported by splitting ECC regions of a memory subsystem into a first ECC region 420 and a second ECC region 430. In this example, the first ECC region 420 is specified to load an application image (e.g.. a software (SW) image) during a secondary bootloader (SBL) stage 410 by a secondary bootloader (SBL). Additionally, the second ECC region 430 is specified by the high-level operating system (HLOS) for use during subsequent stages of the bootup. In this example, system bootup is delayed until zero initialization of the first ECC region 420 is completed. Once completed, ECC initialization of the second ECC region 430 is performed in parallel with a bootup flow for the second ECC region 430, which is specified by the HLOS for use during subsequent stages of the bootup.

[0035] As shown in FIGURE 4, zero initialization of the second ECC region 430 is initiated during the SBL stage 410 but does not complete until a trust zone (TZ) stage 440 of the system bootup process. That is, initialization of the second ECC region 430 involves waiting for the completion status at the conclusion of the TZ stage 440. This example shown in FIGURE 4 of a reference test device having twenty-four (24) gigabytes (GB) is used in which fifteen (15) GB are ECC enabled regions.Additionally, the first ECC region 420 has a size of two (2) GB, and zero initialization of the first ECC region 420 is performed during an initial phase of the SBL stage 410. As noted, zero initialization of the first ECC region 420 blocks the initiation of thesystem bootup until the initialization completes, because the first ECC region 420 is specified for loading application images.

[0036] In this example, the second ECC region 430 is sized at thirteen (13) GB (= 15 GB - 2 GB) and zero initialization is triggered during a subsequent phase of the SBL stage 410 until completion at an end of the TZ stage 440. Beneficially, parallel system bootup and zero initialization of the second ECC region 430 reduces the boot time 450, which terminates at an end of an operating system (QNX) stage 460. In particular, although the TZ stage 440 is stretched by T4 - T3 milliseconds (ms) (e.g., ~ 14 ms), an execution time of the SBL stage 410 (e.g., T3-T2 ms) is significantly reduced. In this example, the execution time of the SBL stage 410 is significantly reduced by hundreds of milliseconds, for a total savings of hundreds of millisecond (e.g., three hundred (300) ms). Additionally, a total execution time until completion of the TZ stage 440 (e g., T4- T0 ms) is reduced by hundreds of milliseconds as compared to a previous execution time of nine hundred and four (904), for a substantial total savings (e.g., two hundred and sixteen (216) ms).

[0037] FIGURES 5A and 5B illustrate a modification to bootstrapping error correction code (ECC) initialization in a memory subsystem during system bootup, according to various aspects of the present disclosure. As shown in FIGURE 5A, a boot flow process 500 begins at block 502, with a power management integrated circuit (PMIC) built-in-self-test (BIST) power on (PON) of non-volatile storage (e.g., embedded multimedia card (eMMC) storage / solid-state drive (SSD) storage / universal flash storage (U)), including clock initialization. Following the non-volatile storage initialization, at block 504, a netw ork-on-chip (GEMNOC) initialization is performed. Following the GEMNOC initialization, at block 506, a last-level-cache controller (LLCC) boot and initialization is performed. Additionally, at block 508, an LLCC co-processor (LCP) boot and initialization is performed. The boot flow process 500 further includes a memory controller boot and initialization at block 510, a memory' subsystem physical layer (DDR PHY) boot and initialization at block 512, and a memory subsystem (e g., DDR DRAM) boot and initialization at block 514.

[0038] As shown in FIGURE 2, the LCP 250 may include a scrubber for performing zero-initialization of ECC regions as part of a DDR ECC initialization. For example, FIGURE 5B is a block diagram illustrating a DDR memory space 550, which is dividedinto a DDR ECC protected region 560, an ECC non-protected region 570, and an ECC syndrome data region 580. Conventional DDR ECC initialization involves an address region and attribute configuration, followed by an ECC region and ECC syndrome initialization, which consumes a significant amount of time due to the gigabytes of the DDR memory space 550. In particular, the ECC region and ECC syndrome initialization involves zero-initialization of the DDR ECC protected region 560 using the scrubber of the LCP 250, as shown in FIGURE 2.

[0039] During the zero-initialization of the DDR ECC protected region 560, the ECC syndrome data is computed and written to ECC syndrome data region 580 of the DDR memory space 550 reserved for ECC syndrome data. In practice, ECC syndrome data describes the cause of the error and the ECC syndrome data region 580 is populated bywriting a known pattern to the DDR ECC protected region 560. Additionally, a data ECC check is performed against the ECC syndrome data region 580 when reads are initiated. In this example, the writes to the DDR ECC protected region 560 creates / changes the ECC syndrome data region 580.

[0040] During a conventional boot, a first set of DDR writes is performed as part of the zero-initialization of the DDR ECC protected region 560. Subsequently, a second set of DDR writes is performed during copy of a large software image (e.g., GBs in size) from the non-volatile storage (e.g., eMMC / SSD / universal flash storage (UFS)) to the DDR. In various aspects of the present disclosure, DDR writes performed during copying of the SW image from the non-volatile storage to DDR are used to populate the ECC syndrome data region 580 for the DDR ECC protected region 560. In these aspects of the present disclosure, the software image copy from the non-volatile storage to the DRAM is performed as part of the initialization of the DDR ECC protected region 560 and ECC syndrome data region 580. In this example, the DDR writes initiated due to the SW image copy from the non-volatile storage to the DDR are used to compute and write to the ECC syndrome data region 580 of the DDR memory space 550 reserved for ECC syndrome data. Beneficially, combining the write to the DDR may provide a significant reduction (e.g., six (6) or more seconds) of the total boot time.

[0041] Various aspects of the present disclosure are directed to reducing boot time by parallelizing ECC initialization with data memory copying from non-volatile storage to DDR. These aspects of the present disclosure provide a solution to boot time reductionby introducing a memoir copy / data write based initialization of the DDR ECC protected region 560 and the ECC syndrome data region 580 to significantly reduce boot time in SoCs with ECC protection enabled on DDR data. The proposed solution can reduce the boot time on a scale of seconds, which can create a substantial impact and put SoC manufactures ahead of the competition by a significant margin. A process for bootstrapping memory subsystem initialization of error correction code (ECC) regions during system bootup is shown, for example, in FIGURE 6.

[0042] FIGURE 6 is a process flow diagram illustrating a method 600 for bootstrapping memory subsystem initialization of error correction code (ECC) regions during system bootup, according to various aspects of the present disclosure. The method 600 begins at block 602, in which a memory subsystem is divided into a plurality of subsystem memory fragments. For example, as shown in FIGURE 2, the memory subsystem 220 is divided into multiple subsystem memory fragments (e.g.. 222, 224. 226, and 228). In this example, the various subsystem memory fragments (e.g., 222, 224, 226, and 228) are defined based on memory' ranges of the memory' subsystem 220 from programming registers (not shown) of the LLCC 240.

[0043] At block 604, a first subsystem memory fragment of the plurality of subsystem memory' fragments is initialized to provide a first ECC region using a last-level-cache coprocessor (LCP). For example, as shown in FIGURE 4, bootstrapping of ECC region initialization is supported by splitting ECC regions of the memory’ subsystem into the first ECC region 420 and the second ECC region 430. In this example, the first ECC region 420 is specified to load an application image (e.g., a software (SW) image) during a secondary bootloader (SBL) stage 410 by a secondary’ bootloader (SBL).

[0044] At block 606, the system is booted with the first ECC region of the memory' subsystem. For example, as shown in FIGURE 4, system bootup is delayed until zero initialization of the first ECC region 420 is completed. Once completed, ECC initialization of the second ECC region 430 is performed in parallel with a bootup flow for the second ECC region 430, which is specified by the HLOS for use during subsequent stages of the bootup. As noted, zero initialization of the first ECC region 420 blocks the initiation of the system bootup until the initialization completes, because the first ECC region 420 is specified for loading application images.

[0045] At block 608. remaining ones of the plurality of subsystem memory fragments are initialized using the LCP during the booting to enable a second ECC region of the memory^ subsystem. For example, As shown in FIGURE 4, zero initialization of the second ECC region 430 is initiated during the SBL stage 410 but does not complete until a trust zone (TZ) stage 440 of the system bootup process. That is. initialization of the second ECC region 430 involves waiting for the completion status at the conclusion of the TZ stage 440.

[0046] In some aspects, the method 600 may be performed by the SoC 100 (FIGURE 1). That is, each of the elements of method 600 may, for example, but without limitation, be performed by the SoC 100 or one or more processors (e.g., CPU 102 and / or NPU 130) and / or other components included therein.

[0047] FIGURE 7 is a block diagram showing an exemplary wireless communications system 700 in which an aspect of the disclosure may be advantageously employed. For purposes of illustration, FIGURE 7 shows three remote units 720, 730, and 750, and two base stations 740. It will be recognized that wireless communications systems may have many more remote units and base stations. Remote units 720. 730, and 750 include IC devices 725A, 725C, and 725B that include the disclosed bootstrapping of error correction code (ECC) region initialization. It will be recognized that other devices may also include the disclosed bootstrapping of ECC region initialization, such as the base stations, switching devices, and network equipment. FIGURE 7 shows forward link signals 780 from the base stations 740 to the remote units 720, 730, and 750, and reverse link signals 790 from the remote units 720, 730, and 750 to base stations 740.

[0048] In FIGURE 7, remote unit 720 is show n as a mobile telephone, remote unit 730 is shown as a portable computer, and remote unit 750 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be a mobile phone, a hand-held personal communications systems (PCS) unit, a portable data unit, such as a personal data assistant, a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit, such as meter reading equipment, or other device that stores or retrieves data or computer instructions, or combinations thereof. Although FIGURE 7 illustrates remote units according to aspects of the present disclosure, the disclosure is not limited to theseexemplary illustrated units. Aspects of the present disclosure may be suitably employed in many devices, which include the bootstrapping of ECC region initialization.

[0049] FIGURE 8 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as that of the bootstrapping of error correction code (ECC) region initialization technique disclosed above. A design workstation 800 includes a hard disk 801 containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation 800 also includes a display 802 to facilitate design of a circuit 810 or an integrated circuit (IC) component 812 such as the disclosed bootstrapping of ECC region initialization technique. A storage medium 804 is provided for tangibly storing the design of the circuit 810 or the IC component 812 (e.g., the memory' of the bootstrapping of ECC region initialization). The design of the circuit 810 or the IC component 812 may be stored on the storage medium 804 in a file format such as GDSII or GERBER. The storage medium 804 may be a CD-ROM, DVD, hard disk, flash memory', or other appropriate device. Furthermore, the design workstation 800 includes a drive apparatus 803 for accepting input from or writing output to the storage medium 804.

[0050] Data recorded on the storage medium 804 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium 804 facilitates the design of the circuit 810 or the IC component 812 by decreasing the number of processes for designing semiconductor wafers.

[0051] Implementation examples are described in the following numbered clauses:1. A method for bootstrapping memory system initialization of error correction code (ECC) regions during system bootup, the method comprising: dividing a memory subsystem into a plurality of subsystem memory' fragments; initializing, using a last-level-cache coprocessor (LCP), a first subsystem memory' fragment of the plurality' of subsystem memory fragments to provide a first ECC region;booting a system with the first ECC region of the memory subsystem; and initializing, using the LCP, remaining ones of the plurality of subsystem memon fragments during the booting to enable a second ECC region of the memory subsystem.2. The method of clause 1, in which initializing the first subsystem memory fragment is performed during a central processing unit (CPU) idle state.3. The method of any of clauses 1 or 2, in which dividing the memory subsystem comprises programming registers of a last-level cache controller (LLCC) according to a memory range of the plurality of subsystem memory fragments.4. The method of any of clauses 1-3, in which initializing the first subsystem memory fragment comprises: performing, using a direct memory' access (DMA) controller, a zeroing operation on a memory range associated with the first subsystem memory fragment to provide the first ECC region; and issuing an interrupt once the zeroing operation on the memory range associated with the first subsystem memory fragment is complete.5. The method of any of clauses 1-4, further comprising: performing a hotplug operation to add the first ECC region to a memory pool of the memory subsystem; and performing a hotplug operation to add the second ECC region to the memory pool of the memory' subsystem.6. The method of any of clauses 1 -5, in which initializing the remaining ones of the plurality of subsystem memory' fragments comprises: performing, using a direct memory access (DMA) controller, a zeroing operation on a memory range associated with the remaining ones of the plurality of subsystem memory fragments to provide the second ECC region; and issuing an interrupt once the zeroing operation on the memory7range associated with the remaining ones of the plurality of subsystem memory' fragments is complete.7. The method of any of clauses 1-6, in which booting comprises loading, using a secondary bootloader (SBL), an application image using the first ECC region.8. The method of any of clauses 1-8, in which booting is delayed until initializing of the first subsystem memory fragment is complete.9. The method of any of clauses 1-9, in which initializing the remaining ones of the plurality of subsystem memory fragments occurs during a secondary bootloader (SBT) stage and completes during a trust zone (TZ) stage of the system bootup.10. The method of any of clauses 1-9, in which initializing the remaining ones of the plurality of subsystem memory' fragments in performed in parallel with copying a software image from non-volatile storage to the memory subsystem.11. A non-transitory computer-readable medium having program code recorded thereon for bootstrapping memory system initialization of error correction code (ECC) regions during system bootup, the program code being executed by a processor and comprising: program code to divide a memory subsystem into a plurality of subsystem memory fragments; program code to initialize, using a last-level-cache coprocessor (LCP), a first subsystem memory' fragment of the plurality' of subsystem memory' fragments to provide a first ECC region; program code to boot the system with the first ECC region of the memory subsystem; and program code to initialize, using the LCP, remaining ones of the plurality' of subsystem memory fragments during the booting to enable a second ECC region of the memory subsystem.12. The non-transitory computer-readable medium of clause 11, in which the program code to initialize the first subsystem memory fragment is performed during a central processing unit (CPU) idle state.13. The non-transitory computer-readable medium of any of clauses 11 or 12, in which the program code to divide the memory' subsystem comprises program code to program registers of a last-level cache controller (LLCC) according to a memory range of the plurality of subsystem memory fragments.14. The non-transitory computer-readable medium of any of clauses 1 1-13. in which the program code to initialize the first subsystem memory fragment comprises: program code to perform, using a direct memory' access (DMA) controller, a zeroing operation on a memory' range associated with the first subsystem memory' fragment to provide the first ECC region; and program code to issue an interrupt once the zeroing operation on the memory range associated with the first subsystem memory fragment is complete.15. The non-transitory computer-readable medium of any of clauses 11-14, further comprising: program code to perform ahotplug operation to add the first ECC region to a memory' pool of the memory subsystem; and program code to perform a hotplug operation to add the second ECC region to the memory pool of the memory subsystem.16. The non-transitory' computer-readable medium of any of clauses 11-15, in which the program code to initialize the remaining ones of the plurality’ of subsystem memory fragments comprises: program code to perform, using a direct memory' access (DMA) controller, a zeroing operation on a memory' range associated with the remaining ones of the plurality' of subsy stem memory' fragments to provide the second ECC region; and program code to issue an intermpt once the zeroing operation on the memory range associated with the remaining ones of the plurality of subsystem memory fragments is complete.17. The non-transitory computer-readable medium of any of clauses 11-16, in which the program code to boot comprises program code to load, using a secondary bootloader (SBL), an application image using the first ECC region.18. The non-transitory computer-readable medium of any of clauses 11-17, in which the program code to boot is delayed until the program code to initialize the first subsystem memory fragment is complete.19. The non-transitory computer-readable medium of any of clauses 11-18, in which the program code to initialize the remaining ones of the plurality' of subsystemmemory fragments occurs during a secondary bootloader (SBL) stage and completes during a trust zone (TZ) stage of the system bootup.20. The non-transitory computer-readable medium of any of clauses 11-19, in which the program code to initialize the remaining ones of the plurality of subsystem memory fragments in performed in parallel with copying a software image from nonvolatile storage to the memory subsystem.

[0052] For a firmware and / or software implementation, the methodologies may be implemented with modules (e g., procedures, functions, etc.) that perform the functions described herein. A machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described herein. For example, software codes may be stored in a memory and executed by a processor unit. Memory may be implemented within the processor unit or external to the processor unit. As used herein, the term “memory” refers to types of long term, short term, volatile, nonvolatile, or other memory7and is not limited to a particular type of memory or number of memories, or type of media upon which memory is stored.

[0053] If implemented in firmware and / or software, the functions may be stored as one or more instructions or code on a non-transitory computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium may be an available medium that can be accessed by a computer. By way of example, and not limitation, such computer- readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray® disc, where disks usually reproduce data magnetically, yvhile discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0054] In addition to storage on a non-transitory computer-readable medium, instructions and / or data may be provided as signals on transmission media included in acommunications apparatus. For example, a communications apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

[0055] Although the present disclosure and its advantages have been described in detail, various changes, substitutions, and alterations can be made herein without departing from the technology of the disclosure as defined by the appended claims. For example, relational terms, such as “above’7and “below” are used with respect to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. Additionally, if oriented sideways, above, and below may refer to sides of a substrate or electronic device. Moreover, the scope of the present application is not intended to be limited to the configurations of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform the same function or achieve the same result as the corresponding configurations described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

[0056] Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0057] The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with a general- purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general- purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0058] The steps of a method or algorithm described in connection with the disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

[0059] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

CLAIMSWHAT IS CLAIMED IS:

1. A method for bootstrapping memory system initialization of error correction code (ECC) regions during system bootup, the method comprising: dividing a memory subsystem into a plurality7of subsystem memory' fragments; initializing, using a last-level-cache coprocessor (LCP), a first subsystem memory fragment of the plurality of subsystem memory fragments to provide a first ECC region; booting a system with the first ECC region of the memory subsystem; and initializing, using the LCP, remaining ones of the plurality of subsystem memory fragments during the booting to enable a second ECC region of the memory subsystem.

2. The method of claim 1 , in which initializing the first subsystem memory7fragment is performed during a central processing unit (CPU) idle state.

3. The method of claim 1, in which dividing the memoiy subsystem comprises programming registers of a last-level cache controller (LLCC) according to a memory range of the plurality of subsystem memory fragments.

4. The method of claim 1 , in which initializing the first subsystem memory7fragment comprises: performing, using a direct memory access (DMA) controller, a zeroing operation on a memory range associated with the first subsystem memory fragment to provide the first ECC region; and issuing an interrupt once the zeroing operation on the memory' range associated with the first subsystem memory' fragment is complete.

5. The method of claim 1, further comprising: performing a hotplug operation to add the first ECC region to a memory7pool of the memory subsystem; and performing a hotplug operation to add the second ECC region to the memory pool of the memory' subsystem.

6. The method of claim 1. in which initializing the remaining ones of the plurality of subsystem memory fragments comprises: performing, using a direct memory' access (DMA) controller, a zeroing operation on a memory range associated with the remaining ones of the plurality of subsystem memory fragments to provide the second ECC region: and issuing an interrupt once the zeroing operation on the memory’ range associated with the remaining ones of the plurality of subsystem memory' fragments is complete.

7. The method of claim 1, in which booting comprises loading, using a secondary’ bootloader (SBL). an application image using the first ECC region.

8. The method of claim 1. in which booting is delayed until initializing of the first subsystem memory fragment is complete.

9. The method of claim 1, in which initializing the remaining ones of the plurality’ of subsystem memory' fragments occurs during a secondary’ bootloader (SBL) stage and completes during a trust zone (TZ) stage of the system bootup.

10. The method of claim 1. in which initializing the remaining ones of the plurality of subsystem memory' fragments in performed in parallel with copying a software image from non-volatile storage to the memory subsystem.

11. A non-transitory computer-readable medium having program code recorded thereon for bootstrapping memory system initialization of error correction code (ECC) regions during system bootup, the program code being executed by a processor and comprising: program code to divide a memory’ subsystem into a plurality’ of subsystem memory' fragments; program code to initialize, using a last-level-cache coprocessor (LCP), a first subsystem memory’ fragment of the plurality of subsystem memory fragments to provide a first ECC region; program code to boot the system with the first ECC region of the memory subsystem; andprogram code to initialize, using the LCP, remaining ones of the plurality of subsystem memory fragments during the booting to enable a second ECC region of the memory subsystem.

12. The non-transitory computer-readable medium of claim 11, in which the program code to initialize the first subsystem memory fragment is performed during a central processing unit (CPU) idle state.

13. The non-transitory computer-readable medium of claim 11, in which the program code to divide the memory subsystem comprises program code to program registers of a last-level cache controller (LLCC) according to a memory range of the plurality of subsystem memory’ fragments.

14. The non-transitory computer-readable medium of claim 11, in which the program code to initialize the first subsystem memory7fragment comprises: program code to perform, using a direct memory’ access (DMA) controller, a zeroing operation on a memory range associated with the first subsystem memoryfragment to provide the first ECC region; and program code to issue an interrupt once the zeroing operation on the memory range associated with the first subsystem memory7fragment is complete.

15. The non-transitory7computer-readable medium of claim 11, further comprising: program code to perform a hotplug operation to add the first ECC region to a memory pool of the memory7subsystem; and program code to perform a hotplug operation to add the second ECC region to the memory7pool of the memory subsystem.

16. The non-transitory computer-readable medium of claim 11, in which the program code to initialize the remaining ones of the plurality of subsystem memory7fragments comprises: program code to perform, using a direct memory access (DMA) controller, a zeroing operation on a memory7range associated with the remaining ones of the plurality of subsystem memory7fragments to provide the second ECC region; andprogram code to issue an interrupt once the zeroing operation on the memory range associated with the remaining ones of the plurality of subsystem memory fragments is complete.

17. The non-transitory computer-readable medium of claim 11, in which the program code to boot comprises program code to load, using a secondary bootloader (SBL), an application image using the first ECC region.

18. The non-transitory computer-readable medium of claim 11, in which the program code to boot is delayed until the program code to initialize the first subsystem memory fragment is complete.

19. The non-transitory computer-readable medium of claim 11, in which the program code to initialize the remaining ones of the plurality of subsystem memory' fragments occurs during a secondary' bootloader (SBL) stage and completes during a trust zone (TZ) stage of the system bootup.

20. The non-transitory computer-readable medium of claim 11, in which the program code to initialize the remaining ones of the plurality of subsystem memory’ fragments in performed in parallel with copying a software image from non-volatile storage to the memory subsystem.

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