Display substrate and display device

Abstract

The present application discloses a display substrate and a display device. The display substrate comprises a substrate, an insulating layer structure, a semiconductor structure, and a metal layer structure; the insulating layer structure is located on the substrate; the semiconductor structure is located in the insulating layer structure; the metal layer structure is located in the insulating layer structure; the metal layer structure is connected to the semiconductor structure; the metal layer structure comprises at least one metal layer; and the at least one metal layer is configured to be connected to a grounding jig of an external device, the metal layer has a first orthographic projection on the substrate, the semiconductor structure has a second orthographic projection on the substrate, and the first orthographic projection covers the second orthographic projection.

Description

Display substrate and display device

[0001] This application claims priority to Chinese patent application No. 202311684943.6 filed on December 7, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of display substrates, and in particular to a display substrate and a display device. Background Art

[0003] As Micro LED (Micro Light Emitting Diode) chips shrink in size, the precision requirements for solder bumps are becoming increasingly stringent. Electron beam evaporation (EBV) can achieve high-precision Micro LED solder bump production. However, poor grounding performance of display substrates can cause electrical drift in thin-film transistors (TFTs) within the substrates during EBV, leading to display anomalies. SUMMARY OF THE INVENTION

[0004] The present application provides a display substrate and a display device, which can solve the problem of display abnormality in the display device caused by poor grounding performance of the display substrate.

[0005] In a first aspect, the present application provides a display substrate, comprising:

[0006] substrate;

[0007] an insulating layer structure, the insulating layer structure being located on the substrate;

[0008] a semiconductor structure, wherein the semiconductor structure is located in the insulating layer structure;

[0009] a metal layer structure, the metal layer structure being connected to the insulating layer structure, the metal layer structure being electrically connected to the semiconductor structure, and the metal layer structure comprising at least one metal layer;

[0010] At least one of the metal layers is configured as a grounding fixture connected to an external device, and the metal layer has a first orthographic projection on the substrate, and the semiconductor structure has a second orthographic projection on the substrate, and the first orthographic projection covers the second orthographic projection.

[0011] In a second aspect, the present application further provides a display device, comprising a display substrate as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a schematic diagram of a longitudinal cross-sectional structure of a display substrate provided in an embodiment of the present application;

[0013] FIG2 is a schematic diagram of a longitudinal cross-sectional structure of another display substrate provided in an embodiment of the present application;

[0014] FIG3 is a schematic diagram of a longitudinal cross-sectional structure of another display substrate provided in an embodiment of the present application;

[0015] FIG4 is a schematic diagram of a longitudinal cross-sectional structure of another display substrate provided in an embodiment of the present application;

[0016] FIG5 is a schematic top view of a shielding metal layer in a display substrate according to an embodiment of the present application;

[0017] FIG6 is a schematic top view of the structure of another shielding metal layer in a display substrate provided by an embodiment of the present application;

[0018] FIG7 is a schematic diagram of a connection structure between a display substrate and an electron beam evaporation device provided in an embodiment of the present application.

[0019] The reference numerals are as follows:

[0020] 100, substrate; 200, semiconductor structure; 210, source layer; 220, active layer; 230, gate layer; 240, connection part; 300, insulation layer structure; 310, first insulation layer; 320, second insulation layer; 330, third insulation layer; 340, fourth insulation layer; 350, fifth insulation layer; 400, dielectric layer; 500, grounding fixture; 600, metal layer structure; 610, source and drain layer; 611, first connection end; 612, second connection end; 620, shielding metal layer; 621, first shielding layer; 622, second shielding layer; 630, external metal layer; 700, photoresist block. Modes for Carrying Out the Invention

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0022] The embodiments of the present application further disclose, in combination with the first aspect, that the metal layer structure includes a shielding metal layer, the shielding metal layer is located in the insulating layer structure, and the metal layer orthographic projection of the shielding metal layer on the substrate includes the first orthographic projection.

[0023] The embodiments of the present application further disclose, in combination with the first aspect, that the shielding metal layer is a mesh structure.

[0024] The embodiment of the present application further discloses, in combination with the first aspect, that the metal layer structure further comprises an external metal layer, the external metal layer is located on a side of the insulating layer structure away from the substrate, and the metal layer orthographic projection of the external metal layer on the substrate includes the first orthographic projection;

[0025] The external metal layer includes a first connecting portion and a second connecting portion, the first connecting portion is configured to be connected to a grounding fixture of an external device, and the second connecting portion is configured to be connected to an electrode of the light-emitting unit.

[0026] The embodiment of the present application further discloses in combination with the first aspect that at least a portion of the structure of the external metal layer is located at the edge of the display substrate.

[0027] The embodiments of the present application further disclose, in combination with the first aspect, that the metal layer structure also includes a source-drain layer, and the source-drain layer includes a first connection end and a second connection end, the first connection end is not connected to the second connection end, the first connection end and the second connection end are respectively connected to the semiconductor structure, and the shielding metal layer is connected to the second connection end.

[0028] The embodiments of the present application further disclose, in combination with the first aspect, that a dielectric layer is provided between the substrate and the insulating layer structure, the semiconductor structure is provided on a side of the dielectric layer away from the substrate, and the semiconductor structure includes an active layer, a gate layer, a source layer and a connecting portion.

[0029] The embodiments of the present application further disclose, in combination with the first aspect, that the insulating layer structure includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer stacked in sequence; and the first insulating layer is connected to the dielectric layer.

[0030] The embodiment of the present application further discloses, in combination with the first aspect, that the shielding metal layer includes a first shielding layer and a second shielding layer;

[0031] The source-drain electrode layer is located in the third insulating layer, and the source-drain electrode layer passes through the second insulating layer and the first insulating layer and is connected to the connecting portion;

[0032] The first shielding layer is located in the fourth insulating layer, and the first shielding layer passes through the third insulating layer and is connected to the source and drain layer;

[0033] The second shielding layer is located in the fifth insulating layer, and the second shielding layer passes through the fourth insulating layer and is connected to the first shielding layer;

[0034] The external metal layer is located on a side of the fifth insulating layer away from the fourth insulating layer, and the external metal layer penetrates the fourth insulating layer and is connected to the second shielding layer;

[0035] A photoresist block is provided on a side of the fifth insulating layer away from the fourth insulating layer, and the photoresist block is spaced apart from the external metal layer.

[0036] One of the above technical solutions has the following advantages or beneficial effects:

[0037] Compared with the prior art, the present application provides a display substrate, comprising: a substrate, an insulating layer structure, a semiconductor structure and a metal layer structure. The insulating layer structure is located on the substrate. The semiconductor structure is located in the insulating layer structure. The metal layer structure is connected to the insulating layer structure, and the metal layer structure is electrically connected to the semiconductor structure, and the metal layer structure includes at least one metal layer. Among them, at least one metal layer is configured as a grounding fixture for connecting an external device, and the metal layer has a first orthographic projection on the substrate, and the semiconductor structure has a second orthographic projection on the substrate, and the first orthographic projection covers the second orthographic projection. The display substrate provided by the present application completely covers the semiconductor structure in the vertical direction through the metal layer structure provided, so that the metal layer structure can form an electrostatic field to protect the semiconductor structure after being grounded, thereby preventing the semiconductor structure from being affected by the external electric field during the preparation process and causing electrical drift. Therefore, the metal layer structure of the present application utilizes the electrostatic shielding principle to improve the display effect of the display device.

[0038] The relevant technical personnel of this application have noticed that due to the lack of a grounding design specifically for electron beam evaporation in existing Micro LED display substrates, the grounding of the electron beam evaporation equipment is connected to the process edge of the substrate (non-patterned area) or the non-conductive organic photoresist during electron beam evaporation. In the initial stage of electron beam evaporation, the evaporated metal cannot form an effective grounding connection with the grounding of the electron beam evaporation equipment, and cannot effectively extract the charge or play an electric field shielding role. This application uses a grounding design for the display substrate, and when the display substrate is assembled on the evaporation jig before evaporation, the grounding design of the display substrate is connected to the grounding of the electron beam evaporation equipment, so that the grounding design of the display substrate can effectively shield the external electric field, thereby effectively improving the electrical drift problem of the display substrate TFT caused by poor grounding in the early stage of electron beam evaporation.

[0039] The specific implementation of this application is described below through examples:

[0040] As shown in Figure 1, an embodiment of the present application provides a display substrate comprising: a substrate 100, an insulating layer structure 300, a semiconductor structure 200, and a metal layer structure 600. The insulating layer structure 300 is located on the substrate 100. The semiconductor structure 200 is located within the insulating layer structure 300. The metal layer structure 600 is connected to the insulating layer structure 300 and electrically connected to the semiconductor structure 200. The metal layer structure 600 includes at least one metal layer. The at least one metal layer is configured to serve as a grounding fixture 500 for connecting to an external device. The metal layer has a first orthographic projection on the substrate 100. The semiconductor structure 200 has a second orthographic projection on the substrate 100. The first orthographic projection overlaps the second orthographic projection. Specifically, the insulating layer structure 300, the semiconductor structure 200, and the metal layer structure 600 are formed on the provided substrate 100 through processes such as cleaning, film formation, photolithography, etching, and impurity removal. Among them, the insulating layer structure 300 and the metal layer structure 600 both include a multi-layer structure. The metal layer structure 600 and the insulating layer structure 300 can be stacked on each other as needed, and it is ensured that the metal layer of one of the metal layer structures 600 can completely cover the semiconductor structure 200 in the vertical direction. In other words, the second orthographic projection of the semiconductor structure 200 on the substrate 100 is completely located on the first orthographic projection of the metal layer structure 600 on the substrate 100. This allows the metal layer structure 600 to form an electrostatic field to protect the semiconductor structure 200 after being grounded to the grounding fixture 500 of the external device, thereby preventing the semiconductor structure 200 from being affected by the external electric field during the preparation process and causing electrical drift, thereby improving the display effect of the display device.

[0041] As shown in Figure 1, in an embodiment of the present application, the metal layer structure 600 includes a shielding metal layer 620. The shielding metal layer 620 is located in the insulating layer structure 300. The metal layer orthographic projection of the shielding metal layer 620 on the substrate 100 includes a first orthographic projection. Specifically, the shielding metal layer 620 is connected to the semiconductor structure 200. The shielding metal layer 620 has a first orthographic projection on the substrate 100. In other words, the shielding metal layer 620 completely covers the semiconductor structure 200 in the vertical direction. Therefore, the shielding metal layer 620 shields the external electric field during the preparation process of the semiconductor structure 200, thereby playing a protective role, thereby preventing the semiconductor structure 200 from being affected by the external electric field during the preparation process and causing electrical drift.

[0042] As shown in Figure 5, in an embodiment of the present application, the shielding metal layer 620 is a mesh structure. Specifically, when the metal layer orthographic projection of the shielding metal layer 620 on the substrate 100 includes a first orthographic projection, the shielding metal layer 620 includes a plurality of longitudinal metal sheets extending in the longitudinal direction and transverse metal sheets extending in the transverse direction. The longitudinal metal sheets and the transverse metal sheets are interwoven to form intersections. In order for the shielding metal layer 620 to completely cover the semiconductor structure 200 in the vertical direction, it is necessary to ensure that the longitudinal metal sheets or the transverse metal sheets have sufficient width to cover the semiconductor structure 200. This ensures that the shielding metal layer 620 can shield the external electric field, thereby playing a protective role.

[0043] As shown in Figures 1 to 3, in an embodiment of the present application, the metal layer structure 600 further includes an external metal layer 630. The external metal layer 630 is located on the side of the insulating layer structure 300 away from the substrate 100. The orthographic projection of the external metal layer 630 on the substrate 100 includes a first orthographic projection. The external metal layer 630 includes a first connecting portion and a second connecting portion. The first connecting portion is configured to connect to a grounding fixture of an external device. The second connecting portion is configured to connect to an electrode of a light-emitting unit. Specifically, the external metal layer 630 is located on the outermost layer of the display substrate 100 away from the substrate 100. The external metal layer 630 is connected to the semiconductor structure 200 by sequentially connecting to the shielding metal layer 620 and the source / drain layer 610. The first connecting portion of the external metal layer 630 connects to the grounding fixture 500 of the external device, thereby grounding the semiconductor structure 200. The external metal layer 630 is provided with a port at the edge of the display substrate for providing a ground connection for an external device. The width of the port is 5 to 10 mm. The second connecting portion is used to connect to the electrode of the light-emitting unit to provide the required current or voltage to the light-emitting unit, thereby driving the light-emitting unit to emit light.

[0044] As shown in Figures 5, 6 and 7, the external metal layer 630 has at least a partial structure located at the edge of the display substrate. Specifically, the external metal layer 630 is used to facilitate connection with the ground terminal of the external device when preparing the display substrate. By connecting the ground terminal of the external device, the shielding metal layer 620 can form an electrostatic field, thereby protecting the semiconductor structure 200 and preventing the electric field generated by the external device during operation from affecting the semiconductor structure 200 and causing electrical drift. Therefore, the external metal layer 630 of the present application provides a better connection terminal for grounding for the external device, thereby utilizing the electrostatic shielding principle to improve the display effect of the display device.

[0045] As shown in Figures 5 and 6, in some embodiments of the present application, when the metal layer orthographic projection of the shielding metal layer 620 on the substrate 100 includes a first orthographic projection, the shielding metal layer 620 includes a plurality of metal sheets distributed in the horizontal and vertical directions. The plurality of metal sheets are staggered to form a mesh structure, and are sufficient to cover the semiconductor structure 200 in the vertical direction (as shown in Figure 5). Alternatively, the semiconductor structure 200 is covered by a plurality of metal sheets, and at the same time, metal strips with smaller widths are used to connect each other in the vertical and horizontal directions to form a mesh structure (as shown in Figure 6), so that the plurality of metal sheets form an integral structure. Connecting the metal sheets through metal strips can ensure that the display substrate has a larger aperture ratio, thereby reducing the parasitic capacitance of the display substrate, and further ensuring that the shielding metal layer 620 can shield the external electric field, thereby playing a protective role.

[0046] As shown in Figures 1 to 3, in an embodiment of the present application, the metal layer structure 600 further includes a source-drain layer 610. The source-drain layer 610 includes a first connection terminal 611 and a second connection terminal 612. The first connection terminal 611 and the second connection terminal 612 are not connected. The first connection terminal 611 and the second connection terminal 612 are respectively connected to the semiconductor structure 200. The shielding metal layer 620 is connected to the second connection terminal 612. Specifically, the first connection terminal 611 is connected to the semiconductor structure 200 and provides current to the semiconductor structure 200. The second connection terminal 612 is connected to the semiconductor structure 200 for grounding the semiconductor structure 200. The shielding metal layer 620 passes through the insulating layer structure 300 and is connected to the second connection terminal 612.

[0047] As shown in Figures 1 to 3, in an embodiment of the present application, a dielectric layer 400 is provided between the substrate 100 and the insulating layer structure 300. The semiconductor structure 200 is provided on a side of the dielectric layer 400 away from the substrate 100. The semiconductor structure 200 includes an active layer 220, a gate layer 230, a source layer 210, and a connecting portion 240. Specifically, the dielectric layer 400 is used to provide an intermediary for the semiconductor structure 200, thereby enabling the semiconductor structure 200 to be better attached to the dielectric layer 400 and providing adhesion for the subsequent insulating layer structure 300. The dielectric layer 400 may be made of silicon nitride, and the semiconductor structure 200 may be a P-type semiconductor or an N-type semiconductor.

[0048] As shown in Figures 1 to 3, in an embodiment of the present application, the insulating layer structure 300 includes a first insulating layer 310, a second insulating layer 320, a third insulating layer 330, a fourth insulating layer 340, and a fifth insulating layer 350 stacked in sequence. The first insulating layer 310 is connected to the dielectric layer 400. Specifically, the first insulating layer 310, the second insulating layer 320, the third insulating layer 330, the fourth insulating layer 340, and the fifth insulating layer 350 are sequentially formed on the dielectric layer 400 through processes such as cleaning, film formation, photolithography, etching, and impurity removal. Before preparing the first insulating layer 310, the active layer 220, the source layer 210, and the connecting portion 240 in the semiconductor structure 200 are first formed, and then the first insulating layer 310 is deposited, and the gate layer 230 is formed on the first insulating layer 310. The second insulating layer 320 is deposited on the gate layer 230. The first insulating layer 310 , the second insulating layer 320 , the third insulating layer 330 , the fourth insulating layer 340 and the fifth insulating layer 350 may be made of materials including silicides such as silicon nitride and silicon oxide that can perform an insulating function.

[0049] As shown in Figures 1 to 3, in an embodiment of the present application, the shielding metal layer 620 includes a first shielding layer 621 and a second shielding layer 622. The source-drain electrode layer 610 is located in the third insulating layer 330. The source-drain electrode layer 610 penetrates the second insulating layer 320 and the first insulating layer 310 and is connected to the connection portion 240. The first shielding layer 621 is located in the fourth insulating layer 340, penetrates the third insulating layer 330 and is connected to the source-drain electrode layer 610. The second shielding layer 622 is located in the fifth insulating layer 350, penetrates the fourth insulating layer 340 and is connected to the first shielding layer 621. The external metal layer 630 is located on the side of the fifth insulating layer 350 away from the fourth insulating layer 340, penetrates the fourth insulating layer 340 and is connected to the second shielding layer 622. A photoblock 700 is provided on the side of the fifth insulating layer 350 away from the fourth insulating layer 340, and is spaced apart from the external metal layer 630. Specifically, after the second insulating layer 320 is formed through a deposition process, a first connection hole extending to the semiconductor structure 200 is formed on the second insulating layer 320 through an etching process. A source-drain electrode layer 610 is formed through a deposition process on the second insulating layer 320, and the source-drain electrode layer 610 is connected to the semiconductor structure 200 through the first connection hole. A third insulating layer 330 is formed through a deposition process on the source-drain electrode layer 610, and a second connection hole extending to the source-drain electrode layer 610 is formed through an etching process. A first shielding layer 621 is formed through a deposition process on the third insulating layer 330, and the first shielding layer 621 is connected to the source-drain electrode layer 610 through the second connection hole. A fourth insulating layer 340 is formed through a deposition process on the first shielding layer 621, and a third connection hole extending to the first shielding layer 621 is formed through an etching process. A second shielding layer 622 is formed through a deposition process on the fourth insulating layer 340, and the second shielding layer 622 is connected to the first shielding layer 621 through the third connection hole. A fifth insulating layer 350 is formed on the second shielding layer 622 through a deposition process, and a fourth connection hole extending to the second shielding layer 622 is formed through an etching process. An external metal layer 630 is also formed on the fifth insulating layer 350 through a deposition process, and the external metal layer 630 is connected to the second shielding layer 622 through the fourth connection hole. Multiple slots extending to the fifth insulating layer 350 are formed in the external metal layer 630 through an etching process, and photoresist blocks 700 are formed in the slots through a deposition process. The photoresist blocks 700 are connected to the fifth insulating layer 350 and spaced apart from the external metal layer 630.

[0050] Based on the same inventive concept, as shown in Figures 4 and 7, embodiments of the present application provide a method for fabricating solder bumps on a display substrate, comprising: an electron beam evaporation apparatus including a grounding jig 500. The grounding jig 500 is connected to a metal layer structure 600 in the display substrate provided in any of the above-described embodiments. The electron beam evaporation apparatus is used to perform evaporation on the display substrate to form solder bumps. Specifically, the electron beam evaporation apparatus uses a high-energy electron beam to heat a material, causing it to melt and evaporate. The evaporated material is deposited on the surface of the display substrate, forming a thin film. During electron beam evaporation, the display substrate is placed in a vacuum environment, referred to as an evaporation chamber or deposition chamber. The chamber contains an electron beam source and an evaporation source. The electron beam source generates a high-energy electron beam. This electron beam is focused and accelerated, then aimed at the material in the evaporation source. When the electron beam strikes the evaporation source, its energy heats the material to a sufficiently high temperature, causing it to melt and evaporate. The evaporated material forms vapor, which is deposited on the surface of the display substrate. After cooling, the surface of the display substrate recondenses to form a thin film. This film can have desired properties, such as hardness and corrosion resistance. Throughout the entire fabrication process, the evaporation source, the power and focus of the electron beam, and the material deposition rate must be controlled to achieve optimal film quality and uniformity.

[0051] Based on the same inventive concept, an embodiment of the present application provides a display device, which includes a display substrate as provided in any one of the above items, or the display substrate in the display device adopts the solder bump preparation method provided in the above items to obtain solder bumps.

[0052] The above is a detailed introduction to a display substrate and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display substrate, comprising: substrate; an insulating layer structure, wherein the insulating layer structure is located on the substrate; a semiconductor structure, wherein the semiconductor structure is located in the insulating layer structure; and A metal layer structure, wherein the metal layer structure is connected to the insulating layer structure, the metal layer structure is electrically connected to the semiconductor structure, and the metal layer structure includes at least one metal layer; Among them, at least one layer of the metal layer is configured as a grounding fixture connected to an external device, and the metal layer has a first orthographic projection on the substrate, and the semiconductor structure has a second orthographic projection on the substrate, and the first orthographic projection covers the second orthographic projection.

2. The display substrate according to claim 1, wherein: The metal layer structure comprises a shielding metal layer, the shielding metal layer is located in the insulating layer structure, and the metal layer orthographic projection of the shielding metal layer on the substrate comprises the first orthographic projection.

3. The display substrate according to claim 2, wherein: The shielding metal layer is a mesh structure.

4. The display substrate according to claim 3, wherein: The shielding metal layer includes a plurality of longitudinal metal sheets extending in a longitudinal direction and transverse metal sheets extending in a transverse direction, and the longitudinal metal sheets and the transverse metal sheets are interwoven with each other to form intersections.

5. The display substrate according to claim 2, wherein: The metal layer structure further includes an external metal layer, the external metal layer is located on a side of the insulating layer structure away from the substrate, and the metal layer orthographic projection of the external metal layer on the substrate includes the first orthographic projection; The external metal layer includes a first connection portion and a second connection portion, the first connection portion is configured to be connected to a grounding fixture of an external device, and the second connection portion is configured to be connected to an electrode of the light-emitting unit.

6. The display substrate according to claim 5, wherein: At least a part of the structure of the external metal layer is located at the edge of the display substrate.

7. The display substrate according to claim 6, wherein: The external metal layer is provided with a port at the edge of the display substrate to provide a ground connection for external equipment.

8. The display substrate according to claim 7, wherein: The width of the port is in the range of 5 mm to 10 mm.

9. The display substrate according to claim 5, wherein: The metal layer structure also includes a source-drain layer, which includes a first connection end and a second connection end, wherein the first connection end is not connected to the second connection end, the first connection end and the second connection end are respectively connected to the semiconductor structure, and the shielding metal layer is connected to the second connection end.

10. The display substrate according to claim 9, wherein: The first connection terminal is configured to provide current to the semiconductor structure, and the second connection terminal is configured to ground the semiconductor structure; The shielding metal layer passes through the insulating layer structure and is connected to the second connecting end.

11. The display substrate according to claim 9, wherein: A dielectric layer is arranged between the substrate and the insulating layer structure, the semiconductor structure is arranged on a side of the dielectric layer away from the substrate, and the semiconductor structure comprises an active layer, a gate layer, a source layer and a connecting portion.

12. The display substrate according to claim 11, wherein: The insulating layer structure comprises a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer which are stacked in sequence; the first insulating layer is connected to the dielectric layer.

13. The display substrate according to claim 12, wherein: The material of the first insulating layer includes at least one of silicon nitride and silicon oxide; The material of the second insulating layer includes at least one of silicon nitride and silicon oxide; The material of the third insulating layer includes at least one of silicon nitride and silicon oxide; The material of the fourth insulating layer includes at least one of silicon nitride and silicon oxide; The material of the fifth insulating layer includes at least one of silicon nitride and silicon oxide; The material of the dielectric layer includes silicon nitride; The semiconductor structure is one of a P-type semiconductor and an N-type semiconductor.

14. The display substrate according to claim 12, wherein: The shielding metal layer includes a first shielding layer and a second shielding layer; The source-drain electrode layer is located in the third insulating layer, and the source-drain electrode layer penetrates the second insulating layer and the first insulating layer and is connected to the connecting portion; The first shielding layer is located in the fourth insulating layer, and the first shielding layer penetrates the third insulating layer and is connected to the source and drain layer; The second shielding layer is located in the fifth insulating layer, and the second shielding layer penetrates the fourth insulating layer and is connected to the first shielding layer; The external metal layer is located at a side of the fifth insulating layer away from the fourth insulating layer, and the external metal layer penetrates the fourth insulating layer and is connected to the second shielding layer; A photoblock is disposed on a side of the fifth insulating layer away from the fourth insulating layer, and the photoblock is spaced apart from the external metal layer.

15. The display substrate according to claim 14, wherein: A first connection hole is formed in the first insulating layer and the second insulating layer, and the source and drain layer is connected to the semiconductor structure through the first connection hole.

16. The display substrate according to claim 14, wherein: A second connection hole is formed in the third insulating layer, and the first shielding layer is connected to the source and drain layer through the second connection hole.

17. The display substrate according to claim 14, wherein: A third connection hole is formed in the fourth insulating layer, and the second shielding layer is connected to the first shielding layer through the third connection hole.

18. The display substrate according to claim 14, wherein: A fourth connection hole is formed in the fifth insulating layer, and the external metal layer is connected to the second shielding layer through the fourth connection hole.

19. The display substrate according to claim 14, wherein: A slot is formed in the external metal layer, the photoresist block is arranged in the slot, the photoresist block is connected to the fifth insulating layer, and the photoresist block is spaced apart from the external metal layer.

20. A display device, comprising the display substrate according to any one of claims 1 to 19.

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