Packaging structure for high bandwidth memory and method for forming same

Abstract

The present invention relates to a packaging structure for a high bandwidth memory (HBM) and a method for forming same. The packaging structure comprises: a silicon substrate provided with cavities; chip stack structures embedded in the silicon substrate, the chip stack structures each comprising a plurality of vertically stacked HBM chips and one or more logic chips; conductive through silicon vias (TSVs) passing through the silicon substrate; and interconnection structures electrically connected to the conductive TSVs and the chip stack structures. According to the packaging structure for an HBM and the method for forming same disclosed by the present invention, the conductive TSVs are manufactured in the silicon substrate to form TSV interposer structures, grooves are etched in the interposer structures, and the stacked HBM chips are embedded in the grooves, thereby improving the functionality and the integration of the TSV interposers; additionally, compared with the mode of welding the HBM chips to the surfaces of the TSV interposers and plastically packaging same, pre-embedding the HBM chips in a silicon-based material can reduce a part of warpage.

Description

A packaging structure of a high bandwidth memory and a forming method thereof Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a packaging structure of a high-bandwidth memory and a forming method thereof. Background Art

[0002] High Bandwidth Memory (HBM) is a type of CPU / GPU memory chip, also known as RAM. HBM consists of multiple DDR chips stacked vertically. These chips are connected to the CPU or GPU via an ultra-fast interconnect called an interposer, or directly to the substrate, creating a large-capacity, high-bitwidth DDR array.

[0003] Typically, HBM is packaged and assembled into a specific module along with CPUs, GPUs, and other components, and then connected to a circuit board. In practical applications, each HBM also requires a logic chip to perform DDR memory management tasks. Traditional HBM packaging typically involves soldering the HBM and logic chip separately onto a substrate for overall packaging, resulting in low packaging efficiency. Furthermore, the HBM is soldered onto the surface of a TSV adapter board and then plastic-sealed, which can lead to severe warping at high temperatures.

[0004] Summary of the Invention

[0005] To solve at least some of the above problems in the prior art, the present invention provides a high-bandwidth memory packaging structure, comprising:

[0006] a silicon substrate having a cavity;

[0007] a chip stack structure embedded in the silicon substrate, the chip stack structure comprising a plurality of vertically stacked high-bandwidth memory chips and one or more logic chips;

[0008] a conductive through-silicon via penetrating the silicon substrate; and

[0009] The interconnect structure has the conductive through silicon via and the chip stacking structure electrically connected.

[0010] Furthermore, a molding material is included, which is filled in the cavity to mold the chip stacking structure.

[0011] Furthermore, it also includes a bump electrically connected to the interconnection structure.

[0012] Furthermore, the high-bandwidth memory chips and the logic chip and the high-bandwidth memory chip in the chip stacking structure are connected via micro-bumps.

[0013] Furthermore, the interconnect structure is located on the first surface of the silicon substrate, and includes a dielectric layer and a redistribution layer located in the dielectric layer, wherein a surface of the redistribution layer is exposed to the dielectric layer.

[0014] Furthermore, it also includes a second redistribution layer, which is located on the second surface of the silicon substrate and is electrically connected to the conductive silicon via. The second surface of the silicon substrate is opposite to the first surface.

[0015] The present invention also provides a method for forming a packaging structure of a high bandwidth memory, comprising:

[0016] Providing a chip stacking structure;

[0017] Fabricating conductive through-silicon vias and grooves on the first side of the silicon substrate, embedding the chip stack structure in the grooves, and filling them with plastic packaging material;

[0018] forming an interconnection structure on the first surface of the silicon substrate, and arranging bumps on the surface of the interconnection structure; and

[0019] The second surface of the silicon substrate is thinned until both the conductive silicon through via and the chip stacking structure are exposed, and the second surface is opposite to the first surface.

[0020] Furthermore, the chip stacking structure includes a plurality of vertically stacked high-bandwidth memory chips and one or more logic chips, and the high-bandwidth memory chips and the logic chip and the high-bandwidth memory chip are connected via micro-bumps.

[0021] Furthermore, the method further includes forming interconnection lines on the second surface of the silicon substrate, wherein the interconnection lines are electrically connected to the conductive silicon through vias.

[0022] Furthermore, the groove is filled with molding material to a first height, the chip stacking structure is placed in the groove, and the groove is filled with molding material again, wherein the sum of the first height and the height of the chip stacking structure is equal to the depth of the groove.

[0023] The present invention has at least the following beneficial effects: (1) The present invention discloses a packaging structure of a high-bandwidth memory and a method for forming the same, wherein a conductive through-silicon via is made in a silicon substrate to form a TSV adapter plate structure, and a groove is etched in the silicon substrate to bury the stacked HBM stacked chips, thereby increasing the functionality and integration of the TSV adapter plate. At the same time, the stacked chips are pre-buried in the silicon-based material, which can reduce some warping compared to welding on the surface of the TSV adapter plate and then plastic-sealing; (2) The silicon substrate and the plastic sealing material are thinned by means of plastic sealing thinning and polishing, which, on the one hand, forms a smoother surface, and on the other hand, releases the stress of the plastic sealing material and the silicon-based adapter plate, thereby alleviating warping. Moreover, thinning to the point where the HBM chip leaks out is beneficial to the heat dissipation of the entire chip; (3) The HBM chip is stacked with the logic chip to improve the integration and reduce the package size. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings depict only typical embodiments of the present invention and are not to be considered as limiting the scope thereof. In the drawings, for clarity, identical or corresponding parts will be represented by the same or similar reference numerals.

[0025] FIG1 is a schematic cross-sectional view showing a packaging structure of a high bandwidth memory according to an embodiment of the present invention; and

[0026] 2 to 8 are schematic diagrams illustrating a process of forming a high bandwidth memory package structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] It should be noted that components in the drawings may be shown exaggerated for illustrative purposes and are not necessarily true to scale.

[0028] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0029] In the present invention, unless otherwise specified, the quantifiers "a" and "an" do not exclude the presence of multiple elements.

[0030] It should also be pointed out that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but a person skilled in the art will understand that under the teachings of the present invention, the required parts or components may be added according to the needs of the specific scenario.

[0031] It should also be pointed out that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the two values ​​are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0032] It should also be noted that in the description of the present invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the present invention. They do not explicitly or implicitly state that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0033] In addition, the embodiments of the present invention describe the process steps in a specific order, but this is only for the convenience of distinguishing the steps, and does not limit the order of the steps. In different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0034] FIG1 is a cross-sectional schematic diagram showing a packaging structure of a high bandwidth memory according to an embodiment of the present invention.

[0035] As shown in FIG1 , a high bandwidth memory package structure includes: a silicon substrate 100 , a chip stacking structure 101 , conductive through silicon vias 102 , an interconnection structure 103 , a molding material 104 , bumps 105 , and interconnection lines 106 .

[0036] Chip stacking structure 101 includes one or more logic chips 1011 and multiple vertically stacked high-bandwidth memory chips 1012. In one embodiment of the present invention, multiple high-bandwidth memory chips are stacked using a vertical 3D TSV stacking process. Each high-bandwidth memory chip can be considered a storage area, and each storage area is connected via microbumps (uBumps). Logic chip 1011 is connected to the stacked high-bandwidth memory chips 1012 using the vertical 3D TSV stacking process. Each chip has a through-silicon via (TSV), and the TSV of one chip is connected to the TSV of another chip via microbumps.

[0037] The silicon substrate 100 has a cavity extending through the silicon substrate 100. The chip stacking structure 101 is located within the cavity of the silicon substrate 100, and the cavity is filled with a molding material 104 to encapsulate the chip stacking structure 101. The front surface of the logic chip 1011 of the chip stacking structure 101 is flush with the first surface of the silicon substrate 100.

[0038] The conductive through silicon via 102 penetrates the silicon substrate 100 .

[0039] Interconnect structure 103 is located on the first surface of silicon substrate 100 and is electrically connected to conductive through silicon vias 102 and logic chip 1011. Interconnect structure 103 includes dielectric layer 1031 and redistribution layer 1032. Redistribution layer 1032 is located in dielectric layer 1031 and has dielectric layer 1031 exposed on its surface.

[0040] The bump 105 is electrically connected to the redistribution layer 1032 of the interconnect structure 103 .

[0041] The interconnection line 106 is located on the second surface of the silicon substrate 100 , which is opposite to the first surface, and is electrically connected to the conductive through silicon via 102 .

[0042] 2 to 8 are schematic diagrams illustrating a process of forming a high bandwidth memory package structure according to an embodiment of the present invention.

[0043] A method for forming a high bandwidth memory package structure includes:

[0044] Step 1, as shown in FIG2 , provides a chip stacking structure 200. Chip stacking structure 200 includes one or more logic chips 2001 and multiple high-bandwidth memory chips 2002. In one embodiment of the present invention, multiple high-bandwidth memory chips are stacked using a vertical 3D TSV stacking process. Each high-bandwidth memory chip can be considered a storage area, and each storage area is connected via microbumps (uBumps). Each chip has a through-silicon via (TSV), and the TSV of one chip is connected to the TSV of another chip via microbumps.

[0045] In step 2, as shown in FIG3 , conductive through-silicon vias 202 and grooves 203 are formed on the first side of the silicon substrate 201. The chip stacking structure 200 is embedded in the grooves 203 and filled with molding compound 208. Specifically, blind holes are etched on the first side of the silicon substrate 201 and filled with metal to form conductive through-silicon vias 202. A groove 203 is then etched on the first side of the silicon substrate 201. The molding compound is then filled into the grooves 203 to a first height. The chip stacking structure 200 is then placed into the grooves 203, with the chip stacking structure 200 not protruding from the first side of the silicon substrate 201. The molding compound is then filled into the grooves 203. The sum of the first height and the height of the chip stacking structure 200 equals the depth of the grooves 203.

[0046] In step 3, as shown in FIG4 , an interconnect structure 204 is formed on the first surface of the silicon substrate 201, and bumps 205 are arranged on the surface of the interconnect structure 204. The redistribution layer 2042 is electrically connected to the chip stacking structure 200 and the conductive silicon vias 202. Specifically, the interconnect structure 204 includes a dielectric layer 2041 and a redistribution layer 2042. The dielectric layer 2041 is first formed on the first surface of the silicon substrate 201, and the dielectric layer 2041 is etched to form a circuit pattern. The circuit pattern is then filled with metal to obtain the redistribution layer 2042. Bumps 205 are arranged on the surface of the redistribution layer 2042.

[0047] In step 4, as shown in FIG5 , the carrier wafer 206 is bonded to the bump 205 through a temporary bonding process.

[0048] In step 5, as shown in FIG6 , the second surface of the silicon substrate 201 is thinned until both the conductive through silicon vias 202 and the chip stacking structure 200 are exposed, and the second surface is opposite to the first surface.

[0049] In step 6, as shown in FIG7 , interconnect lines 207 are formed on the second side of silicon substrate 201. Interconnect lines 207 are electrically connected to conductive through-silicon vias 202. Specifically, a photoresist is deposited on the second side of silicon substrate 201, a circuit pattern is formed through a photolithography process, and metal is filled into the circuit pattern to form interconnect lines 207. Finally, the photoresist is removed.

[0050] In step 7, as shown in FIG8 , the slide 206 is removed.

[0051] Although certain embodiments of the present invention have been described in this application, those skilled in the art will appreciate that these embodiments are provided by way of example only. Numerous variations, alternatives, and modifications will be contemplated by those skilled in the art in light of the teachings of this disclosure without departing from the scope of the present invention. The appended claims are intended to define the scope of the present invention and are intended to encompass methods and structures within the scope of these claims and their equivalents.

Claims

1. A packaging structure of a high bandwidth memory, characterized in that: include: a silicon substrate having a cavity; A chip stacking structure, which is buried in the silicon substrate, the chip stacking structure comprising a plurality of vertically stacked high-bandwidth memory chips and one or more logic chips; A conductive through silicon via, which penetrates the silicon substrate; as well as An interconnection structure, wherein the conductive silicon through via and the chip stacking structure are electrically connected.

2. The packaging structure according to claim 1, characterized in that: Also included is a molding material which is filled in the cavity to mold the chip stacking structure.

3. The packaging structure according to claim 1, characterized in that: Also included is a bump electrically connected to the interconnect structure.

4. The packaging structure according to claim 1, characterized in that: The high-bandwidth memory chips in the chip stacking structure and the logic chip and the high-bandwidth memory chip are connected via micro-bumps.

5. The packaging structure according to claim 1, characterized in that: The interconnect structure is located on the first surface of the silicon substrate, and comprises a dielectric layer and a redistribution layer located in the dielectric layer, wherein a surface of the redistribution layer is exposed from the dielectric layer.

6. The packaging structure according to claim 5, characterized in that: It also includes a second redistribution layer, which is located on the second surface of the silicon substrate and is electrically connected to the conductive silicon through-hole. The second surface of the silicon substrate is opposite to the first surface.

7. A method for forming a packaging structure of a high bandwidth memory, characterized in that: include: Providing a chip stacking structure; Conductive silicon through vias and grooves are made on the first surface of the silicon substrate, and the chip stacking structure is buried in the grooves and filled with plastic packaging material; forming an interconnect structure on the first surface of the silicon substrate, and arranging bumps on the surface of the interconnect structure; as well as The second surface of the silicon substrate is thinned to expose both the conductive silicon through via and the chip stacking structure, the second surface being opposite to the first surface.

8. The forming method according to claim 7, characterized in that: The chip stacking structure includes a plurality of vertically stacked high-bandwidth memory chips and one or more logic chips, and the high-bandwidth memory chips and the logic chip and the high-bandwidth memory chip are connected via micro-bumps.

9. The forming method according to claim 7, characterized in that: The method also includes forming interconnection lines on the second surface of the silicon substrate, wherein the interconnection lines are electrically connected to the conductive silicon through vias.

10. The forming method according to claim 7, characterized in that: The molding material is filled in the groove to a first height, the chip stacking structure is placed in the groove, and the molding material is filled in the groove again, wherein the sum of the first height and the height of the chip stacking structure is equal to the depth of the groove.

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