Interleaving method and communication apparatus

Abstract

The present application provides an interleaving method and a communication apparatus. An encoded bit sequence is interleaved by means of a first indication sequence, the interleaved bit sequence is mapped onto a quadrature amplitude modulation (QAM) symbol, and the QAM symbol is outputted, wherein the first indication sequence is used for indicating the correspondence between M columns of an LDPC base matrix and R energy levels comprised in the QAM symbol. By means of the interleaving method provided in embodiments of the present application, additional protection can be provided to the least reliable bits, thereby improving communication performance.

Description

Interleaving method and communication device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on December 4, 2023, with application number 202311648762.8 and application name “Interleaving Method and Communication Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of channel coding, and more specifically, to an interleaving method in channel coding and a related communication device. Background Art

[0003] The key performance indicator (KPI) for wireless communications is the block error rate (BLER), which is the probability that at least one of all transmitted bits is erroneous. A transmission requires that all bits are correct, so the BLER is primarily determined by the least reliable bits. Existing information bit protection methods do not provide additional protection for these least reliable bits, so the BLER of wireless communications cannot be effectively improved. Summary of the Invention

[0004] The present application provides an interleaving method and a communication device, which can improve the communication performance of wireless communications.

[0005] In a first aspect, an interleaving method is provided, comprising: obtaining an LDPC base matrix, the LDPC base matrix comprising M columns; encoding a first bit sequence according to the LDPC base matrix to obtain a second bit sequence; performing bit interleaving on the second bit sequence according to a first indicator sequence to obtain a third bit sequence, the first indicator sequence being used to indicate a correspondence between the M columns and the R energy levels contained in a QAM symbol, where M and R are positive integers; mapping bits in the third bit sequence to QAM symbols; and outputting the modulated QAM symbols.

[0006] It should be noted that, this application uses the R energy levels contained in the QAM symbol as an example to illustrate the interleaving method of this application, but this application does not limit the above-mentioned first indicator sequence to indicate the correspondence between the above-mentioned M columns and the R energy levels contained in the QAM symbol. The above-mentioned first indicator sequence can also be used to indicate the correspondence between multiple other energy levels and bits. For example, the correspondence between streams (layers) with different reliability levels and bits in the multiple-input multiple-output (MIMO) technology, the correspondence between bits with different reliability levels in cascade coding, etc., can all use the interleaving method provided by this application to correspond to energy levels. Alternatively, the interleaving method provided by this application can also be used for scenarios where multiple technologies are applied simultaneously. For example, the high-order modulation scheme in the MIMO low-energy-level stream can also be corresponded to the energy level and then the interleaving method of this application can be used to correspond energy levels and bits.

[0007] Exemplarily, the M columns are columns corresponding to the lowest code rate supported by the LDPC base matrix or columns corresponding to the highest code rate supported by the LDPC base matrix.

[0008] Through the above method, the bit sequence can be interleaved and mapped according to the first indication sequence, the energy level of the QAM symbol mapped by the bits corresponding to the columns of the LDPC base matrix can be controlled, and the communication performance of wireless communication can be improved.

[0009] With reference to the first aspect, in certain implementations of the first aspect, the first indication sequence may satisfy at least one of the following characteristics:

[0010] The elements in the first indicator sequence correspond one-to-one to the columns of the LDPC base matrix; the number S of elements in the first indicator sequence is the same as the number of M columns excluding punctured columns; the smaller the sequence number of the element in the first indicator sequence, the higher the corresponding energy level.

[0011] Exemplarily, the serial number of the element in the first indicator sequence may also be understood as the position of the element in the first indicator sequence.

[0012] The smaller the serial number of the element in the first indicator sequence, the higher the corresponding energy level. Specifically, the smaller the serial number of the element in the first indicator sequence, the lower the column weight of the column corresponding to the element, and the higher the energy level corresponding to the column corresponding to the element.

[0013] It can be seen that the closer the position of an element in the first indicator sequence is, the higher the energy level of the column corresponding to the element.

[0014] In conjunction with the first aspect, in certain implementations of the first aspect, the first indicator sequence is used to indicate the correspondence between the M columns and the R energy levels included in the QAM symbol, including: the first indicator sequence is used to indicate the correspondence between K intervals and the R energy levels, where K is a positive integer greater than 2. The K intervals are re-divided based on the columns of the M columns.

[0015] For example, the K intervals may be [d1, d2], [d3, d4], ..., [d 2k-5 ,d 2k-4 ]、[d 2k-3 ,d 2k-2 ]、[d 2k-1 ,d 2k ]; among them, [d 2k- 3,d 2k-2 The maximum value d in ] 2k-2 Less than [d 2k-1 ,d 2k ] the minimum value d 2k-1 , and [d 2k-3 ,d 2k-2 The minimum value d in ] 2k-3 Greater than [d 2k-5 ,d 2k-4 The maximum value d in ] 2k-4 ,

[0016] Among them, the first interval [d1, d2] includes M1 column weights of M1 columns, the second interval [d3, d4] includes M2 column weights of M2 columns; ...; the K-2th interval [d 2k-5 ,d 2k-4 ]Including M K-2 M of columns K-2 The K-1th interval [d 2k-3 ,d 2k-2 ]Including M K-1 M of columns K-1 The Kth interval [d 2k-1 ,d 2k ]Including M K M of columns K The M1 columns, the M2 columns, ..., the M K-2 columns, the M K-1 columns, the M K columns belong to the above M columns.

[0017] Specifically, the bits of the columns included in each of the K intervals are mapped to the same energy level of the QAM symbol.

[0018] Optionally, the above K intervals may also be K sets.

[0019] The above method performs bit mapping according to column weight, which can provide additional protection for the least reliable bits and improve communication performance.

[0020] In conjunction with the first aspect, in certain implementations of the first aspect, the first indicator sequence is used to indicate a correspondence between the M columns and the R energy levels included in the QAM symbol, including: the first indicator sequence is used to indicate a correspondence between P sets and the R energy levels, where P is a positive integer greater than 2. The P sets are divided according to types of the M columns, and the types of the M columns include: information columns, core check columns, and extended check columns.

[0021] Exemplarily, the P sets include a first set and / or a second set and / or a third set. For example, the first set includes information columns, the second set includes core check columns, and the third set includes extended check columns; or the first set includes information columns and core check columns, and the second set includes extended check columns.

[0022] Specifically, the bits of the columns included in each of the P sets are mapped to the same energy level of the QAM symbol.

[0023] Optionally, the multiple columns included in the first set, the second set, or the third set in the P sets are arranged in ascending order of column weight. Alternatively, it can be understood that the lower the column weight of the multiple columns included in the first set, the second set, or the third set in the P sets, the higher the corresponding energy at the same energy level of the QAM symbol.

[0024] This approach not only protects information bits, but also ensures that the most important information is always mapped to the highest energy level of the QAM symbol. Furthermore, it can further refine the energy levels corresponding to information bits, providing additional protection for unreliable bits within the information, thereby improving communication performance.

[0025] In combination with the first aspect, in certain implementations of the first aspect, the above-mentioned bit interleaving of the second bit sequence according to the first indicator sequence to obtain the third bit sequence includes: performing a first interleaving on the second bit sequence according to the first indicator sequence to obtain a fourth bit sequence; and performing row-column interleaving on the fourth bit sequence to obtain the above-mentioned third bit sequence.

[0026] Exemplarily, the first interleaving is as follows:

[0027] Assume that the second bit sequence is e, the fourth bit sequence is e1, and e1 and e satisfy the following relationship:

[0028] Where S represents the number of elements in the first indicator sequence, j represents the index of the sequence number of the element contained in the first indicator sequence, s(j) represents the jth element of the first indicator sequence, and Z c is the boost value of the LDPC basis matrix.

[0029] The first interleaving may be performed before or after the second bit sequence is circularly buffered.

[0030] In conjunction with the first aspect, in certain implementations of the first aspect, mapping bits in the third bit sequence to QAM symbols includes: mapping bits corresponding to at least one fourth column in the third bit sequence to a first energy level of the QAM symbol, and mapping bits corresponding to at least one fifth column in the third bit sequence to a second energy level of the QAM symbol, where the at least one fourth column and the at least one fifth column belong to the M columns. The column weight of the at least one fourth column is less than the column weight of the at least one fifth column, and the first energy level is higher than the second energy level.

[0031] Through the above method, the bits of columns with low column weight are mapped to the high energy level of the QAM symbol, and the bits of columns with high column weight are mapped to the low energy level of the QAM symbol, providing additional protection for the least reliable bits, which can reduce the BLER of data transmission and improve wireless communication performance.

[0032] In a second aspect, an interleaving method is provided, which includes: obtaining a first LDPC base matrix, the first LDPC base matrix including M columns, the M columns being divided into K intervals according to a column variable, the column variable being a column weight or a column type of a first submatrix, the column type including an information column, a core check column, and an extended check column, the first submatrix being a partial or complete matrix of the above-mentioned first LDPC base matrix; encoding a first bit sequence according to the first LDPC base matrix to obtain a second bit sequence; performing bit interleaving on the second bit sequence to obtain a third bit sequence; mapping bits in the third bit sequence to QAM symbols; and outputting modulated QAM symbols.

[0033] It should be noted that, this application uses the R energy levels contained in the QAM symbol as an example to illustrate the interleaving method of this application, but this application does not limit the above-mentioned first indicator sequence to indicate the correspondence between the above-mentioned M columns and the R energy levels contained in the QAM symbol. The above-mentioned first indicator sequence can also be used to indicate the correspondence between multiple other energy levels and bits. For example, the correspondence between streams (layers) with different reliability levels and bits in the multiple-input multiple-output (MIMO) technology, the correspondence between bits with different reliability levels in cascade coding, etc., can all use the interleaving method provided by this application to correspond to energy levels. Alternatively, the interleaving method provided by this application can also be used for scenarios where multiple technologies are applied simultaneously. For example, the high-order modulation scheme in the MIMO low-energy-level stream can also be corresponded to the energy level and then the interleaving method of this application can be used to correspond energy levels and bits.

[0034] In combination with the second aspect, in certain implementations of the second aspect, when the above-mentioned column variable is the column weight of the first basis matrix, the K intervals include the first interval and / or the second interval and / or the third interval, the maximum column weight of at least one second column of the second interval is less than the minimum column weight of at least one first column of the first interval, the minimum column weight of at least one second column of the second interval is greater than the maximum column weight of at least one third column of the third interval, the number of columns of any column in the at least one third column is greater than the number of columns of any column in the at least one second column, and the number of columns of any column in the at least one second column is greater than the number of columns of any column in the at least one first column.

[0035] Exemplarily, the smaller the column weight of the K intervals, the higher the corresponding energy level.

[0036] The first sub-matrix is ​​a matrix corresponding to the lowest code rate supported by the first LDPC base matrix or a matrix corresponding to the highest code rate supported by the first LDPC base matrix.

[0037] The column weight of the first LDPC base matrix shown in the above method shows a certain pattern. As the number of columns increases, the column weight decreases. After subsequent bit interleaving and mapping, the energy level of the QAM symbol mapped to the bits corresponding to the columns of the first LDPC base matrix can be controlled, thereby improving the communication performance of wireless communication.

[0038] In combination with the second aspect, in certain implementations of the second aspect, when the above-mentioned column variable is a column type, the above-mentioned K intervals include a first interval and / or a second interval and / or a third interval, and the column weight of at least one column included in the first interval and / or the second interval and / or the third interval decreases as the number of columns increases.

[0039] Exemplarily, the first interval includes an information column, the second interval includes a core check column, and the third interval includes an extended check column; or, the first interval includes an information column and a core check column, and the second interval includes an extended check column.

[0040] In conjunction with the second aspect, in some implementations of the second aspect, the first LDPC base matrix includes N rows, the i-th row of the N rows corresponds to an indicator sequence θ(i),

[0041] When θ(i)>0, it means that when the first LDPC basis matrix is ​​expanded from a high code rate to a low code rate, the i-th row is related to the θ(i)-th row, and the i-th row is obtained by eliminating the θ(i)-th row. In this case, the expansion of the i-th row will not increase the column weight of the columns of the first LDPC basis matrix. When θ(i)=0, it means that when the first LDPC basis matrix is ​​expanded from a high code rate to a low code rate, the i-th row is independent of the other rows of the first LDPC basis matrix. In this case, the expansion of the i-th row will increase the column weight of the columns of the first LDPC basis matrix. The rows of the above-mentioned first submatrix are all rows corresponding to θ(i)=0 in the above-mentioned N rows, and the columns of the above-mentioned first submatrix include information columns and core check columns.

[0042] By using the above method, the column weight of the first submatrix included in the expanded first LDPC base matrix can be quickly calculated, and the first LDPC base matrix that conforms to the above column weight change rule can be reconstructed according to the column weight of the first submatrix.

[0043] Exemplarily, the extended parity check column may be a default column with the lowest column weight. For example, the extended parity check column is located in a region with the largest number of columns in the first LDPC base matrix.

[0044] In conjunction with the second aspect, in certain implementations of the second aspect, the step of performing bit interleaving on the second bit sequence to obtain the third bit sequence includes:

[0045] Assume that the second bit sequence is e, the third bit sequence is f, and f and e satisfy the following relationship:

[0046] Where, E represents the transmission length of the second bit sequence or the third bit sequence, Q m represents the number of bits contained in each modulation symbol, j represents the index of the QAM symbol, and i represents the index of the bit position contained in each QAM symbol.

[0047] The above-mentioned bit interleaving can also be called reverse row-column interleaving.

[0048] In conjunction with the second aspect, in certain implementations of the second aspect, mapping bits in the third bit sequence to QAM symbols includes: mapping bits corresponding to at least one fourth column in the third bit sequence to a first energy level of the QAM symbol, and mapping bits corresponding to at least one fifth column in the third bit sequence to a second energy level of the QAM symbol, where the at least one fourth column and the at least one fifth column belong to the M columns. The column weight of the at least one fourth column is less than the column weight of the at least one fifth column, and the first energy level is higher than the second energy level.

[0049] Through the above method, the bits of the columns with low column weight of the first LDPC basis matrix are mapped to the high energy level of the QAM symbol, and the bits of the columns with high column weight are mapped to the low energy level of the QAM symbol, providing additional protection for the least reliable bits, reducing the BLER of data transmission, and improving wireless communication performance.

[0050] In a third aspect, a communication device is provided, wherein the communication device has the function of implementing the method of the first aspect or the second aspect, or the method in any possible implementation of the first aspect or the second aspect. The function can be implemented by hardware, or by hardware executing corresponding software implementation. The hardware or software includes one or more units corresponding to the above-mentioned functions.

[0051] In a fourth aspect, the present application provides a communication device comprising at least one processor, wherein the at least one processor is coupled to at least one memory, wherein the at least one memory is used to store a computer program or instruction, and the at least one processor is used to call and run the computer program or instruction from the at least one memory, so that the communication device executes the method in the first aspect or any possible implementation thereof, or executes the method in the second aspect or any possible implementation thereof.

[0052] In one example, the communication device described in the third aspect or the fourth aspect may be an encoding device.

[0053] In a fifth aspect, the present application provides a communication device comprising a communication interface and a circuit, wherein the communication interface is configured to receive a first bit sequence to be encoded and input the first bit sequence into the circuit; the circuit encodes and bit-interleaves the first bit sequence based on the interleaving method provided in the present application, and maps a third bit sequence obtained by bit interleaving onto a QAM symbol; the communication interface is further configured to output the modulated QAM symbol. Exemplarily, the communication device in the fifth aspect is an encoding device.

[0054] In a sixth aspect, a communication device is provided, comprising a communication interface and a circuit, wherein the communication interface is configured to receive a QAM symbol to be demodulated and input the QAM symbol to the circuit.

[0055] In a seventh aspect, the present application provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer, the method in the first aspect or any possible implementation thereof is implemented, or the method in the second aspect or any possible implementation thereof is implemented.

[0056] In an eighth aspect, the present application provides a computer program product, comprising computer program code, which, when the computer program code is run on a computer, enables the method in the first aspect or any possible implementation thereof to be implemented, or the method in the second aspect or any possible implementation thereof to be implemented.

[0057] In a ninth aspect, the present application provides a wireless communication system, comprising a communication device as described in any one of the third to sixth aspects, such as an encoding device and / or a decoding device. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] FIG1 is a schematic diagram of an LDPC check matrix H.

[0059] FIG2 is a Tanner graph of an LDPC check matrix H.

[0060] FIG3 is a schematic diagram of the structure of an LDPC base matrix.

[0061] FIG4 is a schematic diagram of the information transmission process.

[0062] FIG5 is an example of information bit protection of LDPC.

[0063] FIG6 is a schematic diagram of a system architecture 100 applicable to an embodiment of the present application.

[0064] FIG7 is a schematic flowchart of the interleaving method 200 provided in this application.

[0065] FIG8 is a schematic diagram of a first indicator sequence provided in this application.

[0066] FIG9 is a schematic diagram of another first indicator sequence provided in this application.

[0067] FIG10 is a schematic diagram of another first indicator sequence provided in this application.

[0068] FIG11 is a schematic flow chart of the communication method 300 provided in this application.

[0069] FIG12 is a schematic diagram of a second LDPC base matrix provided in this application.

[0070] FIG13 is a schematic diagram of another second LDPC base matrix provided in this application.

[0071] FIG14 is a performance simulation comparison diagram of the interleaving method 200, the communication method 300, and the row-column interleaving method provided in this application.

[0072] FIG15 is a schematic structural diagram of a communication device provided in this application.

[0073] FIG16 is a schematic structural diagram of another communication device provided in this application.

[0074] FIG17 is a schematic structural diagram of another communication device provided in this application. DETAILED DESCRIPTION

[0075] The technical solution in this application will be described below with reference to the accompanying drawings.

[0076] In order to facilitate understanding of the solution of this application, the terms involved in this application are first introduced.

[0077] 1. Low-density parity check (LDPC) code

[0078] An LDPC code is a linear block code whose parity check matrix is ​​a sparse matrix. When the code length is long, the number of zero elements in the LDPC parity check matrix far exceeds the number of non-zero elements. In other words, the row and column weights of the parity check matrix are very small compared to the LDPC code length. An LDPC code with an information bit sequence length equal to k and a code length equal to n can be uniquely determined by its parity check matrix or generator matrix. This information bit sequence can be payload information bits or a bit sequence with CRC check bits added, which is not limited in this application.

[0079] In 1981, Tanner represented LDPC codewords using a graph, now called a Tanner graph. There is a one-to-one correspondence between a Tanner graph and a parity check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits, called variable nodes, and the other type is called check nodes, representing check constraints. Each check node represents a check constraint. This is explained below using Figures 1 and 2.

[0080] FIG1 is a schematic diagram of a check matrix H of LDPC.

[0081] In Figure 1, {Vi} represents the set of variable nodes, and {Ci} represents the set of check nodes. Each row of the check matrix H represents a check equation, each corresponding to a check node. Each column represents a codeword bit, each corresponding to a variable node. In Figure 1, there are eight variable nodes and four check nodes. If a codeword bit is included in the corresponding check equation, a line is drawn to connect the variable node and the check node involved, resulting in a Tanner graph.

[0082] FIG2 is a Tanner graph of the LDPC check matrix H.

[0083] As shown in Figure 2, the Tanner graph represents the LDPC parity check matrix. For example, for a parity check matrix H with m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the parity check matrix H, and the m check nodes correspond to the m rows of the parity check matrix H. A cycle in the Tanner graph consists of interconnected vertices. The cycle starts and ends at a vertex in this group and passes through each node only once. The variable nodes in the Tanner graph correspond to each column of the parity check matrix H, that is, to each codeword bit of the LDPC. The check nodes in the Tanner graph correspond to each row of the parity check matrix H, that is, to each check bit of the LDPC. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. For example, if there is a connection between the i-th check node and the j-th variable node, the value of the element (i, j) in the H matrix is ​​1; if there is no connection, the corresponding element is 0. The connection between the variable node and the check node can also be called an edge. There is a connection between the check node and the variable node, which can also be described as: there is a connection relationship between the check node and the variable node.

[0084] 2. Quasi-cyclic low density parity check (QC-LDPC) code

[0085] QC-LDPC code is a type of structured LDPC code. Due to the unique structure of its check matrix, it can be encoded using a simple feedback shift register, reducing the coding complexity of LDPC. When the code length is long, the LDPC check matrix H will be very large, so H is usually represented in blocks: the complete check matrix H is regarded as consisting of multiple Z c ×Z c Specifically, the complete check matrix H can be generated by an indicator matrix H b Indicates that H b Each element in corresponds to a Z c ×Zc Each submatrix can be represented by the number of cyclic shift bits, thus greatly reducing the storage space required for the complete check matrix H. b The elements in can also be called quasi-cyclic (QC) blocks.

[0086] Based on the exponential matrix H b and the expansion factor Z c , the exponential matrix H can be b Expanded to a complete check matrix for encoding or decoding. c (lifting size) may also be referred to as a lifting factor, lifting value, expansion value, expansion coefficient, lifting size, etc., and the description of lifting value is used in this application.

[0087] For example, the exponential matrix H of QC-LDPC b As shown below:

[0088] It can be seen that the exponential matrix H b The size is 4 rows and 24 columns, and the elements Represents the cyclic permutation matrix, i represents the cyclic shift value, where 0≤i≤Z c -1, i is an integer. In addition, the exponential matrix H b The "-1" in represents an all-zero matrix, and "0" represents an identity matrix.

[0089] For example, As shown below:

[0090] It should be noted that the exponential matrix H b In addition to "-1", the zero elements in can also have other representations, such as using "-" or null values ​​to represent an all-zero matrix.

[0091] 3. Non-zero elements and zero elements

[0092] In this application, a zero element in the check matrix indicates that there is no connection between the variable node and the check node, and a non-zero element in the check matrix indicates that there is a connection between the variable node and the check node.

[0093] This application does not limit the specific representation of zero elements and non-zero elements. For example, in the exponential matrix H b In the check matrix H, "-1" can be used to represent a zero element, and "non-negative value" can be used to represent a non-zero element. For another example, in the check matrix H, "0" can be used to represent a zero element, and "1" can be used to represent a non-zero element.

[0094] For ease of description, the LDPC base matrix below uses "0" to represent a zero element and "1" to represent a non-zero element.

[0095] 4. Column weight and row weight

[0096] For a column of a matrix, the column weight can refer to the number of non-zero elements contained in the column. For a row of a matrix, the row weight can refer to the number of non-zero elements contained in the row. For example, as shown in Figure 1, the column weight of the first column of the check matrix H is 2, and the row weight of the first row is 4. For another example, as described above, the exponential matrix H b The first column has a column weight of 4 and the first row has a row weight of 20.

[0097] 5. Basic structure of basis matrix

[0098] As shown in FIG3(a), the base matrix may include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high rate region may include part A and part B shown in FIG3(b), wherein part A corresponds to information bits (or information bits, etc.), part B is a square matrix and corresponds to core parity bits (or core parity bits), and part B may also be a region corresponding to parity columns with column weights greater than 1. The all-zero region may correspond to part C of FIG3(b), which is an all-zero matrix. The incremental redundancy region may correspond to part D of FIG3(b). The raptor-like region may correspond to part E of FIG3(b), which may be a unit matrix corresponding to the parity bits of the low rate extension.

[0099] The base matrix of the LDPC code shown in Figure 3 employs a "raptor-like" structure, allowing for gradual expansion to lower code rates through a high-rate kernel matrix. This allows for flexible support of various code rates. In practice, as shown in Figure 3(a), the first X rows and Y columns of the base matrix can be truncated. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also expands. The difference between X and Y is the number of information columns.

[0100] It should be noted that the LDPC base matrix can be represented by a check matrix, so the structure of the check matrix is ​​similar to that of the LDPC base matrix and will not be described in detail here.

[0101] 6. Core Matrix, Core Row, Core Column

[0102] Core row: This is the row corresponding to the core parity bit. In other words, the core row is the row corresponding to the high bit rate area.

[0103] Core columns: This includes all information columns and all core check columns. In other words, core columns are the columns corresponding to the high bitrate area, or the columns corresponding to part A + part B.

[0104] Kernel Matrix: This is the portion consisting of all core rows and columns of the LDPC base matrix or LDPC parity check matrix. In other words, the core matrix is ​​the high-rate region of the LDPC base matrix or LDPC parity check matrix, or the portion consisting of Part A and Part B.

[0105] 7. Expanded columns, non-expanded columns, expanded rows, and non-expanded rows

[0106] For LDPC codes, each additional extended node adds a row and column. In this application, the added row and column are referred to as the extended column and extended row. The extended column is the column corresponding to the extended node; in other words, the extended column corresponds to the extended parity bit. Columns outside the extended column are non-extended columns. Rows outside the extended row are non-extended rows. Taking Figure 3 as an example, the columns in C and E are extended columns, and the rows in D and E are extended rows.

[0107] In addition, in this application, the part composed of non-expanded columns can also be called the core part, and the part composed of expanded columns can also be called the expanded part. Taking Figure 3 as an example, the part composed of A, B and D is the core part, and the part composed of C and E is the expanded part.

[0108] 8. Punch column

[0109] Punctured columns in LDPC codes can refer to columns that are not transmitted. Punctured columns can be either information columns or parity columns. Furthermore, columns that are not punctured in LDPC codes can also be called non-punctured columns. Similarly, non-punctured columns can be either information columns or parity columns.

[0110] For example, the Tanner graph corresponding to the base matrix is ​​called the base graph (BG). Currently, 5G LDPC defines two base graphs, BG1 and BG2. The selection of BG1 and BG2 is based on the length of the code block (CB) and the target transmission bit rate. Generally speaking, the punctured columns of BG1 and BG2 are the first and second columns.

[0111] 9. Information transmission process

[0112] Figure 4 is a schematic diagram of the information transmission process. As shown in Figure 4, information is transmitted from a source and undergoes processing such as source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery before reaching the destination, completing the information transmission from the source to the destination. The processing shown in the upper layer of Figure 4 (including source coding, channel coding, and modulation) is performed at the transmitting end (also known as the encoding device described below), while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed at the receiving end (also known as the decoding device described below).

[0113] The embodiments of the present application mainly relate to source coding, channel coding, channel decoding and source recovery shown in FIG4 .

[0114] Among them, the modulation involved in the above-mentioned Figure 4 generally adopts quadrature amplitude modulation (QAM) mode. QAM modulation is a high-order modulation, and a QAM symbol can carry multiple bits of information. For example, a 64QAM symbol carries 6 bits of information. In high-order modulation, the reliability of the bits carried by a QAM symbol is different, or the energy of the bits is different. For example, a 256QAM symbol can contain 8 bits, of which the first two bits have the highest energy and the highest reliability, the third and fourth bits have the second highest reliability, the fifth and sixth bits have the lower reliability, and the seventh and eighth bits have the lowest reliability. It should be noted that the 256QAM symbol is not limited to the first two bits having the highest energy and the highest reliability, the third and fourth bits having the second highest reliability, the fifth and sixth bits having the lower reliability, and the seventh and eighth bits having the lowest reliability. The reliability of the bits in the 256QAM symbol can also be distributed in other ways, which is not limited in this application.

[0115] Figure 5 shows an example of LDPC information bit protection. The purpose of LDPC information bit protection is to map LDPC information bits to high-energy bit positions in QAM symbols. For example, the LDPC information length is 8448 and the transmission length is 12672, which is an LDPC code rate of 2 / 3. In the new radio (NR) coding protocol, BG1 coding is used, and the selected lifting size is 384, resulting in 22 information columns, each containing 384 bits. The NR protocol stipulates that the first two columns are punctured, so the number of parity columns should be 12672 / 384-(22-2) = 13 columns, as shown in Figure 5. The core parity columns include 4 columns, and the extended parity columns include 9 columns. These 13 columns serve as the parity columns for this LDPC. After the first two columns are punctured and not transmitted, there are 20 information columns remaining. Adding the 13 parity columns, the total number of transmitted columns is 33. The column indexes of these 33 transmission columns are 3 to 35 in FIG5 . 22 information columns / 33 transmission columns=2 / 3, which is the code rate of this LDPC.

[0116] Furthermore, 5G stipulates that rate matching is performed after LDPC encoding to produce a transmit sequence, which typically undergoes bit interleaving. Bit interleaving scrambles the bit order after rate matching to combat burst interference. After interleaving, previously clustered bursts of interference are reduced to random, individual interference, facilitating decoding. Interleaving is particularly effective when using high-order modulation schemes.

[0117] The most commonly used interleaving method is row-column interleaving, which rearranges the bit order by writing rows and reading columns. Assume that the sequence obtained after rate matching is denoted as e, and the sequence obtained after interleaving is denoted as sequence f. If row-column interleaving is used, the relationship between sequence f and sequence e can be as follows:

[0118] Among them, E represents the sequence length, Q m Indicates the number of bits contained in each modulation symbol, j represents the index of the QAM symbol, and i represents the index of the bit position contained in each QAM symbol. For a bit sequence of length E, the number of QAM symbols is E / Q m Therefore, the value of j ranges from 0 to E / Q m -1. If the number of bits contained in a QAM symbol is Q m , then the value of i ranges from 0 to Q m -1.

[0119] The relationship between sequence e and sequence f shows that the position index in sequence e is i*E / Q m +j bits, after bit interleaving, have position index i+j*Q in sequence f.m .

[0120] Based on the above introduction, if 64QAM modulation is used, Q m =6, then there are three energy levels. According to the relationship formula between the transmitted sequence e and the interleaved sequence f, the information bits from columns 3 to 13 are mapped to the first and second bit positions of the QAM symbol, which are the two bit positions with the highest energy. Information bits from columns 14 to 24 are mapped to the third and fourth bit positions of the QAM symbol, which are the two bit positions with the second highest energy. The third and fourth columns of the core parity column and all columns of the extended parity column, i.e., columns 25 to 35, are mapped to the fifth and sixth bit positions of the QAM symbol, which are the two bit positions with the lowest energy. In other words, the first bit position of each QAM symbol is a bit from the first 192 bits in columns 3 to 8, and the second bit position is a bit from the 193rd to 13th bits in columns 8. The 3rd bit position of each QAM symbol is a bit from the first 192 bits in columns 14 to 19, and the 4th bit position is a bit from the 193rd bit in column 19 to a bit from the 24th bit in column 24. The 5th bit position of each QAM symbol is a bit from the first 192 bits in columns 25 to 30, and the 6th bit position is a bit from the 193rd bit in column 30 to a bit from the 35th bit in column 35.

[0121] A key performance indicator (KPI) for wireless communications is the block error rate (BLER), which is the probability that at least one of all transmitted bits is erroneous. A transmission requires that all transmitted bits are correct, so the BLER is primarily determined by the least reliable bit. The information bit protection shown in Figure 5 does not provide additional protection for the least reliable bits, and therefore cannot effectively improve the BLER of wireless communications.

[0122] Based on the above technical status, the present application provides an interleaving method and a corresponding communication device, which can provide additional protection for the least reliable bits, thereby improving the BLER of wireless communication.

[0123] Figure 6 is a schematic diagram of a system architecture 100 applicable to an embodiment of the present application. As shown in Figure 6, system architecture 100 may include an encoding device and a decoding device. The encoding device is not limited to one or more, and the decoding device is not limited to one or more. For example, one of the encoding device and the decoding device may be the network device shown in Figure 6, and the other may be terminal device 1 or terminal device 2 shown in Figure 6.

[0124] The terminal devices in the embodiments of the present application include various communication kits with wireless communication functions (the communication kits may include, for example, antennas, power supply templates, cables, and wireless fidelity (WiFi) modules), handheld devices, vehicle-mounted devices, or other processing devices connected to a wireless modem. Specifically, they may refer to user equipment (UE), users, access terminals, user units, user stations, mobile stations, mobile stations, remote stations, remote terminals, mobile devices, user terminals, terminals, wireless communication devices, user agents, user devices, wireless modems, machine type communication devices, or other processing devices connected to a wireless modem. They may also be virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, wireless terminals in industrial control, terminals in self-driving, terminals in remote medical care, terminals in smart grids, terminals in transportation safety, terminals in smart cities, terminals in smart homes, or terminal devices in future communication networks. Of course, the terminal device in this application may also refer to a chip, modem, system on a chip (SoC) or a communication platform that may include a radio frequency (RF) part, which is mainly responsible for the relevant communication functions in the device.

[0125] The network devices in the embodiments of the present application may include, but are not limited to, next-generation base stations (gNodeBs, gNBs) in fifth-generation (5G) communication systems, base stations in sixth-generation (6G) mobile communication systems, base stations in future mobile communication systems, access points (APs), wireless relay nodes, wireless backhaul nodes, transmission points (TPs) or transmission reception points (TRPs) in wireless fidelity (WiFi) systems, evolved node Bs (eNBs) in long-term evolution (LTE) systems, and network devices in non-terrestrial network (NTN) communication systems. The network device may also be one or a group (i.e., multiple) antenna panels of a base station. In addition, the network device may also be a network node constituting a gNB or TP, such as a baseband unit (BBU), a centralized unit (CU), a distributed unit (DU), or a radio unit (RU). Alternatively, the network device may also be a device-to-device (D2D) communication system, a machine-to-machine (M2M) communication system, an Internet of Things (IoT), an Internet of Vehicles communication system, or a device that performs network-side functions in other communication systems, without limitation.

[0126] In the embodiments of the present application, the device for realizing the functions of the terminal device may be a terminal device, or a device capable of supporting the terminal device to realize the corresponding functions, such as a chip (or chip system) or a circuit, which may be installed in the terminal device. In addition, the device for realizing the functions of the network device may be a network device, or a device capable of supporting the network device to realize the corresponding functions, such as a chip (or chip system) or a circuit, which may be installed in the network device. Optionally, the chip system may include a chip, or include a chip and other discrete devices.

[0127] In the system architecture shown in FIG6 , in uplink communication, the encoding device is terminal device 1 or terminal device 2, and the decoding device is a network device. In downlink communication, the encoding device is a network device, and the decoding device is terminal device 1 or terminal device 2.

[0128] Figure 7 is a schematic flow chart of interleaving method 200 provided in this application. Steps 210 to 218 in method 200 can be performed by an encoding device or by a device (e.g., a chip, a chip system, or a circuit) applied to the encoding device; steps 220 to 226 can be performed by a decoding device or by a device (e.g., a chip, a chip system, or a circuit) applied to the decoding device. The following description uses encoding devices and decoding devices as examples.

[0129] In addition, the technical solution of the present application can be applied to QAM modulation, but is also applicable to some other modulation methods. For example, pulse amplitude modulation (PAM) and phase shift keying (PSK) modulation. The following uses the application of the technical solution of the present application in QAM modulation as an example to illustrate.

[0130] In step S210 , the encoding device obtains an LDPC base matrix, where the LDPC base matrix includes M columns.

[0131] Specifically, the encoding device may select an LDPC base matrix based on the length of the CB and the target code rate of the transmission. For example, the BG corresponding to the selected LDPC base matrix may be BG1 or BG2, which is not limited in this application.

[0132] Step S212: The encoding device encodes the first bit sequence according to the LDPC base matrix to obtain a second bit sequence.

[0133] Illustratively, the first bit sequence is a bit sequence to be encoded, and the second bit sequence is a bit sequence to be sent.

[0134] For example, the encoding device can divide the information sequence to be encoded into groups of w bits. The encoder then performs a linear operation on these w information bits to obtain g parity bits. These w information bits and the g parity bits are then combined to form a codeword of length v = w + g. The mapping from w information bits to a codeword of length v bits can be represented by the aforementioned LDPC base matrix. Based on this LDPC base matrix, a codeword sequence can be generated to complete the encoding process.

[0135] Optionally, the second bit sequence may be a bit sequence that has undergone rate matching.

[0136] Step S214: The encoding device interleaves the second bit sequence according to the first indicator sequence to obtain a third bit sequence.

[0137] Specifically, the first indicator sequence is used to indicate the correspondence between the M columns and the R energy levels included in the QAM symbol, where M and R are positive integers.

[0138] Exemplarily, the first indication sequence satisfies at least one of the following characteristics:

[0139] Feature 1: The elements in the first indicator sequence correspond one-to-one to the columns of the above LDPC basis matrix.

[0140] Feature 2: The number of elements S in the first indicator sequence is the same as the number of the M columns excluding the punctured columns.

[0141] It should be noted that when rate matching is not required, there may be no puncturing sequence, and in this case S=M; when rate matching is required, puncturing is required, and in this case S<M.

[0142] Feature 3: The smaller the sequence number of an element in the first indicator sequence, the higher the energy level corresponding to the element.

[0143] Exemplarily, the first indicator sequence is used to indicate the correspondence between the M columns and the R energy levels included in the QAM symbol, including the following three indication modes:

[0144] Indication method 1: The first indicator sequence is used to indicate the correspondence between M columns and R energy levels contained in the QAM symbol.

[0145] The corresponding relationship between the M columns and the R energy levels contained in the QAM symbol may be: the smaller the column weight of the M columns, the higher the corresponding energy level.

[0146] Taking FIG. 5 as an example, the number of elements in the first indicator sequence is 33 (the punctured columns of the first and second columns are deleted). Assume that as the number of columns of the 33 columns increases, the column weights of the 33 columns are 11, 11, 11, 10, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, the first indicator sequence may be indicator sequence #1: {35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15,14,13,12,11,10,9,8,7,6,5,4,3}, wherein the i-th element (sequence number is i) of the indicator sequence #1 indicates that the i-th priority of the column corresponding to the element corresponds to the high energy level of the QAM symbol. For example, the first element "35" of the indicator sequence #1 indicates that the first priority of the bit of the 35th column corresponds to the high energy level of the QAM symbol, and the third element "33" of the indicator sequence #1 indicates that the third priority of the bit of the 33rd column corresponds to the high energy level of the QAM symbol. Alternatively, the first indicator sequence may be indicator sequence #2: {32, 34, 33, 35, 27, 31, 29, 30, 28, 24, 26, 23, 25, 21, 22, 19, 18, 20, 15, 17, 16, 14, 13, 12, 10, 9, 11, 8, 7, 6, 5, 3, 4}, and the positions of columns with the same column weight in indicator sequence #1 may be interchanged.

[0147] The example of indicator sequence #1 above can be considered as a complete indicator sequence. When bits of a part of the columns need to be interleaved, the first indicator sequence used is a subsequence of the complete indicator sequence. For example, if the bits of columns 10 to 20 need to be interleaved, the subsequence corresponding to columns 10 to 20 in the above indicator sequence #1 is selected as the first indicator sequence. At this time, the first indicator sequence is indicator sequence #1A: {20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10}, where the first element "20" of the indicator sequence #1A indicates that the first priority of the bits of the 20th column corresponds to the high energy level of the QAM symbol, and the third element "18" of the indicator sequence #1A indicates that the third priority of the bits of the 18th column corresponds to the high energy level of the QAM symbol.

[0148] In addition, in the above example, the QAM symbol of the 64QAM modulation mode has 3 energy levels, but the first indicator sequence indicates 33 columns. In this case, priority is given to ensuring bit mapping of the high energy level. For example, the bits in the 35th column can be mapped to the highest energy level first. If the bits in the 35th column occupy all the bits of the highest energy level of the QAM symbol, then the bits in the 34th column are mapped to the second highest energy level; if the bits in the 35th column occupy part of the bits of the highest energy level of the QAM symbol, then the bits in the 34th column continue to be mapped to the highest energy level of the QAM symbol, and so on.

[0149] Indication method 2: M columns are divided into K intervals according to the columns, and the first indicator sequence is used to indicate the correspondence between the K intervals and the R energy levels included in the QAM symbol.

[0150] Among them, the above K intervals include the first interval and / or the second interval and / or the third interval, the maximum column weight of the second interval is less than the minimum column weight of the third interval, and the minimum column weight of the second interval is greater than the maximum column weight of the first interval.

[0151] For example, the correspondence between the K intervals and the R energy levels contained in the QAM symbol can be: the smaller the column weight of the K intervals, the higher the corresponding energy level. For example, the column weight of the K intervals can be the maximum column weight, the minimum column weight, or the average column weight of the first interval, the second interval, or the third interval, etc., which is not limited in this application.

[0152] Here, Figure 5 is still used as an example. The number of elements in the first indicator sequence is 33 (the punched columns of the first and second columns are deleted). Assume that as the number of columns of the 33 columns increases, the column weights of the 33 columns are 11, 11, 11, 10, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, and the column weights of the 33 columns are divided into three intervals: [1], [4, 7], and [8, 11]. These three intervals can be examples of the first interval, the second interval, and the third interval. The first indicator sequence can be divided into three sections according to these three intervals, such as the first, second, and third sections of the indicator sequence #3 shown in (a) of Figure 8 and the first, second, and third sections of the indicator sequence #4 shown in (b) of Figure 8.

[0153] The first segment shown in FIG8 includes columns corresponding to the column weight in the first interval [1], the second segment includes columns corresponding to the column weight in the second interval [4, 7], and the third segment includes columns corresponding to the column weight in the third interval [8, 11]. The i-th segment of indicator sequence #3 and indicator sequence #4 indicates that the i-th priority of the column corresponding to the element of the i-th segment corresponds to the high energy level of the QAM symbol. For example, the element "35" of the first segment of indicator sequence #3 indicates that the first priority of the bit of the 35th column corresponds to the high energy level of the QAM symbol, the element "33" of the first segment of indicator sequence #3 indicates that the first priority of the bit of the 33rd column corresponds to the high energy level of the QAM symbol, and the element "19" of the second segment of indicator sequence #3 indicates that the second priority of the bit of the 19th column corresponds to the high energy level of the QAM symbol.

[0154] The elements contained in each segment in indicator sequence #3 can be arranged arbitrarily within the segment, as shown in indicator sequence #4.

[0155] Optionally, the positions of columns with the same column weight contained in each segment of indication sequence #3 may be interchanged within the segment.

[0156] In the above example, the QAM symbols of the 64QAM modulation mode have three energy levels. At this time, the bits of the columns contained in the first interval shown in Figure 8 can be mapped to the highest energy level of the QAM symbol, the bits of the columns contained in the second interval can be mapped to the second highest energy level of the QAM symbol, and the bits corresponding to the columns contained in the third interval can be mapped to the lowest energy level of the QAM symbol.

[0157] For another example, the QAM symbols of the 16QAM modulation mode have two energy levels. In this case, the bits of the columns contained in the first interval shown in Figure 8 can be mapped to the highest energy level of the QAM symbol, and the bits of the columns contained in the third interval can be mapped to the lowest energy level of the QAM symbol. The bits of the columns contained in the second interval can be mapped to the highest energy level of the QAM symbol or the lowest energy level of the QAM symbol.

[0158] Optionally, the 33 columns can be further divided into two intervals [1, 7] and [8, 11], which can be examples of the first interval and the second interval. The first indicator sequence can be divided into two sections based on the two intervals. This application does not limit the number of the K intervals.

[0159] Another implementation of the second indication method is: the M columns are divided into K sets according to the columns, and the first indication sequence is used to indicate the correspondence between the K sets and the R energy levels included in the QAM symbol.

[0160] Here, Figure 5 is still used as an example. The number of elements in the first indicator sequence is 33 (the punched columns of the first and second columns are deleted). Assume that as the number of columns of the 33 columns increases, the column weights of the 33 columns are 11, 11, 11, 10, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, and the column weights of the 33 columns are divided into three sets: {1}, {4, 5, 7}, and {8, 9, 10, 11}. The first indicator sequence can be divided into three segments according to these three sets, such as the first, second, and third segments of the indicator sequence #3 shown in (a) of Figure 8 and the first, second, and third segments of the indicator sequence #4 shown in (b) of Figure 8.

[0161] The first segment shown in FIG8 includes columns corresponding to the column weights in the first set {1}, the second segment includes columns corresponding to the column weights in the second set {4, 5, 7}, and the third segment includes columns corresponding to the column weights in the third set {8, 9, 10, 11}. The i-th segment of indicator sequence #3 and indicator sequence #4 indicates that the i-th priority of the column corresponding to the element in the i-th segment corresponds to the high energy level of the QAM symbol. For example, element "35" of the first segment of indicator sequence #3 indicates that the first priority of the bit in the 35th column corresponds to the high energy level, element "33" of the first segment of indicator sequence #3 indicates that the first priority of the bit in the 33rd column corresponds to the high energy level of the QAM symbol, and element "19" of the second segment of indicator sequence #3 indicates that the second priority of the bit in the 19th column corresponds to the high energy level of the QAM symbol.

[0162] The elements contained in each segment in indicator sequence #3 can be arranged arbitrarily within the segment, as shown in indicator sequence #4.

[0163] Optionally, the positions of columns with the same column weight contained in each segment of indication sequence #3 may be interchanged within the segment.

[0164] In the above example, the QAM symbols of the 64QAM modulation method have three energy levels. At this time, the bits of the columns contained in the first set shown in Figure 8 can be mapped to the highest energy level of the QAM symbol, the bits of the columns contained in the second set can be mapped to the second highest energy level of the QAM symbol, and the bits corresponding to the columns contained in the third set can be mapped to the lowest energy level of the QAM symbol.

[0165] For another example, the QAM symbols of the 16QAM modulation mode have two energy levels. In this case, the bits of the columns contained in the first set shown in Figure 8 can be mapped to the highest energy level of the QAM symbol, and the bits of the columns contained in the third set can be mapped to the lowest energy level of the QAM symbol. The bits of the columns contained in the second set can be mapped to the highest energy level of the QAM symbol or the lowest energy level of the QAM symbol.

[0166] Optionally, the 33 columns can be further divided into two sets {1, 4, 5, 7} and {8, 9, 10, 11}. The first indicator sequence can be divided into two sections according to the two sets. The present application does not limit the number of the K sets.

[0167] The first indication method and the second indication method perform bit mapping according to column weight, which can provide additional protection for the least reliable bits and improve communication performance.

[0168] Indication method three: M columns are divided into P sets based on type. The first indicator sequence is used to indicate the correspondence between the P sets and the R energy levels contained in the QAM symbol. Exemplarily, the types of the M columns include information columns, core parity columns, and extended parity columns. The columns included in the first set, / or the second set, and / or the third set of the P sets are arranged in ascending order of column weight.

[0169] The P sets include a first set and / or a second set and / or a third set. The first set may include information columns, the second set may include core check columns, and the third set may include extended check columns. Alternatively, the first set may include information columns and core check columns, and the second set may include extended check columns.

[0170] Still taking FIG. 5 as an example, the number of elements in the first indicator sequence is 33 (the punctured columns of the first and second columns are deleted). Assume that, as the number of columns of the 33 columns increases, the column weights of the 33 columns are 11, 11, 11, 10, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, and the 33 columns are divided into the first set, the second set, and the third set shown in indicator sequence #5 of FIG. 9 (a) and indicator sequence #6 of FIG. 9 (b) according to their types.

[0171] Exemplarily, the first set includes information columns from columns 3 to 22, the second set includes core parity columns from columns 23 to 26, and the third set includes extended parity columns from columns 27 to 35. The i-th set of indicator sequence #5 and indicator sequence #6 indicates that the i-th priority of the column corresponding to the element of the i-th set corresponds to the high energy level of the QAM symbol. For example, element "22" of the first set of indicator sequence #5 indicates that the bit of column 22 has the first priority corresponding to the high energy level, element "20" of the first set of indicator sequence #5 indicates that the bit of column 20 has the first priority corresponding to the high energy level of the QAM symbol, and element "25" of the second set of indicator sequence #5 indicates that the bit of column 25 has the second priority corresponding to the high energy level of the QAM symbol.

[0172] Among them, the multiple columns included in each of the first set, the second set, and the third set are arranged in order of column weight from small to large. Take the information columns from the 3rd to the 22nd columns included in the first set as an example for explanation. As shown in (a) of FIG9 , the column weight of the 22nd column corresponding to the element "22" of the first set is 4, and the column weight of the 20th column corresponding to the element "20" of the first set is 5. Therefore, the index of the serial number of the element "22" of the first set in the indication sequence #5 is smaller than the index of the serial number of the element "20" of the first set in the indication sequence #5. In other words, the position of the element "22" of the first set in the indication sequence #5 is closer to the front than the position of the element "20" of the first set in the indication sequence #5.

[0173] Optionally, the elements contained in each set in indicator sequence #5 may be arranged arbitrarily within the set, as shown in indicator sequence #6.

[0174] Optionally, the positions of columns with the same column weight contained in each set in indication sequence #5 may be interchanged within the set.

[0175] In the above example, the QAM symbols of the 64QAM modulation mode have three energy levels. At this time, the bits of the columns contained in the first set shown in Figure 9 can be mapped to the highest energy level of the QAM symbol, the bits of the columns contained in the second set can be mapped to the second highest energy level of the QAM symbol, and the bits of the columns contained in the third set can be mapped to the lowest energy level of the QAM symbol.

[0176] For another example, the QAM symbols of the 16QAM modulation mode have two energy levels. In this case, the bits of the columns contained in the first set shown in Figure 9 can be mapped to the highest energy level of the QAM symbol, and the bits of the columns contained in the third set can be mapped to the lowest energy level of the QAM symbol. The bits of the columns contained in the second set can be mapped to the highest energy level of the QAM symbol or the lowest energy level of the QAM symbol.

[0177] Optionally, the 33 columns can be divided into two sets, a first set and a second set, based on type. For example, the first set includes information columns from columns 3 to 22 and core check columns from columns 23 to 26, and the second set includes extended check columns from columns 27 to 35. This application does not limit the number of the P sets or the division method of the P sets.

[0178] The third indication method mentioned above can also take into account information bit protection, always mapping the most important information to the highest energy level of the QAM symbol. In addition, it can further refine the energy levels corresponding to the information bits, providing additional protection for unreliable bits in the information bits, thereby improving communication performance.

[0179] Another implementation of indication method three is as follows: the first set includes extended parity columns from columns 27 to 35, the second set includes core parity columns from columns 23 to 26, and the third set includes information columns from columns 3 to 22, as shown in indication sequence #7 in FIG10(a) and indication sequence #8 in FIG10(b). The i-th set of indication sequence #7 and indication sequence #8 indicates that the column i-th priority corresponding to the element of the i-th set corresponds to the high energy level of the QAM symbol. For example, element "35" of the first set of indication sequence #7 indicates that the bit of column 35 has the first priority corresponding to the high energy level, element "33" of the first set of indication sequence #7 indicates that the bit of column 33 has the first priority corresponding to the high energy level, and element "25" of the second set of indication sequence #7 indicates that the bit of column 25 has the second priority corresponding to the high energy level of the QAM symbol.

[0180] Among them, the multiple columns included in each of the first set, the second set, and the third set are arranged in order of column weight from small to large. Take the information columns from the 1st to the 22nd column included in the third set as an example for explanation. As shown in (a) of FIG10 , the column weight of the 22nd column corresponding to the element "22" of the third set is 4, and the column weight of the 20th column corresponding to the element "20" of the third set is 5. Therefore, the index of the serial number of the element "22" of the third set in the indication sequence #7 is smaller than the index of the serial number of the element "20" of the third set in the indication sequence #7. In other words, the position of the element "22" of the third set in the indication sequence #7 is closer to the front than the position of the element "20" of the third set in the indication sequence #7.

[0181] Optionally, the elements contained in each set in indicator sequence #7 may be arranged arbitrarily within the set, as shown in indicator sequence #8.

[0182] Optionally, the positions of columns with the same column weight contained in each set in indication sequence #7 may be interchanged within the set.

[0183] In the above example, the QAM symbols of the 64QAM modulation mode have three energy levels. At this time, the bits of the columns contained in the first set shown in Figure 10 can be mapped to the highest energy level of the QAM symbol, the bits of the columns contained in the second set can be mapped to the second highest energy level of the QAM symbol, and the bits of the columns contained in the third set can be mapped to the lowest energy level of the QAM symbol.

[0184] For another example, the QAM symbols of the 16QAM modulation mode have two energy levels. In this case, the bits of the columns contained in the first set shown in Figure 10 can be mapped to the highest energy level of the QAM symbol, and the bits of the columns contained in the third set can be mapped to the lowest energy level of the QAM symbol. The bits of the columns contained in the second set can be mapped to the highest energy level of the QAM symbol or the lowest energy level of the QAM symbol.

[0185] Optionally, the 33 columns can be divided into two sets, a first set and a second set, based on type. For example, the first set includes core check columns from columns 23 to 26 and extended check columns from columns 27 to 35, and the second set includes information columns from columns 1 to 22. This application does not limit the number of the P sets or the division method of the P sets.

[0186] Illustratively, the first indication sequence may be generated according to the rules described in the above indication mode 1, indication mode 2, or indication mode 3, or may be pre-stored, which is not limited in this application.

[0187] As mentioned above, the LDPC base matrix adopts a "raptor-like" structure, which can be gradually expanded to a low code rate through a high code rate core matrix, so that it can flexibly support encoding of various code rates. The code rates required in different communication scenarios are different, so the M columns involved in the above-mentioned first indicator sequence may change during the process of expanding the LDPC base matrix from a high code rate to a low code rate. The embodiment of the present application can provide the following methods for determining the M columns of the LDPC base matrix:

[0188] Method 1: The M columns are columns corresponding to the lowest code rate supported by the LDPC base matrix.

[0189] For example, the number of information columns in the matrix corresponding to BG1 is 22, the number of core parity columns and extended parity columns is 46, and the minimum code rate supported by BG1 is 1 / 3. Therefore, the number of M columns of the LDPC base matrix is ​​considered to be 22 + 46 = 68. The first indicator sequence can indicate the correspondence between the 68 columns and the R energy levels of the QAM symbol according to the above-mentioned indication method 1, indication method 2, or indication method 3.

[0190] Method 2: The above M columns are columns corresponding to the highest code rate supported by the LDPC base matrix.

[0191] For example, the number of information columns in the matrix corresponding to BG1 is 22, the number of core check columns is 4, and the highest code rate supported by BG1 is 22 / 24. Therefore, the number of M columns of the LDPC base matrix is ​​considered to be 22+4=26. The first indicator sequence can indicate the correspondence between the 26 columns and the R energy levels of the QAM symbol according to the above-mentioned indication method 1, indication method 2, or indication method 3.

[0192] Method 3: The code rate supported by the LDPC base matrix is ​​divided into multiple intervals, each code rate interval corresponds to a different number of columns, and one code rate interval corresponds to one first indicator sequence.

[0193] Exemplarily, the bit rate range supported by BG1 is [1 / 3, 22 / 24], which is divided into multiple bit rate ranges [1 / 3, 1 / 2], [1 / 2, 2 / 3], and [2 / 3, 22 / 24]. The number of columns of the matrix corresponding to each bit rate range can be the number of columns of the matrix corresponding to the lowest bit rate of the bit rate range, the number of columns of the matrix corresponding to the highest bit rate of the bit rate range, or the number of columns of the matrix corresponding to the intermediate bit rate of the bit rate range. This application does not limit this.

[0194] Exemplarily, the embodiment of the present application is explained by taking the example that the number of columns of the matrix corresponding to each code rate interval can be the number of columns of the matrix corresponding to the lowest code rate in the code rate interval: the number of matrix columns corresponding to the code rate interval [1 / 3, 1 / 2] is 68, the number of matrix columns corresponding to the code rate interval [1 / 2, 2 / 3] is 56, and the number of matrix columns corresponding to the code rate interval [2 / 3, 22 / 24] is 44. Therefore, the LDPC base matrix under mode three corresponds to three first indicator sequences. The first first indicator sequence can indicate the correspondence between 68 columns corresponding to the code rate interval [1 / 3, 1 / 2] and the R energy levels of the QAM symbol according to the above-mentioned indication mode one, indication mode two, or indication mode three. The second first indicator sequence can indicate the correspondence between 56 columns corresponding to the code rate interval [1 / 2, 2 / 3] and the R energy levels of the QAM symbol according to the above-mentioned indication mode one, indication mode two, or indication mode three. The third first indicator sequence can indicate the correspondence between 44 columns corresponding to the code rate interval [2 / 3, 22 / 24] and the R energy levels of the QAM symbol according to the above-mentioned indication mode one, indication mode two, or indication mode three.

[0195] Alternatively, when the M columns involved in the first indicator sequence may change during the process of expanding the LDPC base matrix from a high code rate to a low code rate, the column weights of the M columns may also change, that is, the positions of the columns of the LDPC base matrix in the first indicator sequence may also change. For example, embodiments of the present application may provide the following methods for determining the column weights of the M columns of the LDPC base matrix:

[0196] Method 1: The column weights of the M columns are the column weights of the columns corresponding to the lowest code rate supported by the LDPC base matrix. Alternatively, the column weights of the M columns are the column weights of the entire LDPC base matrix.

[0197] Exemplarily, the column weight of the M columns is the column weight of the column of part A+part B+part C+part D+part E shown in FIG. 3 .

[0198] Method 2: The column weights of the M columns are the column weights of the columns corresponding to the highest code rate supported by the LDPC base matrix.

[0199] Exemplarily, the column weight of the M columns is the column weight of the columns of part A+part B shown in FIG3 .

[0200] Method three: The code rate supported by the LDPC base matrix is ​​divided into multiple intervals. The column weights corresponding to each code rate interval are different. One code rate interval may correspond to one first indicator sequence.

[0201] Exemplarily, the code rate range supported by BG1 is [1 / 3, 22 / 24], which is divided into multiple code rate ranges [1 / 3, 1 / 2], [1 / 2, 2 / 3], and [2 / 3, 22 / 24]. The column weight of the matrix corresponding to each code rate range can be the column weight of the matrix corresponding to the lowest code rate in the code rate range, or the column weight of the matrix corresponding to the highest code rate in the code rate range, or the column weight of the matrix corresponding to the intermediate code rate in the code rate range. This application does not limit this. In the above-mentioned step S214, the encoding device interleaves the above-mentioned second bit sequence according to the above-mentioned first indication sequence to obtain a third bit sequence. Exemplarily, the above-mentioned step S214 may specifically include: the encoding device performs a first interleaving on the second bit sequence according to the above-mentioned first indication sequence to obtain a fourth bit sequence; the encoding device performs row-column interleaving on the fourth bit sequence to obtain the above-mentioned third bit sequence.

[0202] Illustratively, the first interleaving process described below may be performed before the encoding device performs circular buffering on the second bit sequence, or may be performed after the encoding device performs circular buffering on the second bit sequence, and this application does not limit this.

[0203] Exemplarily, the first interleaving process may be as follows: assuming that the transmitted sequence obtained after rate matching is denoted as e (which may be an example of the second bit sequence described above), the sequence obtained after the first interleaving is denoted as sequence e1 (which may be an example of the fourth bit sequence described above). Exemplarily, the relationship between sequence e1 and sequence e may be as follows:

[0204] Wherein, S represents the number of elements in the first indicator sequence, j represents the index of the sequence number of the element contained in the first indicator sequence, s(j) represents the jth element of the first indicator sequence, and Z c is the lifting value of the LDPC base matrix, and can also be understood as the number of bits corresponding to each column indicated in the first indicator sequence.

[0205] From the relationship between sequence e and sequence e1, it can be seen that the position index in sequence e is s(j)*Z c After bit interleaving, the position index of the bit +i in sequence e1 is j*Z c +i.

[0206] Next, the sequence e1 may be interleaved in rows and columns to obtain a sequence f (which may be an example of the third bit sequence mentioned above). For example, the relationship between the sequence f and the sequence e1 may be as follows:

[0207] Among them, E represents the sending length, Q m Indicates the number of bits contained in each modulation symbol, j represents the index of the QAM symbol, and i represents the index of the bit position contained in each QAM symbol. For a bit sequence of length E, the number of QAM symbols is E / Q m Therefore, the value of j ranges from 0 to E / Q m -1. If the number of bits contained in a QAM symbol is Q m , then the value of i ranges from 0 to Q m -1.

[0208] From the relationship between sequence e1 and sequence f, we can see that the position index in sequence e1 is i*E / Q m +j bits, after bit interleaving, have position index i+j*Q in sequence f. m .

[0209] It should be noted that the closer the position of the element in the first indicator sequence (that is, the column of the LDPC base matrix) is in the first indicator sequence, the lower the column weight of the column of the LDPC base matrix. The present application may also provide another representation of the first indicator sequence: the closer the position of the element in the first indicator sequence (that is, the column of the LDPC base matrix) is in the first indicator sequence, the higher the column weight of the column of the LDPC base matrix. , 17, 15, 20, 18, 19, 22, 21, 25, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35} may also be used to represent the first indication sequence, or the above indication sequence #2 may be changed to {4, 3, 5, 6, 7, 8, 11, 9, 10, 12, 13, 14, 16, 17, 15, 20, 18, 19, 22, 21, 25, 23, 26, 24, 28, 30, 29, 31, 27, 35, 33, 34, 32} may also be used to represent the first indication sequence. In this case, the encoding device can interleave the second bit sequence by the method of the first interleaving + reverse row and column interleaving to obtain a third bit sequence.

[0210] For example, the first interleaving can be the same as above, and the sequence e1 obtained by the first interleaving is interleaved in reverse order to obtain a sequence f (which can be an example of the third bit sequence mentioned above). For example, the relationship between the sequence f and the sequence e1 can be as follows:

[0211] Among them, E represents the sending length, Q m Indicates the number of bits contained in each modulation symbol, j represents the index of the QAM symbol, and i represents the index of the bit position contained in each QAM symbol. For a bit sequence of length E, the number of QAM symbols is E / Q m Therefore, the value of j ranges from 0 to E / Q m -1. If the number of bits contained in a QAM symbol is Q m , then the value of i ranges from 0 to Q m -1.

[0212] From the relationship between sequence e1 and sequence f, we can see that the position index in sequence e1 is i*E / Q m The position index of the bit +j in sequence f after bit interleaving is Q m -1-i+j*Q m .

[0213] Step S216: The encoding device maps the bits in the third bit sequence to QAM symbols.

[0214] Specifically, the encoding device maps bits corresponding to at least one fourth column in the third bit sequence to a first energy level of the QAM symbol, and maps bits corresponding to at least one fifth column in the third bit sequence to a second energy level of the QAM symbol.

[0215] The at least one fourth column and the at least one fifth column belong to the M columns, the column weight of the at least one fourth column is smaller than the column weight of the at least one fifth column, and the first energy level is higher than the second energy level.

[0216] It should be noted that if the first indication sequence is indicated using the third indication method, then the at least one fourth column and the at least one fifth column belong to the same set in the first set, the second set, or the third set in the third indication method.

[0217] Step S218: The encoding device outputs the modulated QAM symbols.

[0218] The “output modulated QAM symbols” here can also be understood as sending the modulated QAM symbols to the decoding device.

[0219] In step S220, the decoding device obtains the QAM symbol to be demodulated and demodulates it to obtain a first information sequence.

[0220] The first information sequence is a sequence of LLR information obtained after demodulation, wherein each LLR information represents the probability that the bit at the corresponding bit position is 0 or 1.

[0221] Step S222: The decoding device deinterleaves the first information sequence to obtain a second information sequence.

[0222] The second information sequence is a sequence of LLR information.

[0223] Step S224: The decoding device decodes the second information sequence, determines the information bits, and obtains a third information sequence.

[0224] Step S226: The decoding device outputs a third information sequence.

[0225] In steps S220 through S226, the demodulation, deinterleaving, and decoding performed by the decoding device are the inverse of the modulation, interleaving, and encoding performed by the encoding device, respectively. The principles are the same as those of the encoding device. On the decoding device, the LLR information obtained after demodulating the QAM symbols corresponds to the bits of the encoding device, specifically the information bits and parity bits. Based on the description of the encoding device, those skilled in the art will understand how the decoding device performs demodulation, deinterleaving, and decoding, and will not be further elaborated here.

[0226] The interleaving method 200 described above can map the least reliable bits to a high energy level of a QAM symbol, thereby providing additional protection for the least reliable bits, reducing the BLER of data transmission, and improving wireless communication performance.

[0227] The present application may also provide a communication method 300 , which can omit the first interleaving process in the above-mentioned interleaving method 200 by designing a suitable LDPC base matrix, thereby simplifying the above-mentioned interleaving method 200 .

[0228] Figure 11 is a schematic flow chart of the communication method 300 provided in this application. Steps 310 to 318 in the communication method 300 can be performed by an encoding device or by an apparatus (e.g., a chip, a chip system, or a circuit) applied to the encoding device; steps 320 to 326 can be performed by a decoding device or by an apparatus (e.g., a chip, a chip system, or a circuit) applied to the decoding device. The following description uses encoding devices and decoding devices as examples.

[0229] In step S310 , the encoding device obtains a first LDPC base matrix, where the first LDPC base matrix includes M columns, and the M columns are divided into K intervals according to column variables.

[0230] Optionally, the first LDPC base matrix may be generated based on the first indicator sequence.

[0231] Exemplarily, the column variable may be a column weight or a column type of the first submatrix, and the column type includes an information column, a core check column, and an extended check column.

[0232] The first submatrix is ​​a partial or complete matrix of the first LDPC base matrix. Exemplarily, the first submatrix may be a matrix corresponding to the lowest code rate supported by the first LDPC base matrix, or the first submatrix may be a matrix corresponding to the highest code rate supported by the first LDPC base matrix.

[0233] Exemplarily, when the column variable is the column weight of the first submatrix, the first LDPC base matrix may satisfy at least one of the following characteristics:

[0234] Feature 1: The column weight of the M columns of the first LDPC base matrix increases as the number of columns increases.

[0235] Specifically, the first LDPC base matrix with feature 1 does not distinguish between the arrangement of information columns and check columns.

[0236] Feature 2: The M columns of the first LDPC base matrix can be divided into K intervals, the K intervals including the first interval and / or the second interval and / or the third interval, the maximum column weight of at least one second column in the second interval is less than the minimum column weight of at least one first column in the first interval, the minimum column weight of at least one second column in the second interval is greater than the maximum column weight of at least one third column in the third interval, the number of columns in at least one third column in the third interval is greater than the number of columns in at least one second column in the second interval, and the number of columns in at least one first column in the first interval is greater than the number of columns in at least one first column in the first interval.

[0237] In which, the column weight of at least one first column in the first interval decreases as the number of columns increases, or the position (or number of columns) of at least one first column in the first interval can be exchanged within the first interval; and / or, the column weight of at least one second column in the second interval decreases as the number of columns increases, or the position (or number of columns) of at least one second column in the second interval can be exchanged within the second interval; and / or, the column weight of at least one third column in the third interval decreases as the number of columns increases, or the position (or number of columns) of at least one third column in the third interval can be exchanged within the third interval.

[0238] The smaller the column weight of the K intervals, the higher the energy level of the bitmap of the column in the interval. For example, the column weight of the K intervals can be the maximum column weight, the minimum column weight, or the average column weight of the first interval, the second interval, or the third interval, etc., which is not limited in this application.

[0239] When the column variable is a column type, the first LDPC basis matrix may satisfy the following feature 3:

[0240] Feature 3: The M columns of the first LDPC base matrix are divided into the K intervals or P sets according to column type. The column weights of the multiple columns included in the first interval, the second interval, and / or the third interval of the K intervals decrease as the number of columns increases.

[0241] The column types include information columns, core check columns, and extended check columns. For example, the first interval may include an information column, the second interval may include a core check column, and the third interval may include an extended check column; or the first interval may include an information column and a core check column, and the second interval may include an extended check column.

[0242] Step S312: The encoding device encodes the first bit sequence according to the first LDPC base matrix to obtain a second bit sequence.

[0243] Exemplarily, the first bit sequence is an information sequence to be encoded, and the second bit sequence is an information sequence to be sent.

[0244] For example, the encoding device can divide the information sequence to be encoded into groups of w bits. The encoder then performs a linear operation on these w information bits to obtain g check bits. These w information bits and the g check bits are then combined to obtain a codeword of length v = w + g. The mapping relationship from w information bits to a codeword of length v bits can be represented by the first LDPC base matrix described above. Based on this first LDPC base matrix, a codeword sequence can be generated to complete the encoding process.

[0245] Alternatively, the second bit sequence may be a bit sequence that has undergone rate matching.

[0246] Step S314: The encoding device performs bit interleaving on the second bit sequence to obtain a third bit sequence.

[0247] Exemplarily, the encoding device may interleave the first bit sequence using the reverse row-column interleaving method to obtain a third bit sequence.

[0248] In step S316, the encoding device maps the third bit sequence onto QAM symbols.

[0249] Specifically, the encoding device maps bits corresponding to at least one fourth column in the third bit sequence to a first energy level of the QAM symbol, and maps bits corresponding to at least one fifth column in the third bit sequence to a second energy level of the QAM symbol.

[0250] The at least one fourth column and the at least one fifth column belong to the M columns, the column weight of the at least one fourth column is smaller than the column weight of the at least one fifth column, and the first energy level is higher than the second energy level.

[0251] Step S318: The encoding device outputs the modulated QAM symbols.

[0252] The “output modulated QAM symbols” here can also be understood as sending the modulated QAM symbols to the decoding device.

[0253] Step S320: The decoding device obtains the QAM symbol to be demodulated and demodulates it to obtain a first information sequence.

[0254] The first information sequence is a sequence of LLR information obtained after demodulation, wherein each LLR information represents the probability that the bit at the corresponding bit position is 0 or 1.

[0255] Step S322: The decoding device deinterleaves the first information sequence to obtain a second information sequence.

[0256] The second information sequence is a sequence of LLR information.

[0257] Step S324: The decoding device decodes the second information sequence, determines the information bits, and obtains a third information sequence.

[0258] Step S326: The decoding device outputs a third information sequence.

[0259] In steps S320 through S326, the demodulation, deinterleaving, and decoding performed by the decoding device are the inverse of the modulation, interleaving, and encoding performed by the encoding device, respectively. The principles are the same as those of the encoding device. On the decoding device, the LLR information obtained after demodulating the QAM symbols corresponds to the bits of the encoding device, specifically the information bits and parity bits. Based on the description of the encoding device, those skilled in the art will understand how the decoding device performs demodulation, deinterleaving, and decoding, and will not be further elaborated here.

[0260] It should be noted that the closer the number of columns of the first LDPC base matrix is ​​to the front (that is, the higher the column weight of the column of the first LDPC base matrix is), the lower the energy level of the bit mapping of the column of the first LDPC base matrix is. The present application can also provide another first LDPC base matrix: the closer the number of columns of the first LDPC base matrix is ​​to the front (that is, the lower the column weight of the column of the first LDPC base matrix is), the higher the energy level of the bit mapping of the column of the first LDPC base matrix is. In this case, the encoding device can interleave the second bit sequence by the above-mentioned row-column interleaving method to obtain a third bit sequence.

[0261] The communication method 300 described above provides a first LDPC base matrix with better performance. The first LDPC base matrix can not only omit the first interleaving process in the above interleaving method 200 and simplify the above interleaving method 200, but also accelerate the convergence speed and improve the overall performance.

[0262] Specifically, the first LDPC base matrix also adopts a "raptor-like" structure, which can be gradually expanded to a low code rate through a high code rate core matrix, so that it can flexibly support encoding of various code rates. The code rates required in different communication scenarios are different, so the column weight of the above-mentioned first LDPC base matrix will change during the process of expanding the first LDPC base matrix from a high code rate to a low code rate. Based on this, the present application provides a second LDPC base matrix, and the column weight of the second LDPC base matrix will basically not change during the process of expanding from a high code rate to a low code rate.

[0263] For example, Figure 12 shows an example of the second LDPC. During the expansion process, a new check equation c2 (corresponding to an expanded row) is added to the second LDPC base matrix. C2 is used to eliminate a check equation c1 (corresponding to a row in the high-rate region) in the high-rate region of the second LDPC base matrix to perform low-rate expansion. After elimination, an equivalent check equation c3 is obtained. Using check equation c3 to replace c1 can be understood as splitting c1 into c2 and c3. During this expansion process, the column weight of each column of the second LDPC base matrix will not increase.

[0264] Exemplarily, the second LDPC base matrix shown in FIG12 includes N rows, each of which corresponds to an indicator sequence θ. The i in θ(i) on the far left of FIG12 represents the number of rows of the second LDPC base matrix, and θ(i) indicates that the i-th row of the second LDPC base matrix needs to be eliminated with the θ(i) row when it is expanded, so the i-th row is related to the θ(i)-th row. For example, θ(5) = 3 corresponding to the 5th row indicates that the 3rd row needs to be eliminated with the 5th row, and the result of the elimination is used to replace the 3rd row; for another example, θ(6) = 4 corresponding to the 6th row indicates that the 4th row of the second LDPC base matrix needs to be eliminated with the 6th row, and the result of the elimination is used to replace the 4th row.

[0265] Exemplarily, the above-mentioned elimination process may not be performed at the encoding device end (ie, the transmitting end), and the elimination process may be performed by the decoding device (ie, the receiving end) during decoding.

[0266] Optionally, the protocol may store a basis matrix and an indicator sequence θ corresponding to the basis matrix.

[0267] As can be seen from Figure 12, except for the first four rows of the second LDPC base matrix corresponding to the high code rate area, θ(i)=0, the θ(i) corresponding to the other extended rows is greater than 0. Therefore, the other extended rows are all expanded based on the core rows of the high code rate area.

[0268] The design of the matrix corresponding to the row with θ(i)=0 of the second LDPC base matrix shown in FIG12 may refer to the design rules for the first LDPC base matrix in the above communication method 300 and will not be repeated here.

[0269] The second LDPC base matrix shown in FIG12 can always maintain the characteristics of fast convergence speed and good overall performance during the process of expanding from high code rate to low code rate.

[0270] FIG12 shows a case where the extended rows of the second LDPC base matrix are all extended based on the core rows of the high code rate region. Another possible case is that the extended rows of the second LDPC base matrix are not all extended based on the core rows of the high code rate region, as shown in the second LDPC base matrix in FIG13 .

[0271] In the second LDPC base matrix shown in FIG13 , except for the first four rows corresponding to the high code rate region, θ(i)=0 is set for the extended rows of the 9th row, the extended rows of the 13th row, the extended rows of the 18th row, and the extended rows of the 20th row. Therefore, the extended rows of the 9th row, the extended rows of the 13th row, the extended rows of the 18th row, and the extended rows of the 20th row are irrelevant to the other rows of the second LDPC base matrix. In this case, the extended rows of the 9th row, the extended rows of the 13th row, the extended rows of the 18th row, and the extended rows of the 20th row increase the column weight of the second LDPC base matrix.

[0272] One implementation method is to ensure that the column weight in the high bit rate area is monotonically increasing or monotonically decreasing. This method can give priority to meeting the needs of high bit rate data transmission.

[0273] Exemplarily, the rows corresponding to the high-code rate region in the above implementation are the rows consecutive to the row with the smallest row number θ(i)=0.

[0274] Another implementation method is to control the number of extended rows with θ(i)=0 to be smaller than a first threshold, thereby keeping the column weight of the second LDPC basis matrix consistent with the changing trend of the column weight of the core region.

[0275] Another implementation method is: calculate the column weights of all columns of the second LDPC base matrix corresponding to the lowest code rate, and re-sort them in a monotonically increasing or monotonically decreasing order to form a new second LDPC base matrix that can meet the data transmission requirements of each code rate.

[0276] Exemplarily, the rows of the first submatrix may be all rows in the second LDPC base matrix where θ(i) = 0, and the columns of the first submatrix include information columns and core check columns. If the column weight of the second LDPC base matrix decreases as the number of columns increases, then the extended check columns are located in a region of the second LDPC base matrix where the number of columns is the largest; if the column weight of the second LDPC base matrix increases as the number of columns increases, then the extended check columns are located in a region of the second LDPC base matrix where the number of columns is the smallest.

[0277] Exemplarily, when the second LDPC base matrix shown in FIG12 or FIG13 is arranged in such a manner that the larger the number of columns, the lower the column weight, the extended check column can be placed in the area with the largest number of columns; when the second base matrix shown in FIG12 or FIG13 is arranged in such a manner that the larger the number of columns, the higher the column weight, the extended check column can be placed in the area with the smallest number of columns. In other words, the extended check column can be defaulted to the column with the lowest column weight. It should be noted that the column weight of the second LDPC base matrix is ​​the column weight of the columns of the above-mentioned first submatrix composed of rows with θ(i) = 0.

[0278] The above describes in detail the application of the technical solution provided by the present application in QAM high-order modulation. Compared to the prior art method of mapping the bits of columns with high column weight to the high energy level of the QAM symbol, the embodiments of the present application map the bits of columns with low column weight to the high energy level of the QAM symbol. Specifically, this can be achieved through the interleaving method 200 for performing first interleaving using a first indicator sequence and the communication method 300 for performing row-column interleaving using a first LDPC base matrix provided in the embodiments of the present application, thereby improving the communication performance of wireless communication and accelerating the convergence speed.

[0279] Figure 14 is a performance simulation comparison chart of the interleaving method 200 and communication method 300 provided by the present application and the row-column interleaving method of the prior art. Figure 14 shows a performance simulation comparison chart under different code rates (22 / 24, 22 / 25, 22 / 26, 22 / 27, 22 / 28, 22 / 29, 22 / 30, and 22 / 31). At each code rate, the BLER-SNR performance curve of the "interleaving method 200" or "communication method 300" provided by the present application (such as the "proposed solution" in the figure legend) and the "row-column interleaving" solution of the prior art (such as the "row-column interleaving" in the figure legend) are shown. It can be seen that compared to row-column interleaving, the interleaving method 200 or communication method 300 of the present application converges faster and has performance gains. As the code rate decreases, the convergence speed of the interleaving method 200 or communication method 300 of the present application becomes faster and the performance gain becomes higher.

[0280] The interleaving method provided by the present application has been described in detail above. The following describes the communication device provided by the present application.

[0281] Referring to FIG. 15 , the present application provides a communication device 1000 .

[0282] The communication device 1000 may be an encoding device, or a device applied to an encoding device and capable of implementing the corresponding functions of the encoding device in the embodiment of the method of the present application, such as a chip, a chip system, or a circuit. Alternatively, the communication device 1000 may be a decoding device, or a device applied to a decoding device and capable of implementing the corresponding functions of the decoding device in the embodiment of the method of the present application, such as a chip, a chip system, or a circuit.

[0283] Optionally, the communication device 1000 includes a processing module 1001, which can be a processor, a processing board, a processing unit, or a processing device. When the communication device 1000 is an encoding device or an apparatus applied to an encoding device, the processing module 1001 is configured to perform bit interleaving on the second bit sequence according to the first indicator sequence to obtain a third bit sequence. For the specific process, reference can be made to the detailed description of the interleaving process in the interleaving method 200, which will not be repeated here. When the communication device 1000 is a decoding device or an apparatus applied to a decoding device, the processing module 1001 is configured to demodulate the QAM symbols to be demodulated.

[0284] Optionally, the communication device 1000 further includes a communication module 1002, which may also be referred to as a transceiver module, transceiver, transceiver, or transceiver device, etc., and is configured to perform receiving (or inputting) and / or transmitting (or outputting) operations. For example, when the communication device 1000 is an encoding device or an apparatus applied to an encoding device, the communication module 1002 may be configured to obtain an LDPC base matrix, output modulated QAM symbols, etc. When the communication device 1000 is a decoding device or an apparatus applied to a decoding device, the communication module 1002 may be configured to obtain QAM symbols to be demodulated, etc.

[0285] In addition, it should be noted that the aforementioned communication module and / or processing module can be implemented by a virtual module, for example, the processing module can be implemented by a software functional unit or a virtual device, and the communication module can be implemented by a software function or a virtual device. Alternatively, the processing module or the communication module can also be implemented by a physical device, for example, if the device is implemented using a chip / circuit (such as an integrated circuit or a logic circuit, etc.). The communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operations) and output operations (corresponding to the aforementioned sending operations); the processing module is an integrated processor or microprocessor or circuit (such as an integrated circuit, a logic circuit, etc.).

[0286] The division of modules in this application is illustrative and represents only a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the examples of this application may be integrated into a single processor, exist physically as separate modules, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in either hardware or software functional modules.

[0287] As shown in Figure 16, the present application further provides a communication device 1100. The communication device 1100 includes at least one processor 1110, which implements the functions of the encoding device or decoding device described in the above method embodiments.

[0288] Optionally, the processor 1110 is coupled to a memory, which may be located within the communication device, integrated with the processor, or external to the communication device. The communication device 1100 may further include at least one memory 1120. Memory 1120 stores computer programs, instructions, or data necessary to implement any of the aforementioned method embodiments. Processor 1110 may execute the computer programs, instructions, or data stored in memory 1120 to perform the interleaving method or deinterleaving method of any of the aforementioned embodiments.

[0289] Optionally, the communication device 1100 may further include a communication interface 1130, and the communication device 1100 may exchange information with other devices via the communication interface 1130. Exemplarily, the communication interface 1130 may be a transceiver, circuit, bus, module, pin, or other type of interface.

[0290] Coupling in this application refers to an indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, and is used for information exchange between devices, units, or modules. Processor 1110 may operate in conjunction with memory 1120 and communication interface 1130. This application does not limit the specific connection medium between the processor 1110, memory 1120, and communication interface 1130.

[0291] As shown in Figure 17, the present application also provides a chip (or chip system). The chip (or chip system) 30 may include a circuit 31 and an input / input interface 32. The circuit 31 may be a logic circuit, an integrated circuit, etc., and the input / output interface 32 may also be an input / output circuit, or an interface circuit, which can input information (or receive information) and output information (or send information). Optionally, the chip system can be composed of chips, or it can include chips and other discrete devices. The chip 30 can be used to execute the method performed by the encoding device or the decoding device in each embodiment of the present application.

[0292] In addition, the present application also provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are run on a computer, the operations and / or processing performed by the encoding device or decoding device in each method embodiment of the present application are executed.

[0293] The present application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processing performed by the encoding device or decoding device in the various method embodiments of the present application are executed.

[0294] In addition, the present application further provides a chip, the chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is configured to execute the computer program stored in the memory so that the operations and / or processing performed by the encoding device or the decoding device in any method embodiment are performed.

[0295] Furthermore, the chip may further include a communication interface. The communication interface may be an input / output interface, or an interface circuit, etc. Furthermore, the chip may further include a memory.

[0296] The present application provides a communication system, including the encoding device and decoding device in the above method embodiment.

[0297] In this application, a processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in this application. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in this application may be directly executed by a hardware processor, or by a combination of hardware and software modules within the processor.

[0298] The memory may be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), or a volatile memory, such as a random-access memory (RAM). The memory is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory in this application may also be a circuit or any other device that can perform a storage function, for storing program instructions and / or data.

[0299] The technical solutions provided in this application can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in this application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal device, an access network device, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital video disc (DVD)), or a semiconductor medium.

[0300] In this application, under the premise of no logical contradiction, the examples can reference each other, for example, the methods and / or terms between method embodiments can reference each other, for example, the functions and / or terms between device embodiments can reference each other, for example, the functions and / or terms between device examples and method examples can reference each other.

[0301] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0302] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0303] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0304] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0305] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0306] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0307] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An interleaving method, characterized in that: The method comprises: Obtaining an LDPC base matrix, wherein the LDPC base matrix includes M columns; Encoding the first bit sequence according to the LDPC base matrix to obtain a second bit sequence; bit-interleaving the second bit sequence according to a first indicator sequence to obtain a third bit sequence, wherein the first indicator sequence is used to indicate a correspondence between the M columns and R energy levels included in a quadrature amplitude modulation (QAM) symbol, where M and R are positive integers; Mapping bits in the third bit sequence onto QAM symbols; Output modulated QAM symbols.

2. The method according to claim 1, characterized in that The first indication sequence satisfies at least one of the following characteristics: The elements in the first indicator sequence correspond one-to-one to the columns of the LDPC base matrix; The number of elements S in the first indication sequence is the same as the number of the M columns excluding the punctured columns; The smaller the sequence number of the element in the first indication sequence is, the higher the corresponding energy level is.

3. The method according to claim 1 or 2, characterized in that: The first indicator sequence is used to indicate the corresponding relationship between the M columns and the R energy levels included in the QAM symbol, including: the first indicator sequence is used to indicate the corresponding relationship between K intervals and the R energy levels, K is a positive integer greater than 2, The K intervals are divided according to the columns of the M columns.

4. The method according to claim 3, characterized in that The corresponding relationship between the K intervals and the R energy levels includes: the smaller the column weight of the K intervals, the higher the corresponding energy level.

5. The method according to claim 1 or 2, characterized in that: The first indicator sequence is used to indicate the corresponding relationship between the M columns and the R energy levels included in the QAM symbol, including: the first indicator sequence is used to indicate the corresponding relationship between P sets and the R energy levels, P is a positive integer greater than 2, The P sets are divided according to the types of the M columns, and the types of the M columns include: information columns, core check columns, and extended check columns.

6. The method according to claim 5, characterized in that The first set includes information columns, the second set includes core check columns, and the third set includes extended check columns; Alternatively, the first set includes information columns and core check columns, and the second set includes extended check columns.

7. The method according to claim 5 or 6, characterized in that: The multiple columns included in the first set of the P sets are arranged in ascending order of column weight.

8. The method according to any one of claims 1 to 7, characterized in that The bit interleaving the second bit sequence according to the first indicator sequence to obtain a third bit sequence includes: Perform a first interleaving on the second bit sequence according to the first indicator sequence to obtain a fourth bit sequence; Perform row-column interleaving on the fourth bit sequence to obtain the third bit sequence.

9. The method according to claim 8, characterized in that Assume that the second bit sequence is e, the fourth bit sequence is e1, and e1 and e satisfy the following relationship: Wherein, S represents the number of elements of the first indicator sequence, j represents the index of the sequence number of the element contained in the first indicator sequence, s(j) represents the jth element of the first indicator sequence, and Z c is the lifting value of the LDPC basis matrix.

10. The method according to claim 8 or 9, characterized in that: The first interleaving is performed before circularly buffering the second bit sequence or after circularly buffering the second bit sequence.

11. The method according to any one of claims 1 to 10, characterized in that The M columns are columns corresponding to the lowest code rate supported by the LDPC base matrix, or the M columns are columns corresponding to the highest code rate supported by the LDPC base matrix.

12. The method according to any one of claims 1 to 10, characterized in that Mapping bits in the third bit sequence onto QAM symbols, comprising: mapping bits corresponding to at least one fourth column in the third bit sequence to a first energy level of a QAM symbol, and mapping bits corresponding to at least one fifth column in the third bit sequence to a second energy level of the QAM symbol, the at least one fourth column and the at least one fifth column belonging to the M columns, The column weight of the at least one fourth column is smaller than the column weight of the at least one fifth column and the first energy level is higher than the second energy level.

13. A communication method, characterized in that: The method comprises: Obtain a first LDPC base matrix, where the first LDPC base matrix includes M columns, where the M columns are divided into K intervals according to a column variable, where the column variable is a column weight or a column type of a first submatrix, where the column type includes an information column, a core check column, and an extended check column, and the first submatrix is ​​a partial or complete matrix of the first LDPC base matrix; Encoding the first bit sequence according to the first LDPC base matrix to obtain a second bit sequence; performing bit interleaving on the second bit sequence to obtain a third bit sequence; Mapping bits in the third bit sequence onto QAM symbols; Output modulated QAM symbols.

14. The method according to claim 13, characterized in that When the column variable is the column weight of the first submatrix, the K intervals include the first interval and / or the second interval and / or the third interval, the maximum column weight of at least one second column of the second interval is less than the minimum column weight of at least one first column of the first interval, the minimum column weight of at least one second column of the second interval is greater than the maximum column weight of at least one third column of the third interval, the number of columns of any column in the at least one third column is greater than the number of columns of any column in the at least one second column, and the number of columns of any column in the at least one second column is greater than the number of columns of any column in the at least one first column.

15. The method according to claim 14, characterized in that The smaller the column weight of the K intervals, the higher the corresponding energy level.

16. The method according to any one of claims 13 to 15, characterized in that The first sub-matrix is ​​a matrix corresponding to the lowest code rate supported by the first LDPC base matrix or a matrix corresponding to the highest code rate supported by the first LDPC base matrix.

17. The method according to claim 13, characterized in that When the column variable is a column type, the K intervals include a first interval and / or a second interval and / or a third interval, and the column weight of the at least one first column of the first interval decreases as the number of columns increases. The first interval includes an information column, the second interval includes a core check column, and the third interval includes an extended check column; Alternatively, the first interval includes an information column and a core check column, and the second interval includes an extended check column.

18. The method according to any one of claims 13 to 17, characterized in that The first LDPC base matrix includes N rows, and the i-th row of the N rows corresponds to an indicator sequence θ(i). When θ(i)>0, it means that when the first LDPC basis matrix is ​​expanded from a high code rate to a low code rate, the i-th row is related to the θ(i)-th row, and the i-th row is obtained by eliminating the θ(i)-th row; When θ(i)=0, it means that when the first LDPC base matrix is ​​expanded from a high code rate to a low code rate, the i-th row is independent of other rows of the first LDPC base matrix; The rows of the first submatrix are all rows corresponding to θ(i)=0 in the N rows, and the columns of the first submatrix include information columns and core check columns.

19. The method according to claim 18, characterized in that The extended check column has the largest number of columns.

20. The method according to any one of claims 13 to 19, characterized in that The performing bit interleaving on the second bit sequence to obtain a third bit sequence includes: Assume that the second bit sequence is e, the third bit sequence is f, and f and e satisfy the following relationship: Wherein, E represents the transmission length of the second bit sequence or the third bit sequence, Q m represents the number of bits contained in each modulation symbol, j represents the index of the QAM symbol, and i represents the index of the bit position contained in each QAM symbol.

21. The method according to any one of claims 13 to 20, characterized in that Mapping bits in the third bit sequence onto QAM symbols, comprising: mapping bits corresponding to at least one fourth column in the third bit sequence to a first energy level of a QAM symbol, and mapping bits corresponding to at least one fifth column in the third bit sequence to a second energy level of the QAM symbol, the at least one fourth column and the at least one fifth column belonging to the M columns, The column weight of the at least one fourth column is smaller than the column weight of the at least one fifth column and the first energy level is higher than the second energy level.

22. A communication device, characterized in that: It includes a communication interface and a circuit, the communication interface is used to obtain a first bit sequence to be encoded, and input the first bit sequence to the circuit; the circuit is used to execute the method as described in any one of claims 1-21, encode the first bit sequence, obtain a second bit sequence, and bit interleave the second bit sequence to obtain a third bit sequence, and map the third bit sequence to a QAM symbol; the communication interface is also used to output the modulated QAM symbol.

23. A communication device, characterized in that: It includes a communication interface and a circuit, wherein the communication interface is used to receive QAM symbols to be demodulated and input the QAM symbols to be demodulated to the circuit; the circuit is used to demodulate the QAM symbols to be demodulated to obtain a first information sequence, deinterleave the first information sequence to obtain a second information sequence, and decode the second information sequence to obtain a third information sequence; the communication interface is also used to output the third information sequence.

24. A communication device, characterized in that: The method comprises a module or a unit for executing the method as claimed in any one of claims 1 to 21.

25. A communication device, characterized in that: include: A processor, the processor is coupled to a memory, and the processor is used to execute a computer program or instruction stored in the memory so that the communication device executes the method according to any one of claims 1 to 21.

26. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions. When the computer instructions are executed on a computer, the method according to any one of claims 1 to 21 is implemented.

27. A wireless communication system, characterized in that: Comprising a communication device as claimed in claim 22 and claim 23.

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