Storage unit, memristor array, compute-in-memory circuit, and operation method

Abstract

Provided in the embodiments of the present disclosure are a storage unit, a memristor array, a compute-in-memory circuit and an operation method. The storage unit comprises n weight units and a lateral gate transistor. Each of the n weight units comprises a first memristor element and a first switch element, a first electrode of the first memristor element being electrically connected to a first electrode of the first switch element, and a second electrode of the first memristor element being used as a second end of the corresponding weight unit and being used for receiving a first bit line signal. The second electrodes of the first switch elements of the N weight units are respectively used as the first ends of the corresponding weight units and are electrically connected to each other, and are electrically connected to a first end of the lateral gate transistor. The control electrodes of the first switch elements are respectively used for receiving different first word line signals. A second end of the lateral gate transistor is used for receiving a source line signal, and a control end of the lateral gate transistor is used for receiving a second word line signal.

Description

Storage unit, memristor array, storage-computing integrated circuit and operation method

[0001] This application claims priority to Chinese Patent Application No. 202311657064.4 filed on December 5, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a storage unit, a memristor array, a storage-computing integrated circuit, and an operating method. Background Art

[0003] With the rapid development of artificial intelligence and neural network technologies, the importance of hardware acceleration technology has become increasingly prominent. Storage and computing integration is a computing architecture used for neural network hardware acceleration. The storage cell array also integrates computing functions, significantly reducing data handling and memory access overhead. Taking the memristor storage cell array as an example, the non-volatile conductivity state of the device is used to store network weights. After applying a voltage pulse that encodes the input information, the matrix-vector multiplication result is represented by the output analog current value. This current-type storage and computing integration circuit built on non-volatile devices can be used to achieve highly parallel and high-throughput matrix calculations, greatly improving the system computing power. Among them, the storage cell array is the basic structure of the storage and computing integration system. Different computing accuracy and system computing power, energy efficiency, and cost requirements require matching different array structures. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a storage unit, the storage unit comprising:

[0005] n weight units, where n is a positive integer, each of the n weight units includes a first memristor element and a first switch element, the first memristor element includes a first electrode and a second electrode, and the first switch element includes a control electrode, a first electrode, and a second electrode;

[0006] A transverse gating tube comprising a control end, a first end, and a second end,

[0007] In which, the first electrode of the first memristor element is electrically connected to the first electrode of the first switching element, the second electrode of the first memristor element serves as the second end of the corresponding weight unit and is used to receive the first bit line signal, the second electrodes of the first switching elements of the n weight units are respectively used as the first ends of the corresponding weight units and are electrically connected to each other, and are electrically connected to the first end of the horizontal selection tube, the control electrodes of each of the first switching elements are respectively used to receive different first word line signals, the second end of the horizontal selection tube is used to receive the source line signal, and the control end of the horizontal selection tube is used to receive the second word line signal.

[0008] For example, in the storage unit provided in at least one embodiment of the present disclosure, each of the n weight units also includes a second memristor element and a second switch element, the first electrode of the second memristor element is electrically connected to the first electrode of the second switch element, the second electrode of the second memristor element serves as the third end of the corresponding weight unit and is used to receive a second bit line signal, the control end of the second switch element is electrically connected to the control end of the first switch element, and the second electrode of the second switch element is electrically connected to the second electrode of the first switch element.

[0009] At least one embodiment of the present disclosure provides a memristor array, comprising:

[0010] A plurality of memory cells according to at least one embodiment of the present disclosure, wherein the plurality of memory cells are arranged in m memory cell rows and p memory cell columns along a first direction and a second direction, where m and p are positive integers;

[0011] p groups of first word lines extending along the second direction and connected to the p memory cell columns in a one-to-one correspondence, wherein each of the p groups of first word lines includes n first word lines, and each of the n first word lines is electrically connected to a first electrode of a first switching element of a corresponding memory cell column;

[0012] m second word lines extending along the first direction and connected to the m memory cell rows in a one-to-one correspondence, wherein each of the m second word lines is electrically connected to a control terminal of a lateral selection transistor of a corresponding memory cell row;

[0013] p source lines extending along the second direction and connected to the p memory cell columns in a one-to-one correspondence, wherein each of the p source lines is electrically connected to the second end of the lateral selection transistor of a corresponding memory cell column;

[0014] m first bit lines extend along the first direction and are connected to the m memory cell rows in a one-to-one correspondence, wherein each of the m first bit lines is electrically connected to the second electrode of the first memristor element of a corresponding memory cell row.

[0015] For example, in the memristor array provided in at least one embodiment of the present disclosure, each of the n weight units further includes a second memristor element and a second switch element, and the memristor array further includes:

[0016] m second bit lines extend along the first direction and are connected to the m memory cell rows in a one-to-one correspondence, wherein each of the m second bit lines is electrically connected to the second electrode of the second memristor element of a corresponding memory cell row.

[0017] For example, in at least one embodiment of the present disclosure, the memristor array further includes a driving circuit, wherein the driving circuit includes:

[0018] A bit line driving circuit electrically connected to the first bit line to provide the first bit line signal;

[0019] The word line driving circuit is electrically connected to the second word line to provide the second word line signal.

[0020] For example, in the memristor array provided in at least one embodiment of the present disclosure, the bit line driver circuit includes an amplifier circuit unit, a first output circuit, a second output circuit, a first control circuit, a second control circuit, a third control circuit, a fourth control circuit and a bit line driver output terminal; the amplifier circuit unit includes a first input terminal, a second input terminal and a first output terminal, a second output terminal; the first output circuit is electrically connected to a first node, a first voltage terminal and the bit line driver output terminal, respectively, and is configured to turn on or off the connection between the bit line driver output terminal and the first voltage terminal under the control of the potential of the first node; the second output circuit is electrically connected to a second node, a second voltage terminal and the bit line driver output terminal, respectively, and is configured to turn on or off the connection between the bit line driver output terminal and the first voltage terminal under the control of the potential of the second node. and the second voltage terminal; the first control circuit is electrically connected to the first voltage terminal and the first node, respectively, and is configured to turn on or off the connection between the first node and the first voltage terminal; the second control circuit is electrically connected to the second voltage terminal and the second node, respectively, and is configured to turn on or off the connection between the second node and the second voltage terminal; the third control circuit is electrically connected to the first output terminal of the amplifying circuit unit and the first node, respectively, and is configured to turn on or off the connection between the first node and the first output terminal of the amplifying circuit unit; the fourth control circuit is electrically connected to the second output terminal of the amplifying circuit unit and the second node, respectively, and is configured to turn on or off the connection between the second node and the second output terminal of the amplifying circuit unit.

[0021] For example, in the memristor array provided in at least one embodiment of the present disclosure, the word line drive circuit includes a fifth control circuit, a sixth control circuit and a word line drive output terminal; the fifth control circuit is electrically connected to the first voltage terminal and the word line drive output terminal, respectively, and is configured to turn on or off the connection between the first voltage terminal and the word line drive output terminal; the sixth control circuit is electrically connected to the second voltage terminal and the word line drive output terminal, respectively, and is configured to turn on or off the connection between the second voltage terminal and the word line drive output terminal.

[0022] At least one embodiment of the present disclosure provides a memory-computing integrated circuit, comprising a memristor array as provided in at least one embodiment of the present disclosure.

[0023] At least one embodiment of the present disclosure provides an operating method for a memristor array as provided in at least one embodiment of the present disclosure, the operating method comprising: applying a second selected voltage to a second word line corresponding to a row where a target operating unit is located, applying a first selected voltage to a first word line corresponding to a column where the target operating unit is located, thereby selecting the target operating unit; and applying an operating voltage to a first bit line and a source line corresponding to the target operating unit.

[0024] For example, in the operating method provided in at least one embodiment of the present disclosure, applying an operating voltage to the first bit line and source line corresponding to the target operating unit includes: applying an operating voltage for setting to the first bit line and source line corresponding to the target operating unit.

[0025] For example, in the operating method provided in at least one embodiment of the present disclosure, applying an operating voltage to the first bit line and source line corresponding to the target operating unit includes: applying an operating voltage for resetting to the first bit line and source line corresponding to the target operating unit.

[0026] For example, in the operating method provided in at least one embodiment of the present disclosure, the target operating unit includes a non-zero input unit, and applying an operating voltage to the first bit line and source line corresponding to the target operating unit includes: applying an input signal to the first bit line corresponding to the target operating unit; and applying a source line voltage to the column where the target operating unit is located.

[0027] At least one embodiment of the present disclosure provides an electronic device, comprising: a selection module configured to apply a second selection voltage to a second word line corresponding to a row where a target operation unit is located, and to apply a first selection voltage to a first word line corresponding to a column where the target operation unit is located, thereby selecting the target operation unit; and an operation module configured to apply an operation voltage to a first bit line and a source line corresponding to the target operation unit.

[0028] For example, in the electronic device provided by at least one embodiment of the present disclosure, the operating module is further configured to apply an operating voltage for setting to the first bit line and the source line corresponding to the target operating unit.

[0029] For example, in the electronic device provided by at least one embodiment of the present disclosure, the operating module is further configured to apply an operating voltage for resetting to the first bit line and the source line corresponding to the target operating unit.

[0030] For example, in the electronic device provided by at least one embodiment of the present disclosure, the operating module is further configured to apply an input signal to a first bit line corresponding to the target operating unit; and apply a source line voltage to a column where the target operating unit is located. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0032] FIG1A is a schematic diagram of a common memristor array used for current-mode storage and computing;

[0033] FIG1B is a schematic diagram of another common memristor array used for current-mode storage and computing;

[0034] FIG1C is a schematic diagram of a situation causing calculation errors;

[0035] FIG1D is a schematic diagram of another situation causing calculation errors;

[0036] FIG2A is a schematic diagram of a memory cell based on a 1T1R structure according to at least one embodiment of the present disclosure;

[0037] FIG2B is a schematic diagram of a memory cell based on a 2T2R structure according to at least one embodiment of the present disclosure;

[0038] FIG3A is a schematic diagram of a memristor array provided by at least one embodiment of the present disclosure;

[0039] FIG3B is a schematic diagram of a memristor array provided by at least one embodiment of the present disclosure;

[0040] FIG4A is a schematic diagram of a driving circuit provided by at least one embodiment of the present disclosure;

[0041] FIG4B is a schematic diagram of a driving circuit provided by at least one embodiment of the present disclosure;

[0042] FIG5 is a schematic diagram of a storage-computation-in-one circuit provided by at least one embodiment of the present disclosure;

[0043] FIG6A is a schematic diagram of a set operation method provided by at least one embodiment of the present disclosure;

[0044] FIG6B is a schematic diagram of a reset operation method provided by at least one embodiment of the present disclosure;

[0045] FIG6C is a schematic diagram of a calculation operation method provided by at least one embodiment of the present disclosure; and

[0046] FIG7 is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0049] The memristor array includes multiple rows and columns of memory cells, each memory cell includes a weight unit, and is implemented in the form of a memristor unit. The memristor unit can be a 1T1R structure or a 2T2R structure, wherein the memristor unit of the 1T1R structure includes a switch element and a memristor element, and the first end of the memristor element is electrically connected to the first end of the switch element (such as the drain of the transistor), and the memristor unit of the 2T2R structure includes two switch elements and two memristor elements. The present disclosure has no restrictions on the type, structure, etc. of the memristor element. The memristor element used in the embodiments of the present disclosure can be, for example, a resistive memory, a phase change memory, a conductive bridge memory or other memristor elements with the same characteristics. The switching element used in the embodiments of the present disclosure can be, for example, a thin film transistor, a field effect transistor or other switching elements with the same characteristics. The source and drain of the transistor used here can be symmetrical in structure, so its source and drain can be structurally indistinguishable.

[0050] A memristor element is a non-volatile device whose conductance state can be adjusted by applying an external stimulus. As a two-terminal device, a memristor element has adjustable resistance and is non-volatile, making it widely used in storage and computing. Memristor elements can perform operations directly in the analog domain. For example, a memristor element can perform multiplication operations based on Ohm's law and addition operations based on Kirchhoff's current law. For example, according to Kirchhoff's law, by setting the state of the memristor element (e.g., resistance) and applying corresponding wordline and bitline signals to the wordline and bitline, the memristor array can perform multiplication and accumulation calculations in parallel, with both storage and calculation occurring in each element of the array.

[0051] Writing to a memristor cell can be accomplished by performing set and reset operations on the memristor cell. For example, a set operation can be performed by applying a positive voltage pulse to the bit line while grounding the source line, which lowers the resistance of the memristor cell. A reset operation can be performed by applying a positive voltage pulse to the source line while grounding the bit line, which raises the resistance of the memristor cell. A single set or reset operation can be considered a single write operation.

[0052] A read operation on a memristor cell can include applying a read voltage to the memristor cell, obtaining the current value output by the memristor cell under the influence of the read voltage, and determining the current resistance / conductance value of the memristor cell based on the current value and the read voltage. For example, a read voltage can be applied to a source line, and the resistance / conductance value of the memristor cell can be determined using Ohm's law based on the current value output by a bit line.

[0053] After the memristor cell is manufactured, it needs to be initialized. For example, the initialization operation can be to apply a higher voltage to the memristor cell, that is, to apply a positive voltage pulse to the bit line while grounding the source line. The amplitude and duration of the positive voltage pulse should be higher than that of the set operation. This operation causes the resistance value of the memristor cell to change, giving it an initial resistance value. Because the resistance value of the memristor cell is random, even under the same initialization conditions, the resistance value of each memristor cell will be different.

[0054] The inventors of the present disclosure noticed that in high parallel mode, the traditional array cannot shut down the non-selected weight units, resulting in complex external circuit loads and additional leakage, thereby affecting calculation accuracy and energy efficiency.

[0055] For example, Figure 1A is a schematic diagram of a common memristor array used for current-type storage and computing. In this array, it is necessary to implement multiple columns of weight units (memristor units) to multiplex the analog-to-digital converter (ADC), so vertical word lines WL (WL[0] to WL[3]) are required to control the selection of the columns and turn off the word lines of non-selected columns to reduce additional leakage power consumption. In this array structure, since the selection of the word line will cause all weight units on a column corresponding to a source line SL to be turned on, the array load conductance seen on the ADC side is very large, resulting in large current noise, and the voltage deviation corresponding to zero input will cause leakage, affecting the calculation accuracy.

[0056] For example, Figure 1B is a schematic diagram of another common memristor array used for current-mode memory and computing. In this array, the word lines WL and bit lines BL are parallel. Therefore, for a row with zero (0) input (i.e., input value 0), the word line BL signal can be pulled low to completely shut down the row, thereby reducing the impact of leakage on calculation accuracy in the zero input case. However, this structure is not suitable for the case of multiplexing ADCs with multiple columns. Columns not involved in the calculation will generate additional power consumption, reducing the calculation energy efficiency.

[0057] One type of calculation error is the current error caused by the source line SL clamp voltage deviation. FIG1C shows a schematic diagram of the situation causing this calculation error. FIG1C shows the array current under m input parallelism, where G i Represents the equivalent conductance of the weighted unit in row i, V READ[i] Represents the read voltage of the weight unit in row i, when the voltage on the source line SL is accurately clamped to the clamping voltage V by the analog-to-digital converter ADC CLAMP When the current flowing into the analog-to-digital converter ADC is the ideal current I ideal : I ideal =Σ i G i ·V READ[i]

[0058] When the clamping voltage has a deviation voltage ΔV, it will cause an additional current deviation I ε : I ε =ΔV·Σ i G i

[0059] Among them, the deviation current I ∈ This is equal to the product of the clamping offset voltage ΔV and the corresponding array conductance sum. The clamping offset voltage includes static deviations due to mismatch and dynamic deviations due to factors like noise. The higher the array computational parallelism, the larger the conductance sum, and the greater the current error caused by the clamping offset voltage.

[0060] Another calculation error is the current error caused by the zero input voltage deviation of the bit line BL. FIG1D shows a schematic diagram of the situation causing this calculation error. In an ideal state, the bit line BL voltage corresponding to zero input and the clamping voltage V CLAMP As shown in Figure 1D, the voltage of the bit line BL has a deviation of ΔV i , which can cause leakage current in the zero input row, resulting in serious calculation errors.

[0061] At least one embodiment of the present disclosure provides a memory cell comprising n weight units and a lateral gating tube, where n is a positive integer. Each of the n weight units comprises a first memristor element and a first switch element, the first memristor element comprising a first electrode and a second electrode, and the first switch element comprising a control electrode, a first electrode, and a second electrode. The lateral gating tube comprises a control end, a first end, and a second end. The first electrode of the first memristor element is electrically connected to the first electrode of the first switch element, the second electrode of the first memristor element serves as the second end of the corresponding weight unit and is used to receive a first bit line signal, the second electrodes of the first switch elements of the n weight units serve as the first ends of the corresponding weight units and are electrically connected to each other and to the first end of the lateral gating tube, the control electrodes of the respective first switch elements are respectively used to receive different first word line signals, the second end of the lateral gating tube is used to receive a source line signal, and the control end of the lateral gating tube is used to receive a second word line signal.

[0062] The storage unit provided by at least one embodiment of the present disclosure can effectively utilize input sparsity and completely shut down non-selected weight units to improve calculation accuracy by introducing a lateral selection tube and a second word line signal control; at least one embodiment of the present disclosure can also be further used for efficient multiplexing of peripheral circuits, avoiding the leakage problem of traditional memristor array structures.

[0063] The following non-restrictive description of the storage unit provided according to the present disclosure is provided through multiple embodiments and examples. As described below, different features in these specific examples or embodiments can be combined with each other without conflicting with each other to obtain new examples or embodiments, and these new examples or embodiments also fall within the scope of protection of the present disclosure.

[0064] FIG. 2A is a schematic diagram of a memory cell based on a 1T1R structure according to at least one embodiment of the present disclosure.

[0065] For example, as shown in FIG2A , the memory cell 30 based on the 1T1R structure provided by the embodiment of the present disclosure includes n weight units 10 and a lateral gate tube 20, where n is a positive integer. Each weight unit 10 includes a first memristor element 101 and a first switch element 102, that is, the weight unit is a 1T1R structure, the first memristor element 101 includes a first electrode 1011 and a second electrode 1012, and the first switch element 102 includes a first electrode 1021, a second electrode 1022, and a control electrode 1023. The lateral gate tube 20 includes a first terminal 201, a second terminal 202, and a control terminal 203.

[0066] For example, as shown in FIG2A , the first electrode 1011 of the first memristor element 101 is electrically connected to the first electrode 1021 of the first switch element 102. The second electrode 1012 of the first memristor element 101 serves as the second end of the corresponding weight unit 102 and is used to receive the first bit line (BL) signal. The second electrodes 1022 of the first switch elements 102 of the n weight units serve as the first ends of the corresponding weight units 102 and are electrically connected to each other and to the first end 201 of the lateral gate transistor 20. In FIG2A , WV[0], WV[1], ..., WV[n-1] represent the first, second, ..., nth first word lines, respectively. The control electrode 1023 of each first switch element is used to receive a different first word line (WV) signal. The second end 202 of the lateral gate transistor 20 is used to receive the source line SL signal, and the control end 203 of the lateral gate transistor 20 is used to receive the second word line (WH) signal.

[0067] The first word line signal controls the multiplexing of the n weight units in the storage unit 30. For a weight unit that needs to be selected for calculation, the first word line signal corresponding to the weight unit can be enabled, and the current of the weight unit can be connected to the first terminal 201 of the lateral selection transistor 20 to enable participation in the calculation; for an unselected weight unit, the first word line signal corresponding to the weight unit can be pulled low to achieve shutdown.

[0068] FIG. 2B is a schematic diagram of a memory cell based on a 2T2R structure according to at least one embodiment of the present disclosure.

[0069] For example, as shown in FIG2B , a memory cell 40 based on a 2T2R structure provided in an embodiment of the present disclosure includes n weight units 10 and a lateral gate transistor 20, where n is a positive integer. Each weight unit 10 includes a first memristor element 101, a first switch element 102, a second memristor element 103, and a second switch element 104, i.e., the weight unit has a 2T2R structure.

[0070] For example, as shown in FIG2B , the first electrode 1031 of the second memristor element 103 is electrically connected to the first electrode 1041 of the second switch element 104, the second electrode 1032 of the second memristor element 103 serves as the third terminal of the corresponding weight unit 10 and is used to receive the second bit line BLD signal, the control terminal 1043 of the second switch element 104 is electrically connected to the control terminal 1023 of the first switch element 102, and the second electrode 1042 of the second switch element 104 is electrically connected to the second electrode 1022 of the first switch element 102. The connection method of the remaining components is similar to that in FIG2A and will not be repeated here.

[0071] FIG3A is a schematic diagram of a memristor array provided by at least one embodiment of the present disclosure. The memristor array includes a plurality of memory cells 30 based on the 1T1R structure shown in FIG2A .

[0072] For example, referring to Figures 2A and 3A, the memristor array includes p groups of first word lines WV (WV[n-1:0] to WV[pn-1:(p-1)n]), m second word lines WH (WH[0] to WH[m-1]), p source lines SL (SL[0] to SL[p-1]), and m first bit lines BL (BL[0] to BL[m-1]), as well as a plurality of memory cells 30 as shown in Figure 2A, arranged along a first direction D1 and a second direction D2 into m memory cell rows and p memory cell columns. Each group of first word lines WV includes n first word lines, for example, WV[n-1:0]. m, n, p, etc. are positive integers and are not further described below.

[0073] For example, the p-group first word lines WV extend along the second direction D2 and are connected one-to-one with the p-column memory cells 30. Each group of the p-group first word lines WV includes n first word lines, and each of the n first word lines WV is electrically connected to the first pole of the first switch element of the corresponding column of memory cells 30. Taking the first word line WV[n-1:0] as an example, the first word line WV[n-1:0] realizes the control of multiplexing of the n weight units in the memory cell 30. For the weight unit that needs to be selected to participate in the calculation, the first word line signal corresponding to the weight unit can be enabled, and the weight unit current can be connected to the first end of the horizontal selection tube to realize participation in the calculation; for the unselected weight unit, the first word line signal corresponding to the weight unit can be pulled down to realize shutdown.

[0074] For example, m second word lines WH extend along the first direction D1 and are connected one-to-one to m rows of memory cells 30. Each of the m second word lines WH is electrically connected to the control terminal of the lateral selection transistor of a corresponding row of memory cells 30. The second word line WH controls the conduction of the lateral selection transistor, determining whether to connect the current of the weight unit selected by the first word line WV to the source line SL.

[0075] For example, p source lines SL extend along the second direction D2 and are connected one-to-one with p columns of memory cells 30. Each of the p source lines SL is electrically connected to the second end of the lateral select transistor of the corresponding column of memory cells 30. The n weight units in a memory cell 30 multiplex a set of source lines SL for output.

[0076] For example, m first bit lines BL extend along the first direction D1 and are connected one-to-one with m rows of memory cells 30. Each of the m first bit lines BL is electrically connected to the second electrode of the first memristor element of a corresponding row of memory cells 30. The n weight units in one memory cell 30 share a set of first bit lines BL inputs.

[0077] In the case of zero (0) input, the second word line signal of the corresponding row is pulled low to turn off the selection tube. At this time, the corresponding weight unit is disconnected from the source line, which effectively eliminates the leakage caused by the zero input voltage deviation of the first bit line, reduces the total conductance load on the source line, and improves the calculation accuracy.

[0078] FIG3B is a schematic diagram of a memristor array provided by at least one embodiment of the present disclosure, wherein the memristor array includes the memory cell 40 based on the 2T2R structure in FIG2B .

[0079] For example, referring to Figures 2B and 3B , the memristor array further includes m second bit lines BLD (BLD[0] to BLD[m-1]). For example, the m second bit lines BLD extend along the first direction D1 and are connected to m rows of memory cells 40 in a one-to-one correspondence. Each of the m second bit lines BLD is electrically connected to the second electrode of the second memristor element of a corresponding row of memory cells 40. The remaining components of the memristor array and their connection methods are similar to those in Figure 3A and are not further described here.

[0080] The memristor array provided in at least one embodiment of the present disclosure also includes various driving circuits, which include bit line driving circuits and word line driving circuits. For example, as needed, they may also include input circuits, output circuits, etc. For example, the input circuit may include a digital-to-analog converter (DAC), etc., and the output circuit may include an analog-to-digital converter (ADC), etc.

[0081] For example, the bit line driving circuit is electrically connected to the first bit line BL to provide a first bit line signal.

[0082] For example, the bit line driver circuit includes an amplifier circuit unit OTA, a first output circuit PM0, a second output circuit NM0, a first control circuit SW1, a second control circuit SW2, a third control circuit SW3, a fourth control circuit SW4, and a bit line driver output terminal OB. For example, the bit line driver circuit adopts a Class-AB output stage design.

[0083] For example, the amplifying circuit unit OTA includes a first input terminal VIP, a second input terminal VIN, a first output terminal, and a second output terminal.

[0084] For example, the first output circuit PM0 is electrically connected to the first node N1, the first voltage terminal V1 and the bit line driver output terminal OB, respectively, and is configured to turn on or off the connection between the bit line driver output terminal OB and the first voltage terminal V1 under the control of the potential of the first node N1; the second output circuit NM0 is electrically connected to the second node N2, the second voltage terminal V0 and the bit line driver output terminal OB, respectively, and is configured to turn on or off the connection between the bit line driver output terminal OB and the second voltage terminal V0 under the control of the potential of the second node N2.

[0085] For example, the first control circuit SW1 is electrically connected to the first voltage terminal V1 and the first node N1, respectively, and is configured to turn on or off the connection between the first node N1 and the first voltage terminal V1; the second control circuit SW2 is electrically connected to the second voltage terminal V0 and the second node N2, respectively, and is configured to turn on or off the connection between the second node N2 and the second voltage terminal V0; the third control circuit SW3 is electrically connected to the first output terminal of the amplifying circuit unit OTA and the first node N1, respectively, and is configured to turn on or off the connection between the first node N1 and the first output terminal of the amplifying circuit unit OTA; the fourth control circuit SW4 is electrically connected to the second output terminal of the amplifying circuit unit OTA and the second node N2, respectively, and is configured to turn on or off the connection between the second node N2 and the second output terminal of the amplifying circuit unit OTA.

[0086] It should be noted that, in the case of a 2T2R structure, the memristor array also includes a second bit line. In this case, the driving voltages required for the first bit line and the second bit line are different. Therefore, two bit line driving circuits are required for each row of the memristor array, which are electrically connected to the first bit line and the second bit line respectively to provide the first bit line signal and the second bit line signal.

[0087] For example, the word line driving circuit is electrically connected to the second word line to provide a second word line signal.

[0088] For example, the word line driver circuit includes a fifth control circuit SW5, a sixth control circuit SW6, and a word line driver output terminal OW. The fifth control circuit SW5 is electrically connected to the first voltage terminal V1 and the word line driver output terminal OW, respectively, and is configured to connect or disconnect the first voltage terminal V1 and the word line driver output terminal OW. The sixth control circuit SW6 is electrically connected to the second voltage terminal V0 and the word line driver output terminal OW, respectively, and is configured to connect or disconnect the second voltage terminal V0 and the word line driver output terminal OW.

[0089] As shown in FIG4A , in the case of zero input, the voltage applied to the first input terminal VIP of the amplifier circuit unit OTA is equal to the clamping voltage on the source line SL. At this time, the first control circuit SW1 and the second control circuit SW2 are turned on, and the third control circuit SW3 and the fourth control circuit SW4 are turned off, so that the control terminal of the first output circuit PM0 is connected to the first voltage terminal V1, and the control terminal of the second output circuit NM0 is connected to the second voltage terminal V2. For example, the first voltage terminal V1 is a power supply, and the second voltage terminal V2 is ground (GND).

[0090] As shown in Figure 4B , in the presence of a non-zero input, the voltage applied to the first input terminal VIP of the amplifier circuit unit OTA is equal to the sum of the input voltage and the clamping voltage. At this point, the first and second control circuits SW1 and SW2 are disconnected, while the third and fourth control circuits SW3 and SW4 are turned on. This connects the control terminals of the first and second output circuits PM0 and NM0 to the two output terminals of the amplifier circuit unit OTA, respectively. The bitline driver output terminal OB outputs the calculated voltage required for the first bitline BL. Simultaneously, the fifth control circuit SW5 is turned on, the sixth control circuit SW6 is turned off, and the wordline driver output terminal OW outputs the voltage required to drive the second wordline WH, thereby raising the voltage of the corresponding second wordline WH.

[0091] For example, the first input terminal VIP and the second input terminal VIN of the amplifier circuit unit OTA are connected in a feedback structure, that is, in the form of a unity-gain buffer. Therefore, there is no need to apply a voltage to VIN. The VIN voltage is consistent with the VIP voltage through the feedback virtual short circuit, so that the two output terminals of the amplifier circuit unit OTA output the same voltage.

[0092] Based on the above driving circuit, not only the weight unit corresponding to zero input can be completely turned off, but also the bit line driving circuit of the row corresponding to zero input can be completely turned off, which greatly reduces the computing power consumption of the network when the input sparsity is high.

[0093] FIG5 is a schematic diagram of a storage-computation-in-one circuit provided by at least one embodiment of the present disclosure.

[0094] As shown in FIG5 , the memory-computing integrated circuit includes a memristor array provided by at least one of the above-described embodiments, the memristor array including p groups of first word lines WV (WV[n-1:0] to WV[pn-1:(p-1)n]), m second word lines WH (WH[0] to WH[m-1]), p source lines SL (SL[0] to SL[p-1]), and m first bit lines BL (BL[0] to BL[m-1]), as well as a plurality of memory cells 30 arranged along a first direction D1 and a second direction D2 into m memory cell rows and p memory cell columns. The memristor array also includes a drive circuit 50, which includes a bit line drive circuit 51 and a word line drive circuit 52.

[0095] As shown in Figure 5, the integrated storage and computing circuit further includes an input circuit 61, an output circuit 62, a first word line programming and driving circuit 71, a second word line programming and driving circuit 72, a first bit line programming and driving circuit 73, and a source line programming and driving circuit 74. The input circuit 61 includes a plurality of digital-to-analog converters (DACs), and the output circuit 62 includes a plurality of analog-to-digital converters (ADCs).

[0096] For example, m digital-to-analog converters DAC (DAC[0] to DAC[m-1]) are electrically connected one-to-one to the bit line driving circuit 51 of the corresponding row. The digital-to-analog converter DAC is used to convert the input digital signal into an analog signal so as to input the analog signal to the first input terminal of the amplifier circuit unit of the corresponding bit line driving circuit when performing parallel calculation.

[0097] For example, the first word line programming drive circuit 71 is electrically connected to the first word line WV (WV[n-1:0]~WV[pn-1:(p-1)n]) to provide a first word line programming signal, and the second word line programming drive circuit 72 is electrically connected to the second word line WH (WH[0]~WH[m-1]) to provide a second word line programming signal. The first word line programming signal and the second word line programming signal can be used to select the unit that needs to be operated.

[0098] For example, the first bit line programming drive circuit 73 is electrically connected to the first bit line BL (BL[0]~BL[m-1]) to provide a first bit line programming signal, and the source line programming drive circuit 74 is electrically connected to the source line SL (SL[0]~SL[p-1]) to provide a source line programming signal. The first bit line programming signal can be used to provide a set voltage to a unit that needs to be set, and the source line programming signal can be used to provide a reset voltage to a unit that needs to be reset.

[0099] For example, p analog-to-digital converters ADC (ADC[0] to ADC[p-1]) are electrically connected to source lines SL (SL[0] to SL[p-1]) in a one-to-one correspondence. The analog-to-digital converters ADC are used to convert analog signals into digital signals and provide a clamping voltage to the source lines for calculation. The n weight units of each storage cell in the memristor array reuse the same ADC circuit, and the first word line WV controls which of the n weight units participates in the calculation. This circuit architecture can improve the calculation accuracy and energy efficiency of the integrated storage and computing circuit.

[0100] For example, the integrated storage and computing circuit may further include a pre-control circuit (not shown) that provides control voltages to the first to sixth control circuits in the bit line driver circuit 51 based on whether the input digital signal is zero or non-zero data. For example, the pre-control circuit may include analog / digital circuits, etc.

[0101] It should be noted that, in the case of a 2T2R structure, the memristor array further includes a second bit line. In this case, the integrated storage and computing circuit further includes a second bit line programming driver circuit. The second bit line programming driver circuit is electrically connected to the second bit line to provide a second bit line programming signal. The second bit line programming signal can be used to provide a set voltage to a cell requiring a set operation. In addition, in the case of a 2T2R structure, the remaining components of the integrated storage and computing circuit and their connection methods are similar to those in FIG5 and are not described in detail here.

[0102] At least one embodiment of the present disclosure further provides an operating method for the memristor array as described above, comprising step S1 and step S2.

[0103] Step S1 : applying a second selected voltage to a second word line corresponding to a row where a target operation unit is located, and applying a first selected voltage to a first word line corresponding to a column where a target operation unit is located, thereby selecting the target operation unit.

[0104] For example, the first selected voltage may be applied by the first word line programming and driving circuit 71 as shown in FIG. 5 , and the second selected voltage may be applied by the second word line programming and driving circuit 72 as shown in FIG. 5 .

[0105] Step S2: applying an operating voltage to the first bit line and the source line corresponding to the target operation unit.

[0106] For example, a memristor array includes an operating mode and a computational mode. When the memristor array is in the operating mode, the memristor cells are initialized, and the values ​​of the elements in the matrix to be multiplied can be written into the memristor array, for example, by mapping weight values ​​to the conductance values ​​of the memristors. This writing is accomplished, for example, through set and reset operations.

[0107] For example, when performing a set operation, step S2 further includes: applying an operating voltage for setting to the first bit line and the source line corresponding to the target operation unit.

[0108] FIG6A is a schematic diagram of a set operation method provided by at least one embodiment of the present disclosure. As shown in FIG6A , the specific operation method is:

[0109] Applying a second selected voltage to the second word line WH[1] corresponding to the row where the target operation unit to be set is located, and applying a first selected voltage to the first word line WV[n-1] corresponding to the column where the target operation unit is located, thereby selecting the target operation unit to be set;

[0110] Apply a set voltage V to the first bit line BL[1] corresponding to the target operation unit. SET, pull down the voltage on the source line SL[0] corresponding to the target operation unit, and pull down the voltage on the other signal lines, thereby achieving the set operation on the target operation unit. For example, the set voltage V SET The first bit line voltage may be applied by the first bit line programming driving circuit 73 as shown in FIG. 5 , and the source line voltage may be applied by the source line programming driving circuit 74 as shown in FIG. 5 .

[0111] For example, when performing a reset operation, step S2 further includes: applying an operation voltage for resetting to the first bit line and the source line corresponding to the target operation unit.

[0112] FIG6B is a schematic diagram of a reset operation method provided by at least one embodiment of the present disclosure. As shown in FIG6B , the specific operation method is as follows:

[0113] Applying a second selected voltage to the second word line WH[1] corresponding to the row where the target operation unit to be reset is located, and applying a first selected voltage to the first word line WV[n-1] corresponding to the column where the target operation unit is located, thereby selecting the target operation unit to be reset;

[0114] Apply a reset voltage V to the source line SL[0] corresponding to the target operation unit. RESET , pull down the voltage on the first bit line BL[1] corresponding to the target operation unit, and pull down the voltage on the other signal lines, thereby achieving the reset operation of the target operation unit. For example, the first bit line voltage can be applied by the first bit line programming driving circuit 73 shown in FIG5 , and the reset voltage V RESET It can be applied through the source line programming driver circuit 74 as shown in FIG5 .

[0115] For example, when the memristor array is in computing mode, the memristors in the memristor array are in a conductive state that can be used for computing, and the voltage input on the first bit line does not change the conductance value of the memristor. For example, multiplication and addition operations can be performed through the memristor array to complete the calculation.

[0116] For example, when performing a parallel computing operation, the target operation unit includes a non-zero input unit, and step S2 further includes: applying an input signal to a first bit line corresponding to the target operation unit, and applying a source line voltage to the column where the target operation unit is located.

[0117] FIG6C is a schematic diagram of a parallel computing operation method provided by at least one embodiment of the present disclosure. As shown in FIG6C , the specific operation method is:

[0118] Apply the second selected voltage to the second word lines WH[0] to WH[m-1] corresponding to the rows of all target operation cells participating in the calculation, and apply the first selected voltage to the first word lines WV[0] to WV[n-1] corresponding to the columns of all target operation cells participating in the calculation, thereby selecting the target operation cells participating in the calculation. Specifically, assuming that only the second row of the entire array has zero inputs, and the remaining rows have non-zero inputs, then for non-zero input cells, the voltages on the corresponding second word lines WH[0], WH[2] to WH[m-1] are pulled high, and for zero input cells, the voltage on the corresponding second word line WH[1] is pulled low;

[0119] An input signal is applied to the first bit lines BL[0]-BL[m-1] corresponding to the target operation unit, and a clamping voltage is applied to the source line SL[0] of the column where the target operation unit is located, thereby implementing a parallel computing operation. For example, the input digital signal can be first converted to an analog signal by a digital-to-analog converter DAC, and then the computing voltage, i.e., the input signal applied to the first bit line, is output through the bit line driver circuit 51. For example, the clamping voltage applied to the source line can be provided by an analog-to-digital converter ADC.

[0120] At least one embodiment of the present disclosure further provides an electronic device. Figure 7 is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure. The electronic device may be, for example, a server device or a terminal device, such as a server, a computer, a controller, etc.

[0121] For example, as shown in FIG. 7 , the electronic device 700 includes a selection module 701 and an operation module 702 .

[0122] For example, the selection module 701 is configured to apply a second selection voltage to the second word line corresponding to the row where the target operation unit is located, and apply a first selection voltage to the first word line corresponding to the column where the target operation unit is located, thereby selecting the target operation unit. For example, the selection module 701 may include the first word line programming drive circuit 71 and the second word line programming drive circuit 72 as shown in Figure 5.

[0123] For example, the operating module 702 is configured to apply an operating voltage to a first bit line and a source line corresponding to the target operating unit.

[0124] For example, the operation module 702 is further configured to apply a set operation voltage to the first bit line and source line corresponding to the target operation unit. For example, the operation module 702 is further configured to apply a reset operation voltage to the first bit line and source line corresponding to the target operation unit. For example, the operation module 702 may include the first bit line programming driver circuit 73 and the source line programming driver circuit 74 shown in FIG. 5 .

[0125] For example, the operation module 702 is further configured to apply an input signal to the first bit line corresponding to the target operation unit and apply a source line voltage to the column where the target operation unit is located. For example, the operation module 702 may also include the input circuit 61, the output circuit 62, and the bit line driver circuit 51 shown in FIG5.

[0126] For the relevant contents of the selection module 701 and the operation module 702, reference may be made to the relevant descriptions of step S1 and step S2 in the embodiment of the above operation method, which will not be repeated here.

[0127] One or more embodiments of the present disclosure provide a memory cell, a memristor array, a memory-computing integrated circuit, an operating method, and an electronic device, which have one or more of the following beneficial effects:

[0128] (1) The memory cell provided by at least one embodiment of the present disclosure can be effectively applied to a memristor array. By introducing a lateral gating tube and a lateral second word line signal control, the row corresponding to zero input can be completely shut down, thereby reducing the source line conductance and load, reducing the zero input leakage current, and improving the calculation accuracy.

[0129] (2) The memristor array provided by at least one embodiment of the present disclosure, including a bit line driving circuit and a lateral second word line driving circuit, can effectively reduce the power consumption of the peripheral circuit under zero input, thereby improving the computing energy efficiency of the system in a highly sparse network.

[0130] (3) The integrated storage and computing circuit provided by at least one embodiment of the present disclosure is implemented based on the memristor array of the storage unit of the above embodiment, and can be used to solve the problem of reduced calculation accuracy caused by excessive array conductivity load in high-parallel integrated storage and computing.

[0131] (3) The integrated storage and computing circuit provided by at least one embodiment of the present disclosure is implemented based on the memristor array of the storage unit of the above embodiment, and can be combined with a switchable driving circuit to effectively improve the computing efficiency of the integrated storage and computing when calculating a network with high input sparsity.

[0132] Although the present disclosure has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made based on the embodiments of the present disclosure. Therefore, such modifications or improvements, as long as they do not depart from the spirit of the present disclosure, are within the scope of protection claimed by the present disclosure.

[0133] Regarding this disclosure, the following points need to be explained:

[0134] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0135] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale.

[0136] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0137] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A storage unit, comprising: n weight units, wherein n is a positive integer, each of the n weight units comprises a first memristor element and a first switch element, the first memristor element comprises a first electrode and a second electrode, and the first switch element comprises a control electrode, a first electrode and a second electrode; A transverse gating tube includes a control end, a first end, and a second end. Among them, the first electrode of the first memristor element is electrically connected to the first electrode of the first switch element, the second electrode of the first memristor element serves as the second end of the corresponding weight unit and is used to receive the first bit line signal, the second electrodes of the first switch elements of the n weight units are respectively used as the first ends of the corresponding weight units and are electrically connected to each other and to the first end of the lateral selection tube, the control electrodes of each of the first switch elements are respectively used to receive different first word line signals, the second end of the lateral selection tube is used to receive the source line signal, and the control end of the lateral selection tube is used to receive the second word line signal.

2. The storage unit according to claim 1, wherein: Each of the n weight units further includes a second memristor element and a second switch element, The first electrode of the second memristor element is electrically connected to the first electrode of the second switch element, the second electrode of the second memristor element serves as the third end of the corresponding weight unit and is used to receive a second bit line signal, the control end of the second switch element is electrically connected to the control end of the first switch element, and the second electrode of the second switch element is electrically connected to the second electrode of the first switch element.

3. A memristor array, comprising: A plurality of memory cells according to claim 1, wherein the plurality of memory cells are arranged in m memory cell rows and p memory cell columns along a first direction and a second direction, where m and p are positive integers; p groups of first word lines extending along the second direction and connected to the p memory cell columns in a one-to-one correspondence, wherein each of the p groups of first word lines includes n first word lines, and each of the n first word lines is electrically connected to a first electrode of a first switch element of a corresponding memory cell column; m second word lines extending along the first direction and connected to the m memory cell rows one by one, wherein each of the m second word lines is electrically connected to a control terminal of a lateral selection transistor of a corresponding memory cell row; p source lines extending along the second direction and connected to the p memory cell columns one by one, wherein each of the p source lines is electrically connected to the second end of a lateral selection tube of a corresponding memory cell column; m first bit lines extend along the first direction and are connected to the m memory cell rows in a one-to-one correspondence, wherein each of the m first bit lines is electrically connected to the second electrode of the first memristor element of a corresponding memory cell row.

4. The memristor array according to claim 3, wherein: Each of the n weight units further includes a second memristor element and a second switch element, The memristor array further comprises: m second bit lines extend along the first direction and are connected to the m memory cell rows in a one-to-one correspondence, wherein each of the m second bit lines is electrically connected to the second electrode of the second memristor element of a corresponding memory cell row.

5. The memristor array according to claim 3 or 4, further comprising a driving circuit, wherein: The driving circuit comprises: A bit line driving circuit, electrically connected to the first bit line to provide the first bit line signal; The word line driving circuit is electrically connected to the second word line to provide the second word line signal.

6. The memristor array according to claim 5, wherein: The bit line driving circuit comprises an amplifying circuit unit, a first output circuit, a second output circuit, a first control circuit, a second control circuit, a third control circuit, a fourth control circuit and a bit line driving output terminal; The amplifying circuit unit comprises a first input terminal, a second input terminal, a first output terminal, and a second output terminal; The first output circuit is electrically connected to the first node, the first voltage terminal and the bit line driver output terminal respectively, and is configured to switch on or off the connection between the bit line driver output terminal and the first voltage terminal under the control of the potential of the first node; The second output circuit is electrically connected to the second node, the second voltage terminal and the bit line driver output terminal respectively, and is configured to switch on or off the connection between the bit line driver output terminal and the second voltage terminal under the control of the potential of the second node; The first control circuit is electrically connected to the first voltage terminal and the first node respectively, and is configured to switch on or off the connection between the first node and the first voltage terminal; The second control circuit is electrically connected to the second voltage terminal and the second node respectively, and is configured to switch on or off the connection between the second node and the second voltage terminal; The third control circuit is electrically connected to the first output terminal of the amplifier circuit unit and the first node respectively, and is configured to turn on or off the connection between the first node and the first output terminal of the amplifier circuit unit; The fourth control circuit is electrically connected to the second output terminal of the amplifier circuit unit and the second node respectively, and is configured to switch on or off the connection between the second node and the second output terminal of the amplifier circuit unit.

7. The memristor array according to claim 5 or 6, wherein: The word line driving circuit comprises a fifth control circuit, a sixth control circuit and a word line driving output terminal; The fifth control circuit is electrically connected to the first voltage terminal and the word line driving output terminal respectively, and is configured to switch on or off the connection between the first voltage terminal and the word line driving output terminal; The sixth control circuit is electrically connected to the second voltage terminal and the word line driving output terminal respectively, and is configured to switch on or off the connection between the second voltage terminal and the word line driving output terminal.

8. A storage and computing integrated circuit, comprising a memristor array as described in any one of claims 3 to 7.

9. A method for operating a memristor array according to any one of claims 3 to 7, comprising: Applying a second selected voltage to a second word line corresponding to a row where a target operation unit is located, and applying a first selected voltage to a first word line corresponding to a column where a target operation unit is located, thereby selecting the target operation unit; An operating voltage is applied to a first bit line and a source line corresponding to the target operation unit.

10. The operating method according to claim 9, wherein: The step of applying an operating voltage to a first bit line and a source line corresponding to the target operating unit comprises: An operation voltage for setting is applied to a first bit line and a source line corresponding to the target operation unit.

11. The operating method according to claim 9, wherein: The step of applying an operating voltage to a first bit line and a source line corresponding to the target operating unit comprises: An operation voltage for resetting is applied to a first bit line and a source line corresponding to the target operation unit.

12. The operating method according to any one of claims 9 to 11, wherein: The target operation unit includes a non-zero input unit, The applying an operating voltage to a first bit line and a source line corresponding to the target operating unit comprises: Applying an input signal to a first bit line corresponding to the target operation unit; Applying a source line voltage to the column where the target operation unit is located.

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