Output circuit

Abstract

An output circuit (1) is provided with a plurality of output drive circuits (10) connected to an output node (out), and each output drive circuit (10) is provided with a plurality of output buffers (20). Each output buffer (20) is provided with a first transistor of a first conductivity type and a first resistor that are provided in series with each other between a first power supply node and the output node (out), and a second transistor of a second conductivity type provided in series with the first resistor between a second power supply node and the output node. On the basis of a first control signal, one of the first transistor or the second transistor operates, and the other stops.

Description

Output Circuit

[0001] The present invention relates to an output circuit that outputs a signal to the outside of a semiconductor device (LSI (Large Scale Integration)).

[0002] Recently, there are many LSI-to-LSI interface specifications associated with a wide variety of LSI mounting structures, and there are technologies for transmitting high-speed data in gigabit units. Output circuits for high-speed data transmission must be able to meet output impedance specifications in particular.

[0003] For example, Patent Document 1 discloses an output circuit that realizes a plurality of output impedance characteristics by arranging a plurality of circuit blocks (drive units) each having a predetermined output impedance value and selectively operating them. Patent Document 2 discloses an output circuit that realizes a plurality of frequency characteristics and voltage characteristics by mixing transistors of different conductivity types in an output driver and selectively operating them.

[0004] U.S. Patent No. 7,961,008 U.S. Patent No. 1,404,094

[0005] Here, there is no prior art example disclosed in which an output circuit such as that in Patent Document 2 constitutes a drive unit such as that in Patent Document 1 in order to realize a plurality of output impedance characteristics.

[0006] An object of the present disclosure is to provide an output circuit that can accommodate a variety of output characteristics, is suppressed from increasing in area, and operates at high speed.

[0007] In one aspect of the present disclosure, an output circuit includes a plurality of output driver circuits connected to the output node, each of the output driver circuits including a plurality of output buffers, each of the output buffers including a first transistor of a first conductivity type and a first resistor arranged in series with each other between a first power supply node and the output node, and a second transistor of a second conductivity type arranged in series with the first resistor between a second power supply node and the output node, and one of the first transistor or the second transistor operates and the other stops based on a first control signal.

[0008] In the above-described embodiment, in each output driver circuit, a first transistor of a first conductivity type is provided between the first power supply node and the output node, and a second transistor of a second conductivity type is provided between the second power supply node and the output node. By mixing transistors of different conductivity types in this manner, the number of units in the output driver circuit can be reduced compared to when an output driver circuit is configured for each transistor of a different conductivity type. By reducing the number of units, the area occupied by the output circuit can be reduced.

[0009] In addition, the first resistor is shared between the first and second transistors. This reduces the amount of resistor elements used and the footprint of the output circuit. Note that the larger the impedance value per unit of the output driver circuit, the larger the footprint of the resistor elements used. In such cases, the footprint reduction effect is more pronounced. Furthermore, if the footprint of the resistor elements can be reduced, the parasitic capacitance attached to the output node decreases, resulting in a faster transition (slew rate) of the output signal. This results in a waveform with a good eye pattern opening, enabling the output of a high-speed signal with a short cycle time.

[0010] In the above aspect, transistors of different conductivity types are selectively operated in each output driver circuit. This makes it possible to generate a full-amplitude output signal and a small-amplitude output signal. Here, the small-amplitude output signal is effective for outputting a high-speed signal. Furthermore, in this embodiment, variation is added by dividing the power supply into a first power supply node and a second power supply node. This makes it possible to output output signals that comply with a wide variety of external interface specifications.

[0011] The output circuit of the present disclosure can accommodate a variety of output characteristics, suppresses an increase in area, and is capable of high-speed operation.

[0012] 1 is a block diagram showing an example of the configuration of an output circuit according to the first embodiment; a circuit diagram showing an example of the configuration of an output driving circuit according to the first embodiment; a block diagram showing an example of the configuration of a data processing unit according to the first embodiment; a circuit diagram showing an example of the configuration of a data processing unit according to the first embodiment; a truth table showing an example of the operation of the data processing unit; a block diagram showing an example of the configuration of an output circuit according to the second embodiment; a circuit diagram showing an example of the configuration of an output driving circuit according to the second embodiment; a block diagram showing an example of the configuration of a data processing unit according to the second embodiment; a circuit diagram showing an example of the configuration of an output driving circuit according to the third embodiment; a block diagram showing an example of the configuration of an output driving circuit according to the fourth embodiment; a block diagram showing an example of the configuration of an output circuit according to the fifth embodiment; a circuit diagram showing an example of the configuration of an output driving circuit according to the fifth embodiment; a block diagram showing an example of the configuration of a data processing unit according to the fifth embodiment; a block diagram showing a modified example of the data processing unit according to the first embodiment; a circuit diagram showing a modified example of the output driving circuit according to the first embodiment; a diagram showing an example of an output signal waveform output from an output terminal; a diagram showing an example of output impedance characteristics;

[0013] Hereinafter, embodiments will be described. Note that specific numerical values ​​and the like shown in the following embodiments are merely examples to facilitate understanding of the invention, and are not intended to limit the scope of the invention.

[0014] In the following explanation, the nodes and terminals of a circuit and the signals passing through those nodes and terminals may be described using common symbols or names, and the names of power supplies and the power supply voltages of those power supplies may be described using common symbols. The voltages of each terminal and each node may be written as "(terminal name or node name) = (symbol indicating voltage)." Specifically, if the voltage of the output node out is VDD1 (the voltage of the power supply VDD1), it may be written as out = VDD1. Similarly, the signals of each terminal and each node may be written as "(signal name) = (signal state)." The gate-source voltage Vgs of a transistor may be written simply as "Vgs."

[0015] First Embodiment An output circuit 1 is a circuit that outputs an output signal out according to an input signal in input from an input terminal IN to the outside of an LSI via an output terminal OUT.

[0016] 1, the output circuit 1 includes a plurality of output drive circuits 10 connected to an output node out, and an output control circuit 30. The output circuit 1 in FIG. 1 includes n (n: natural number) output drive circuits 10. In FIG. 1, the output drive circuits 10 are denoted by the symbols DRV[0], DRV[1], ..., DRV[n-1].

[0017] -Output Drive Circuit- FIG. 2 is a circuit diagram showing an example of the configuration of the output drive circuit 10 according to this embodiment.

[0018] 2, each output driver circuit 10 includes a plurality of output buffers 20. The plurality of output buffers 20 are arranged in parallel between power supply nodes VDD1, VDD2 and a ground node VSS. The output driver circuit 10 in FIG. 2 includes m (m: natural number) output buffers 20.

[0019] The output buffer 20 is, for example, a push-pull structure with a pull-up transistor and a pull-down transistor.

[0020] Specifically, each output buffer 20 includes a P-type pull-up transistor Pu, an N-type pull-up transistor Nu, a pull-up resistor Ru, a pull-down resistor Rd, and an N-type pull-down transistor Nd.

[0021] In this embodiment, P-type corresponds to the "first conductivity type," and N-type corresponds to the "second conductivity type." Furthermore, the pull-up transistor Pu corresponds to the "first transistor," the pull-up transistor Nu corresponds to the "second transistor," and the pull-down transistor Nd corresponds to the "third transistor." Furthermore, the pull-up resistor Ru corresponds to the "first resistor," and the pull-down resistor Rd corresponds to the "second resistor."

[0022] The pull-up transistor Pu is provided between a power supply node VDD2 (corresponding to a "first power supply node") and a node Au (corresponding to a first node), and a control line pu2 is connected to its gate. The pull-up transistor Nu is provided between a power supply node VDD1 (corresponding to a "second power supply node") and a node Au, and a control line pu1 is connected to its gate. The pull-up resistor Ru is provided between the node Au and an output node out. Note that in this disclosure, "connection" is a concept that broadly encompasses electrical connection. That is, "connection" in this disclosure includes not only direct connection but also indirect electrical connection via a passive element or the like.

[0023] In other words, a pull-up transistor Pu and a pull-up resistor Ru are provided in series between the power supply node VDD2 and the output node out. Also, a pull-up transistor Nu and a pull-up resistor Ru are provided in series between the power supply node VDD1 and the output node out. In other words, the pull-up transistor Pu and the pull-up transistor Nu share the pull-up resistor Ru.

[0024] The pull-down transistor Nd is provided between a ground node VSS (corresponding to a "third power supply node") and a node Ad (corresponding to a second node), and a control line pd is connected to its gate. The pull-down resistor Rd is provided between the node Ad and an output node out. In other words, the pull-down transistor Nd and the pull-down resistor Rd are provided in series between the ground node VSS and the output node out.

[0025] Here, the voltage of the power supply node VDD1 is equal to or lower than the voltage of the power supply node VDD2. That is, VDD1≦VDD2. The voltage of the ground node VSS is lower than the voltages of the power supply nodes VDD1 and VDD2.

[0026] The source of the pull-up transistor Pu is connected to the power supply node VDD2. Therefore, when the pull-up transistor Pu is turned on, the gate-source voltage (Vgs) becomes "Vgs = VDD2," ensuring stable operation. A full-amplitude signal between the power supply voltage VDD2 and the reference voltage (ground) is output from the output terminal OUT (see the first waveform from the top in Figure 19).

[0027] The drain of the pull-up transistor Nu is connected to the power supply node VDD1. Therefore, when the pull-up transistor Nu is on, the voltage of the output signal out output from the output terminal OUT becomes "VDD1-Vthn" (Vthn: threshold value of NMOS) (see the second waveform from the top in FIG. 19).

[0028] As described above, since VDD1≦VDD2, when the pull-up transistor Nu is turned on, a signal with a lower voltage and smaller amplitude is output compared to when the pull-up transistor Pu is turned on. For example, a small-amplitude signal is effective for high-speed output with a short cycle time.

[0029] The output impedance value of the output driver circuit 10 is not particularly limited, but is determined based on, for example, the specifications of the external interface connected to the output terminal OUT and the area efficiency of the output circuit 1. In this case, the output impedance value of each output driver circuit 10 may be designed to be large in order to comply with various output impedance standards. Furthermore, some or all of the multiple output driver circuits 10 may have a common impedance value, or may have different impedance values. The same applies to the output impedance values ​​of output driver circuits 10 according to other embodiments described below.

[0030] 2, the output buffers 20 are labeled BUF[0], BUF[1], ..., BUF[m-1]. The components included in each BUF[0:m-1] and the control lines connected to those components are also labeled in the same way. Specifically, for the components included in BUF[0], the pull-up transistor is represented as Pu[0], the pull-up transistor is represented as Nu[0], the pull-up resistor is represented as Ru[0], the pull-down transistor is represented as Nd[0], and the pull-down resistor is represented as Rd[0]. The gate of the pull-up transistor Pu[0] is connected to the control line pu2[0], the gate of the pull-up transistor Nu[0] is connected to the control line pu1[0], and the gate of the pull-down transistor Nd is connected to the control line pd[0]. The same applies to BUF[1], ..., BUF[m-1].

[0031] Returning to FIG. 1, the output circuit 1 is provided with, in addition to the input terminal IN and the output terminal OUT, selection terminals MSELU, CDRV[0:n-1], CBUFU[0:m-1], CBUFD[0:m-1] and an enable control terminal OEN.

[0032] - Output Control Circuit - The output control circuit 30 outputs control signals pu1[0:m-1], pu2[0:m-1], and pd[0:m-1] to each output driver circuit 10 (DRV[0:n-1]). The control signal pu2[0:m-1] controls the operation / stop of the pull-up transistor Pu[0:m-1] of each output buffer 20 (BUF[0:m-1]). Similarly, the control signal pu1[0:m-1] controls the operation / stop of the pull-up transistor Nu[0:m-1], and the control signal pd[0:m-1] controls the operation / stop of the pull-down transistor Nd[0:m-1].

[0033] More specifically, for example, the control signal pu2[0] controls the operation / stop of the pull-up transistor Pu[0] of the output buffer 20 (BUF[0]). The control signal pu1[0] controls the operation / stop of the pull-up transistor Nu[0] of the output buffer 20 (BUF[0]). The control signal pd[0] controls the operation / stop of the pull-down transistor Nd[0] of the output buffer 20 (BUF[0]). The same applies to the control of the operation / stop of the output buffer 20 (BUF[1:m-1]). The control signals pu1[0:m-1] and pu2[0:m-1] correspond to first control signals.

[0034] An input signal in is input to the output control circuit 30 via an input terminal IN. Selection signals mselu, cdrv[0:n-1], cbufu[0:m-1], cbufd[0:m-1] and an enable control signal oen are input to the output control circuit 30 via selection terminals MSELU, CDRV, CBUFU, CBUFD and an enable control terminal OEN, respectively.

[0035] The selection terminal MSELU is a selection terminal for the pull-up transistor, and the selection signal mselu collectively selects the pull-up transistor Pu or the pull-up transistor Nu of all the output drive circuits 10. For example, when "mselu=1", the pull-up transistor Pu is selected in all the output drive circuits 10, and when "mselu=0", the pull-up transistor Nu is selected in all the output drive circuits 10.

[0036] The selection terminals CDRV[0:n-1] are selection terminals of the output driving circuits 10, and the selection signals cdrv[0:n-1] select whether to drive or stop the output driving circuits 10 corresponding to the respective selection signals cdrv[0:n-1]. For example, when "cdrv[0] = 1", the output driving circuit 10 (DRV[0]) is driven, and when "cdrv[0] = 0", the output driving circuit 10 (DRV[0]) is stopped. Similarly, the selection signals cdrv[1:n-1] select whether to drive or stop each output driving circuit 10 (DRV[1:n-1]). The number of output driving circuits 10 to be driven is determined, for example, by the external interface specifications of the output terminal OUT. For example, if the output impedance of each output driver circuit 10 is designed to be uniformly 150 [Ω], and the output impedance standard corresponds to an external interface specification of 30 [Ω], the number of output driver circuits 10 to be driven will be 150 [Ω] ÷ 30 [Ω] = 5. The selection signal cdrv[0:n-1] corresponds to the second control signal.

[0037] The selection terminal CBUFU[0:m-1] is a selection terminal for the drive transistor (pull-up side), and the selection signal cbufu[0:m-1] selects whether to drive or stop the pull-up transistor (pull-up transistor Pu or pull-up transistor Nu) selected by the selection signal mselu in the output drive circuit 10 corresponding to each selection signal cdrv[0:n-1]. For example, when "mselu=1" and "cbufu[0]=1", the pull-up transistor Pu of the output buffer 20 (BUF[0]) is driven, and when "mselu=1" and "cbufu[0]=0", the pull-up transistor Pu of the output buffer 20 (BUF[0]) is stopped. Also, for example, when "mselu=0" and "cbufu[0]=1", the pull-up transistor Nu of the output buffer 20 (BUF[0]) is driven, and when "mselu=0" and "cbufu[0]=0", the pull-up transistor Nu of the output buffer 20 (BUF[0]) is stopped. Similarly, the selection signal cbufu[1:m-1] selects whether to drive or stop the pull-up transistor (pull-up transistor Pu or pull-up transistor Nu) in each output buffer 20 (BUF[1:n-1]).

[0038] The selection terminal CBUFD[0:m-1] is a selection terminal for the drive transistor (pull-down side), and the drive / stop of the pull-down transistor Nd is selected by the selection signal cbufd[0:m-1]. For example, the pull-down transistor Nd of the output buffer 20 (BUF[0]) is driven when "cbufd[0]=1", and the pull-down transistor Nd of the output buffer 20 (BUF[0]) is stopped when "cbufd[0]=0". Similarly, the drive / stop of the pull-down transistor Nd of the specified output buffer 20 (BUF[1:m-1]) is selected by the selection signal cbufd[1:m-1].

[0039] The selection signals cbufu[0:m-1] and cbufd[0:m-1] correspond to the third control signal.

[0040] Here, the number of transistors (pull-up transistors (Pu or Nu) and pull-down transistors Nd) driven by the selection signals cbufu[0:m-1] and cbufd[0:m-1] is determined so as to match the output impedance standard in the specifications of the external interface connected to the output terminal OUT. The impedance of the output buffer 20 may be affected by variations in the manufacturing process of the elements, the ambient temperature, the power supply voltage, and the like. Therefore, for example, if an error in the output impedance standard is specified, the number of transistors to be driven must be adjusted appropriately in accordance with that specification.

[0041] The selection signals cbufu[0:m-1] and cbufd[0:m-1] are generated, for example, by a logic circuit (not shown) within the LSI. In particular, when high accuracy in output impedance is required, a calibration circuit (not shown) may be used to fine-tune the impedance.

[0042] The enable control signal oen selects whether to drive or stop all of the output drive circuits 10. For example, when "oen=1", all of the output drive circuits 10 (DRV[0:n-1]) are driven, and when "oen=0", all of the output drive circuits 10 (DRV[0:n-1]) are stopped. In other words, when the enable control signal oen is set to an enable state (hereinafter also referred to as "drive"), that is, when "oen=1" is set, the input signal in input to the input terminal IN is output to the output terminal OUT as the output signal out. On the other hand, when the enable control signal oen is set to a disable state (hereinafter also referred to as "stop"), that is, when "oen=0" is set, the output signal out becomes indefinite (high impedance) regardless of the state of the input signal in.

[0043] Figure 5 shows an example of a truth table showing the relationship between the inputs (input signal in, each selection signal mselu, cdrv, cbufu[0:m-1], cbufd[0:m-1], and enable control signal oen) and outputs (control signals pu1[0:m-1], pu2[0:m-1], pd[0:m-1]) and output signal out of the output control circuit 30.

[0044] The output control circuit 30 includes data processing units 40 and 50 that implement the logical functions of the truth table of FIG. 5. FIGS. 3 and 4 show examples of logic circuit configurations that implement the logical functions of the truth table of FIG. 5. However, the configuration of the output control circuit 30 is not limited to the examples of FIGS. 3 and 4, and other circuit configurations having equivalent logical functions may be used. Furthermore, some of the functions of the data processing units 40 and 50 may be implemented by a program installed in a microcontroller (not shown) or the like. This also applies to other embodiments described below.

[0045] [Effects of the First Embodiment] In this embodiment, each output driver circuit 10 is configured to include a mixture of pull-up transistors Pu and Nu of different conductivity types. This allows the number of units in the output driver circuit 10 to be reduced compared to when a separate output driver circuit 10 is configured for each pull-up transistor Pu and Nu. The reduced number of units allows the area occupied by the output circuit 1 to be reduced.

[0046] In this embodiment, the pull-up transistors Pu and Nu share a pull-up resistor Ru. This reduces the amount of resistors used and the footprint of the output circuit 1 compared to when separate pull-up resistors Ru are used for each pull-up transistor Pu and Nu. In the output circuit 1, the resistance value of the pull-up resistor Ru tends to be designed to be larger than the on-resistance of the transistors in order to maintain the linearity of the output impedance characteristics. Therefore, the larger the impedance value per unit of the output driver circuit 10, the larger the footprint of the resistors used. In such cases, the effect of this embodiment is more pronounced.

[0047] Furthermore, if the layout area of ​​the resistor element can be reduced, the parasitic capacitance of the output node out and the output terminal OUT will decrease, and the transition (slew rate) of the output signal will become faster. In other words, the opening of the so-called eye diagram, which is a result of overlapping sampling waveforms, will become a waveform with good opening, making it possible to output a high-speed signal with a short cycle time.

[0048] In this embodiment, pull-up transistors Pu and Nu of different conductivity types are selectively operated in each output driver circuit 10. This allows for the generation of a full-amplitude output signal out and a small-amplitude output signal out. In other words, they can be used interchangeably. Here, the small-amplitude output signal is effective for outputting high-speed signals. Furthermore, in this embodiment, the power supplies VDD1 and VDD2 can also have different power supply voltages, adding variation. This allows for the output signal out to be output in accordance with a wide variety of external interface specifications.

[0049] Second Embodiment FIG. 6 shows an example of a circuit diagram of an output circuit 1 according to a second embodiment. In FIG. 6, components corresponding to those in FIG. 1 are assigned common reference numerals. The following description will focus on differences from the first embodiment. Note that elements (e.g., transistors and resistors) assigned the same reference numerals in FIGS. 1 and 6 are not intended to be limited to the same design parameters / process parameters, etc. In other words, the technical scope of the present disclosure includes configurations in which the various parameters of elements assigned the same reference numerals in FIGS. 1 and 6 are different from each other. The same applies to the relationships between the other drawings.

[0050] The output circuit 1 of this embodiment is different from the first embodiment in the configuration of the output drive circuit 10. Accordingly, the control signals input to the output drive circuit 10 and the configuration of the output control circuit 30 are also different.

[0051] 7 is a circuit diagram showing an example of the configuration of an output driver circuit 10 according to this embodiment. As in the first embodiment, the output driver circuit 10 includes a plurality of output buffers 20.

[0052] In this embodiment, each output buffer 20 includes a P-type pull-up transistor Pu as the pull-up transistor, and an N-type pull-down transistor Nd and a P-type pull-up transistor Pd as the pull-down transistors. Also, as in the first embodiment, each output buffer 20 includes a pull-up resistor Ru and a pull-down resistor Rd.

[0053] In this embodiment, N-type corresponds to the "first conductivity type," and P-type corresponds to the "second conductivity type." Furthermore, the pull-down transistor Nd corresponds to the "first transistor," the pull-down transistor Pd corresponds to the "second transistor," and the pull-up transistor Pu corresponds to the "third transistor." Furthermore, the pull-down resistor Rd corresponds to the "first resistor," and the pull-up resistor Ru corresponds to the "second resistor."

[0054] Specifically, the pull-up transistor Pu is provided between a power supply node VDD (corresponding to the "third power supply node") and a node Au (corresponding to the second node), and a control line pu is connected to the gate of the pull-up transistor Pu. The pull-up resistor Ru is provided between the node Au and the output node out. In other words, the pull-up transistor Pu and the pull-up resistor Ru are provided in series between the power supply node VDD and the output node out.

[0055] The pull-down transistor Nd is provided between a ground node VSS (corresponding to a "first power supply node") and a node Ad (corresponding to a first node), and has a gate connected to a control line pd1. The pull-down transistor Pd is provided between the ground node VSS (corresponding to a "second power supply node") and the node Ad, and has a gate connected to a control line pd2. The pull-down resistor Rd is provided between the node Ad and an output node out.

[0056] In other words, a pull-down transistor Nd and a pull-down resistor Rd are connected in series between the ground node VSS and the output node out. Also, a pull-down transistor Pd and a pull-down resistor Rd are connected in series between the ground node VSS and the output node out. That is, the pull-down transistor Nd and the pull-down transistor Pd share the pull-down resistor Rd.

[0057] Here, the voltage of the power supply node VDD is greater than the voltage of the ground node VSS, i.e., VDD>VSS.

[0058] The source of the pull-down transistor Nd is connected to the ground node VSS, so that when the pull-down transistor Nd is turned on, a full-amplitude signal is output from the output terminal OUT.

[0059] The drain of the pull-down transistor Pd is connected to the power supply node VSS. Therefore, when the pull-down transistor Pd is on, the voltage of the output signal out output from the output terminal OUT becomes "VSS+Vthp" (Vthp: PMOS threshold value).

[0060] As described above, when the pull-down transistor Pd is turned on, a signal with a lower voltage and smaller amplitude is output compared to when the pull-down transistor Nd is turned on. For example, a small-amplitude signal is effective for high-speed output with a short cycle time.

[0061] 7, similarly to FIG. 2, the output buffers 20 are denoted by symbols BUF[0], BUF[1], ..., BUF[m-1]. The components included in each BUF[0:m-1] and the control lines connected to these components are also denoted in the same manner.

[0062] - Output Control Circuit - As shown in FIG. 6, the output control circuit 30 outputs control signals pu[0:m-1], pd1[0:m-1], and pd2[0:m-1] to each output drive circuit 10 (DRV[0:n-1]).

[0063] 7, the control signal pu[0:m-1] controls whether the pull-up transistors Pu[0:m-1] of each output buffer 20 (BUF[0:m-1]) are enabled or disabled. Similarly, the control signal pd1[0:m-1] controls whether the pull-down transistors Nd[0:m-1] are enabled or disabled, and the control signal pd2[0:m-1] controls whether the pull-down transistors Pd[0:m-1] are enabled or disabled.

[0064] 6, similarly to the first embodiment, an input signal in is input via an input terminal IN to the output control circuit 30. Selection signals mseld, cdrv[0:n-1], cbufu[0:m-1], cbufd[0:m-1] and an enable control signal oen are input via selection terminals MSELD, CDRV, CBUFU, CBUFD and an enable control terminal OEN to the output control circuit 30, respectively.

[0065] The selection terminal MSELD is a selection terminal for the pull-down transistor, and the selection signal mseld collectively selects the pull-down transistor Nd or the pull-down transistor Pd of all the output drive circuits 10. For example, when "mseld=1", the pull-down transistor Nd is selected in all the output drive circuits 10, and when "mseld=0", the pull-down transistor Pd is selected in all the output drive circuits 10.

[0066] The selection terminals CDRV, CBUFU, CBUFD and the enable control terminal OEN, as well as the selection signals cdrv[0:n-1], cbufu[0:m-1], cbufd[0:m-1] and the enable control signal oen are the same as in the first embodiment, and detailed explanations thereof will be omitted here.

[0067] The output control circuit 30 includes data processing units 40 and 50 that implement the logical functions of the truth table corresponding to Fig. 5. Figs. 8 and 9 show examples of the configuration of a logic circuit that implements the logical functions of the truth table corresponding to Fig. 5. However, the configurations are not limited to the examples of Figs. 8 and 9, and other circuit configurations having equivalent logical functions may also be used.

[0068] [Operation and Effects of Second Embodiment] In this embodiment, the same effects as in the first embodiment can be obtained.

[0069] Specifically, compared to configuring an output drive circuit 10 corresponding to each pull-down transistor Nd, Pd, the number of units in the output drive circuit 10 can be reduced. By reducing the number of units, the area occupied by the output circuit 1 can be reduced.

[0070] Since the pull-down resistor Rd is shared by the pull-down transistors Nd and Pd, it is possible to reduce the amount of resistor elements used and the area occupied by the output circuit 1. In addition, the transition (slew rate) of the output signal out becomes faster, enabling the output of a high-speed signal with a short cycle time.

[0071] By selectively operating the pull-down transistors Nd and Pd of different conductivity types, it is possible to generate an output signal out with a small amplitude, and also to output an output signal out that complies with a wide variety of external interface specifications.

[0072] Third Embodiment This embodiment differs from the first embodiment in that each output buffer 20 includes a P-type pull-down transistor Pd as a pull-down transistor. Other configurations (e.g., the configurations of the pull-up transistors (Nu, Pu), pull-up resistor Ru, pull-down resistor Rd of the output buffer 20, and the output control circuit 30) are the same as those of the first embodiment.

[0073] 10 shows an example of the configuration of an output driver circuit 10 according to this embodiment. As in the first embodiment, the output driver circuit 10 includes a plurality of output buffers 20.

[0074] As described above, the output buffer 20 includes a P-type pull-down transistor Pd as a pull-down transistor. That is, each output buffer 20 includes a P-type pull-up transistor Pu, an N-type pull-up transistor Nu, a pull-up resistor Ru, a pull-down resistor Rd, and a P-type pull-down transistor Pd.

[0075] In this embodiment, N-type corresponds to the "first conductivity type," and P-type corresponds to the "second conductivity type." Furthermore, the pull-up transistor Nu corresponds to the "first transistor," the pull-up transistor Pu corresponds to the "second transistor," and the pull-down transistor Pd corresponds to the "third transistor." Furthermore, the pull-up resistor Ru corresponds to the "first resistor," and the pull-down resistor Rd corresponds to the "second resistor." Furthermore, the power supply node VDD1 corresponds to the first power supply node, and the power supply node VDD2 corresponds to the second power supply node.

[0076] Here, the voltage of the power supply node VDD1 is equal to or lower than the voltage of the power supply node VDD2. That is, VDD1≦VDD2. The voltage of the ground node VSS is lower than the voltages of the power supply nodes VDD1 and VDD2.

[0077] In this embodiment, when the pull-down transistor Pd is on, i.e., when the "control signal pd=0," the drain voltage of the pull-down transistor Pd, i.e., the low output voltage of the output node out, becomes out=VSS+Vthp, and a small-amplitude signal is output. Specifically, for example, when the pull-up transistor Nu is selected and the pull-down transistor Pd is on, the output terminal OUT outputs the waveform shown in the first row from the bottom in FIG. 19. Also, when the pull-up transistor Pu is selected and the pull-down transistor Pd is on, the output terminal OUT outputs the waveform shown in the second row from the bottom in FIG.

[0078] [Operation and Effects of the Third Embodiment] In this embodiment, the same effects as in the first embodiment can be obtained.

[0079] Specifically, compared to configuring an output drive circuit 10 corresponding to each of the pull-up transistors Nu and Pu, the number of units in the output drive circuit 10 can be reduced. By reducing the number of units, the area occupied by the output circuit 1 can be reduced.

[0080] Because the pull-up resistor Ru is shared by the pull-up transistors Nu and Pu, it is possible to reduce the amount of resistor elements used and the area occupied by the output circuit 1. Furthermore, the reduction in the layout area of ​​the resistor elements reduces the parasitic capacitance attached to the output node out and the output terminal OUT, which speeds up the transition (slew rate) of the output signal out and enables the output of a high-speed signal with a short cycle time.

[0081] By selectively operating the pull-up transistors Nu and Pu of different conductivity types, it is possible to generate an output signal out with a small amplitude, and also to output an output signal out that complies with a wide variety of external interface specifications.

[0082] Fourth Embodiment This embodiment differs from the second embodiment in that each output buffer 20 includes an N-type pull-up transistor Nu as a pull-up transistor. Other configurations (e.g., the configurations of the pull-down transistors (Nd, Pd) of the output buffer 20, the pull-up resistor Ru, the pull-down resistor Rd, and the output control circuit 30) are the same as those of the second embodiment.

[0083] 11 shows an example of the configuration of an output driver circuit 10 according to this embodiment. As in the second embodiment, the output driver circuit 10 includes a plurality of output buffers 20.

[0084] As described above, the output buffer 20 includes an N-type pull-up transistor Nu as a pull-up transistor. That is, each output buffer 20 includes an N-type pull-up transistor Nu, a pull-up resistor Ru, a pull-down resistor Rd, a P-type pull-down transistor Pd, and an N-type pull-down transistor Nd.

[0085] In this embodiment, P-type corresponds to the "first conductivity type," and N-type corresponds to the "second conductivity type." Furthermore, the pull-down transistor Pd corresponds to the "first transistor," the pull-down transistor Nd corresponds to the "second transistor," and the pull-up transistor Nu corresponds to the "third transistor." Furthermore, the pull-down resistor Rd corresponds to the "first resistor," and the pull-up resistor Ru corresponds to the "second resistor." Furthermore, the ground node VSS corresponds to the first power supply node and the second power supply node, and the power supply node VDD corresponds to the third power supply node.

[0086] Here, the voltage of the power supply node VDD is greater than the voltage of the ground node VSS, i.e., VDD>VSS.

[0087] In this embodiment, when the pull-up transistor Nu is on, i.e., when the "control signal pu=1", the drain voltage of the pull-up transistor Nu, i.e., the High output voltage of the output node out, becomes out=VDD-Vthn (Vthn: NMOS threshold), and therefore a small amplitude signal is output.

[0088] [Operation and Effects of the Fourth Embodiment] In this embodiment, the same effects as in the first embodiment can be obtained.

[0089] Specifically, compared to configuring an output drive circuit 10 corresponding to each pull-down transistor Nd, Pd, the number of units in the output drive circuit 10 can be reduced. By reducing the number of units, the area occupied by the output circuit 1 can be reduced.

[0090] Since the pull-down resistor Rd is shared by the pull-down transistors Nd and Pd, it is possible to reduce the amount of resistor elements used and the area occupied by the output circuit 1. Furthermore, the reduction in the layout area of ​​the resistor elements reduces the parasitic capacitance attached to the output node out and the output terminal OUT, which speeds up the transition (slew rate) of the output signal out and enables the output of a high-speed signal with a short cycle time.

[0091] By selectively operating the pull-down transistors Nd and Pd of different conductivity types, it is possible to generate an output signal out with a small amplitude, and also to output an output signal out that complies with a wide variety of external interface specifications.

[0092] Fifth Embodiment Fig. 12 is a circuit diagram showing an example of the configuration of an output circuit 1 according to this embodiment. As in the first embodiment, the output circuit 1 includes a plurality of output drive circuits 10. In Fig. 12, components corresponding to those in Fig. 1 are assigned the same reference numerals. The following description will focus on the differences from the first embodiment.

[0093] The output circuit 1 of this embodiment is different from the first embodiment in the configuration of the output drive circuit 10. Accordingly, the control signals input to the output drive circuit 10 and the configuration of the output control circuit 30 are also different.

[0094] 13 is a circuit diagram showing an example of the configuration of an output driver circuit 10 according to this embodiment. As in the first embodiment, the output driver circuit 10 includes a plurality of output buffers 20.

[0095] In this embodiment, each output buffer 20 includes a P-type pull-up transistor Pu and an N-type pull-up transistor Nu as pull-up transistors, and an N-type pull-down transistor Nd and a P-type pull-down transistor Pd as pull-down transistors. Similarly to the first embodiment, each output buffer 20 also includes a pull-up resistor Ru and a pull-down resistor Rd. That is, this embodiment differs from the first embodiment in that each output buffer 20 includes a P-type pull-down transistor Pd as a pull-down transistor in addition to the N-type pull-down transistor Nd.

[0096] Specifically, the pull-down transistor Nd is provided between a ground node VSS (corresponding to a "third power supply node") and a node Ad (corresponding to a second node), and has a gate connected to a control line pd1. The pull-down transistor Pd is provided between the ground node VSS and the node Ad, and has a gate connected to a control line pd2. The pull-down resistor Rd is provided between the node Ad and an output node out.

[0097] In this embodiment, P-type corresponds to the "first conductivity type," and N-type corresponds to the "second conductivity type." Furthermore, the pull-up transistor Pu corresponds to the "first transistor," the pull-up transistor Nu corresponds to the "second transistor," the pull-down transistor Pd corresponds to the "third transistor," and the pull-down transistor Nd corresponds to the "fourth transistor." Furthermore, the pull-up resistor Ru corresponds to the "first resistor," and the pull-down resistor Rd corresponds to the "second resistor."

[0098] As in the first embodiment, the voltage of the power supply node VDD1 is equal to or lower than the voltage of the power supply node VDD2. That is, VDD1≦VDD2. The voltage of the ground node VSS is lower than the voltages of the power supply nodes VDD1 and VDD2. As a result, when the pull-up transistor Nu is turned on, a signal with a lower voltage and smaller amplitude is output compared to when the pull-up transistor Pu is turned on. For example, a small-amplitude signal is effective for high-speed output with a short cycle time.

[0099] As in the second embodiment, the pull-down transistor Nd has a source connected to the ground node VSS. Therefore, when the pull-down transistor Nd is turned on, a full-amplitude signal is output from the output terminal OUT. The pull-down transistor Pd has a drain connected to the power supply node VSS. Therefore, when the pull-down transistor Pd is turned on, the voltage of the output signal out output from the output terminal OUT becomes "VSS+Vthp" (Vthp: PMOS threshold value), and a small-amplitude signal is output from the output terminal OUT.

[0100] 12, the output control circuit 30 outputs control signals pu1[0:m-1], pu2[0:m-1], pd1[0:m-1], and pd2[0:m-1] to each output drive circuit 10 (DRV[0:n-1]). The control signal pu1[0:m-1] controls the operation / stop of the pull-up transistors Nu[0:m-1] of each output buffer 20 (BUF[0:m-1]). Similarly, the control signal pu2[0:m-1] controls the operation / stop of the pull-up transistor Pu[0:m-1] of each output buffer 20 (BUF[0:m-1]), the control signal pd1[0:m-1] controls the operation / stop of the pull-down transistor Nd[0:m-1], and the control signal pd2[0:m-1] controls the operation / stop of the pull-down transistor Pd[0:m-1].

[0101] As in the first embodiment, an input signal in is input to the output control circuit 30 via an input terminal IN. Selection signals mselu, mseld, cdrv[0:n-1], cbufu[0:m-1], cbufd[0:m-1] and an enable control signal oen are input to the output control circuit 30 via selection terminals MSELU, MSELD, CDRV, CBUFU, CBUFD and an enable control terminal OEN, respectively.

[0102] As in the second embodiment, the selection terminal MSELD is a selection terminal for the pull-down transistors, and the selection signal mseld collectively selects the pull-down transistors Nd or Pd of all the output drive circuits 10. For example, when "mseld=1", the pull-down transistors Nd are selected in all the output drive circuits 10, and when "mseld=0", the pull-down transistors Pd are selected in all the output drive circuits 10.

[0103] The selection terminals MSELU, CDRV, CBUFU, CBUFD and the enable control terminal OEN, as well as the selection signals mselu, cdrv[0:n-1], cbufu[0:m-1], cbufd[0:m-1] and the enable control signal oen are the same as in the first embodiment, and detailed explanations thereof will be omitted here.

[0104] The output control circuit 30 includes data processing units 40 and 50 that implement the logical functions of the truth table corresponding to Fig. 5. Figs. 14 and 15 show examples of the configuration of a logic circuit that implements the logical functions of the truth table corresponding to Fig. 5. However, the configuration is not limited to the examples of Figs. 14 and 15, and other circuit configurations having equivalent logical functions may also be used.

[0105] [Operation and Effects of Fifth Embodiment] In this embodiment, the same effects as in the first embodiment can be obtained.

[0106] Specifically, compared to configuring output drive circuits 10 corresponding to each of pull-up transistors Nu and Pu and pull-down transistors Nd and Pd, the number of units in output drive circuit 10 can be reduced. The reduction in the number of units allows the area occupied by output circuit 1 to be reduced.

[0107] Because the pull-up resistor Ru is shared by the pull-up transistors Nu and Pu, it is possible to reduce the amount of resistive elements used and the area occupied by the output circuit 1. Similarly, because the pull-down transistors Nd and Pd share the pull-down resistor Rd, it is possible to reduce the amount of resistive elements used and the area occupied by the output circuit 1. Furthermore, by reducing the layout area of ​​the resistive elements, the parasitic capacitance attached to the output node out and the output terminal OUT decreases, which speeds up the transition (slew rate) of the output signal out and enables the output of a high-speed signal with a short cycle time.

[0108] By selectively operating the pull-up transistors Nu and Pu and the pull-down transistors Nd and Pd of different conductivity types, it is possible to generate an output signal out with a small amplitude and to output an output signal out that complies with a wide variety of external interface specifications.

[0109] It should be noted that the technology disclosed herein is not limited to the configurations described in the above embodiments, and can be applied to embodiments in which appropriate modifications, substitutions, additions, omissions, etc. Furthermore, the components described in the above embodiments can be combined to create new embodiments.

[0110] <Variation 1> In each of the above embodiments, the selection signals cbufu[0:m-1] and cbufd[0:m-1] select whether to drive or stop the pull-up transistor or pull-down transistor of the output buffer 20 (BUF[0:m-1]), but this is not limiting.

[0111] For example, some of the multiple output buffers 20 may be in an operable state regardless of the selection signals cbufu[0:m-1] and cbufd[0:m-1].

[0112] 16 and 17 show an example of a data processing unit 40 (CNTL[n-1]), 50(0) in an output driving circuit 10 (Drv[n-1]) for making a specific output buffer 20 (e.g., BUF[0]) operable regardless of the selection signals cbufu[0:m-1], cbufd[0:m-1].

[0113] 16 and 17, the selection signals cbufu[0:m-1] and cbufd[0:m-1] are not input to the data processing unit 50(0). As a result, the output buffer 20 (BUF[0]), which operates based on the output of the data processing unit 50(0), is in an operable state regardless of the selection signals cbufu[0:m-1] and cbufd[0:m-1]. In other words, BUF[0] is in a state independent of the selection signals cbufu[0:m-1] and cbufd[0:m-1].

[0114] An output control circuit 30 including data processing sections 40 and 50 shown in FIGS. 16 and 17 is configured to output a control signal to any one of the output drive circuits 10 shown in the first to fifth embodiments.

[0115] By adopting such a configuration, as shown by the solid line in Figure 20, the range of variation of the output impedance characteristic Ron (vertical axis) adjusted by the selection signal cbufu[0:m-1], cbuf using the code signal [0:m-1] (horizontal axis) is reduced compared to the range of variation in other embodiments (e.g., the first embodiment) shown by the dashed line.

[0116] [Effects of Modification 1] The configuration of Modification 1 makes it possible to narrow the impedance fluctuation range (ΔRon) compared to the output impedance characteristics of other embodiments (e.g., Embodiment 1). As a result, even for an output impedance standard with a narrow range of standard values ​​D (standard value [MIN]≦D≦standard value [MAX]) as shown in Fig. 20, for example, the standard can be more easily met by adjusting the code increment / decrement (increase / decrease).

[0117] <Modification 2> FIG. 18 shows a modification of the output driver circuit 10 according to the first embodiment.

[0118] 18, in this modification, the positions of the pull-up transistors (pull-up transistor Pu and pull-up transistor Nu) and the pull-up resistor Ru (corresponding to the first resistor) are interchanged. That is, the pull-up resistor Ru is provided between the power supply node VDD (corresponding to the fourth power supply node) and a node Au (corresponding to the first node), and a P-type pull-up transistor Pu (corresponding to the first transistor) and an N-type pull-up transistor Nu (corresponding to the second transistor) are provided in parallel between the node Au and an output node out.

[0119] In addition, a pull-down resistor Rd (corresponding to a second resistor) is provided between a ground node VSS (corresponding to a third power supply node) and a node Ad (corresponding to a second node), and an N-type pull-down transistor Nd (corresponding to three transistors) is provided between the node Ad and an output node out.

[0120] [Operation and Effects of Modification 2] In this modification, the same effects as in the first embodiment can be obtained.

[0121] Specifically, compared to configuring an output drive circuit 10 corresponding to each of the pull-up transistors Nu and Pu, the number of units in the output drive circuit 10 can be reduced. By reducing the number of units, the area occupied by the output circuit 1 can be reduced.

[0122] Because the pull-up resistor Ru is shared by the pull-up transistors Nu and Pu, it is possible to reduce the amount of resistor elements used and the area occupied by the output circuit 1. Furthermore, the reduction in the layout area of ​​the resistor elements reduces the parasitic capacitance attached to the output node out and the output terminal OUT, which speeds up the transition (slew rate) of the output signal out and enables the output of a high-speed signal with a short cycle time.

[0123] By selectively operating the pull-up transistors Nu and Pu of different conductivity types, it is possible to generate an output signal out with a small amplitude, and also to output an output signal out that complies with a wide variety of external interface specifications.

[0124] Although FIG. 18 shows a modified example of the output driver circuit 10 according to the first embodiment, in the configurations of the output driver circuits 10 according to the second to fifth embodiments, it is also possible to change the positions of the pull-up resistor Ru and the pull-up transistor, and to change the positions of the pull-down resistor Rd and the pull-down transistor, and the same effect can be obtained.

[0125] <Other Modifications> In each of the above embodiments, the pull-up resistor Ru and the pull-down resistor Rd have the function of imparting linearity to the impedance characteristics of the output buffer and suppressing impedance fluctuations due to manufacturing variations in transistors. In other words, when it is not necessary to impart linearity to the output impedance characteristics or to suppress impedance fluctuations with high precision, for example, when the output circuit 1 of the present disclosure is used for medium to low speed output signals, the pull-up resistor Ru and / or the pull-down resistor Rd may not be provided.

[0126] In each of the above embodiments, the pull-up transistor Pu, the pull-up transistor Nu, and the pull-down transistor Nd are provided one for each output buffer 20 (BUF[0:m-1]), which is a so-called "single structure." However, this structure is not limited to this. For example, when transistors with low breakdown voltages are used due to the miniaturization of transistors, the pull-up transistor Pu, the pull-up transistor Nu, and / or the pull-down transistor Nd may be connected in series to form a "cascode structure" (not shown). This makes it possible to alleviate applied voltage stress.

[0127] In each of the above embodiments, the output control circuit 30 may be omitted. For example, the output control circuit 30 may be omitted from the output circuit 1 of FIG. 1 (first embodiment), and the control signals pu1, pu2, and pd may be input from outside the output circuit 1. The same applies to the other embodiments.

[0128] The output circuit of the present disclosure is extremely useful because it can accommodate a variety of output characteristics, suppresses an increase in area, and is capable of high-speed operation.

[0129] 1 Output circuit 10 Output driver circuit 20 Output buffer Nu Pull-up transistor (second transistor) Pu Pull-up transistor (first transistor) Nd Pull-down transistor (third transistor) Rd Pull-down resistor (second resistor) Ru Pull-up resistor (first resistor) out Output node pu1, pu2 Control signal (first control signal)

Claims

1. An output circuit that outputs an output signal corresponding to an input signal from an output node, comprising a plurality of output driving circuits connected to the output node, each of the output driving circuits comprising a plurality of output buffers, each of the output buffers comprising: a first transistor of a first conductivity type and a first resistor provided in series with each other between a first power supply node and the output node; and a second transistor of a second conductivity type provided in series with the first resistor between a second power supply node and the output node, wherein one of the first transistor or the second transistor operates and the other stops based on a first control signal.

2. The output circuit according to claim 1, wherein each of the output buffers further comprises: a third transistor of the second conductivity type provided between a third power supply node and a second node; and a second resistor provided between the second node and the output node, the first transistor being provided between the first power supply node and a first node, the second transistor being provided between the second power supply node and the first node, and the first resistor being provided between the first node and the output node.

3. The output circuit according to claim 2, wherein the first conductivity type is P-type, the second conductivity type is N-type, the voltage of the third power supply node is lower than the voltage of the second power supply node, and the voltage of the second power supply node is less than or equal to the voltage of the first power supply node.

4. The output circuit according to claim 2, wherein the first conductivity type is N-type, the second conductivity type is P-type, the voltage of the third power supply node is higher than the voltage of the second power supply node, and the voltage of the second power supply node is equal to the voltage of the first power supply node.

5. The output circuit according to claim 2, wherein the first conductivity type is N-type, the second conductivity type is P-type, the voltage of the third power supply node is lower than the voltage of the first power supply node, and the voltage of the first power supply node is less than or equal to the voltage of the second power supply node.

6. In the output circuit according to claim 2, the first conductivity type is P-type, the second conductivity type is N-type, the voltage of the third power supply node is greater than the voltage of the second power supply node, and the voltage of the second power supply node is equal to the voltage of the first power supply node. Output circuit.

7. In the output circuit according to claim 1, each of the output buffers further includes a second resistor provided between the third power supply node and the second node, and a third transistor of the second conductivity type provided between the second node and the output node. The first power supply node and the second power supply node are connected to each other via a fourth power supply node. The first resistor is provided between the fourth power supply node and the first node. The first transistor and the second transistor are provided in parallel with each other between the first node and the output node. Output circuit.

8. In the output circuit according to claim 7, the first conductivity type is P-type, the second conductivity type is N-type, the voltage of the third power supply node is smaller than the voltage of the second power supply node, and the voltage of the second power supply node is equal to the voltage of the first power supply node. Output circuit.

9. In the output circuit according to claim 7, the first conductivity type is N-type, the second conductivity type is P-type, the voltage of the third power supply node is greater than the voltage of the second power supply node, and the voltage of the second power supply node is equal to the voltage of the first power supply node. Output circuit.

10. In the output circuit according to claim 7, the first conductivity type is N-type, the second conductivity type is P-type, the voltage of the third power supply node is smaller than the voltage of the first power supply node, and the voltage of the first power supply node is equal to the voltage of the second power supply node. Output circuit.

11. In the output circuit according to claim 7, the first conductivity type is P-type, the second conductivity type is N-type, the voltage of the third power supply node is greater than the voltage of the second power supply node, and the voltage of the second power supply node is equal to the voltage of the first power supply node. Output circuit.

12. In the output circuit according to claim 1, each of the output buffers further includes a third transistor of the second conductivity type and a fourth transistor of the first conductivity type provided in parallel between the third power supply node and the second node, and a second resistor provided between the second node and the output node. The first transistor is provided between the first power supply node and the first node, the second transistor is provided between the second power supply node and the first node, and the first resistor is provided between the first node and the output node. Output circuit.

13. In the output circuit according to claim 1, each of the output buffers further includes a second resistor provided between the third power supply node and the second node, and a third transistor of the second conductivity type and a fourth transistor of the first conductivity type provided in parallel between the second node and the output node. The first power supply node and the second power supply node are connected to each other via a fourth power supply node. The first resistor is provided between the fourth power supply node and the first node. The first transistor and the second transistor are provided in parallel between the first node and the output node. Output circuit.

14. In the output circuit according to claim 1, the operation or stop of each output drive circuit is selected based on a second control signal input to each output drive circuit. Output circuit.

15. In the output circuit according to claim 1, the operation or stop of each output buffer is selected based on a third control signal input to each output buffer. Output circuit.

16. In the output circuit according to claim 15, some of the plurality of output buffers are in an operable state regardless of the third control signal. Output circuit.

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