Method for manufacturing semiconductor device

Abstract

The present invention discloses a method for fabricating an interposer using an encapsulation resin. The fabrication method involves forming a resist layer 20 on top of a support substrate 10 and forming a separate resist layer 30 on top of the resist layer 20. A mask M having an exposure pattern is placed above the resist layer 30, and the resist layer 20 and the resist layer 30 are batch-exposed. The exposed resist layer 20 and resist layer 30 are batch-developed to obtain an aperture pattern P. Metal pillars 40 are formed with respect to the aperture pattern P by means of a metal plating solution. In this fabrication method, the diameter or width R2 of an aperture 31 formed in the outer resist layer 30 is greater than the diameter or width R1 of an aperture 21 formed in the inner resist layer 20. This allows for easy infiltration of the metal plating solution from the aperture 31 toward the aperture 21, and metal pillars 40 of sufficient height can be formed.

Description

Semiconductor device manufacturing method

[0001] The present disclosure relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that is highly required to achieve high-speed transmission efficiently and at low cost.

[0002] To achieve high-speed transmission in semiconductor packages, methods have been proposed for mounting semiconductor chips with different performance characteristics in a single package. In this packaging method, high-density interconnect technology between chips is becoming important to enable high-speed transmission and miniaturization (see, for example, Non-Patent Document 1).

[0003] To achieve high-speed transmission and miniaturization of semiconductor packages, semiconductor packages that combine materials with different physical properties to achieve high density have been proposed. In particular, fan-out packaging technology (FO-WLP) requires a fine-wiring layer to ensure high-density electrical continuity when semiconductor chips are mounted in parallel (see, for example, Non-Patent Document 2). Furthermore, many technologies, including 2.5D packaging, have been developed to connect adjacent semiconductor chips at high density via fine wiring and vertically stack package substrates incorporating semiconductor chips, thereby achieving miniaturization and high-speed transmission of semiconductor devices. 2.5D packaging is a technology that forms an interconnect substrate called a silicon interposer between a semiconductor chip and a wiring substrate. This technology allows for fine connections between semiconductor chips placed on the silicon interposer, while also connecting the upper semiconductor chip to the lower wiring substrate via through-silicon vias (TSVs) formed within the silicon interposer.

[0004] JP 2004-006773 A JP 2016-213238 A

[0005] Die Embedded Challenges for EMIB Advanced Packaging Technology, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021System on Integrated Chips(SoIC(TM)) for System for 3D Heterogeneous Integration, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019

[0006] As silicon interposers used in 2.5D packages become larger, the difference in thermal expansion coefficient between the silicon interposer and the wiring substrate has led to increased warpage of the entire substrate. For this reason, packaging forms using methods other than silicon interposers have attracted attention. As an example, a packaging form (chip-embedded interposer) has been considered in which an encapsulant with an embedded semiconductor chip is used as the interposer instead of a silicon wafer. In this chip-embedded interposer, the upper semiconductor chips are finely connected to each other via a micro-connection chip embedded in the encapsulant and a redistribution layer (RDL) formed on the upper part of the interposer substrate using a photosensitive insulating material. Meanwhile, the upper semiconductor chips are connected to the lower wiring substrate via through-electrodes (TIVs) formed in the encapsulant. This connection method, which uses a resin encapsulant as an intermediate substrate, reduces the difference in thermal expansion coefficient between the substrate and the interposer, and also enables low cost.

[0007] The following method is considered for forming a TIV. A semi-additive process (SAP) is applied to a carrier substrate, which has a temporary fixing material layer formed on a substrate such as glass, to form columnar metal wiring (metal pillars) by electroplating. Since the formed metal pillars must be thicker than the microconnection chips to be embedded in the encapsulant, a thick resist layer must be formed, followed by exposure and development processes, followed by electrolytic via-fill plating on the resulting via-pattern. However, the via-pattern formed with the thick resist layer has a large aspect ratio, making it difficult for the plating solution to penetrate into the vias during electroplating, raising concerns about a decrease in the in-plane yield of electroplating. According to the inventor's research, the reason for this difficulty is thought to be the low wettability of the resist layer with respect to the electroplating solution. Therefore, the inventor conducted extensive research and focused on the openings on the side where the plating solution enters, conceiving a method for promoting the infiltration of the plating solution by varying the size of the openings. Furthermore, the inventors further investigated the possibility of stacking another resist layer with high wettability to the electroplating solution on top of the base resist layer, and then patterning both resist layers at the same time, thereby maintaining productivity while improving the in-plane yield of electroplating.

[0008] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that is capable of forming metal pillars with sufficient height.

[0009] [1] One aspect of the present disclosure relates to a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the steps of forming a first resist layer on a support substrate, forming a second resist layer on the first resist layer, positioning a mask having an exposure pattern over the second resist layer and simultaneously exposing the first and second resist layers, developing the exposed first and second resist layers, forming metal pillars in the opening patterns formed in the developed first and second resist layers using a metal plating solution, and removing the first and second resist layers. In this method for manufacturing a semiconductor device, the diameter or width of the second opening in the opening pattern formed in the second resist layer is larger than the diameter or width of the first opening in the opening pattern formed in the first resist layer.

[0010] In this semiconductor device manufacturing method, the diameter or width of the second opening in the second resist layer is larger than the diameter or width of the first opening in the first resist layer. Therefore, when forming a metal pillar using a metal plating solution, the metal plating solution easily penetrates from the second opening toward the first opening. Therefore, this manufacturing method allows for the formation of metal pillars of sufficient height. Furthermore, this manufacturing method uses two types of resist layers, but performs simultaneous patterning, thereby providing a semiconductor device manufacturing method with a higher yield while maintaining production speed.

[0011] [2] In the semiconductor device manufacturing method according to [1] above, the second resist layer may have a contact angle with the liquid of 40° or less. In this case, the second resist layer is easily wetted by the metal plating solution. This allows the metal plating solution to easily penetrate from the second opening toward the first opening when forming the metal pillar with the metal plating solution. Therefore, this manufacturing method allows the formation of metal pillars of sufficient height. Note that the liquid here is water.

[0012] [3] In the semiconductor device manufacturing method described in [2] above, it is preferable that the contact angle of the second resist layer with respect to the liquid is 30° or less. In this case, the second resist layer is more easily wetted by the metal plating solution. This makes it easier for the metal plating solution to penetrate from the second opening toward the first opening when forming metal pillars with the metal plating solution. Therefore, this manufacturing method makes it easy to form metal pillars of sufficient height.

[0013] [4] The semiconductor device manufacturing method according to any one of [1] to [3] above may further include a step of performing a treatment to improve the wettability of the second resist layer. In this case, the second resist layer is reliably made more wettable by a metal plating solution. This ensures that the metal plating solution will easily penetrate from the second opening toward the first opening when forming metal pillars using the metal plating solution. Therefore, this manufacturing method allows for the formation of metal pillars of sufficient height.

[0014] [5] In the method for manufacturing a semiconductor device according to [4] above, the step of improving wettability preferably includes irradiating the second resist layer with at least one of oxygen plasma and ultraviolet light. In this case, the wettability of the second resist layer to a metal plating solution can be reliably improved, and penetration of the metal plating solution through the second openings formed in the second resist layer can be facilitated by a simple means.

[0015] [6] In the semiconductor device manufacturing method according to any one of [1] to [5] above, the second resist layer may be formed so that its thickness is thinner than that of the first resist layer. In this case, peeling of the second resist layer during collective development of the resist layers can be suppressed. Therefore, the metal pillars can be reliably formed while leaving the second resist layer.

[0016] [7] In the method for manufacturing a semiconductor device according to [6] above, it is preferable to form the second resist layer so that its thickness is half or less of that of the first resist layer. In this case, peeling of the second resist layer during development of the resist layer can be reliably prevented. Therefore, the metal pillar can be reliably formed while leaving the second resist layer.

[0017] [8] In any of the semiconductor device manufacturing methods [1] to [7] above, it is preferable that the thickness of the first resist layer is 15 μm or more and the thickness of the second resist layer is 15 μm or less. In this case, peeling of the second resist layer during development of the resist layer can be reliably suppressed. Therefore, metal pillars can be reliably formed while leaving the second resist layer.

[0018] [9] In any of the semiconductor device manufacturing methods [1] to [8] above, the absorption coefficient of the second resist material used to form the second resist layer may be lower than the absorption coefficient of the first resist material used to form the first resist layer. In this case, even if the second resist layer is stacked on the first resist layer, the first resist layer can be reliably developed to form the opening pattern (first opening). Therefore, the metal pillar can be reliably formed.

[0019]

[10] In the method for manufacturing a semiconductor device according to [9] above, the second resist material has an absorption coefficient of 0.018 mol L －１ μm ―１ the extinction coefficient of the first resist material is less than 0.018 mol L －１ μm ―１ In this case, even if the second resist layer is laminated on the first resist layer, the first resist layer can be reliably developed to form the opening pattern (first opening), thereby enabling the metal pillar to be reliably formed.

[0020]

[11] In the semiconductor device manufacturing method according to any one of [1] to

[10] above, in the step of forming the first resist layer, the first resist layer may be formed on a seed layer on a support substrate, and in the step of forming the metal pillar, the metal pillar may be formed from the seed layer. This semiconductor device manufacturing method may further include the step of removing a portion of the seed layer other than the region where the metal pillar is formed. In this case, the seed layer can be used to easily form the metal pillar from a metal plating solution.

[0021]

[12] The method for manufacturing a semiconductor device according to any one of [1] to

[11] above may further include a step of forming an encapsulant layer on the support substrate on which the metal pillars are formed so as to cover the metal pillars. In this case, the metal pillars can be provided in the encapsulant layer.

[0022]

[13] The method for manufacturing a semiconductor device according to

[12] above may further include a step of performing at least one of grinding and polishing on the encapsulant layer to expose the tip of the metal pillar from the encapsulant layer.

[0023]

[14] The method for manufacturing a semiconductor device according to

[12] or

[13] may further include a step of mounting a first semiconductor chip on a support substrate on which metal pillars are formed, and in the step of forming an encapsulant layer, the first semiconductor chip may be encapsulated together with the metal pillars. This makes it possible to easily form a connecting chip in the encapsulant layer.

[0024]

[15] The semiconductor device manufacturing method according to any one of [1] to

[14] above may further include a step of connecting a second semiconductor chip to a first end of the metal pillar and connecting a wiring substrate to a second end of the metal pillar. In this case, a semiconductor device including an interposer made of a resin material can be obtained. Furthermore, by making the expansion coefficients of the interposer, which serves as a relay substrate, and the wiring substrate closer to each other, the semiconductor device can be made less susceptible to warping.

[0025] According to the present disclosure, metal pillars having sufficient height can be formed.

[0026] FIGS. 1A to 1C are schematic cross-sectional views sequentially showing a method for manufacturing a semiconductor device according to an embodiment. FIGS. 2A to 2C are schematic cross-sectional views sequentially showing a method for manufacturing a semiconductor device according to an embodiment. FIGS. 3A and 3B are schematic cross-sectional views sequentially showing a method for manufacturing a semiconductor device according to an embodiment. FIGS. 4A to 4D are schematic cross-sectional views sequentially showing a method for manufacturing a semiconductor device according to an embodiment. FIG. 5 is a schematic cross-sectional view showing an example of a semiconductor device. FIG. 6 is a diagram showing the contact angle of a liquid with respect to a resist layer. FIGS. 7A to 7D are schematic cross-sectional views sequentially showing a method for manufacturing a semiconductor device according to a modified example.

[0027] Hereinafter, several embodiments of the present disclosure will be described in detail, with reference to the drawings as necessary. In the following description, identical or equivalent parts will be designated by the same reference numerals, and duplicate explanations will be omitted. Furthermore, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings unless otherwise specified. When terms such as "left," "right," "front," "back," "top," "bottom," "upper," and "lower" are used in the description and claims of this specification, these are intended for explanatory purposes and do not necessarily mean that these relative positions will always be the same. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0028] In this specification, the term "layer" encompasses not only a structure with a shape formed over the entire surface when observed in a plan view, but also a structure with a shape formed on a portion of the surface. In this specification, the term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes, as long as the intended effect of the process is achieved. A numerical range indicated using "to" indicates a range that includes the numerical values ​​before and after "to" as the minimum and maximum values, respectively.

[0029] In this specification, (meth)acrylate means acrylate or the corresponding methacrylate. This also applies to other similar expressions such as (meth)acryloyl group, (meth)acrylic copolymer, etc. Unless otherwise specified, each component and material exemplified in this specification may be used alone or in combination of two or more.

[0030] A method for manufacturing a semiconductor device according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 4. FIGS. 1 to 4 are schematic cross-sectional views sequentially illustrating a method for manufacturing a semiconductor device (intermediate substrate) according to one embodiment. The method for manufacturing a semiconductor device according to this embodiment is particularly suitable for configurations requiring high density and high productivity, and is suitable for package configurations requiring interposers or fan-out technology for mounting heterogeneous chips. More specifically, the manufacturing method according to this embodiment is suitable for package configurations in which the gap between pins (metal pillars) is 100 μm or less (for example, 20 to 100 μm in smaller cases) and the number of pins is 500 or more (for example, 1,000 to 10,000 in smaller cases). However, the present invention is not limited to the above-described aspects.

[0031] The semiconductor device according to this embodiment can be manufactured, for example, through the following steps (a) to (m). Some steps may be omitted or overlapped. (a) A step of preparing a support substrate. (b) A step of forming a first resist layer on the support substrate. (c) A step of forming a second resist layer on the first resist layer. (d) A step of exposing the first resist layer and the second resist layer together. (e) A step of developing the exposed first resist layer and the second resist layer. (f) A step of forming metal pillars in the opening patterns formed in the first resist layer and the second resist layer. (g) A step of removing the first resist layer and the second resist layer. (h) A step of removing portions of the seed layer other than the regions where the metal pillars are formed. (i) A step of mounting a semiconductor chip on the support substrate on which the metal pillars are formed. (j) A step of forming an encapsulant layer on the support substrate so as to cover the metal pillars and the semiconductor chip. (k) A step of performing at least one of grinding and polishing on the encapsulant layer. (l) A step of removing the support substrate. (m) connecting a second semiconductor chip to the first end of the metal pillar and connecting a wiring substrate to the second end of the metal pillar;

[0032] [Step (a)] In step (a), a support substrate 10 is prepared as shown in FIG. 1(a). A temporary fixing layer 11 and a seed layer 12 are formed on the support substrate 10. The support substrate 10 is preferably a highly rigid substrate, such as a silicon plate, a glass plate, a SUS plate, a substrate containing glass cloth, or a semiconductor chip containing sealing resin. The thickness of the support substrate 10 is, for example, 0.2 mm to 2.0 mm. A thickness of 0.2 mm or more improves handleability. A thickness of 2.0 mm or less reduces material costs. The planar shape of the support substrate 10 may be a wafer shape or a panel shape. The size of the support substrate 10 is not particularly limited, but a wafer with a diameter of 200 mm, 300 mm, or 450 mm, or a rectangular panel with a side length of 300 to 700 mm is preferably used. The temporary fixing layer 11 is a resin layer for temporarily fixing the support substrate 10 and the seed layer 12 together, and is a layer that peels off when the support substrate 10 is removed. In step (a), the temporary fixing layer 11 is formed on the support substrate 10, and then the seed layer 12 is formed by deposition using a PVD method or a CVD method. The seed layer 12 is a portion that serves as a seed for metal plating when forming metal pillars, and is formed from, for example, copper.

[0033] [Step (b)] In step (b), as shown in (b) of Figure 1, a resist layer 20 (first resist layer) is formed on the surface of the seed layer 12 formed on the support substrate 10. The method for forming the resist layer 20 is not particularly limited, but a resist film can be formed using a film forming device such as a vacuum laminator, a roll laminator, or a pressure bonding machine. The thickness of the resist layer 20 is, for example, 15 µm or more, for example, 20 µm.

[0034] 1(c), a resist layer 30 (second resist layer) is formed on the resist layer 20 formed on the support substrate 10. The resist layer 30 is preferably formed to be thinner than the resist layer 20, and the thickness of the resist layer 30 may be half or less of the thickness of the resist layer 20. The thickness of the resist layer 30 is, for example, 15 μm or less, and is, for example, 10 μm.

[0035] (Resist Material) Here, the resist material used in step (c) and step (d) will be described. The resist material for forming the resist layer 20 and the resist layer 30 is not particularly limited, but is, for example, a photosensitive resin composition containing a binder polymer, a photopolymerizable compound having an ethylenically unsaturated bond, and a photopolymerization initiator. The resist material is, for example, a negative resist material.

[0036] The binder polymer may be, for example, a copolymer containing benzyl (meth)acrylate or a derivative thereof, styrene or a styrene derivative, a (meth)acrylic acid alkyl ester, and (meth)acrylic acid as monomer units.

[0037] Specific examples of the benzyl (meth)acrylate derivative constituting the binder polymer include 4-methylbenzyl (meth)acrylate, 4-ethylbenzyl (meth)acrylate, 4-tert-butylbenzyl (meth)acrylate, 4-methoxybenzyl (meth)acrylate, 4-ethoxybenzyl (meth)acrylate, 4-hydroxybenzyl (meth)acrylate, and 4-chlorobenzyl (meth)acrylate.

[0038] Specific examples of the styrene derivative that constitutes the binder polymer include vinyltoluene, p-methylstyrene, and p-chlorostyrene.

[0039] The proportion of monomer units derived from benzyl (meth)acrylate or a derivative thereof in the binder polymer may be 50 to 80% by mass, 50 to 75% by mass, 50 to 70% by mass, or 50 to 65% by mass, based on the mass of the binder polymer. The proportion of monomer units derived from styrene or a styrene derivative in the binder polymer may be 5 to 40% by mass, or 5 to 35% by mass, based on the mass of the binder polymer. The proportion of monomer units derived from (meth)acrylic acid alkyl ester in the binder polymer may be 1 to 20% by mass, 1 to 15% by mass, 1 to 10% by mass, or 1 to 5% by mass, based on the mass of the binder polymer. The proportion of monomer units derived from (meth)acrylic acid in the binder polymer may be 5 to 30% by mass, 5 to 25% by mass, or 10 to 25% by mass, based on the mass of the binder polymer.

[0040] The weight average molecular weight (Mw) of the binder polymer may be 20,000 to 150,000, 30,000 to 100,000, 40,000 to 80,000, or 40,000 to 60,000. The weight average molecular weight here refers to a value calculated in terms of standard polystyrene determined by gel permeation chromatography (GPC).

[0041] The acid value (mg KOH / g) of the binder polymer may be 13 to 78, 39 to 65, or 52 to 62. The acid value here means the amount (mg) of potassium oxide in the electroplating solution required to neutralize 1 g of the binder polymer.

[0042] Specific examples of photopolymerizable compounds having an ethylenically unsaturated bond include bisphenol A (meth)acrylate compounds, bisphenol A (meth)acrylate compounds added to electroplating solutions, polyalkylene glycol (meth)acrylates, urethane monomers, pentaerythritol (meth)acrylate, and trimethylolpropane (meth)acrylate. These may be used alone or in combination of two or more. The bisphenol A di(meth)acrylate compound may be, for example, a compound represented by the following general formula (1):

[0043]

[0044] In formula (1), each R independently represents a hydrogen atom or a methyl group. EO and PO represent an oxyethylene group and an oxypropylene group, respectively. １ , m ２ , n １ , n ２ each independently represents 0 to 40, m １ +m ２ is 1 to 40, and n １ +n ２ is 0 to 20. Either EO or PO may be on the acid group side of the phenolic electrolytic plating solution. １ , m ２ , n １ and n ２ indicates the number of EO or PO, respectively. １ +m ２ a compound having an average of 5 or less, and m １ +m ２ It may be combined with a compound having an average of 6 to 40.

[0045] The polyalkylene glycol (meth)acrylate may be a compound represented by the following formula (2): As the photopolymerizable compound having an ethylenically unsaturated bond, a bisphenol A-based di(meth)acrylate compound may be combined with a compound represented by the following formula (2):

[0046]

[0047] In formula (2), R １４ and R １５ each independently represents an atom or a methyl group, EO and PO are as defined above, and s １ indicates 1 to 30, and r １ and r ２ indicates 0 to 30, and r １ +r ２ is 1 to 30. Examples of commercially available compounds represented by formula (2) include １４ and R １５ is a methyl group, r １ +r ２ = 4 (average value), s １An example is a vinyl compound (manufactured by Resonac Corporation, trade name: FA-023M) having a viscosity index of 12 (average value).

[0048] Specific examples of the photopolymerization initiator include aromatic ketones such as benzophenone, N,N'-tetramethyl-4,4'-diaminobenzophenone (Michler's ketone), N,N'-tetraethyl-4,4'-diaminobenzophenone, 4-methoxy-4'-dimethylaminobenzophenone, 2-benzyl-2-dimethylamino-1-(4-morpholinophenyl)-butanone-1, and 2-methyl-1-[4-(methylthio)phenyl]-2-morpholino-propanone-1. ton; 2-ethylanthraquinone, phenanthrenequinone, 2-tert-butylanthraquinone, octamethylanthraquinone, 1,2-benzanthraquinone, 2,3-benzanthraquinone, 2-phenylanthraquinone, 2,3-diphenylanthraquinone, 1-chloroanthraquinone, 2-methylanthraquinone, 1,4-naphthoquinone, 9,10-phenanthranequinone, 2-methyl-1,4-naphthoquinone, 2,3-dimethylanthraquinone quinones such as benzoinone; benzoin ether compounds such as benzoin methyl ether, benzoin ethyl ether, and benzoin phenyl ether; benzoin compounds such as benzoin, methylbenzoin, and ethylbenzoin; benzyl derivatives such as benzil dimethyl ketal; 2,4,5-triarylimidazole dimers such as 2-(o-chlorophenyl)-4,5-diphenylimidazole dimer, 2-(o-chlorophenyl)-4,5-di(methoxyphenyl)imidazole dimer, 2-(o-fluorophenyl)-4,5-diphenylimidazole dimer, 2-(o-methoxyphenyl)-4,5-diphenylimidazole dimer, and 2-(p-methoxyphenyl)-4,5-diphenylimidazole dimer; acridine derivatives such as 9-phenylacridine and 1,7-bis(9,9'-acridinyl)heptane; N-phenylglycine, N-phenylglycine derivatives, and coumarin compounds. These may be used alone or in combination of two or more. The photoinitiator may comprise a 2,4,5-triarylimidazole dimer, particularly a 2-(O-chlorophenyl)-4,5-diphenylimidazole dimer.

[0049] The content of the binder polymer in the photosensitive resin composition may be 40 to 80 parts by mass, 45 to 75 parts by mass, or 50 to 70 parts by mass, relative to 100 parts by mass of the total amount of the binder polymer and the photopolymerizable compound. The content of the photopolymerization initiator in the photosensitive resin composition may be 0.01 to 5 parts by mass, 0.1 to 4.5 parts by mass, or 1 to 4 parts by mass, relative to 100 parts by mass of the total amount of the binder polymer and the photopolymerizable compound.

[0050] The photosensitive resin composition may contain other components as needed. Examples of other components include a photopolymerizable compound having a cationically polymerizable cyclic ether group, a cationic polymerization initiator, a sensitizer, a dye such as malachite green, a photocoloring agent such as tribromomethylphenyl sulfone or leucocrystal violet, a thermal color-developing inhibitor, a plasticizer such as p-toluenesulfonamide, a pigment, a filler, an antifoaming agent, a flame retardant, a stabilizer, an adhesion promoter, a leveling agent, a release accelerator, an antioxidant, a fragrance, an imaging agent, and a thermal crosslinking agent. The content of each of the other components may be about 0.01 to 20 parts by mass per 100 parts by mass of the combined amount of the binder polymer and the photopolymerizable compound.

[0051] The total content of the binder polymer, the photopolymerizable compound, and the photopolymerization initiator in the photosensitive resin composition may be 90 to 100% by mass, or 95 to 100% by mass, based on the total mass of the components other than the solvent in the photosensitive resin composition.

[0052] The resist material used to form the resist layer 20 and the resist layer 30 preferably has the following absorption coefficient: Specifically, the absorption coefficient of the resist material used to form the resist layer 30 is preferably lower than the absorption coefficient of the resist material used to form the resist layer 20. More specifically, the absorption coefficient of the resist material used to form the resist layer 30 is preferably 0.018 mol L−1. －１ μm ―１ and the resist material used to form the resist layer 20 has an absorption coefficient of 0.018 mol L －１ μm ―１As an example, the absorption coefficient of the resist material used to form the resist layer 30 is preferably 0.015 mol L －１ μm ―１ The resist material used to form the resist layer 20 has an absorption coefficient of 0.021 mol L －１ μm ―１ The "absorption coefficient" referred to here can be measured using, for example, an ultraviolet-visible spectrophotometer UV-2600 (manufactured by Shimadzu Corporation), and is the absorption coefficient at a wavelength of 365 nm. In this case, even if the resist layer 30 is laminated on the resist layer 20, the lower resist layer 20 can be reliably developed in the developing step described below to form an opening pattern.

[0053] Furthermore, the upper resist layer 30 preferably has a contact angle with water of 40° or less. The contact angle here is an index of the wettability of the constituent material of the resist layer 30 to a liquid, and refers to the contact angle θ when water D is dropped onto the resist layer 30, as shown in FIG. 6 . Note that the contact angle θ here is the contact angle with water for the sake of measurement reliability, but it is also 40° or less in the case of a metal plating solution. A metal plating solution, for example, a copper plating solution, is largely composed of water, and its contact angle with the resist is similar to that of water. Therefore, the contact angle of the resist layer 30 with the metal plating solution can be treated as an approximation of the contact angle with water. A large contact angle θ indicates low wettability, and a smaller contact angle θ indicates improved wettability. More specifically, the resist layer 30 preferably has a contact angle θ with water D (or a metal plating solution) of 30° or less. By setting the contact angle θ to 30° or less, the electrolytic plating solution can easily penetrate into the via-shaped pattern (opening) formed in the resist layer 30, thereby improving the yield of electrolytic plating.

[0054] To reduce the contact angle θ of the resist layer 30 with a liquid, for example, a predetermined surface treatment may be performed. While the surface treatment method is not particularly limited, preferred methods include immersion in a cleaning solution containing an acid component, plasma treatment using argon gas or oxygen gas, and UV modification. The inventors evaluated the contact angle θ of a resist layer 30 made of a negative-type photosensitive dry film resist containing a binder polymer, a photopolymerizable compound having an ethylenically unsaturated bond, and a photopolymerization initiator. In this evaluation, as shown in FIG. 6 , a resist layer 30 was formed from the negative-type photosensitive dry film resist, and the change in the contact angle θ was evaluated between cases with and without surface treatment. In this evaluation, the contact angle θ with water was evaluated as shown in Table 1 below. Without surface treatment, the contact angle θ with water was 67.9°, whereas various surface treatments were able to reduce the contact angle θ with water as follows. Among these, surface treatments using oxygen plasma and UV modification were more preferable. It should be noted that cleaner A was treated using a cleaner solution containing a nonionic surfactant, cleaner B was treated using a cleaner solution containing an anionic surfactant, and cleaner C was treated using a cleaner solution containing an acidic surfactant.

[0055]

[0056] When metal pillars, which will be described later, were formed using the above-mentioned oxygen plasma and UV modification surface treatments, the intrusion of voids into the plating solution was prevented, and plating defects were reliably reduced.

[0057] [Step (d)] Returning to the step (d), the explanation will be continued. In step (d), as shown in FIG. 2(a), a mask M having a predetermined exposure pattern is placed above the resist layer 30, and the resist layer 20 and the resist layer 30 on the support substrate 10 are exposed at once. The exposure method is not particularly limited, but active light such as ultraviolet light, visible light, or radiation is irradiated through the mask M. After exposure, post-exposure baking (PEB) may be performed as necessary. The post-exposure baking temperature is preferably 70°C to 140°C, and the post-exposure baking time is preferably 1 minute to 5 minutes.

[0058] [Step (e)] In step (e), as shown in FIG. 2B, the exposed resist layer 20 and resist layer 30 are developed with a developer. For example, if the resist material is a negative resist, in this step, the exposed resist layer 20 and the unexposed portions 20a, 30a (see FIG. 2A) of the resist layer 30 on the support substrate 10 are removed with a developer, thereby patterning the resist layer 20 and resist layer 30. The openings 21 (first opening) in the resist layer 20 and the openings 31 (second openings) in the resist layer 30 formed by the above-described exposure and development are formed so that the diameter or width R2 of the outer opening 31 is larger than the diameter or width R1 of the inner opening 21. That is, the relationship R2≧R1 is satisfied. By satisfying R2≧R1, the entire opening has a cone shape, which facilitates penetration of the electroplating solution. For example, R1=30 μm and R2=35 μm are preferred.

[0059] In the case of alkaline development, suitable developers for development include aqueous alkaline solutions such as sodium hydroxide, potassium hydroxide, sodium silicate, ammonia, ethylamine, diethylamine, triethylamine, triethanolamine, and tetramethylammonium hydroxide (TMAH). The base concentration of these aqueous solutions is preferably 0.1 to 10% by mass. Furthermore, alcohols or surfactants can also be added to the above-mentioned developers. These can each be blended in an amount of preferably 0.01 to 10 parts by mass, more preferably 0.1 to 5 parts by mass, per 100 parts by mass of the developer.

[0060] [Step (f)] In step (f), as shown in FIG. 2C, metal pillars 40 are formed in the opening patterns P formed in the developed resist layers 20 and 30 using a metal plating solution. The opening patterns P are via-shaped patterns. While the metal type of the metal pillars 40 is not particularly limited, copper is preferred from the viewpoints of workability and versatility. The electrolytic plating method is also not particularly limited. However, from the viewpoint of the efficiency of penetration of the electrolytic plating solution into the via-shaped patterns, it is preferred to use jet-type electrolytic plating, which agitates the plating solution by spraying it vertically onto the plating surface of the object to be plated. Furthermore, from the viewpoint of agitation efficiency, paddle-agitation electrolytic plating, which agitates the plating solution by paddle blades just before the plating surface of the object to be plated, may also be used. In this manufacturing method, the resist layers 20 and 30 are stacked and then patterned at the same time. This facilitates penetration of the metal plating solution into the via-shaped patterns, thereby enabling semiconductor devices to be manufactured with a higher yield than conventional processes.

[0061] 2(c) and 3(a), in step (g), the resist layer 20 and the resist layer 30 remaining on the support substrate 10 after the formation of the metal pillar 40 are removed. The method for removing the resist is not particularly limited, but from the viewpoint of removability, it is preferable to remove the resist using an alkaline remover.

[0062] [Step (h)] In step (h), as shown in Figures 3(a) and 3(b), after forming the metal pillars 40, the seed layer portion 12a of the seed layer 12 remaining on the support substrate 10 is removed from the region other than the region where the metal pillars 40 are formed. The method for removing the seed layer portion 12a is not particularly limited, but is preferably a dipping method, a spraying method, or a puddle method. As a result, only the electrode portion 12b remains. The electrode portion 12b constitutes a part of the pillar electrode mainly composed of the metal pillars 40.

[0063] [Step (i)] In step (i), as shown in (a) of Figure 4, a semiconductor chip 45 (first semiconductor chip) is mounted on a support substrate 10 on which metal pillars 40 are formed. The semiconductor chip 45 is a connecting semiconductor chip for connecting other semiconductor chips to each other. In addition to the metal pillars 40 and the semiconductor chip 45, metal wiring, electrode pads, connection bumps, and pillars may also be formed on the support substrate 10.

[0064] [Step (j)] In step (j), as shown in (b) of FIG. 4 , an encapsulant layer 50 is formed on the support substrate 10 so as to cover the metal pillars 40 and the semiconductor chip 45. In this step, encapsulation is performed by forming an encapsulant material such as epoxy resin in a mold using a compression or transfer molding machine, thereby forming the encapsulant layer 50. The encapsulated body may be heated using an oven, a hot plate, or the like. When metal wiring or the like is formed on the support substrate 10, the metal wiring or the like is also encapsulated together with the metal pillars 40 and the semiconductor chip 45.

[0065] [Step (k)] In step (k), as shown in FIG. 4C , the encapsulant layer 50 is subjected to at least one of grinding and polishing. In this step, the surface of the encapsulant layer 50 is exposed by grinding. This grinding can be performed, for example, by a grinding technique using a grinding wheel that rotates at high speed. This grinding exposes the tips 41 of the metal pillars 40 and the connection terminals 46 of the semiconductor chip 45 that are encapsulated in the encapsulant layer 50 from the surface 51 of the encapsulant layer 50.

[0066] In step (k), polishing by CMP may be performed after grinding in view of grinding variation. For example, the polished portion is polished while supplying a polishing liquid (not shown) between the polishing pad C (abrasive cloth) and the polished portion (sealing material layer 50) on the support substrate 10. Various polishing liquids for CMP are known. CMP polishing liquids are classified according to the type of abrasive grains (abrasive particles) they contain, and examples of the abrasive grains include cerium oxide (ceria) particles, silicon oxide (silica) particles, aluminum oxide (alumina) particles, and organic resin particles. From the viewpoint of polishing rate, it is preferable to use ceria-based particles as the abrasive grains.

[0067] [Step (l)] In step (l), as shown in (d) of Fig. 4, the support substrate 10 is removed. To remove the support substrate 10, a predetermined process for peeling the temporary fixing layer 11 (for example, a heat treatment in the case of thermal peeling) is performed, and the support substrate 10 is removed from the sealing body together with the temporary fixing layer 11. In this way, a relay substrate S that functions as an interposer is obtained.

[0068] [Step (m)] In step (m), as shown in FIG. 5 , a semiconductor chip 55 (second semiconductor chip) is mounted on the front surface 51 of the encapsulant layer 50 of the relay substrate S, and a wiring substrate 60 is attached to the back surface 52 of the encapsulant layer 50 of the relay substrate S. As a result, the tip 41 (first end) of the metal pillar 40 is connected to the semiconductor chip 55, and the other end 42 (second end) of the metal pillar 40 is connected to the wiring substrate 60 via the electrode portion 12b. Redistribution layers 65 may or may not be provided between the relay substrate S and the semiconductor chip 55, and between the relay substrate S and the wiring substrate 60. In this manner, the semiconductor device 100 is fabricated. Note that, for ease of explanation, the configuration of the semiconductor device 100 is simplified in FIG. 5 , but the semiconductor device 100 may include multiple semiconductor chips 55 or mounted components. Furthermore, in the semiconductor device 100, the semiconductor chip 55 may be further encapsulated.

[0069] As described above, according to the semiconductor device manufacturing method of this embodiment, the diameter or width R2 of the opening 31 in the resist layer 30 is larger than the diameter or width R1 of the opening 21 in the resist layer 20. Therefore, when forming the metal pillar 40 using a metal plating solution, the metal plating solution easily infiltrates from the opening 31 toward the opening 21. Therefore, according to this manufacturing method, it is possible to form a metal pillar 40 of sufficient height. Furthermore, because this manufacturing method uses two different types of resist layers and performs patterning simultaneously, it is possible to provide a semiconductor device manufacturing method with a higher yield while maintaining production speed.

[0070] In the semiconductor device manufacturing method according to this embodiment, the contact angle θ of the resist layer 30 with water may be 40° or less, and preferably 30° or less. This makes it easier for the metal plating solution to wet the resist layer 30 and penetrate into it. Therefore, this manufacturing method allows for the formation of metal pillars of sufficient height.

[0071] In the semiconductor device manufacturing method according to this embodiment, a treatment for improving wettability may be performed on the resist layer 30. This ensures that the metal plating solution can easily wet the resist layer 30, and the metal plating solution can easily penetrate from the opening 31 toward the opening 21. Therefore, this manufacturing method makes it possible to form metal pillars of sufficient height. Note that at least one of oxygen plasma and ultraviolet light irradiation is preferably performed as such a treatment for improving wettability.

[0072] In the semiconductor device manufacturing method according to this embodiment, the resist layer 30 is formed so that its thickness is thinner than the resist layer 20. This prevents the resist layer 30 from peeling off when the resist layer is developed. Therefore, the metal pillar 40 can be reliably formed while leaving the resist layer 30. In this case, it is preferable to form the resist layer 30 so that its thickness is half or less of the resist layer 20. It is also preferable that the thickness of the resist layer 20 is 15 μm or more and the thickness of the resist layer 30 is 15 μm or less.

[0073] In the semiconductor device manufacturing method according to this embodiment, the absorption coefficient of the resist material (second resist material) used to form the resist layer 30 may be lower than the absorption coefficient of the resist material (first resist material) used to form the resist layer 20. In this case, even if the resist layer 30 is stacked on the resist layer 20, the lower resist layer 20 can be reliably developed to form the opening 21. Therefore, the metal pillar 40 can be reliably formed. In this case, if the absorption coefficient of the resist material of the resist layer 30 is 0.018 mol·L －１ μm ―１and the absorption coefficient of the resist material of the resist layer 20 is less than 0.018 mol L －１ μm ―１ This is preferable. This allows the resist layer 20 to be developed more reliably to form the opening 21. Therefore, the metal pillar 40 can be formed reliably.

[0074] The above describes the manufacturing method of the semiconductor device according to the present embodiment. However, the manufacturing method of the semiconductor device according to the present invention is not limited to the above embodiment and various modifications are possible. For example, as shown in FIG. 7A, a configuration in which a metal pillar 40 is provided on a support substrate 10 without a semiconductor chip 45 is also possible. In this case, as shown in FIG. 7B, a sealing material layer 50 is formed on the support substrate 10 so as to cover the metal pillar 40. Then, as shown in FIG. 7C, the sealing material layer 50 is subjected to at least one of grinding and polishing. Finally, as shown in FIG. 7D, the support substrate 10 is removed from the sealing body. A semiconductor device 100 may be manufactured using such an interconnect substrate S1.

[0075] 10...Support substrate, 12...Seed layer, 12a...Seed layer portion, 20...Resist layer (first resist layer), 21...Opening (first opening), 30...Resist layer (second resist layer), 31...Opening (second opening), 40...Metal pillar, 45...Semiconductor chip (first semiconductor chip), 50...Encapsulant layer, 55...Semiconductor chip (second semiconductor chip), 60...Wiring substrate, 100...Semiconductor device.

Claims

1. A step of forming a first resist layer on a support substrate, a step of forming a second resist layer on the first resist layer, a step of disposing a mask having an exposure pattern above the second resist layer and exposing the first resist layer and the second resist layer together, a step of developing the exposed first resist layer and second resist layer, a step of forming metal pillars by a metal plating solution with respect to the opening patterns formed in the developed first resist layer and second resist layer, and a step of removing the first resist layer and the second resist layer, wherein a diameter or width of a second opening in the opening pattern formed in the second resist layer is larger than a diameter or width of a first opening in the opening pattern formed in the first resist layer. A method of manufacturing a semiconductor device.

2. The method of manufacturing a semiconductor device according to claim 1, wherein a contact angle of the second resist layer with respect to a liquid is 40° or less.

3. The method of manufacturing a semiconductor device according to claim 2, wherein a contact angle of the second resist layer with respect to a liquid is 30° or less.

4. The method of manufacturing a semiconductor device according to any one of claims 1 to 3, further comprising a step of performing a process for improving wettability with respect to the second opening formed in the second resist layer.

5. In the step of performing the process for improving wettability, at least one of oxygen plasma and ultraviolet irradiation is performed with respect to the second opening formed in the second resist layer. The method of manufacturing a semiconductor device according to claim 4.

6. The second resist layer is formed such that a thickness of the second resist layer is thinner than that of the first resist layer. The method of manufacturing a semiconductor device according to any one of claims 1 to 5.

7. The second resist layer is formed such that a thickness of the second resist layer is half or less of that of the first resist layer. The method of manufacturing a semiconductor device according to claim 6.

8. The method of manufacturing a semiconductor device according to any one of claims 1 to 7, wherein a thickness of the first resist layer is 15 μm or more and a thickness of the second resist layer is 15 μm or less.

9. An absorption coefficient of a second resist material used for forming the second resist layer is lower than an absorption coefficient of a first resist material used for forming the first resist layer. The method of manufacturing a semiconductor device according to any one of claims 1 to 8.

10. The absorption coefficient of the second resist material is less than 0.018 mol·L －１ ·μm ―１ and the absorption coefficient of the first resist material is 0.018 mol·L －１ ·μm ―１ or more. The method of manufacturing a semiconductor device according to claim 9.

11. In the step of forming the first resist layer, the first resist layer is formed on the seed layer on the support substrate. In the step of forming the metal pillar, the metal pillar is formed from the seed layer. The method for manufacturing a semiconductor device further includes a step of removing a portion of the seed layer other than the region where the metal pillar is formed in the seed layer. The method for manufacturing a semiconductor device according to any one of claims 1 to 10.

12. The method for manufacturing a semiconductor device according to any one of claims 1 to 11 further includes a step of forming a sealing material layer on the support substrate on which the metal pillar is formed so as to cover the metal pillar.

13. The method for manufacturing a semiconductor device according to claim 12 further includes a step of performing at least one of grinding and polishing on the sealing material layer to expose the tip of the metal pillar from the sealing material layer.

14. The method for manufacturing a semiconductor device according to claim 12 or 13 further includes a step of mounting a first semiconductor chip on the support substrate on which the metal pillar is formed. In the step of forming the sealing material layer, the first semiconductor chip is sealed together with the metal pillar.

15. The method for manufacturing a semiconductor device according to any one of claims 1 to 14 further includes a step of connecting a second semiconductor chip to the first end of the metal pillar and connecting a wiring substrate to the second end of the metal pillar.

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