Charge discharge element and cooling device

Abstract

The present invention suppresses heat generation during charge discharge. A charge discharge element (100) includes: a Schottky electrode (103) which is an example of a first charge supply source of a first conductivity type excited by heat from a heat source (104); an N-type region (102) which is an example of a first semiconductor having a metastable energy level of the first charge; a Schottky electrode (110) which is an example of a second charge supply source of a second conductivity type; and a high-concentration hole accumulation layer (111) which is an example of a second semiconductor having a metastable energy level of the second charge. The first charge supplied from the Schottky electrode (103) to the N-type region (102) and the second charge supplied from the Schottky electrode (110) to the high-concentration hole accumulation layer (111) are recombined at a similar energy level.

Description

Charge drain element and cooling device

[0001] The present disclosure relates to a charge draining element and a cooling device.

[0002] In general, electronic devices generate signal charges, perform processing operations such as storage and calculation, and then discharge the charges. For example, Patent Document 1 discloses a technology for reducing switching noise by discharging signal charges held in a charge storage node of a CMOS (Complementary Metal Oxide Semiconductor) image sensor through a reset transistor biased to the subthreshold region. Patent Document 2 discloses a technology for cooling a high-temperature heat source by transferring thermal energy absorbed from the high-temperature heat source using conductive charges and dissipating the heat from the low-temperature side.

[0003] Japanese Patent No. 4957925 Publication JP 11-135846 Publication

[0004] However, in the above-mentioned prior art, when a charge is discharged, the charge moves through a path with a potential difference, which causes the thermal energy that the charge had before the charge was discharged to dissipate during the movement (ohmic loss), resulting in the problem that the element generates Joule heat from the charge transfer path (channel).

[0005] For example, in the technology disclosed in Patent Document 1, as shown in Figure 5 of the same document, when thermally excited electrons move from the source to the drain, they release energy equivalent to the potential difference, generating heat. This heat increases thermions (noise) throughout the entire device, particularly in the charge signal storage section. For this reason, it is necessary to suppress this heat generation as much as possible.

[0006] Therefore, the present disclosure provides a charge discharging element that can suppress heat generation when discharging charge, and a cooling device including the same.

[0007] A charge draining device according to one aspect of the present disclosure includes a first charge source that supplies first charges of a first conductivity type excited by heat from a heat source, a first semiconductor having a metastable energy level of the first charges, a second charge source that supplies second charges of a second conductivity type, and a second semiconductor having a metastable energy level of the second charges, wherein the first charges supplied to the first semiconductor from the first charge source and the second charges supplied to the second semiconductor from the second charge source recombine at the same energy level.

[0008] A cooling device according to one aspect of the present disclosure includes the charge discharging element according to the above aspect, and cools the heat source.

[0009] According to the charge discharging element and cooling device of the present disclosure, heat generation during charge discharging can be suppressed.

[0010] FIG. 1 is a cross-sectional view of a charge discharging element according to embodiment 1. FIG. 2A is a schematic diagram of a potential profile of the charge discharging element according to embodiment 1. FIG. 2B is an effective equivalent circuit diagram of the charge discharging element according to embodiment 1. FIG. 3 is a cross-sectional view of a charge discharging element according to embodiment 2. FIG. 4A is a schematic diagram of a potential profile of the charge discharging element according to embodiment 2. FIG. 4B is an effective equivalent circuit diagram of the charge discharging element according to embodiment 2. FIG. 5 is a cross-sectional view of a charge discharging element according to embodiment 3. FIG. 6A is a schematic diagram of a potential profile of the charge discharging element according to embodiment 3. FIG. 6B is an effective equivalent circuit diagram of the charge discharging element according to embodiment 3. FIG. 7 is a cross-sectional view of a charge discharging element according to embodiment 4. FIG. 8A is a schematic diagram of a potential profile of the charge discharging element according to embodiment 4. FIG. 8B is an effective equivalent circuit diagram of the charge discharging element according to embodiment 4. FIG. 9 is a cross-sectional view of a charge discharging element according to embodiment 5. FIG. 10A is a schematic diagram of a potential profile of the charge discharging element according to embodiment 5. Fig. 10B is an effective equivalent circuit diagram of the charge discharging element according to embodiment 5. Fig. 11 is a cross-sectional view of the charge discharging element according to embodiment 6. Fig. 12A is a schematic diagram of a potential profile of the charge discharging element according to embodiment 6. Fig. 12B is an effective equivalent circuit diagram of the charge discharging element according to embodiment 6. Fig. 13 is a block diagram of a cooling device according to embodiment 7.

[0011] (Summary of the Present Disclosure) A charge draining device according to a first aspect of the present disclosure includes a first charge source that supplies first charges of a first conductivity type excited by heat from a heat source, a first semiconductor having a metastable energy level of the first charges, a second charge source that supplies second charges of a second conductivity type, and a second semiconductor having a metastable energy level of the second charges, wherein the first charges supplied from the first charge source to the first semiconductor and the second charges supplied from the second charge source to the second semiconductor recombine at the same energy level.

[0012] In this way, the thermally excited first charge of the first conductivity type and the second charge of the second conductivity type recombine at the same energy level. That is, the first charge and the second charge can recombine directly with substantially no potential difference. Since there is substantially no potential difference in the path of charge recombination, it is possible to suppress heat generation when the charge is discharged.

[0013] A charge draining element according to a second aspect of the present disclosure is the charge draining element according to the first aspect, wherein the first semiconductor and the second semiconductor form a tunnel junction.

[0014] This allows the thermally excited first charge to directly recombine with the second charge by tunneling at the metastable energy level without any potential difference, thereby suppressing heat generation.

[0015] A charge drain element according to a third aspect of the present disclosure is a charge drain element according to the first or second aspect, wherein the first charge source is joined to the first semiconductor via a potential barrier, and the first charge supplied to the first semiconductor is an electron or a hole emitted from the first charge source by heat from the heat source.

[0016] This allows selectively emitting only thermal charges (electrons or holes) excited to a high energy level above a certain level limited by the height of the potential barrier, thereby enabling continued heat absorption from the heat source.

[0017] A charge draining device according to a fourth aspect of the present disclosure is the charge draining device according to the first or second aspect, wherein the first semiconductor includes the first charge source, and the first charges supplied to the first semiconductor are electrons or holes generated in the first semiconductor by heat from the heat source.

[0018] This simplifies the structure by integrating the first charge source and the first semiconductor, which is advantageous for at least one of miniaturizing the charge drain element and reducing its cost. Furthermore, since a certain amount of thermal energy is absorbed, which is determined by the band gap of the first semiconductor, more quantitative control becomes possible.

[0019] A charge draining element according to a fifth aspect of the present disclosure is a charge draining element according to the first or second aspect, wherein the second charge source supplies the second charge excited by heat from the heat source to the second semiconductor.

[0020] This allows heat absorption by two conductive charges, the first charge and the second charge. Therefore, the charge discharging element according to this embodiment can absorb heat more efficiently. Furthermore, since there is substantially no potential difference in the path of charge recombination, heat generation can be suppressed.

[0021] A charge draining device according to a sixth aspect of the present disclosure is the charge draining device according to the fifth aspect, wherein the first charge source is connected to the first semiconductor via a potential barrier. The first charge supplied to the first semiconductor is one of electrons and holes emitted from the first charge source by heat from the heat source. The second charge source is connected to the second semiconductor via a potential barrier. The second charge supplied to the second semiconductor is the other of electrons and holes emitted from the second charge source by heat from the heat source.

[0022] This allows selectively discharging only the thermal charges excited to a high energy level above a certain level limited by the height of the potential barrier for both the first and second charges, thereby enabling the charge sources of both conductivity types to continue absorbing heat.

[0023] A charge draining device according to a seventh aspect of the present disclosure is the charge draining device according to the fifth aspect, wherein the first semiconductor includes the first charge source. The first charge supplied to the first semiconductor is one of electrons and holes generated in the first semiconductor by heat from the heat source. The second semiconductor includes the second charge source. The second charge supplied to the second semiconductor is the other of electrons and holes generated in the second semiconductor by heat from the heat source.

[0024] This allows the first charge source and the first semiconductor to be integrated, and the second charge source and the second semiconductor to be integrated. Therefore, the charge drain element according to this embodiment has a simplified configuration, which is advantageous for at least one of miniaturization and cost reduction. Furthermore, the first charge absorbs a certain amount of thermal energy determined by the band gap of the first semiconductor, and the second charge absorbs a certain amount of thermal energy determined by the band gap of the second semiconductor, allowing for more quantitative control.

[0025] A charge drain element according to an eighth aspect of the present disclosure is a charge drain element according to any one of the first to seventh aspects, wherein the first charge source is an electrode having a barrier height relative to the first semiconductor and is in an electrically floating state.

[0026] As a result, electrical energy is stored in the first charge source so that the potential barrier against the first charge becomes higher each time a thermally excited charge is discharged. Since this stored energy is supplied from the heat source, a higher thermal energy absorption is achieved than when the potential of the first charge source is kept constant.

[0027] A charge draining element according to a ninth aspect of the present disclosure is the charge draining element according to the eighth aspect, further comprising a silicon substrate, wherein the first semiconductor is an N-type impurity region provided in the silicon substrate, the second semiconductor is a high-concentration hole accumulation region formed in at least a portion of the silicon substrate, and the second charge source is a junction electrode having a barrier height relative to the second semiconductor.

[0028] As a result, electrical energy is stored in the first charge source so that the potential barrier against the first charge becomes higher each time a thermally excited charge is discharged. Since this stored energy is supplied from the heat source, a higher thermal energy absorption is achieved than when the potential of the first charge source is kept constant.

[0029] A charge draining element according to a tenth aspect of the present disclosure is the charge draining element according to any one of the first to eighth aspects, further comprising a silicon substrate, wherein the first semiconductor and the first charge source are N-type impurity regions provided in the silicon substrate, the second charge source is a P-type impurity region provided in the silicon substrate, and the second semiconductor is a high-concentration hole accumulation region formed in at least a portion of the P-type impurity region.

[0030] As a result, electrical energy is stored in the first charge source so that the potential barrier against the first charge becomes higher each time a thermally excited charge is discharged. Since this stored energy is supplied from the heat source, a higher thermal energy absorption is achieved than when the potential of the first charge source is kept constant.

[0031] A charge draining element according to an eleventh aspect of the present disclosure is the charge draining element according to any one of the first to eighth aspects, further comprising a stacked structure of an AlGaN layer and a GaN layer as the second semiconductor. The second charge source is a two-dimensional electron gas generated between the AlGaN layer and the GaN layer. The first semiconductor includes P-type silicon provided on the AlGaN layer opposite the GaN layer. The first charge source is an electrode Schottky-connected to the P-type silicon.

[0032] This allows the thermally emitted holes (first charges) to recombine with the electrons (second charges) of the two-dimensional electron gas (2DEG) without any substantial potential difference, suppressing heat generation during recombination. Also, it is possible for the holes to continue absorbing heat from the heat source.

[0033] A charge draining device according to a twelfth aspect of the present disclosure is the charge draining device according to any one of the first to eighth aspects, further comprising GaN disposed between the first semiconductor and the second semiconductor, the first semiconductor and the first charge source being N-type silicon, and the second semiconductor and the second charge source being P-type graphene.

[0034] As a result, the energy level of the conduction band of GaN is approximately equal to the energy level of the valence band of P-type graphene, and therefore, thermions excited in the conduction band of GaN can directly recombine with holes in the valence band of P-type graphene with a small potential difference, thereby suppressing heat generation.

[0035] A charge draining device according to a thirteenth aspect of the present disclosure is the charge draining device according to any one of the first to eighth aspects, wherein the charge draining device has a stacked structure of an AlGaN layer and a GaN layer as the first semiconductor, and the second semiconductor and the second charge source are p-type graphene provided on the AlGaN layer opposite to the GaN layer.

[0036] This allows thermally excited electrons generated in GaN to directly recombine with holes in the valence band of P-type graphene, allowing recombination with virtually no potential difference, thereby suppressing heat generation.

[0037] A charge discharge element according to a fourteenth aspect of the present disclosure is a charge discharge element according to any one of the first to eighth aspects, and includes a plurality of stacked bodies each including the second semiconductor, the first semiconductor, the first charge source, and the second charge source.

[0038] This allows each of the plurality of laminates to absorb heat from the heat source, making it possible to obtain a higher heat absorption effect.

[0039] A charge drain element according to a fifteenth aspect of the present disclosure is a charge drain element according to any one of the first to fourteenth aspects, wherein the metastable energy level of the first semiconductor and the metastable energy level of the second semiconductor are set to a resonant state.

[0040] As a result, the thermally excited first charge of the first conductivity type and the second charge of the second conductivity type recombine at the same energy level set in the resonance state. That is, the first charge and the second charge can directly recombine with a sufficiently small potential difference. Since there is substantially no potential difference in the path of charge recombination, it is possible to suppress heat generation when the charge is discharged.

[0041] A charge discharging device according to a sixteenth aspect of the present disclosure is the charge discharging device according to any one of the first to fifteenth aspects, further comprising the heat source.

[0042] This allows the charge discharging element to be formed integrally with the heat source, so that heat from the heat source is prevented from escaping to other elements.

[0043] A cooling device according to a seventeenth aspect of the present disclosure includes the charge discharging element according to any one of the first to sixteenth aspects, and cools the heat source.

[0044] This makes it possible to suppress heat generation when discharging electric charges, thereby enabling the heat source to be cooled efficiently.

[0045] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0046] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0047] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, the same reference numerals are used for components that are substantially the same as those in other figures, and redundant explanations are omitted or simplified.

[0048] Although specific values ​​such as film thickness and energy barrier height are given in this specification, these values ​​can be changed as appropriate. The charge discharging element according to the present disclosure is not limited to the specific values ​​shown below.

[0049] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upper) and lower direction (vertically lower) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked structure. Furthermore, the terms "upper" and "lower" are used not only when two components are arranged with a gap between them and another component is present between them, but also when two components are arranged in close contact with each other and the two components are in contact. In this specification, the side on which the electrode is provided relative to the substrate is considered to be the "upper side (above)." Furthermore, the upper surface of the substrate may be referred to as the "front surface," and the lower surface of the substrate may be referred to as the "rear surface."

[0050] In addition, in this specification, N-type and P-type refer to the conductivity type (polarity) of a semiconductor. N-type is one of the first conductivity type and the second conductivity type, and P-type is the other of the first conductivity type and the second conductivity type. Specifically, an N-type semiconductor is a semiconductor containing N-type impurities. Depending on the concentration of the N-type impurities, N-type is also called N-type, N+ type, or N++ type. The concentration of N-type impurities is greater in N++ type than in N+ type, and N+ type is greater than in N- type. In other words, the concentrations of N-type impurities are N-type, N+ type, and N++ type in ascending order. Furthermore, P-type semiconductors are semiconductors containing P-type impurities. Depending on the concentration of the P-type impurities, P-type is also called P-type, P+ type, or P++ type. The concentration of P-type impurities is greater in P++ type than in N+ type, and P+ type is greater than P- type. In other words, the concentrations of P-type impurities are P-type, P+ type, and P++ type in descending order. For example, when the semiconductor is silicon, the N-type impurity is a Group V element such as phosphorus (P), and the P-type impurity is a Group III element such as boron (B).

[0051] In this specification, the term "same energy level" means that the energy levels are substantially equal. When charge transfer (e.g., recombination) occurs at the same energy level, no change in potential occurs, and the potential difference is substantially zero, so thermal relaxation does not occur. The same energy level can also be referred to as an energy level set in a resonance state.

[0052] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0053] First Embodiment First, the configuration of a charge discharging element according to a first embodiment will be described with reference to FIG.

[0054] 1 is a cross-sectional view of a charge draining element 100 according to the present embodiment. As shown in FIG. 1, the charge draining element 100 includes a silicon substrate 101, an N-type region 102, a Schottky electrode 103, a heat source 104, a P+ type region 105, a gate insulating film 106, a P++ type polysilicon gate 107, a gate electrode 108, a P++ type region 109, a Schottky electrode 110, and a high-concentration hole accumulation layer 111. The N- type region 102, the P+ type region 105, and the P++ type region 109 are semiconductor regions (impurity regions) made of N-type silicon or P-type silicon formed by adding N-type impurities or P-type impurities to the silicon substrate 101 at concentrations appropriate for each region.

[0055] Specifically, an N-type region 102 is formed in a surface layer portion of a P-type silicon substrate 101 to which a bias voltage of 0 V is applied (grounded to ground potential). Furthermore, a Schottky electrode 103 made of Cu / Ti / TiN is formed on the surface of the N-type region 102. Note that Cu / Ti / TiN means that a layer made of TiN (TiN layer) is the bottom layer, a layer made of Cu (Cu layer) is the top layer, and a layer made of Ti (Ti layer) is located between the Cu layer and the TiN layer. In other words, the TiN layer located in the bottom layer is in contact with the N-type region 102 to form a Schottky junction.

[0056] The Schottky electrode 103 is in thermal contact with the heat source 104. The Schottky electrode 103 is electrically floating. A P+ region 105 having a higher concentration than the silicon substrate 101 is formed in the silicon substrate 101 near the surface adjacent to the N- region 102. Furthermore, a 3-nm-thick gate insulating film 106 is formed on the silicon substrate 101 (at least on the P+ region 105). The gate insulating film 106 is, for example, an insulating film such as a silicon oxide film, but is not particularly limited thereto. The term "thermal contact" refers to contact that transfers heat from the heat source. An example of thermal contact is contact between the main surface of the Schottky electrode 103 and the heat dissipation surface of the heat source 104.

[0057] A P++ type polysilicon gate 107 is formed on the gate insulating film 106. Furthermore, a gate electrode 108 is formed on the polysilicon gate 107. A P++ type region 109 is formed in the outermost surface portion of the P+ type region 105. The P++ type region 109 is formed in a position that does not overlap with the polysilicon gate 107 in a plan view of the silicon substrate 101. With this structure, by applying a negative bias of −1.2 V to the gate electrode 108, the P++ type region 109 functions as a hole source (source S). A negative bias of about 10 V is applied to the outermost surface portion of the P+ type region 105. １２ cm ２ A high-concentration hole accumulation layer 111 is formed.

[0058] Furthermore, a Schottky electrode 110 made of Cu / Ti / TiN is formed adjacent to the P++ type region 109 in the surface layer portion of the silicon substrate 101. The Schottky electrode 110 is in thermal contact with the heat source 104. The Schottky electrode 110 is biased to 0 V. With this structure, holes excited by heat absorbed from the heat source 104 are supplied from the Fermi level of the Schottky electrode 110 to the P- type silicon substrate 101. Furthermore, when a negative bias of −1.2 V is applied to the gate electrode 108, holes are supplied from the Schottky electrode 110 via the P- type silicon substrate 101 to the high-concentration hole accumulation layer 111, which is at the same potential level.

[0059] Next, the potential profile of the charge discharging element 100 according to this embodiment and the discharging operation of thermally excited charges will be described.

[0060] In the charge discharging element 100 according to the present embodiment, the Schottky electrode 103 is an example of a first charge source capable of supplying a first charge of a first conductivity type excited by heat supplied from the heat source 104. The Schottky electrode 103 is also an example of a junction electrode having a barrier height with respect to the first semiconductor. The Schottky electrode 110 is an example of a second charge source capable of supplying a second charge of a second conductivity type excited by heat supplied from the heat source 104. The Schottky electrode 110 is also an example of a junction electrode having a barrier height with respect to the second semiconductor. In the present embodiment, the first charge of the first conductivity type is an electron, and the second charge of the second conductivity type is a hole.

[0061] The heat source 104 is another element provided on the same substrate as the charge discharging element 100. For example, the heat source 104 is an LSI (Large Scale Integration) or an IC (Integrated Circuit). Alternatively, the heat source 104 may be another device different from the charge discharging element 100. For example, the heat source 104 may be a motor or an amplifier. The heat source 104 does not have to be one, and may include a plurality of different heat sources.

[0062] The N-type region 102 is an example of a first semiconductor having a metastable energy level of electrons. The P-type silicon substrate 101, the high-concentration hole accumulation layer 111, and the P++-type region 109 are examples of a second semiconductor having a metastable energy level of holes. In this embodiment, the metastable energy level of electrons in the N-type region 102 is set to a state of resonance with the metastable energy level of holes in the high-concentration hole accumulation layer 111. Specifically, the N-type region 102 and the high-concentration hole accumulation layer 111 form a tunnel junction. Electrons supplied from the Schottky electrode 110 to the N-type region 102 and holes supplied from the Schottky electrode 110 to the high-concentration hole accumulation layer 111 recombine at the same energy level.

[0063] In this embodiment, the Schottky electrode 103 is joined to the N-type region 102 via a potential barrier. The electrons supplied from the Schottky electrode 110 to the N-type region 102 are electrons (thermal electrons) emitted from the Schottky electrode 103 by heat from the heat source 104. The Schottky electrode 110 is joined to the P-type silicon substrate 101 via a potential barrier. The holes supplied from the Schottky electrode 110 to the high-concentration hole accumulation layer 111 via the silicon substrate 101 and the P++ type region 109 are holes (thermal holes) emitted from the Schottky electrode 110 by heat from the heat source 104.

[0064] The means for forming the high-concentration hole accumulation layer 111 shown in this embodiment is not limited to the polysilicon gate 107 and the gate electrode 108 described above. １３ cm －２ ~10 １５ cm －２ If the value is set to a value equal to or greater than a predetermined value in the range of 106, the polysilicon gate 107 is not required. Similarly, the same effect can be achieved by other charge generating means, such as implanting negative ions such as metal ions into the gate insulating film 106, forming the gate insulating film 106 from a metal oxide film or a material having dielectric polarization properties, or introducing fixed negative charges at the interface between the gate insulating film 106 and Si (silicon substrate 101). In this way, the charge discharging element 100 may be provided with charge generating means equivalent to the case where negative charges are charged on the outermost surface of the gate insulating film 106.

[0065] Fig. 2A is a schematic diagram of the potential profile of the charge discharging element 100 according to the present embodiment shown in Fig. 1. Specifically, Fig. 2A shows the potential profile in the path of the Schottky electrode 103 → N-type region 102 → silicon substrate 101 → high-concentration hole accumulation layer 111 → P++-type region 109 → Schottky electrode 110 in the vicinity of the surface of the silicon substrate 101. In Fig. 2A, the corresponding region of the potential diagram for each component on the path is shown by dashed lines, arrows, and shading.

[0066] Region 203 is a potential diagram showing the occupation state of electrons in Schottky electrode 103. The top level of region 203 is the Fermi level of Schottky electrode 103, and E Ｆ The Fermi level E Ｆ is in a floating state in the circuit, as clearly shown by the capacitive circuit element C.

[0067] The region 202 adjacent to the region 203 is shown in the potential (energy band) diagram corresponding to the N-type region 102. The energy levels of the conduction band and the valence band are respectively represented by E Ｃ , E Ｖ The Fermi level E of the Schottky electrode 103 (region 203) Ｆ is the conduction band E Ｃ That is, the Schottky electrode 103 is joined (Schottky junction) to the N-type region 102 via a potential barrier.

[0068] 1, in this embodiment, a narrow region of the silicon substrate 101 is provided between the outermost surface portion of the N-type region 102 and the high-concentration hole accumulation layer 111. The width of this region is extremely narrow, about 2 nm. In addition, a high electric field is generated between the high-concentration hole accumulation layer 111 and the N-type region 102.

[0069] 2A shows an energy band diagram of the narrow region of the silicon substrate 101. The large slope of the region 201a schematically represents the high electric field described above.

[0070] Regions 211 and 209 are energy band diagrams corresponding to the high-concentration hole accumulation layer 111 and the P++ region 109, respectively. The potentials of regions 211 and 209 are controlled by the gate electrode 108. By applying a negative bias of −1.2 V to the gate electrode 108, the P++ region 109 (region 209) becomes a hole source (referred to as source S), and a high-concentration hole channel is formed.

[0071] Region 201b adjacent to region 209 is an energy band diagram corresponding to the P-type silicon substrate 101. Specifically, region 201b corresponds to the overlapping portion of the surface layer of silicon substrate 101 that overlaps with Schottky electrode 110 in plan view and the portion between this overlapping portion and P++ type region 109.

[0072] Region 210 is a potential diagram showing the hole occupation state in Schottky electrode 110. The lowest hole occupation level of region 210 is when a bias voltage of 0 V is applied, and the Fermi level E Ｆ It can be written as:

[0073] The Schottky electrode 110 (region 210) emits holes excited by heat absorbed from the heat source 104 to the silicon substrate 101 (region 201b). As shown in FIG. 2A , the holes emitted (thermally excited) from the region 210 cross the potential barrier to reach the region 201b on the source (S) side, and are supplied to the high-concentration hole accumulation layer 111 (region 211) via the region 201b.

[0074] On the other hand, the Schottky electrode 103 (region 203) emits electrons excited by heat absorbed from the heat source 104 to the N-type region 102 (region 202). The electrons emitted from the region 203 reach the region 202 over the potential barrier. Since the electric field in the region 201a is very high, the conduction band E Ｃ The electrons emitted (thermally excited) to the region 201a easily tunnel through the region 201a, allowing the tunneled electrons to directly recombine with holes in the region 211. The region 202 functions as the drain (D) of the high-concentration hole channel (high-concentration hole accumulation layer 111).

[0075] As described above, in this embodiment, thermally excited electrons are discharged from the N-type region 102 (region 202) to the high-concentration hole accumulation layer 111 (region 211). Since there is no potential difference in the electron migration path, heat generation is suppressed. Furthermore, holes that have disappeared in the high-concentration hole accumulation layer 111 are supplied with low impedance from the Schottky electrode 110 (region 210). Therefore, the charge discharging element 100 according to this embodiment can continuously dissipate excited thermions and thermally excited holes by absorbing heat from the heat source 104 in contact with the Schottky electrodes 103 and 110, respectively. As a result, it is possible to cool the heat source 104. Furthermore, since the Schottky electrode 103, which functions as an electron source, is in a floating state, energy can be stored in the capacitance during electron emission, thereby improving the effective amount of heat absorbed during the emission of one electron. In other words, the cooling efficiency can also be improved compared to when the potential is maintained at a low level.

[0076] FIG. 2B is an effective equivalent circuit diagram of the charge drain element 100 according to this embodiment. The drain (D) side input circuit is represented by a Schottky diode consisting of a Schottky electrode 103 (region 203) and an N-type region 102 (region 202). A portion of the silicon substrate 101 (region 201a) corresponding to the drain end forms a tunnel junction. Specifically, the N-type region 102 (region 202), the tunnel junction (region 201a), and the high-concentration hole accumulation layer 111 (region 211) form a tunnel diode. The cathode of this tunnel diode is different from that of a normal tunnel diode. Specifically, the anode of the diode itself forms the high-concentration hole accumulation layer 111 (region 211), and the bias of the cathode is controlled by the edge electric field of the polysilicon gate 107. On the other hand, on the hole source (S) side, a Schottky diode consisting of the Schottky electrode 110 (region 210) and a part of the silicon substrate 101 (region 201b) is depicted outside the polysilicon gate 107.

[0077] Second Embodiment Next, a second embodiment will be described.

[0078] 3 is a cross-sectional view of a charge draining element 300 according to the present embodiment. As shown in FIG. 3, the charge draining element 300 includes a silicon substrate 301, an N-type region 302, an ohmic electrode 303, a heat source 304, a P+ type region 305, a gate insulating film 306, a polysilicon gate 307, a gate electrode 308, a P++ type region 309, an ohmic electrode 310, a high-concentration hole accumulation layer 311, and an N++ type region 312. The N- type region 302, the N++ type region 312, the P+ type region 305, and the P++ type region 309 are semiconductor regions (impurity regions) made of N-type silicon or P-type silicon formed by adding N-type impurities or P-type impurities to the silicon substrate 301 at concentrations appropriate for each region.

[0079] Specifically, an N-type region 302 is formed in a surface layer portion of a P-type silicon substrate 301 to which a bias voltage of 0 V is applied. Furthermore, an N++-type region 312 is formed in a surface layer portion of the N-type region 302. An ohmic electrode 303 made of Cu / Ti / TiN / Ti is formed on the surface of the N++-type region 312. The ohmic electrode 303 is ohmically connected to the N++-type region 312.

[0080] The ohmic electrode 303 is in thermal contact with a heat source 304. The ohmic electrode 303 is in an electrically floating state. A P+ type region 305 having a higher concentration than the silicon substrate 301 is formed in the silicon substrate 301 near the surface adjacent to the N- type region 302. Furthermore, a gate insulating film 306 having a thickness of 3 nm is formed on the silicon substrate 301 (at least the P+ type region 305). The gate insulating film 306 is, for example, an insulating film such as a silicon oxide film, but is not particularly limited to this.

[0081] A P++ type polysilicon gate 307 is formed on the gate insulating film 306. Furthermore, a gate electrode 308 is formed on the polysilicon gate 307. A P++ type region 309 is formed in the outermost surface portion of the P+ type region 305. The P++ type region 309 is formed in a position that does not overlap with the polysilicon gate 307 in a plan view of the silicon substrate 101. An ohmic electrode 310 made of Cu / Ti / TiN / Ti is connected to the P++ type region 309. A bias voltage of 0 V is applied to the ohmic electrode 310. As a result, holes are supplied from the ohmic electrode 310 to the P++ type region 309 without a voltage drop. On the other hand, by applying a negative bias of −1.2 V to the gate electrode 308, a voltage drop of about 10 V is applied to the outermost surface portion of the P+ type region 305. １２ cm ２ A high concentration hole accumulation layer 311 is formed.

[0082] Next, the potential profile of the charge discharging element 300 according to this embodiment and the discharging operation of thermally excited charges will be described.

[0083] In the charge draining element 300 according to this embodiment, the N++ region 312 and the N- region 302 are an example of a first charge source capable of supplying a first charge of a first conductivity type excited by heat supplied from the heat source 304. The N++ region 312 and the N- region 302 are also an example of a first semiconductor having a metastable energy level of the first charge. In this embodiment, the first semiconductor includes the first charge source. The heat source 304 is the same as the heat source 104.

[0084] The P++ region 309 is an example of a second charge source capable of supplying a second charge of a second conductivity type. The P- type silicon substrate 301, the high-concentration hole accumulation layer 311, and the P++ region 309 are an example of a second semiconductor having a metastable energy level of a second charge. In this embodiment, the second semiconductor includes a second charge source. The first charge of the first conductivity type is an electron, and the second charge of the second conductivity type is a hole.

[0085] In this embodiment, the metastable energy level of electrons in the N-type region 302 is set to a state of resonance with the metastable energy level of holes in the high-concentration hole accumulation layer 311. Specifically, the N-type region 302 and the high-concentration hole accumulation layer 311 form a tunnel junction. The electrons supplied to the N-type region 302 and the holes supplied to the high-concentration hole accumulation layer 311 recombine at the same energy level. In this embodiment, the electrons supplied to the N-type region 302 are electrons (thermions) generated in the N-type region 302 and the N++ type region 312 by heat from the heat source 304.

[0086] The means for forming the high-concentration hole accumulation layer 311 shown in this embodiment is not limited to the polysilicon gate 307 and the gate electrode 308 described above. １３ cm －２ ~10 １５ cm －２ If the value is set to a value equal to or greater than a predetermined value in the range of (1), the polysilicon gate 307 is not required. Similarly, it is possible to obtain the same effect by implanting negative ions such as metal ions into the gate insulating film 306, by forming the gate insulating film 306 from a metal oxide film or a material having dielectric polarization properties, or by introducing fixed negative charges into the interface between the gate insulating film 306 and Si (silicon substrate 301), or by other means.

[0087] Fig. 4A is a schematic diagram of the potential profile of the charge discharging element 300 according to the present embodiment shown in Fig. 3. Specifically, Fig. 4A shows the potential profile in the path of the ohmic electrode 303 near the surface of the silicon substrate 301, followed by the N++ region 312, the N- region 302, the silicon substrate 301, the high-concentration hole accumulation layer 311, the P++ region 309, and the ohmic electrode 310. In Fig. 4A, the corresponding region of the potential diagram for each component on the path is indicated by dashed lines, arrows, and shading.

[0088] Region 403 is a potential diagram showing the occupation state of electrons in the ohmic electrode 303. The top level of region 403 is the Fermi level of the ohmic electrode 303, and EＦ The Fermi level E Ｆ is in a floating state in the circuit, as clearly shown by the capacitive circuit element C.

[0089] The region 412 adjacent to the region 403 is a potential (energy band) diagram of the N++ type region 312. The region 402 adjacent to the region 412 is a potential diagram corresponding to the N- type region 302. The energy levels of the conduction band and the valence band are respectively represented by E Ｃ , E Ｖ It is written as follows.

[0090] Here, the valence bands E Ｖ are excited by the heat supplied from the heat source 304, and the electrons in the conduction band E Ｃ That is, in this embodiment, the N-type region 302 and the N++ type region 312 function as electron sources.

[0091] 3, in this embodiment, a narrow region of the silicon substrate 301 is provided between the outermost surface portion of the N-type region 302 and the high-concentration hole accumulation layer 311. The width of this region is extremely narrow, about 2 nm. In addition, a high electric field is generated between the high-concentration hole accumulation layer 311 and the N-type region 302.

[0092] 4A shows an energy band diagram of the narrow region of silicon substrate 301. The large slope of region 401 represents the high electric field described above.

[0093] Regions 411 and 409 are energy band diagrams corresponding to the high-concentration hole accumulation layer 311 and the P++ region 309, respectively. The potentials of regions 411 and 409 are controlled by the gate electrode 308. By applying a negative bias of −1.2 V to the gate electrode 308, the P++ region 309 and the ohmic electrode 310 become a hole source (source S), and a high-concentration hole channel is formed.

[0094] Region 410 is a potential diagram showing the electron occupation state in ohmic electrode 310. The top electron occupation level of region 410 is the Fermi level E Ｆ The ohmic electrode 310 (region 410) functions as a hole supply source (source S) to the P++ region 309 and the high-concentration hole accumulation layer 311.

[0095] As shown in FIG. 4A, the electric field in region 401 is so high that the conduction band E C The thermally excited electrons easily tunnel through the region 401. This allows the tunneled electrons to directly recombine with holes in the region 411. The region 402 functions as the drain (D) of the high-concentration hole channel (high-concentration hole accumulation layer 311).

[0096] As described above, in this embodiment, thermally excited electrons are discharged from the N-type region 302 (region 402) to the high-concentration hole accumulation layer 311 (region 411). Since there is no potential difference in the electron migration path, heat generation is suppressed. Furthermore, holes that have disappeared in the high-concentration hole accumulation layer 311 are supplied with low impedance from the ohmic electrode 310 (region 410). Therefore, the charge discharging element 300 according to this embodiment can continuously dissipate excited thermoelectrons by absorbing heat from the heat source 304 in contact with the ohmic electrode 303. As a result, it is possible to cool the heat source 304. Furthermore, since the N-type region 302 and the N++-type region 312, which function as electron sources, are in a floating state, energy can be stored in the capacitance during electron generation, thereby improving the effective amount of heat absorbed during the generation of a single electron. In other words, the cooling efficiency can also be improved compared to when a low potential is maintained.

[0097] FIG. 4B is an effective equivalent circuit diagram of the charge drain element 300 according to this embodiment. The input circuit on the drain (D) side is simply a wiring (straight line). This is because the ohmic electrode 303 (region 403) is in ohmic contact with the N++ region 312 and the N- region 302 (regions 412 and 402). The silicon substrate 301 (region 401), which corresponds to the drain end, forms a tunnel junction. Specifically, the N- region 302 (region 402), the tunnel junction (region 401), and the high-concentration hole accumulation layer 311 (region 411) form a tunnel diode. The cathode of this tunnel diode is different from that of a normal tunnel diode. Specifically, the anode of the diode itself forms the high-concentration hole accumulation layer 311 (region 411), and the bias of the cathode is controlled by the edge electric field of the polysilicon gate 307.

[0098] Third Embodiment Next, a third embodiment will be described.

[0099] 5 is a cross-sectional view of a charge discharging element 500 according to this embodiment. As shown in Fig. 5, the charge discharging element 500 includes a GaN substrate 501, an AlGaN thin film 502, a polysilicon layer 503, a Schottky electrode 504, a 2DEG (two-dimensional electron gas) 505, an ohmic electrode 506, and a heat source 507. The layered structure of the GaN substrate 501 and the AlGaN thin film 502 is an example of a layered structure of a GaN layer and an AlGaN layer included in the charge discharging element 500.

[0100] Specifically, a 2-nm-thick Al film was formed on an N-type GaN substrate 501 to which a bias voltage of 0 V was applied. ０．２５ Ga ０．７５ An AlGaN thin film 502 made of N is formed. Furthermore, a P-type polysilicon layer 503 is formed on the AlGaN thin film 502. Furthermore, a Schottky electrode 504 is formed in contact with the P-type polysilicon layer 503. The Schottky electrode 504 is made of TiN and is in thermal contact with a heat source 507.

[0101] At the interface between the AlGaN thin film 502 and the N-type GaN substrate 501, the concentration is about 10 １３ / cm ２ 2DEG 505 is generated.

[0102] The ohmic electrode 506 is made of Ti / Al and is in ohmic contact with the 2DEG 505. A bias voltage of 0 V is applied to the ohmic electrode 506.

[0103] In the charge discharging element 500 according to this embodiment, a current flows along the path of the Schottky electrode 504, the P-type polysilicon layer 503, the AlGaN thin film 502, the 2DEG 505, and the ohmic electrode 506. That is, the charge discharging element 500 forms a two-terminal circuit having the Schottky electrode 504 and the ohmic electrode 506 as terminals.

[0104] Next, the potential profile of the charge discharging element 500 according to this embodiment and the discharging operation of thermally excited charges will be described.

[0105] In the charge drain element 500 according to this embodiment, the Schottky electrode 504 is an example of a first charge source capable of supplying a first charge of a first conductivity type excited by heat supplied from the heat source 507. The P-type polysilicon layer 503 is an example of a first semiconductor having a metastable energy level of the first charge. The 2DEG 505 is an example of a second charge source capable of supplying a second charge of a second conductivity type. The GaN substrate 501 including the 2DEG 505 is an example of a second semiconductor having a metastable energy level of the second charge. In this embodiment, the second semiconductor includes a second charge source. The first charge of the first conductivity type is a hole, and the second charge of the second conductivity type is an electron. The heat source 507 is the same as the heat source 104.

[0106] In this embodiment, the metastable energy level of holes in the polysilicon layer 503 is set to a state of resonance with the metastable energy level of electrons in the 2DEG 505. Specifically, the polysilicon layer 503 and the 2DEG 505 form a tunnel junction. The holes supplied to the polysilicon layer 503 and the electrons supplied to the 2DEG 505 recombine at the same energy level. In this embodiment, the holes supplied to the polysilicon layer 503 are holes (thermal holes) emitted from the Schottky electrode 504 by heat from the heat source 507.

[0107] Fig. 6A is a schematic diagram of the potential profile of the charge discharging element 500 according to the present embodiment shown in Fig. 5. Specifically, Fig. 6A shows the potential profile in the path of the Schottky electrode 504 → P-type polysilicon layer 503 → AlGaN thin film 502 → 2DEG 505 → ohmic electrode 506. In Fig. 6A, the corresponding region of the potential diagram for each component on the path is shown by dashed lines, arrows, and shading.

[0108] Region 604 is a potential diagram that represents the hole occupancy state in Schottky electrode 504. The top level of region 604 is the Fermi level of Schottky electrode 504, and E Ｆ The Fermi level E Ｆ is in a floating state in the circuit, as clearly shown by the capacitive circuit element C.

[0109] The region 603 adjacent to the region 604 is a potential diagram corresponding to the P-type polysilicon layer 503. The energy levels of the conduction band and the valence band are respectively represented by E Ｃ , E Ｖ The Fermi level E of the Schottky electrode 504 (region 604) Ｆ and the valence band E of the P-type polysilicon layer 503 (region 603). Ｖ A potential barrier having a height of 1000 nm for holes is formed between the Fermi level E Ｆ The holes in the valence band EＶ That is, in this embodiment, the Schottky electrode 504 (region 604) functions as a hole source.

[0110] Region 602 adjacent to region 603 is an energy band diagram corresponding to the AlGaN thin film 502. Furthermore, region 601 is an energy band diagram for the GaN substrate 501. At the interface between the GaN substrate 501 (region 601) and the AlGaN thin film 502 (region 602), a 2DEG 505 due to piezoelectric polarization is generated. Region 605 shows the energy level corresponding to the 2DEG 505.

[0111] The AlGaN thin film 502 has a wider band gap than the GaN substrate 501. Therefore, the charge conduction at the band edge is negligibly small. The thickness of the AlGaN thin film 502 is as thin as about 2 nm. Therefore, the valence band E Ｖ Holes from the AlGaN thin film 502 and electrons from the 2DEG 505 (region 605) can tunnel through the AlGaN thin film 502 (region 602).

[0112] In this embodiment, the valence band E Ｖ The energy levels of the 2DEG 505 (region 605) are equal when no external voltage is applied. Therefore, holes and electrons can directly recombine without power loss. Therefore, the charge discharging element 500 according to this embodiment can continuously eliminate excited hot holes by absorbing heat from the heat source 507 in contact with the Schottky electrode 504 (region 604). As a result, it is possible to cool the heat source 507. Furthermore, since the Schottky electrode 504 (region 604), which functions as a hole source, is in a floating state, energy can be stored in the capacitance during hole emission, thereby improving the effective amount of heat absorbed during hole emission. In other words, the cooling efficiency can also be improved compared to when the potential is maintained at a low level.

[0113] Furthermore, in this embodiment, it is not necessary to apply a high bias voltage to either the Schottky electrode 504 or the ohmic electrode 506. For example, the transfer of charges can be promoted by applying a slight potential difference of 0.05 V or more and 1.0 V or less between the Schottky electrode 504 and the ohmic electrode 506. Therefore, the charge discharging element 500 can cool the heat source 507 while sufficiently reducing power loss.

[0114] The GaN substrate 501 may be thermally connected to a heat source 507. The electrons supplied to the 2DEG 505 may be electrons excited by heat supplied from the heat source 507.

[0115] 6B is an effective equivalent circuit diagram of the charge drain element 500 according to this embodiment. The input circuit on the hole source side is represented by a Schottky diode consisting of a Schottky electrode 504 (region 604) and a P-type polysilicon layer 503 (region 603). The AlGaN thin film 502 (region 602) forms a tunnel junction. Specifically, the P-type polysilicon layer 503 (region 603), the AlGaN thin film 502 (region 602), and the 2DEG 505 (region 605) form a tunnel diode.

[0116] (Fourth embodiment) Next, a fourth embodiment will be described.

[0117] 7 is a cross-sectional view of a charge discharging element 700 according to this embodiment. As shown in Fig. 7, the charge discharging element 700 includes an N-type silicon substrate 701, an N++-type silicon layer 702, an ohmic electrode 703, an N-type GaN layer 704, a P-type graphene layer 705, and an ohmic electrode 706.

[0118] Specifically, an N++ type silicon layer 702 formed by ion implantation is formed on the surface of an N type silicon substrate 701 to which a bias voltage of 0 V is applied. Furthermore, an ohmic electrode 703 made of Cu / Ti / TiN / Ti is formed on the N++ type silicon layer 702. The ohmic electrode 703 is electrically grounded to ground potential and thermally connected to a heat source 707.

[0119] An N-type GaN layer 704 having a thickness of 200 nm, a P-type graphene layer 705, and an ohmic electrode 706 are formed in this order on an N-type silicon substrate 701 in a region avoiding the ohmic electrode 703. The ohmic electrode 706 is made of an alloy containing Ca, Gd, and Eu, and is electrically grounded to ground potential. In the charge discharging element 700 according to this embodiment, a current flows along the path of the ohmic electrode 703 → N++-type silicon layer 702 → GaN layer 704 → P-type graphene layer 705 → ohmic electrode 706. That is, the charge discharging element 700 forms a two-terminal circuit having the ohmic electrode 703 and the ohmic electrode 706 as terminals.

[0120] Next, the potential profile of the charge discharging element 700 according to this embodiment and the discharging operation of thermally excited charges will be described.

[0121] In the charge draining element 700 according to this embodiment, the N++ silicon layer 702 is an example of a first charge source capable of supplying a first charge of a first conductivity type excited by heat supplied from the heat source 707. The N++ silicon layer 702 is also an example of a first semiconductor having a metastable energy level of the first charge. In this embodiment, the first semiconductor includes the first charge source.

[0122] Furthermore, the P-type graphene layer 705 is an example of a second charge source capable of supplying a second charge of a second conductivity type. Furthermore, the graphene layer 705 is an example of a second semiconductor having a metastable energy level of the second charge. In this embodiment, the second semiconductor includes a second charge source. The first charge of the first conductivity type is an electron, and the second charge of the second conductivity type is a hole. The heat source 707 is the same as the heat source 104.

[0123] The N++ type silicon layer 702 and the P type graphene layer 705 are bonded to each other via the GaN layer 704. The electrons supplied to the N++ type silicon layer 702 and the holes supplied to the graphene layer 705 recombine at the same energy level. In this embodiment, the electrons supplied to the N++ type silicon layer 702 are electrons (thermions) generated in the N++ type silicon layer 702 by heat from the heat source 707.

[0124] Fig. 8A is a schematic diagram of the potential profile of the charge discharging element 700 according to the present embodiment shown in Fig. 7. Specifically, Fig. 8A shows a potential profile (energy band diagram) along the path of the ohmic electrode 703 → the N++-type silicon layer 702 → the GaN layer 704 → the P-type graphene layer 705 → the ohmic electrode 706. In Fig. 8A, the corresponding region of the potential diagram for each component on the path is indicated by dashed lines, arrows, and shading.

[0125] Region 803 is a potential diagram showing the occupation state of electrons in the ohmic electrode 703. The top level of region 803 is the Fermi level of the ohmic electrode 703, and E Ｆ The Fermi level E Ｆ The ground symbol clearly indicates that the device is electrically grounded.

[0126] The region 802 adjacent to the region 803 is a potential diagram corresponding to the N++ type silicon layer 702. The energy levels of the conduction band and the valence band are respectively represented by E Ｃ , E Ｖ The region 804 adjacent to the region 802 is a potential diagram corresponding to the GaN layer 704. The energy levels of the conduction band and the valence band are denoted as E Ｃ , E Ｖ The conduction band E of the N++ type silicon layer 702 (region 802) Ｃ and the conduction band E of the GaN layer 704 (region 804). Ｃ A potential barrier with a height of 0.7 eV is formed between the electrons and the surface.

[0127] The region 805 adjacent to the region 804 is a potential diagram corresponding to the P-type graphene layer 705 formed on the GaN layer 704. The level of the tip of the pseudo-Dirac cone of the graphene layer 705 is the conduction band E Ｃ However, the Fermi level is lowered by about 0.1 eV due to defects. Therefore, the region 805 is in the valence band E Ｖ is shown as

[0128] A region 806 adjacent to the region 805 represents the hole occupation state in the ohmic electrode 706 .

[0129] In this embodiment, electrons in the N++ type silicon layer 702 (region 802) are excited by absorbing heat from the heat source 707, and the conduction band E Ｃ The excited electrons are supplied to the conduction band E Ｃ The valence band E of the graphene layer 705 (region 805) is at the same level as Ｖ The electrons directly recombine with the holes in the electron-side ohmic electrode 703 (region 803) and the hole-side ohmic electrode 706 (region 806) are both grounded and have approximately the same potential. This allows for a charge discharging operation with little power loss, i.e., little heat generation. Therefore, the charge discharging element 700 according to this embodiment can continuously dissipate excited thermoelectrons by absorbing heat from the heat source 707. As a result, it becomes possible to cool the heat source 707.

[0130] Furthermore, in this embodiment, it is not necessary to apply a high bias voltage to either of the ohmic electrodes 703 and 706. For example, the transfer of charges can be promoted by applying a slight potential difference of 0.05 V or more and 1.0 V or less between the ohmic electrodes 703 and 706. Therefore, the charge discharging element 700 can cool the heat source 707 while sufficiently minimizing power loss.

[0131] The P-type graphene layer 705 may be thermally connected to a heat source 707. The holes supplied to the graphene layer 705 may be holes excited by heat supplied from the heat source 707.

[0132] 8B is an effective equivalent circuit diagram of the charge draining element 700 according to this embodiment. The charge draining element 700 forms a PN diode consisting of a P-type graphene layer 705 and an N++-type silicon layer 702. The input (cathode) on the electron source side is an ohmic electrode 703, and the input (anode) on the hole source side is an ohmic electrode 706.

[0133] Fifth Embodiment Next, a fifth embodiment will be described.

[0134] 9 is a cross-sectional view showing an example of the configuration of a charge discharging element 900 according to this embodiment. As shown in Fig. 9, the charge discharging element 900 includes an N-type GaN substrate 901, an AlGaN thin film 902, a 2DEG 903, an ohmic electrode 904, a P-type graphene layer 905, and an ohmic electrode 906. The layered structure of the GaN substrate 901 and the AlGaN thin film 902 is an example of the layered structure of the GaN layer and the AlGaN layer included in the charge discharging element 900.

[0135] Specifically, a 2-nm-thick Al film was formed on a GaN substrate 901 to which a bias voltage of 0 V was applied. ０．２５ Ga ０．７５ An AlGaN thin film 902 made of N is formed on the GaN substrate 901. In the vicinity of the surface of the N-type GaN substrate 901, which is the interface between the GaN substrate 901 and the AlGaN thin film 902, the concentration due to piezoelectric polarization is 10 １３ cm －２ A 2DEG 903 having a thickness of 1000 nm is formed. An ohmic electrode 904 made of Ti / TiAl is formed in the region where part of the AlGaN thin film 902 has been removed.

[0136] The ohmic electrode 904 is electrically grounded to the ground potential. The ohmic electrode 904 is also thermally in contact with a heat source 907. A P-type graphene layer 905 and an ohmic electrode 906 are formed in this order on the AlGaN thin film 902 in a region avoiding the ohmic electrode 904. The ohmic electrode 906 is made of an alloy containing Ca, Gd, and Eu, and is electrically grounded to the ground potential.

[0137] In the charge discharging element 900 according to this embodiment, a current flows along the path of the ohmic electrode 904 → N-type GaN substrate 901 → 2DEG 903 → AlGaN thin film 902 → P-type graphene layer 905 → ohmic electrode 906. That is, the charge discharging element 900 forms a two-terminal circuit in which the ohmic electrode 904 serves as a cathode terminal and the ohmic electrode 906 serves as an anode terminal.

[0138] Next, the potential profile of the charge discharging element 900 according to this embodiment and the discharging operation of thermally excited charges will be described.

[0139] In the charge draining element 900 according to this embodiment, the 2DEG 903 is an example of a first charge source capable of supplying a first charge of a first conductivity type excited by heat supplied from the heat source 907. The GaN substrate 901 including the 2DEG 903 is an example of a first semiconductor having a metastable energy level of the first charge. In this embodiment, the first semiconductor includes a first charge source. The P-type graphene layer 905 is an example of a second charge source capable of supplying a second charge of a second conductivity type. The graphene layer 905 is an example of a second semiconductor having a metastable energy level of the second charge. In this embodiment, the second semiconductor includes a second charge source. The first charge of the first conductivity type is an electron, and the second charge of the second conductivity type is a hole. The heat source 907 is the same as the heat source 104.

[0140] The electrons supplied to the 2DEG 903 and the holes supplied to the P-type graphene layer 905 recombine at the same energy level. In this embodiment, the electrons supplied to the 2DEG 903 are supplied from the ohmic contact and induced at the interface by piezoelectric polarization.

[0141] Fig. 10A is a schematic diagram of the potential profile of the charge discharging element 900 according to the present embodiment shown in Fig. 9. Specifically, Fig. 10A shows the potential profile (energy band diagram) in the path of the ohmic electrode 904 → GaN substrate 901 → 2DEG 903 → AlGaN thin film 902 → P-type graphene layer 905 → ohmic electrode 906. In Fig. 10A, the corresponding region of the potential diagram for each component on the path is shown by dashed lines, arrows, and shading.

[0142] Region 1004 is a potential diagram that represents the occupation state of electrons in the ohmic electrode 904. The top level of region 1004 is the Fermi level of the ohmic electrode 904, and E Ｆ The Fermi level E ＦThe ground symbol clearly indicates that the device is electrically grounded.

[0143] A region 1001 adjacent to the region 1004 is a potential diagram corresponding to the GaN substrate 901. A region 1003 is a potential diagram corresponding to the 2DEG 903 located in the outermost surface portion of the GaN substrate 901.

[0144] The region 1002 adjacent to the region 1003 is a potential diagram corresponding to the AlGaN thin film 902. The energy levels of the conduction band and the valence band are denoted by E Ｃ , E Ｖ Due to the piezoelectric polarization occurring between the GaN substrate 901 and the GaN substrate 902, an internal electric field is generated that runs from left to right on the paper surface of FIG. 10A, i.e., has an upward sloping slope.

[0145] The conduction band E of the 2DEG 903 (region 1003) and the AlGaN thin film 902 (region 1002) Ｃ A potential barrier with a height of 0.7 eV is formed between the electrons.

[0146] The region 1005 adjacent to the region 1002 is a potential diagram corresponding to the P-type graphene layer 905 formed on the AlGaN thin film 902. The level of the tip of the pseudo-Dirac cone of the graphene layer 905 is the conduction band E Ｃ However, the Fermi level is lowered by about 0.1 eV due to defects. Therefore, the region 1005 is in the valence band E Ｖ is shown as

[0147] A region 1006 adjacent to the region 1005 represents the hole occupation state in the ohmic electrode 906 .

[0148] In this embodiment, electrons in the 2DEG 903 (region 1003) are thermally excited by absorbing heat from the heat source 907, and the conduction band E Ｃ The excited electrons are supplied to the rightmost end of the conduction band E Ｃ The valence band E of the graphene layer 905 (region 1005) is at the same level asＶ The electrons directly recombine with the holes. The electron-side ohmic electrode 904 (region 1004) and the hole-side ohmic electrode 906 (region 1006) are both at the same potential, i.e., grounded. This allows for a charge discharging operation with little power loss, i.e., little heat generation. Therefore, the charge discharging element 900 according to this embodiment can continuously dissipate excited thermoelectrons by absorbing heat from the heat source 907. As a result, it becomes possible to cool the heat source 907.

[0149] Furthermore, in this embodiment, there is no need to apply a high bias voltage to either of the ohmic electrodes 904 and 906. For example, the transfer of charges can be promoted by applying a slight potential difference of 0.05 V or more and 1.0 V or less between the ohmic electrodes 904 and 906. Therefore, the charge discharging element 900 can cool the heat source 907 while sufficiently minimizing power loss.

[0150] The P-type graphene layer 905 may be thermally connected to a heat source 907. The holes supplied to the graphene layer 905 may be holes excited by heat supplied from the heat source 907.

[0151] 10B is an effective equivalent circuit diagram of the charge draining element 900 according to this embodiment. The charge draining element 900 forms a PN diode consisting of a P-type graphene layer 905 and a 2DEG 903. The electron source side input (cathode) is an ohmic electrode 904, and the hole side input (anode) is an ohmic electrode 906.

[0152] Sixth Embodiment Next, a sixth embodiment will be described.

[0153] Fig. 11 is a cross-sectional view showing an example of the configuration of a charge discharging element 1100 according to this embodiment. The charge discharging element 1100 includes a plurality of laminated bodies. As shown in Fig. 11, the plurality of laminated bodies includes a first layer L1, a second layer L2, and a third layer L3. The first layer L1, the second layer L2, and the third layer L3 have the same configuration. The number of laminated bodies may be two, or may be four or more.

[0154] The first layer L1 includes a GaN layer 1101, an AlGaN thin film 1102, a 2DEG 1103, and a P-type graphene layer 1104. The GaN layer 1101, the AlGaN thin film 1102, the 2DEG 1103, and the P-type graphene layer 1104 are substantially the same as the GaN substrate 901, the AlGaN thin film 902, the 2DEG 903, and the P-type graphene layer 905 according to the fifth embodiment.

[0155] Specifically, a 2-nm-thick Al film was formed on the N-type GaN layer 1101. ０．２５ Ga ０．７５ An AlGaN thin film 1102 made of N is formed on the GaN layer 1101. In the vicinity of the surface of the N-type GaN layer 1101, which is the interface between the GaN layer 1101 and the AlGaN thin film 1102, the concentration due to the piezoelectric polarization is 10 １３ cm －２ A 2DEG 1103 having a P-type conductivity is formed on the AlGaN thin film 1102. Furthermore, a P-type graphene layer 1104 is formed on the AlGaN thin film 1102. This constitutes a device denoted as a first layer L1.

[0156] The configuration of the first layer L1 is substantially the same as that of the charge discharging element 900 according to the fifth embodiment. However, in the charge discharging element 1100 according to the present embodiment, as shown in FIG. 11 , a via plug 1105 is formed that extends from the P-type graphene layer 1104 to the rear surface. An insulating film 1106 is provided to cover the side surface of the via plug 1105. The insulating film 1106 prevents the via plug 1105 from contacting and electrically connecting with the GaN layer 1101, the AlGaN thin film 1102, the 2DEG 1103, and the graphene layer 1104.

[0157] Furthermore, a metal film 1107 containing conductive carbon and Ti / TiAl is formed on the back surface. The metal film 1107 is a good conductor and has low resistance, and also contains Ti / TiAl. Therefore, the metal film 1107 can form good ohmic contact with GaN. The metal film 1107 is electrically grounded to ground potential. Furthermore, because the metal film 1107 contains conductive carbon, it also achieves low thermal resistance thermal contact with a heat source 1108 disposed below the back surface.

[0158] In this embodiment, three layers, each having the same structure as the first layer L1, are stacked as the first layer L1 to the third layer L3. Thermoelectric contact between each layer is achieved with low resistance by welding conductive carbon. Therefore, in each layer, the GaN layer 1101 can absorb heat from the heat source 1108 with low resistance.

[0159] Next, the potential profile of the charge discharging element 1100 according to this embodiment and the discharging operation of thermally excited charges will be described.

[0160] In the charge discharging element 1100 according to this embodiment, the first layer L1, the second layer L2, and the third layer L3 each have a first charge source, a second charge source, a first semiconductor, and a second semiconductor. The following description focuses on the first layer L1. The second layer L2 and the third layer L3 are the same as the first layer L1, and therefore will not be repeated here.

[0161] Specifically, in the first layer L1, the 2DEG 1103 is an example of a first charge source capable of supplying a first charge of a first conductivity type excited by heat supplied from the heat source 1108. The GaN layer 1101 including the 2DEG 1103 is an example of a first semiconductor having a metastable energy level of a first charge. In this embodiment, the first semiconductor includes a first charge source. The P-type graphene layer 1104 is an example of a second charge source capable of supplying a second charge of a second conductivity type. The graphene layer 1104 is an example of a second semiconductor having a metastable energy level of a second charge. In this embodiment, the second semiconductor includes a second charge source. The first charge of the first conductivity type is an electron, and the second charge of the second conductivity type is a hole. The heat source 1108 is the same as the heat source 104.

[0162] The electrons supplied to the 2DEG 1103 and the holes supplied to the P-type graphene layer 1104 recombine at the same energy level. In this embodiment, the electrons supplied to the 2DEG 1103 are supplied from the ohmic contact and induced at the interface by piezoelectric polarization.

[0163] 12A is a schematic diagram of the potential profile of the charge discharging element 1100 according to the present embodiment shown in FIG. 11 . Specifically, FIG. 12A shows a potential profile (energy band diagram) for a path from the via plug 1105 to the GaN layer 1101 to the 2DEG 1103 to the AlGaN thin film 1102 to the P-type graphene layer 1104 to the metal film 1107, corresponding to each component of the first layer L1 to the third layer L3 in FIG. 11 . Note that, to avoid complicating the drawing, reference numerals are assigned only to portions corresponding to the first layer L1. Also, in FIG. 12A , dashed lines, arrows, and shading indicate which regions of the potential diagram each component on the path corresponds to.

[0164] Region 1205 is a potential diagram showing the occupation state of electrons in the via plug 1105. The top level of region 1205 is the Fermi level of the via plug 1105, and E Ｆ The Fermi level E Ｆ The ground symbol clearly indicates that the device is electrically grounded.

[0165] A region 1201 adjacent to the region 1205 is a potential diagram corresponding to the GaN layer 1101. A region 1203 is a potential diagram corresponding to the 2DEG 1103 located in the outermost surface portion of the GaN layer 1101.

[0166] The region 1202 adjacent to the region 1203 is a potential diagram corresponding to the AlGaN thin film 1102. The energy levels of the conduction band and the valence band are denoted by E Ｃ , E Ｖ Due to the piezoelectric polarization occurring between the GaN layer 1101 and the GaN layer 1102, an internal electric field is generated that runs from left to right on the paper surface of FIG. 12A, i.e., has an upward sloping slope.

[0167] Conduction band E of the 2DEG 1103 (region 1203) and the AlGaN thin film 1102 (region 1202) Ｃ A potential barrier with a height of 0.7 eV is formed between the electrons.

[0168] The region 1204 adjacent to the region 1202 is a potential diagram corresponding to the P-type graphene layer 1104 formed on the AlGaN thin film 1102. The level of the tip of the pseudo-Dirac cone of the graphene layer 1104 is the conduction band E Ｃ However, the Fermi level is lowered by about 0.1 eV due to defects. Therefore, the region 1204 is in the valence band E Ｖ is shown as

[0169] A region 1207 adjacent to the region 1204 represents the hole occupation state in the metal film 1107 .

[0170] In this embodiment, electrons in the 2DEG 1103 (region 1203) are thermally excited by absorbing heat from the heat source 1108, and the conduction band E Ｃ The excited electrons are supplied to the rightmost end of the conduction band E Ｃ The valence band E of the graphene layer 1104 (region 1204) is at the same level as Ｖ The electrons directly recombine with the holes in the charge drain element 1100. The charge drain element 1100 has a three-layer structure of such diodes. The three electron-side via plugs 1105 (region 1205) and the hole-side metal film 1107 (region 1207) are all at approximately the same potential, close to the ground state. This allows for charge draining with little power loss, i.e., little heat generation. Therefore, the charge drain element 1100 of this embodiment can continuously dissipate excited thermoelectrons by absorbing heat from the heat source 1108. As a result, it is possible to cool the heat source 1108 three times more efficiently than the charge drain element 900 of embodiment 5.

[0171] FIG. 12B is an effective equivalent circuit diagram of the charge draining element 1100 according to this embodiment. The charge draining element 1100 has a configuration in which three PN diodes, each consisting of a P-type graphene layer 1104 (region 1204) and a 2DEG 1103 (region 1203), are connected in series. The electron source input (cathode) is the via plug 1105 (region 1205), and the hole input (anode) is connected to the metal film 1107 (region 1207) and grounded. Inside the charge draining element 1100, as described above, thermally excited electrons recombine with holes in the graphene layer 1104 in each of the first to third layers L1 to L3. This allows holes to be supplied from the ground potential, cooling the heat source 1108. Furthermore, heat generation due to a voltage drop caused by a current flowing through the charge draining element 1100 is suppressed.

[0172] In the present embodiment, an example has been shown in which a plurality of structures equivalent to the charge discharging element 900 according to embodiment 5 are stacked, but this is not limiting. A plurality of structures equivalent to the charge discharging elements 100, 300, 500, or 700 according to embodiments 1 to 4 may be stacked. Furthermore, the plurality of stacks may include stacks of different structures. For example, structures equivalent to the charge discharging elements according to different embodiments may be stacked.

[0173] Seventh Embodiment Next, a seventh embodiment will be described.

[0174] Fig. 13 is a block diagram showing the configuration of a cooling device according to this embodiment. As shown in Fig. 13, the cooling device 1300 includes a charge discharging element 100 and a contact portion 1301. When the contact portion 1301 is brought into contact with a heat source 104, the charge discharging element 100 cools the heat source 104.

[0175] The charge draining element 100 is the charge draining element 100 shown in embodiment 1. The cooling device 1300 may include at least one of the charge draining elements 300, 500, 700, 900, and 1100 instead of or in addition to the charge draining element 100. By including a plurality of charge draining elements, the cooling device 1300 can improve the cooling effect of the heat source 104.

[0176] Although the cooling device 1300 in FIG. 13 cools the heat source 104, it may cool the heat source 304, 507, 707, 907, or 1108.

[0177] Although the charge discharging element according to one or more aspects has been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as it does not deviate from the gist of the present disclosure, various modifications that a person skilled in the art can make to each embodiment and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0178] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0179] The charge discharging element and cooling device of the present disclosure can be used as a charge discharging element that can suppress heat generation during charge discharging, and can be used, for example, as a cooling device for semiconductor devices, electronic circuits, etc. In this way, the charge discharging element and cooling device of the present disclosure are industrially useful.

[0180] 100, 300, 500, 700, 900, 1100 Charge drain element 101, 301, 701 Silicon substrate 102, 302 N-type region 103, 110, 504 Schottky electrode 104, 304, 507, 707, 907, 1108 Heat source 105, 305 P+ type region 106, 306 Gate insulating film 107, 307 Polysilicon gate 108, 308 Gate electrode 109, 309 P++ type region 111, 311 High concentration hole accumulation layer 201a, 201b, 202, 203, 209, 210, 211, 401, 402, 403, 409, 410, 411, 412, 601, 602, 603, 604, 605, 802, 803, 804, 805, 806, 1001, 1002, 1003, 1004, 1005, 1006, 1201, 1202, 1203, 1204, 1205, 1207 Region 303, 310, 506, 703, 706, 904, 906 Ohmic electrode 312 N++ type region 501, 901 GaN substrate 502, 902, 1102 AlGaN thin film 503 Polysilicon layer 505, 903, 1103 2DEG 702 N++ type silicon layer 704, 1101 GaN layer 705, 905, 1104 Graphene layer 1105 Via plug 1106 Insulating film 1107 Metal film 1300 Cooling device 1301 Contact portion

Claims

1. A charge draining element comprising: a first charge source that supplies a first charge of a first conductivity type excited by heat from a heat source; a first semiconductor having a metastable energy level of the first charge; a second charge source that supplies a second charge of a second conductivity type; and a second semiconductor having a metastable energy level of the second charge, wherein the first charge supplied to the first semiconductor from the first charge source and the second charge supplied to the second semiconductor from the second charge source recombine at the same energy level.

2. The charge drain element according to claim 1, wherein the first semiconductor and the second semiconductor form a tunnel junction.

3. A charge discharging element as described in claim 1 or 2, wherein the first charge source is joined to the first semiconductor via a potential barrier, and the first charge supplied to the first semiconductor is an electron or a hole emitted from the first charge source by heat from the heat source.

4. A charge drain element as described in claim 1 or 2, wherein the first semiconductor includes the first charge source, and the first charge supplied to the first semiconductor is an electron or a hole generated in the first semiconductor by heat from the heat source.

5. The charge discharging element according to claim 1 or 2, wherein the second charge source supplies the second charge excited by heat from the heat source to the second semiconductor.

6. A charge drain element as described in claim 5, wherein the first charge source is joined to the first semiconductor via a potential barrier, and the first charge supplied to the first semiconductor is one of electrons and holes emitted from the first charge source by heat from the heat source, and the second charge source is joined to the second semiconductor via a potential barrier, and the second charge supplied to the second semiconductor is the other of electrons and holes emitted from the second charge source by heat from the heat source.

7. A charge drain element as described in claim 5, wherein the first semiconductor includes the first charge source, and the first charge supplied to the first semiconductor is one of electrons and holes generated in the first semiconductor by heat from the heat source, and the second semiconductor includes the second charge source, and the second charge supplied to the second semiconductor is the other of electrons and holes generated in the second semiconductor by heat from the heat source.

8. The charge drainage element according to claim 1, wherein the first charge source is an electrode having a barrier height with respect to the first semiconductor and is in an electrically floating state.

9. The charge drain element according to claim 8, comprising: a silicon substrate; the first semiconductor is an N-type impurity region provided in the silicon substrate; the second semiconductor is a high-concentration hole accumulation region formed in at least a portion of the silicon substrate; and the second charge source is a junction electrode having a barrier height relative to the second semiconductor.

10. The charge drain element of claim 1, comprising a silicon substrate, the first semiconductor and the first charge source being an N-type impurity region provided in the silicon substrate, the second charge source being a P-type impurity region provided in the silicon substrate, and the second semiconductor being a high concentration hole region formed in at least a portion of the P-type impurity region.

11. The charge drainage element according to claim 1, wherein the charge drainage element has a laminated structure of an AlGaN layer and a GaN layer which is the second semiconductor, the second charge source is a two-dimensional electron gas generated between the AlGaN layer and the GaN layer, the first semiconductor includes P-type silicon provided on the AlGaN layer on the opposite side to the GaN layer, and the first charge source is an electrode connected to the P-type silicon via a Schottky connection.

12. The charge draining element of claim 1, comprising a GaN layer provided between the first semiconductor and the second semiconductor, the first semiconductor and the first charge source being N-type silicon, and the second semiconductor and the second charge source being P-type graphene.

13. The charge drainage element of claim 1, wherein the charge drainage element has a laminated structure of an AlGaN layer and a GaN layer which is the first semiconductor, and the second semiconductor and the second charge source are P-type graphene provided on the side of the AlGaN layer opposite to the GaN layer.

14. The charge draining element of claim 1, comprising a plurality of stacks including the second semiconductor, the first semiconductor, the first charge source, and the second charge source.

15. A charge discharging element according to any one of claims 1, 2 and 8 to 14, wherein the metastable energy level of the first semiconductor and the metastable energy level of the second semiconductor are set in a resonant state.

16. The charge discharging element according to any one of claims 1, 2 and 8 to 14, further comprising the heat source.

17. A cooling device comprising the charge discharging element according to any one of claims 1, 2 and 8 to 14, for cooling the heat source.

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