Testing device, testing method, and program

Abstract

Provided is a testing device comprising a voltage generating unit that generates an offset voltage, a control unit that controls the offset voltage and the timing at which the offset voltage is changed, a signal amplifying unit that amplifies the difference between an analog input signal input from a device under test and the offset voltage controlled by the control unit and outputs an analog amplified signal, a measuring unit that measures the analog amplified signal, and a restoring unit that uses the voltage value of the offset voltage to restore the voltage value of the analog input signal from the voltage value measured by the measuring unit, wherein the voltage generating unit changes the offset voltage such that an expected voltage value of the analog input signal is included in a measurement window of a predetermined voltage range.

Description

Testing device, testing method and program

[0001] The present invention relates to a test device, a test method, and a program.

[0002] Patent Document 1 describes an "input device for a signal processing device capable of AD-converting a part of a processed signal with good resolution." [Prior art documents] [Patent documents] [Patent document 1] Japanese Utility Model Application Publication No. 2-58840 General disclosure

[0003] In a first aspect of the present invention, there is provided a test apparatus comprising: a voltage generating section that generates an offset voltage; a control section that controls the offset voltage and the timing for changing the offset voltage; a signal amplifying section that amplifies the difference between an analog input signal input from a device under test and the offset voltage controlled by the control section, and outputs an analog amplified signal; a measuring section that measures the analog amplified signal; and a restoration section that uses the voltage value of the offset voltage to restore the voltage value of the analog input signal from the voltage value measured by the measuring section, wherein the voltage generating section changes the offset voltage so that the expected voltage value of the analog input signal falls within a measurement window of a predetermined voltage range.

[0004] In the test apparatus, the control unit may generate a test pattern for executing a predetermined test program, and the control unit may control a timing for changing the offset voltage in synchronization with the test pattern.

[0005] The test apparatus may further include a storage unit configured to store a voltage table including time-series data generated using the expected voltage value of the analog input signal corresponding to the test program, and the voltage generating unit may change the offset voltage based on the voltage table so that the expected voltage value falls within the measurement window.

[0006] In any of the above test apparatuses, the voltage generating section may include a DA converter, and the storage section may store the voltage table, which is generated using time-series data of the voltage expected values ​​and includes time-series data of voltage values ​​the number of which corresponds to a resolution of the DA converter or less.

[0007] In any of the above test devices, the voltage table may be generated based on expected waveform data of the analog input signal.

[0008] In any of the above test devices, the signal amplifier unit may include a plurality of signal amplifier circuits provided on the same board, and the voltage generator unit may include a DA converter provided on the same board and configured to input a common offset voltage to at least two or more of the plurality of signal amplifier circuits.

[0009] In any of the above test devices, the voltage generating section may include one DA converter that inputs a common offset voltage to the plurality of signal amplifier circuits.

[0010] In any of the above test devices, the plurality of signal amplifier circuits may be classified into a plurality of groups, and the voltage generating section may include a plurality of DA converters each inputting a common offset voltage to each of the plurality of groups.

[0011] In any of the above test devices, each of the plurality of DA converters may change the common offset voltage so that the expected voltage value of the analog input signal corresponding to each of the plurality of groups falls within the measurement window.

[0012] In any of the above test devices, the signal amplifier unit may include a plurality of signal amplifier circuits provided on the same board, and the voltage generator unit may include a plurality of DA converters provided on the same board, each of which inputs the offset voltage to each of the plurality of signal amplifier circuits.

[0013] Any of the above test devices may include a correction section that corrects errors generated in the voltage generating section, the signal amplifying section, or the measuring section using a predetermined correction coefficient.

[0014] In a second aspect of the present invention, there is provided a testing method comprising the steps of generating an offset voltage, amplifying the difference between an analog input signal input from a device under test and the offset voltage and outputting an analog amplified signal, measuring the analog amplified signal, and using the voltage value of the offset voltage to restore the voltage value of the analog input signal from the voltage value measured in the step of measuring the analog amplified signal, wherein the step of generating the offset voltage includes a step of changing the offset voltage so that the expected voltage value of the analog input signal falls within a measurement window of a predetermined voltage range.

[0015] In a third aspect of the present invention, there is provided a program that is executed by a computer provided in a test apparatus to cause the test apparatus to function as a voltage generation unit that generates an offset voltage, a control unit that controls the offset voltage and the timing of changing the offset voltage, a signal amplification unit that amplifies the difference between an analog input signal input from a device under test and the offset voltage and outputs an analog amplified signal, a measurement unit that measures the analog amplified signal, and a restoration unit that uses the voltage value of the offset voltage to restore the voltage value of the analog input signal from the voltage value measured by the measurement unit, wherein the voltage generation unit changes the offset voltage so that the expected voltage value of the analog input signal is included in a measurement window of a predetermined voltage range.

[0016] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0017] 1 shows an example of the configuration of the test apparatus 100 together with the device under test 10. 1 shows an example of the configuration of the acquiring section 20. 1 shows an example of generation of an offset voltage by the voltage generating section 210. 1 shows an example of a voltage table stored in the storage section 260. 1 shows a modified example of a voltage table stored in the storage section 260. 1 shows an example of the measurement resolution of the test apparatus 100. 1 shows a modified example of the configuration of the test apparatus 100 together with the device under test 10. 1 shows a modified example of the configuration of the acquiring section 20. 1 shows a modified example of the configuration of the acquiring section 20. 1 shows a modified example of the configuration of the test apparatus 100 together with the device under test 10. 1 shows an example of a computer 1000 in which multiple aspects of the present invention may be embodied in whole or in part.

[0018] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0019] 1 shows an example of the configuration of a test apparatus 100 together with a device under test 10. Note that the blocks shown are functionally separated functional blocks and do not necessarily correspond to the actual device configuration. That is, blocks shown as one block in this diagram do not necessarily have to be configured by one device. Also, blocks shown as separate blocks in this diagram do not necessarily have to be configured by separate devices.

[0020] The test apparatus 100 includes an acquisition section 20 and a judgment section 30, and tests a device under test 10 such as an analog circuit, a memory, or a system-on-chip (SOC). For example, the device under test 10 is a display driver that controls pixels of a display. The device under test 10 may be capable of outputting signals with multiple gradations. For example, the device under test 10 may be capable of outputting signals with 256 gradations, 1024 gradations, or 4096 gradations. The test apparatus 100 judges the acceptability of the device under test 10 based on the analog input signal input from the device under test 10.

[0021] The acquiring section 20 acquires an analog input signal input from the device under test 10. The acquiring section 20 may convert the acquired analog input signal into a digital signal and supply the acquired result to the judging section 30. The judging section 30 judges whether the device under test 10 is good or bad based on the acquired result by the acquiring section 20.

[0022] The acquisition section 20 includes a voltage generation section 210, a control section 220, a signal amplification section 230, a measurement section 240, and a restoration section 250. The acquisition section 20 may include a storage section 260.

[0023] The voltage generating section 210 generates an offset voltage. The voltage generating section 210 may supply the generated offset voltage to the signal amplifying section 230. The voltage generating section 210 changes the offset voltage so that the expected voltage value of the analog input signal input from the device under test 10 falls within a measurement window of a predetermined voltage range. The generation of the offset voltage by the voltage generating section 210 will be described in detail later.

[0024] The control unit 220 controls the offset voltage and the timing for changing the offset voltage. The control unit 220 may generate a test pattern for executing a predetermined test program. The control unit 220 may control the timing for changing the offset voltage in synchronization with the test pattern.

[0025] When the test apparatus 100 executes a predetermined test program, the device under test 10 inputs an analog input signal corresponding to the test program to the test apparatus 100. The control unit 220 may control the offset voltage and the timing for changing the offset voltage in accordance with an expected voltage value of the analog input signal corresponding to the test program. Furthermore, the device under test 10 inputs the analog input signal corresponding to the test program to the test apparatus 100 in synchronization with a test pattern for executing the test program. The control unit 220 may control the timing for changing the offset voltage in synchronization with the test pattern, so that the voltage generating section 210 changes the offset voltage so that the expected voltage value of the analog input signal falls within the measurement window.

[0026] The signal amplifying section 230 amplifies the difference between the analog input signal input from the device under test 10 and the offset voltage controlled by the control section 220, and outputs an analog amplified signal. The signal amplifying section 230 may supply the output analog amplified signal to the measuring section 240. The signal amplifying section 230 may amplify the difference between the analog input signal and the offset voltage by a predetermined amplification factor.

[0027] The measuring section 240 measures the analog amplified signal. The measuring section 240 may convert the measured analog value of the analog amplified signal into a digital value. The measuring section 240 may supply the digitally converted voltage value to the restoring section 250.

[0028] The measuring section 240 may measure the analog amplified signal within a predetermined input range. For example, the input range of the measuring section is from −FS to +FS, and the center voltage value of the measurement window is the voltage value V of the offset voltage generated by the voltage generating section 210. ｏｆｓ When the amplification factor of the signal amplifier 230 is G, the voltage range of the measurement window is (V ｏｆｓ -FS / G, V ｏｆｓ +FS / G). That is, the lower limit of the voltage range of the measurement window is V ｏｆｓ -FS / G, and the upper limit of the voltage range of the measurement window is V ｏｆｓ +FS / G. The voltage generating section 210 may change the offset voltage so that the expected voltage value of the analog input signal falls within the measurement window thus determined.

[0029] The control unit 220 may control the timing at which the measuring unit 240 measures the analog amplified signal. The control unit 220 may control the timing at which the measuring unit 240 measures the analog amplified signal in synchronization with a test pattern for executing a predetermined test program.

[0030] The restoration section 250 restores the voltage value of the analog input signal from the voltage value measured by the measurement section 240, using the voltage value of the offset voltage. In this example, the measurement section 240 measures the analog amplified signal output by the signal amplification section 230. In this example, the signal amplification section 230 amplifies the difference between the analog input signal and the offset voltage. Therefore, the restoration section 250 may restore the voltage value of the analog input signal by adding the voltage value of the offset voltage to the voltage value measured by the measurement section 240.

[0031] The control unit 220 may control the restoration of the voltage value of the analog input signal by the restoration unit 250. The control unit 220 may control the restoration of the voltage value of the analog input signal by the restoration unit 250 in synchronization with a test pattern for executing a predetermined test program. That is, the control unit 220 may supply the voltage value of the offset voltage synchronized with the test pattern to the restoration unit 250 as the voltage value to be added.

[0032] The storage unit 260 may store a voltage table including time-series data generated using expected voltage values ​​of an analog input signal corresponding to a test program. Details of the voltage table will be described later. The storage unit 260 may store a plurality of voltage tables. The storage unit 260 may supply the voltage tables to the voltage generating unit 210. The control unit 220 may control the voltage generating unit 210 to read out the voltage tables stored in the storage unit 260, or may control the storage unit 260 to supply the voltage tables to the voltage generating unit 210.

[0033] The voltage generating unit 210 may change the offset voltage based on the voltage table so that the expected voltage value falls within the measurement window. The control unit 220 of this example controls the timing at which the offset voltage is changed. The voltage generating unit 210 may refer to time-series data included in the voltage table at a time corresponding to the timing controlled by the control unit 220. The voltage generating unit 210 may change the offset voltage based on the voltage value at the referenced time in the voltage table so that the expected voltage value falls within the measurement window.

[0034] The test apparatus 100 of this example amplifies and measures the difference between the analog input signal input from the device under test 10 and the offset voltage generated by the voltage generating section 210, thereby improving the measurement resolution of the test apparatus 100 without improving the resolution of the measuring section 240 itself. In other words, the test apparatus 100 of this example can achieve high measurement resolution at low cost. Furthermore, the test apparatus 100 of this example changes the offset voltage so that the expected voltage value of the analog input signal falls within the measurement window. This significantly reduces the settling wait time compared to when the reference comparison voltage is changed to match the voltage of the analog input signal for each of multiple gradations of the analog input signal. As described above, the test apparatus 100 of this example can achieve high-precision, high-throughput testing at low cost.

[0035] 2 shows an example of the configuration of the acquisition unit 20. Note that the configuration of the acquisition unit 20 is not limited to this example as long as it can realize the functions of the above-mentioned functional blocks.

[0036] The voltage generating section 210 may include a DA converter 212. The DA converter 212 may convert a digital signal designated as an offset voltage into an analog signal to generate the offset voltage. The resolution of the DA converter 212 may be lower than the resolution of the measuring section 240. The resolution of the DA converter 212 may be a resolution that ensures that the expected voltage value of the analog input signal falls within the measurement window. As an example, the resolution of the DA converter 212 is 3 bits. However, the resolution of the DA converter 212 is not limited to this.

[0037] The signal amplifier section 230 may include a signal amplifier circuit 232. As an example, the signal amplifier circuit 232 is a differential amplifier circuit. An analog input signal from the device under test 10 may be input to a non-inverting input terminal of the signal amplifier circuit 232, and an offset voltage generated by the voltage generating section 210 may be input to an inverting input terminal of the signal amplifier circuit 232. In this manner, the signal amplifier section 230 may amplify the difference between the analog input signal and the offset voltage and output an analog amplified signal. The signal amplifier circuit 232 may amplify the difference between the analog input signal and the offset voltage by a predetermined amplification factor. For example, the amplification factor of the signal amplifier circuit 232 is designed according to the measurement resolution required for the test apparatus 100.

[0038] The measuring section 240 may include an AD converter 242. The AD converter 242 may convert the voltage value of the analog amplified signal output by the signal amplifying section 230 into a digital value and output the digital value. The AD converter 242 may have a predetermined resolution. For example, the resolution of the AD converter 242 is designed according to the measurement resolution value required for the test apparatus 100. As an example, the measurement resolution of the AD converter 242 is 16 bits. However, the resolution of the AD converter 242 is not limited to this.

[0039] In the test apparatus 100 of this example, the difference between the analog input signal input from the device under test 10 and the offset voltage generated by the voltage generating section 210 is amplified and measured, so the measurement resolution of the test apparatus 100 is higher than the resolution of the AD converter 242. Therefore, the test apparatus 100 of this example can improve the measurement resolution of the test apparatus 100 without improving the resolution of the AD converter 242, and can implement high-precision testing at low cost.

[0040] The restoration section 250 may include an adding / subtracting section 252. The adding / subtracting section 252 may add the voltage value of the offset voltage to the voltage value measured by the measuring section 240. In this manner, the restoration section 250 may restore the voltage value of the analog input signal from the voltage value measured by the measuring section 240.

[0041] 3 shows an example of offset voltage generation by the voltage generating unit 210. In the upper graph, the horizontal axis represents time, and the vertical axis represents voltage. In the graph, the solid line represents the offset voltage generated by the voltage generating unit 210, the dashed line represents the expected voltage value of the analog input signal, and the hatched area represents the measurement window. In this example, the center voltage value of the measurement window is the voltage value of the offset voltage. The horizontal axis in the middle corresponds to the horizontal axis of the upper graph, and each arrow indicates the sampling timing of the measuring unit 240. The horizontal axis in the lower graph also corresponds to the horizontal axis of the upper graph, and each arrow indicates the timing of changing the offset voltage.

[0042] The sampling timing of the measurement section 240 may be controlled so that the measurement section 240 measures the voltage for each gradation of the analog input signal. The control section 220 may control the sampling timing of the measurement section 240. The control section 220 may control the sampling timing at which the measurement section 240 measures the analog amplified signal in synchronization with a test pattern for executing a predetermined test program. In other words, the control section 220 may control the sampling timing in synchronization with the test pattern, so that the measurement section 240 measures the voltage for each gradation of the analog input signal.

[0043] In this example, one sampling timing is shown for each gradation, but this is not limiting. The measurement unit 240 may perform multiple measurements for each gradation, and may use the average value of the voltage values ​​obtained by the multiple measurements as the measurement result.

[0044] The timing of changing the offset voltage may be synchronized with the timing at which the gradation of the analog input signal switches. That is, whether or not to change the offset voltage may be determined each time the gradation of the analog input signal switches. The control unit 220 controls the timing of changing the offset voltage. The control unit 220 may control the timing of changing the offset voltage in synchronization with a test pattern for executing a predetermined test program. By the control unit 220 controlling the timing of changing the offset voltage in synchronization with the test pattern, the timing of changing the offset voltage may be synchronized with the timing at which the gradation of the analog input signal switches.

[0045] The control unit 220 performs various controls in synchronization with the test pattern, and may detect the timing at which the gradation of the analog input signal switches based on the expected voltage value of the analog input signal corresponding to the test program. When the control unit 220 detects a switch in the gradation of the analog input signal, the control unit 220 may trigger a determination as to whether or not the offset voltage should be changed. When it is determined that the offset voltage should be changed, the voltage generating unit 210 may change the offset voltage.

[0046] 3, for example, an arrow indicating the timing of changing the offset voltage is shown at the timing when the expected voltage value of the analog input signal switches from the first gradation to the second gradation. At this timing, the expected voltage value after the gradation switching is included in the current measurement window. Therefore, it is determined that the offset voltage will not be changed, and the voltage generating unit 210 does not change the offset voltage.

[0047] 3, an arrow indicates the timing of changing the offset voltage at the timing when the expected voltage value of the analog input signal switches from the fourth gradation to the fifth gradation. At this timing, the expected voltage value after the gradation switching is not included in the current measurement window. Therefore, it is determined that the offset voltage should be changed, and the voltage generating unit 210 changes the offset voltage so that the expected voltage value after the gradation switching is included in the measurement window.

[0048] The voltage change range of the offset voltage may be smaller than the predetermined voltage range of the measurement window. That is, a measurement window whose center voltage value is a first voltage value of the offset voltage and a measurement window whose center voltage value is a second voltage value of the offset voltage may have an overlapping voltage range. As an example, if the voltage change range of the offset voltage is 1.3 V and the voltage range of the measurement window is 2.0 V, adjacent measurement windows have an overlapping voltage range of 0.7 V. However, the values ​​of the voltage change range of the offset voltage, the voltage range of the measurement window, and the overlapping voltage range are not limited to these. For example, the voltage change range of the offset voltage and the voltage range of the measurement window are designed according to the measurement resolution required for the test apparatus 100.

[0049] By having adjacent measurement windows with overlapping voltage ranges, the voltage values ​​of the multiple gradations of the analog input signal may be included in at least one voltage range of the multiple measurement windows corresponding to the offset voltage, which allows the voltage generating unit 210 to change the offset voltage so that the expected voltage value is included in at least one of the measurement windows.

[0050] In the above description, the central voltage value of the measurement window is the voltage value of the offset voltage, but this is not limiting. The lower limit voltage value of the measurement window may be the voltage value of the offset voltage, and the upper limit voltage value of the measurement window may be the voltage value of the offset voltage.

[0051] 4A shows an example of a voltage table stored in the storage unit 260. The storage unit 260 may store a plurality of voltage tables. In this figure, one voltage table is shown as an example.

[0052] The voltage table may be generated based on expected waveform data of the analog input signal. The expected waveform data may be data obtained by previously measuring the analog input signal corresponding to a predetermined test program. Alternatively, the voltage table may be generated by direct input.

[0053] The voltage table may include expected voltage values ​​of the analog input signal corresponding to the test program as time-series data. The voltage table may include a correspondence relationship between the time after the corresponding test program is executed and the expected voltage value at that time. For example, the voltage table in this example may include a correspondence relationship between the time t after the corresponding test program is executed and the expected voltage value at that time. １ In this case, the expected value of the voltage of the analog input signal input from the device under test 10 to the test apparatus 100 is V １ This indicates that

[0054] The voltage generating unit 210 may change the offset voltage based on the voltage table so that the expected voltage value falls within the measurement window. The control unit 220 of this example controls the timing at which the offset voltage is changed. The voltage generating unit 210 may refer to time-series data included in the voltage table at a time corresponding to the timing controlled by the control unit 220. The voltage generating unit 210 may change the offset voltage based on the voltage value at the referenced time in the voltage table so that the expected voltage value falls within the measurement window. The voltage table of this example includes a correspondence between the time since the corresponding test program was executed and the expected voltage value at that time. Therefore, the voltage generating unit 210 of this example may change the offset voltage so that the voltage value (= expected voltage value) at the referenced time in the voltage table falls within the measurement window.

[0055] For example, the control unit 220 ３ When the timing of changing the offset voltage is controlled at time t ３ Then, the voltage generating unit 210 refers to the data of the referenced voltage value V ３ The offset voltage is changed so that the expected voltage value is included in the measurement window based on the voltage value V in this example. ３ is the expected voltage value itself, the voltage generating unit 210 generates the expected voltage value V ３ The offset voltage is changed so that is included in the measurement window.

[0056] 4B shows a modified example of the voltage table stored in the storage unit 260. In this figure, one voltage table is shown as an example, but the storage unit 260 may store a plurality of voltage tables.

[0057] The storage unit 260 may store a voltage table that is generated using the time-series data of the voltage expected value and includes time-series data of voltage values ​​up to a number corresponding to the resolution of the DA converter 212. That is, the storage unit 260 stores １ From t Ｎ and all N expected voltage values ​​V １ From V ＮInstead of storing M voltage values ​​V′, the number of which is equal to or less than the number corresponding to the resolution of the DA converter 212. １ From V' Ｍ The number according to the resolution of the DA converter 212 may be the number of offset voltages that the DA converter 212 can output in a distinguishable manner. For example, if the resolution of the DA converter 212 is 3 bits, the DA converter 212 can output 2 offset voltages. ３ = 8 offset voltages can be output in a distinguishable manner. In this case, the voltage table may have 8 or fewer voltage values ​​(i.e., M is 8 or less).

[0058] Each of the voltage values ​​in the voltage table may be any voltage value included in each of the measurement windows corresponding to the offset voltage. That is, each of the voltage values ​​in the voltage table may be any value whose expected voltage value is included in the measurement window corresponding to the offset voltage changed based on the voltage value in the voltage table. For example, the voltage value V' in the voltage table １ The measurement window corresponding to the offset voltage changed based on １ , V ２ and V ３ In this way, the voltage generating unit 210 may change the offset voltage based on the voltage table so that the expected voltage value is included in the measurement window. As an example, each of the voltage values ​​in the voltage table may be the same as each of the voltage values ​​of the offset voltage generated by the voltage generating unit 210. That is, the voltage value V' １ From V' Ｍ may be equal to each of the voltage values ​​of the offset voltage.

[0059] FIG. 5 shows an example of the measurement resolution of the test apparatus 100. In FIG. 5, the horizontal axis of the graph represents the measurement voltage range, and the vertical axis of the graph represents the resolution. The graph in FIG. 5 is a double logarithmic graph in which both the horizontal and vertical axes are represented on a logarithmic scale. The solid line represents the effective measurement resolution of the test apparatus 100, and the dashed line represents the resolution of the AD converter 242. In this example, the effective resolution of the test apparatus 100 is shown when an AD converter 242 with 16-bit resolution is used and the voltage change range of the offset voltage is set to 4.5 times the voltage range of the measurement window. Here, the voltage change range of the offset voltage is the difference between the maximum and minimum values ​​of the offset voltage that can be generated by the voltage generating unit 210. For example, if the maximum value of the offset voltage that can be generated by the voltage generating unit 210 is 9.5 V and the minimum value is 0.5 V, the voltage change range of the offset voltage is 9.5 V - 0.5 V = 9.0 V.

[0060] When the measurement resolution of the AD converter 242 is 16 bits, the measurement voltage range and the resolution satisfy the trade-off relationship shown by the dashed line. For example, when the measurement voltage range is 40 V, the voltage range is divided by 16 bits, so the resolution is 40 V / (2 １６ -1) = 0.61 mV.

[0061] In the test apparatus 100 of this example, the difference between the analog input signal input from the device under test 10 and the offset voltage generated by the voltage generating section 210 is amplified and measured, so the measurement resolution of the test apparatus 100 is higher than the resolution of the AD converter 242. For example, when measuring a measurement voltage range of 40 V with the test apparatus 100 of this example, a resolution of 0.12 mV (mV) is obtained. This is the same measurement resolution as when an AD converter with a resolution of 18.4 bits is used. In this way, the test apparatus 100 of this example can improve the measurement resolution of the test apparatus 100 without improving the resolution of the AD converter 242, making it possible to achieve high-precision testing at low cost.

[0062] Although this example shows the effective resolution of the test apparatus 100 when the AD converter 242 has a 16-bit resolution and the voltage change range of the offset voltage is set to 4.5 times the voltage range of the measurement window, it is understandable to those skilled in the art that the effect of improving the measurement resolution of the test apparatus 100 can be obtained even when the voltage change range of the offset voltage, etc. is changed. In other words, since the test apparatus 100 of this example amplifies and measures the difference between the analog input signal and the offset voltage, it is possible to improve the measurement resolution of the test apparatus 100 without improving the resolution of the AD converter 242, compared to when the analog input signal is measured directly by an AD converter.

[0063] 6 shows a modified example of the configuration of the test apparatus 100 together with the device under test 10. The device under test 10 may have multiple terminal sections 12. The test apparatus 100 may determine the acceptability of the device under test 10 based on analog input signals input from each of the multiple terminal sections 12. As an example, the device under test 10 may be a display driver having multiple terminal sections 12 that control multiple pixels of a display. Each of the multiple terminal sections 12 is associated with one of the display colors that make up the pixels of the display, and the arrangement of the multiple terminal sections 12 in the device under test 10 may correspond to the arrangement of the corresponding pixels in the display.

[0064] The acquiring section 20 may be connected to a plurality of terminal sections 12 of the device under test 10 via a plurality of channels Ch. In this example, the acquiring section 20 is connected to N terminal sections 12 via N channels Ch_1 to Ch_N.

[0065] 7A shows a modified example of the configuration of the acquisition unit 20. The acquisition unit 20 may perform the same functions as those described using FIGS. 1 to 5 for analog input signals input from each of the multiple terminal units 12. Note that the configuration of the acquisition unit 20 is not limited to this example as long as it can achieve the above-described functions.

[0066] The acquisition unit 20 may include a plurality of boards 200. Each board 200 may be connected to a predetermined number of terminal units 12. In this example, board 200a is connected to M terminal units 12 via channels Ch_1 to Ch_M, and board 200b is connected to (N-L+1) terminal units 12 via channels Ch_L to Ch_N. The number of terminal units 12 connected to each board 200 may be the same or different. As an example, the number of terminal units 12 connected to each board 200 is 128. That is, M = N-L + 1 = 128 may be satisfied. However, the number of terminal units 12 connected to each board 200 is not limited to this.

[0067] The signal amplifier unit 230 may have a plurality of signal amplifier circuits 232 provided on the same board 200. The number of the plurality of signal amplifier circuits 232 provided on each board 200 may be the same as the number of the plurality of terminal units 12 connected to each board 200. In this example, the board 200a may be provided with M signal amplifier circuits 232, and the board 200b may be provided with (N-L+1) signal amplifier circuits 232. In other words, each of the plurality of signal amplifier circuits 232 provided on each board 200 may be connected to each of the plurality of terminal units 12 connected to each board 200 via the corresponding channel Ch.

[0068] The measuring section 240 may have a plurality of AD converters 242 provided on the same board 200. The number of the AD converters 242 provided on each board 200 may be the same as the number of the terminal sections 12 connected to each board 200. In other words, the measuring section 240 may have a plurality of AD converters 242 for measuring analog input signals from each terminal section 12.

[0069] The restoration unit 250 may have a plurality of addition / subtraction units 252 provided on the same board 200. The number of the addition / subtraction units 252 provided on each board 200 may be the same as the number of the terminal units 12 connected to each board 200. In other words, the restoration unit 250 may have a plurality of addition / subtraction units 252 for restoring the voltage value of the analog input signal from each terminal unit 12.

[0070] The voltage generating unit 210 may be provided on the same board 200 as the multiple signal amplifier circuits 232, and may include a DA converter 212 that inputs a common offset voltage to at least two or more of the multiple signal amplifier circuits 232. The voltage generating unit 210 of this example includes one DA converter 212 on each board 200 that inputs a common offset voltage to the multiple signal amplifier circuits 232.

[0071] A control unit 220 may be provided for each board 200. The control unit 220 may control the offset voltage generated by the voltage generating unit 210 provided on the same board 200 and the timing for changing the offset voltage. The control unit 220 may control the timing for changing the offset voltage generated by the voltage generating unit 210 provided on the same board 200 in synchronization with a test pattern for executing a predetermined test program.

[0072] The storage unit 260 may be provided for each board 200. The storage unit 260 may supply a voltage table corresponding to a test program of a test pattern generated by the control unit 220 provided on the same board 200 to the voltage generation unit 210 provided on the same board 200.

[0073] The storage unit 260 may be provided in common to all of the boards 200. In this case, the storage unit 260 may supply the voltage table to the voltage generating unit 210 provided on each board 200.

[0074] The voltage generating unit 210 of this example includes a DA converter 212 that inputs a common offset voltage to multiple signal amplifier circuits 232 on each board 200. This shortens the signal path length that requires a high-speed response. By shortening the signal path length, the influence of interference noise during propagation can be reduced, improving test accuracy. Furthermore, because the influence of interference noise is small, the bandwidth limitation required to remove interference noise can be alleviated, and the settling wait time can be reduced.

[0075] The test apparatus 100 of this example amplifies and measures the difference between the analog input signal and the offset voltage, thereby enabling high-precision, high-throughput testing at low cost. Furthermore, in this example, a common DA converter 212 is provided for multiple signal amplifier circuits 232 on each board 200, thereby synergistically achieving the effect of enabling high-precision, high-throughput testing.

[0076] 7B shows a modified example of the configuration of the acquisition unit 20. The acquisition unit 20 of this example differs from the embodiment of FIG. 7A in that the voltage generation unit 210 has a plurality of DA converters 212 on each board 200. In this example, differences from the embodiment of FIG. 7A will be particularly described, and the rest may be the same as the embodiment of FIG. 7A.

[0077] The signal amplification section 230 may have multiple signal amplification circuits 232 provided on the same board 200. The multiple signal amplification circuits 232 may be classified into multiple groups. Each of the multiple terminal sections 12 of the device under test 10 has a predetermined response to a predetermined test program. The signal amplification circuits 232 connected to terminal sections 12 among the multiple terminal sections 12 that have the same response to the predetermined test program may be classified into the same group. In other words, the expected voltage values ​​of analog input signals input from the terminal sections 12 connected to signal amplification circuits 232 classified into the same group may be the same.

[0078] The voltage generating unit 210 may include, in each board 200, multiple DA converters 212, each of which inputs a common offset voltage to each of the multiple groups. When a predetermined test program is executed, the expected voltage value of the analog input signal input from the terminal unit 12 depends on the terminal unit 12. In this example, each of the multiple groups is connected to a terminal unit 12 having the same expected voltage value of the analog input signal. Therefore, each of the multiple DA converters 212 may change the common offset voltage so that the expected voltage value of the analog input signal corresponding to each of the multiple groups falls within the measurement window. The control unit 220 may control the timing at which each of the multiple DA converters 212 changes the offset voltage in synchronization with a test pattern for executing the predetermined test program. In this manner, the voltage generating unit 210 may change the offset voltage so that the expected voltage value of the analog input signal corresponding to each of the multiple groups falls within the measurement window.

[0079] The voltage generating section 210 in this example has four DA converters 212 on each board 200. Therefore, the multiple signal amplifier circuits 232 may be classified into four groups. That is, the terminal sections 12 of the device under test 10 may also be classified into four groups and may have four different responses. As an example, multiple terminal sections 12 associated with the same display color that constitutes the pixels of a display may be classified into the same group.

[0080] For example, when the test apparatus 100 executes a predetermined test program, the terminal unit 12 associated with the display color red exhibits a first response. The signal amplifier circuits 232 connected to the terminal unit 12 associated with the display color red may be classified into a first group. The DA converter 212, which inputs a common offset voltage to the first group, may change the offset voltage so that the expected voltage value of the analog input signal corresponding to the first response falls within the measurement window.

[0081] Additionally, when the test apparatus 100 executes a predetermined test program, the terminal unit 12 associated with the display color blue exhibits a second response. The signal amplifier circuits 232 connected to the terminal unit 12 associated with the display color blue may be classified into a second group. The DA converter 212 that inputs a common offset voltage to the second group may change the offset voltage so that the expected voltage value of the analog input signal corresponding to the second response falls within the measurement window.

[0082] Additionally, when the test apparatus 100 executes a predetermined test program, the terminal unit 12 associated with the green display color exhibits a third response. The signal amplifier circuits 232 connected to the terminal unit 12 associated with the green display color may be classified into a third group. The DA converter 212 that inputs a common offset voltage to the third group may change the offset voltage so that the expected voltage value of the analog input signal corresponding to the third response falls within the measurement window.

[0083] Additionally, when the test apparatus 100 executes a predetermined test program, the terminal unit 12 associated with the white display color exhibits a fourth response. The signal amplifier circuits 232 connected to the terminal unit 12 associated with the white display color may be classified into a fourth group. The DA converter 212 that inputs a common offset voltage to the fourth group may change the offset voltage so that the expected voltage value of the analog input signal corresponding to the fourth response falls within the measurement window.

[0084] For example, the DA converter 212a may input a common offset voltage to the first group, the DA converter 212b may input a common offset voltage to the second group, the DA converter 212c may input a common offset voltage to the third group, and the DA converter 212d may input a common offset voltage to the fourth group. In this way, the test apparatus 100 can collectively test the devices under test 10, which are display drivers that control RGBW displays.

[0085] However, there are no limitations to the number of groups and the number of DA converters 212. The number of DA converters 212 may be three or less, or five or more.

[0086] In the above description, the number of groups is equal to the number of DA converters 212, but this is not limiting. The number of DA converters 212 may be greater than the number of groups. In this case, there may be DA converters 212 that are not connected to any group.

[0087] As described above, the test apparatus 100 of this example can test multiple terminal units 12 that exhibit multiple different responses in parallel, thereby enabling the test apparatus 100 of this example to achieve a higher throughput than when multiple terminal units 12 that exhibit multiple different responses are tested sequentially.

[0088] The test apparatus 100 of this example amplifies and measures the difference between the analog input signal and the offset voltage, thereby enabling high-precision, high-throughput testing at low cost. Furthermore, in this example, the configuration in which multiple DA converters 212 are provided on each board 200 synergistically exhibits the effect of enabling high-throughput testing.

[0089] 7C shows a modified example of the configuration of the acquisition unit 20. The acquisition unit 20 of this example differs from the embodiment of FIGS. 7A and 7B in that the voltage generation unit 210 has a plurality of DA converters 212 that input offset voltages to the plurality of signal amplifier circuits 232 on each board 200. In this example, differences from the embodiment of FIGS. 7A and 7B will be particularly described, and the rest may be the same as the embodiment of FIGS. 7A and / or 7B.

[0090] The signal amplifier section 230 may have a plurality of signal amplifier circuits 232 provided on the same board 200. The voltage generator section 210 of this example has a plurality of DA converters 212 on each board 200, each of which inputs an offset voltage to a respective one of the plurality of signal amplifier circuits 232. This allows the voltage generator section 210 to change the offset voltage so that the expected voltage value of the analog input signal input from each of the plurality of terminal sections 12 connected to the plurality of signal amplifier circuits 232 falls within the measurement window.

[0091] 8 shows a modified example of the configuration of the test apparatus 100 together with the device under test 10. The test apparatus 100 of this example differs from the example shown in FIG. 1 in that the acquiring section 20 includes a correction section 270. In this example, differences from the example shown in FIG. 1 will be particularly described, and the rest may be the same as the example shown in FIG.

[0092] The correction section 270 may use a predetermined correction coefficient to correct errors generated in the voltage generating section 210, the signal amplifying section 230, or the measuring section 240. The correction coefficient may be acquired in advance by calibration, which measures a reference voltage for each measurement window. The correction section 270 may correct errors generated in the voltage generating section 210, the signal amplifying section 230, or the measuring section 240 by multiplying and / or adding the correction coefficient to the voltage value measured by the measuring section 240. By including the correction section 270, the test apparatus 100 of this example can improve test accuracy.

[0093] The test apparatus 100 of this example amplifies and measures the difference between the analog input signal and the offset voltage, thereby enabling high-precision, high-throughput testing at low cost. Furthermore, in this example, the configuration in which the correction section 270 is provided can synergistically exert the effect of enabling high-precision testing.

[0094] 7A to 7C , a correction unit 270 may also be provided. In this case, the correction unit 270 may include multiple correction units 270 provided on the same board 200. The number of multiple correction units 270 provided on each board 200 may be the same as the number of multiple terminal units 12 connected to each board 200. In other words, the correction unit 270 may correct errors in the measured voltage values ​​of the analog input signals from each terminal unit 12. This makes it possible to suppress inter-board deviations even when the voltage generation units 210 are provided separately for each board 200.

[0095] Various embodiments of the present invention may be described with reference to flowcharts and block diagrams, where the blocks may represent (1) stages of a process in which operations are performed or (2) sections of apparatus responsible for performing the operations. Particular stages and sections may be implemented by dedicated circuitry, programmable circuitry provided with computer-readable instructions stored on a computer-readable medium, and / or a processor provided with computer-readable instructions stored on a computer-readable medium. Dedicated circuitry may include digital and / or analog hardware circuitry, and may include integrated circuits (ICs) and / or discrete circuits. Programmable circuitry may include reconfigurable hardware circuitry including logical AND, OR, XOR, NAND, NOR, and other logic operations, flip-flops, registers, memory elements such as field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), and the like.

[0096] A computer-readable medium may include any tangible device capable of storing instructions that are executed by an appropriate device, such that the computer-readable medium having instructions stored thereon comprises an article of manufacture containing instructions that can be executed to create means for performing the operations specified in the flowcharts or block diagrams. Examples of computer-readable media may include electronic, magnetic, optical, electromagnetic, and semiconductor storage media. More specific examples of computer-readable media may include floppy disks, diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), electrically erasable programmable read-only memories (EEPROMs), static random access memories (SRAMs), compact disc read-only memories (CD-ROMs), digital versatile discs (DVDs), Blu-ray (RTM) discs, memory sticks, integrated circuit cards, and the like.

[0097] The computer readable instructions may include either assembler instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, JAVA®, C++, etc., and conventional procedural programming languages ​​such as the “C” programming language or similar programming languages.

[0098] The computer-readable instructions may be provided to a processor or programmable circuit of a programmable data processing device, such as a computer, locally or via a wide area network (WAN) such as a local area network (LAN) or the Internet, and the computer-readable instructions may be executed to create means for performing the operations specified in the flowcharts or block diagrams. Here, the computer may be a personal computer (PC), a tablet computer, a smartphone, a workstation, a server computer, a general-purpose computer, a special-purpose computer, or the like, or may be a computer system in which multiple computers are connected. Such a computer system in which multiple computers are connected is also called a distributed computing system, and is a broad definition of computer. In a distributed computing system, the multiple computers collectively execute a program by each executing a portion of the program and passing data between the computers as needed during program execution.

[0099] Examples of processors include computer processors, central processing units (CPUs), processing units, microprocessors, digital signal processors, controllers, microcontrollers, etc. A computer may have one processor or multiple processors. In a multiprocessor system with multiple processors, each processor executes a portion of a program and passes data between processors as needed during program execution, allowing the multiple processors to collectively execute the program. For example, in multitasking, each of the multiple processors may execute a portion of each task in small chunks by switching tasks at each time slice. In this case, which portion of a program each processor executes changes dynamically. Which portion of a program each of the multiple processors executes may also be statically determined by multiprocessor-aware programming.

[0100] 9 shows an example of a computer 1000 in which aspects of the present invention may be embodied, in whole or in part. Programs installed on the computer 1000 may cause the computer 1000 to function as or perform operations associated with an apparatus or one or more sections of the apparatus according to embodiments of the present invention, and / or to perform a process or steps of a process according to embodiments of the present invention. Such programs may be executed by the CPU 1012 to cause the computer 1000 to perform specific operations associated with some or all of the blocks in the flowcharts and block diagrams described herein.

[0101] The computer 1000 according to this embodiment includes a CPU 1012, a RAM 1014, a graphics controller 1016, and a display device 1018, which are interconnected by a host controller 1010. The computer 1000 also includes input / output units such as a communication interface 1022, a hard disk drive 1024, a DVD-ROM drive 1026, and an IC card drive, which are connected to the host controller 1010 via an input / output controller 1020. The computer 1000 also includes legacy input / output units such as a ROM 1030 and a keyboard 1042, which are connected to the input / output controller 1020 via an input / output chip 1040.

[0102] The CPU 1012 operates according to programs stored in the ROM 1030 and RAM 1014, thereby controlling each unit. The graphics controller 1016 acquires image data generated by the CPU 1012 into a frame buffer or the like provided in the RAM 1014 or into the graphics controller 1016 itself, and causes the image data to be displayed on the display device 1018.

[0103] The communication interface 1022 communicates with other electronic devices via a network. The hard disk drive 1024 stores programs and data used by the CPU 1012 in the computer 1000. The DVD-ROM drive 1026 reads programs or data from a DVD-ROM 1027 and provides the programs or data to the hard disk drive 1024 via the RAM 1014. The IC card drive reads programs and data from an IC card and / or writes programs and data to an IC card.

[0104] The ROM 1030 stores therein a boot program or the like that is executed by the computer 1000 upon activation, and / or programs that depend on the hardware of the computer 1000. The input / output chip 1040 may also connect various input / output units to the input / output controller 1020 via a parallel port, a serial port, a keyboard port, a mouse port, etc.

[0105] The programs are provided by a computer-readable medium such as a DVD-ROM 1027 or an IC card. The programs are read from the computer-readable medium, installed in the hard disk drive 1024, RAM 1014, or ROM 1030, which are also examples of computer-readable media, and executed by the CPU 1012. Information processing described in these programs is read by the computer 1000, and brings about cooperation between the programs and the various types of hardware resources described above. An apparatus or method may be configured by implementing information manipulation or processing in accordance with the use of the computer 1000.

[0106] For example, when communication is performed between computer 1000 and an external device, CPU 1012 may execute a communication program loaded into RAM 1014 and instruct communication interface 1022 to perform communication processing based on the processing described in the communication program. Under the control of CPU 1012, communication interface 1022 reads transmission data stored in a transmission buffer processing area provided in RAM 1014, hard disk drive 1024, DVD-ROM 1027, or a recording medium such as an IC card, and transmits the read transmission data to the network, or writes received data received from the network to a reception buffer processing area or the like provided on the recording medium.

[0107] The CPU 1012 may also read all or a necessary portion of a file or database stored on an external recording medium such as a hard disk drive 1024, a DVD-ROM drive 1026 (DVD-ROM 1027), an IC card, etc. into the RAM 1014, and perform various types of processing on the data on the RAM 1014. The CPU 1012 then writes back the processed data to the external recording medium.

[0108] Various types of information, such as various types of programs, data, tables, and databases, may be stored on the recording medium and may undergo information processing. The CPU 1012 may perform various types of processing on data read from the RAM 1014, including various types of operations, information processing, conditional judgment, conditional branching, unconditional branching, information search / replacement, etc., as described throughout this disclosure and specified by the instruction sequences of the programs, and write the results back to the RAM 1014. The CPU 1012 may also search for information in a file, database, etc. on the recording medium. For example, if multiple entries each having an attribute value of a first attribute associated with an attribute value of a second attribute are stored on the recording medium, the CPU 1012 may search for an entry that matches a condition specified by the attribute value of the first attribute from among the multiple entries, read the attribute value of the second attribute stored in the entry, and thereby obtain the attribute value of the second attribute associated with the first attribute that satisfies a predetermined condition.

[0109] The above-described programs or software modules may be stored in a computer-readable medium on or near the computer 1000. A recording medium such as a hard disk or RAM provided in a server system connected to a dedicated communication network or the Internet can also be used as a computer-readable medium, thereby providing the programs to the computer 1000 via the network.

[0110] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0111] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0112] 10 Device under test, 12 Terminal section, 20 Acquisition section, 30 Judgment section, 100 Test equipment, 200 Board, 210 Voltage generation section, 212 DA converter, 220 Control section, 230 Signal amplification section, 232 Signal amplification circuit, 240 Measurement section, 242 AD converter, 250 Restoration section, 252 Addition and subtraction section, 260 Storage section, 270 Correction section, 1000 Computer, 1010 Host controller, 1012 CPU, 1014 RAM, 1016 Graphics controller, 1018 Display device, 1020 Input / output controller, 1022 Communication interface, 1024 Hard disk drive, 1026 DVD-ROM drive, 1027 DVD-ROM, 1030 ROM, 1040 Input / output chip, 1042 Keyboard

Claims

1. A test apparatus comprising: a voltage generating unit that generates an offset voltage; a control unit that controls the offset voltage and the timing of changing the offset voltage; a signal amplifying unit that amplifies the difference between an analog input signal input from a device under test and the offset voltage controlled by the control unit, and outputs an analog amplified signal; a measuring unit that measures the analog amplified signal; and a restoration unit that uses the voltage value of the offset voltage to restore the voltage value of the analog input signal from the voltage value measured by the measuring unit, wherein the voltage generating unit changes the offset voltage so that an expected voltage value of the analog input signal is included in a measurement window of a predetermined voltage range.

2. The test device according to claim 1, wherein the control unit generates a test pattern for executing a predetermined test program, and controls the timing for changing the offset voltage in synchronization with the test pattern.

3. The test apparatus according to claim 2, further comprising a memory section for storing a voltage table including time-series data generated using the voltage expected value of the analog input signal corresponding to the test program, wherein the voltage generating section changes the offset voltage based on the voltage table so that the voltage expected value is included in the measurement window.

4. The test device according to claim 3, wherein the voltage generating section has a DA converter, and the memory section stores the voltage table, which is generated using time series data of the voltage expected value and includes time series data of voltage values ​​up to a number corresponding to the resolution of the DA converter.

5. The test device according to claim 3, wherein the voltage table is generated based on expected waveform data of the analog input signal.

6. A test device as claimed in any one of claims 1 to 5, wherein the signal amplification section has a plurality of signal amplification circuits provided on the same board, and the voltage generation section has a DA converter provided on the same board and inputting a common offset voltage to at least two or more of the plurality of signal amplification circuits.

7. The test device according to claim 6, wherein the voltage generating section has one DA converter that inputs a common offset voltage to the plurality of signal amplifier circuits.

8. The test device according to claim 6, wherein the plurality of signal amplifier circuits are classified into a plurality of groups, and the voltage generating section has a plurality of DA converters, each of which inputs a common offset voltage to each of the plurality of groups.

9. The test apparatus according to claim 8, wherein each of the plurality of DA converters varies the common offset voltage so that an expected voltage value of the analog input signal corresponding to each of the plurality of groups falls within the measurement window.

10. A test device as claimed in any one of claims 1 to 5, wherein the signal amplification section has a plurality of signal amplification circuits provided on the same board, and the voltage generation section has a plurality of DA converters provided on the same board, each of which inputs the offset voltage to each of the plurality of signal amplification circuits.

11. A test apparatus as claimed in any one of claims 1 to 5, further comprising a correction section which uses a predetermined correction coefficient to correct errors occurring in the voltage generating section, the signal amplifying section or the measuring section.

12. A test method comprising: a step of generating an offset voltage; a step of amplifying a difference between an analog input signal input from a device under test and the offset voltage, and outputting an analog amplified signal; a step of measuring the analog amplified signal; and a step of restoring a voltage value of the analog input signal from a voltage value measured in the step of measuring the analog amplified signal, using a voltage value of the offset voltage, wherein the step of generating the offset voltage includes a step of changing the offset voltage so that an expected voltage value of the analog input signal is included in a measurement window of a predetermined voltage range.

13. A program executed by a computer included in a test apparatus to cause the test apparatus to function as: a voltage generating unit that generates an offset voltage; a control unit that controls the offset voltage and the timing of changing the offset voltage; a signal amplifying unit that amplifies the difference between an analog input signal input from a device under test and the offset voltage and outputs an analog amplified signal; a measuring unit that measures the analog amplified signal; and a restoration unit that uses the voltage value of the offset voltage to restore the voltage value of the analog input signal from the voltage value measured by the measuring unit, wherein the voltage generating unit changes the offset voltage so that the expected voltage value of the analog input signal is included in a measurement window of a predetermined voltage range.

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