Semiconductor device

Abstract

This semiconductor device comprises a semiconductor layer, a gate trench and a dummy trench which extend in the semiconductor layer, a plurality of contact plugs which penetrate the insulating layer to be in contact with the semiconductor layer. The gate trench and the dummy trench each extend in a first direction in plan view. The semiconductor layer includes a gate-dummy mesa part which is defined between the gate trench and the dummy trench. The plurality of contact plugs include a row of contact plugs which is in contact with the gate-dummy mesa part. The row of contact plugs at least partially overlaps the dummy trench in plan view and is separate from the gate trench. The contact plugs included in the row are arranged so as to be spaced in the first direction.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Japanese Patent Application Laid-Open No. 2006-124493 discloses a semiconductor device including an IGBT having a trench gate structure. The IGBT includes an emitter plug electrode electrically connected to an emitter region and a contact region. The emitter plug electrode is buried in an emitter trench.

[0003] International Publication No. 2020 / 080476

[0004] [Summary] Due to the need for miniaturization of semiconductor devices, it is desirable to reduce the spacing between multiple trenches formed in a semiconductor layer in an IGBT having a trench gate structure. However, there are challenges in achieving miniaturization of the mesa portion defined between the multiple trenches while maintaining or improving the performance of the semiconductor device.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer having a first surface, first and second trenches extending from the first surface into the semiconductor layer, an insulating layer located on the semiconductor layer, a first electrode located in the first trench and separated from the semiconductor layer by the insulating layer, a second electrode located in the second trench and separated from the semiconductor layer by the insulating layer, the second electrode being electrically insulated from the first electrode, and a plurality of contact plugs penetrating the insulating layer and contacting the semiconductor layer. Each of the first and second trenches extends in a first direction in a plan view, and the first and second trenches are separated from each other in a second direction perpendicular to the first direction in a plan view. The semiconductor layer includes a mesa portion defined between the first and second trenches. The plurality of contact plugs includes a row of contact plugs contacting the mesa portion, the row of contact plugs at least partially overlapping the second trench in a plan view and separated from the first trench. The contact plugs included in the row are arranged at intervals in the first direction.

[0006] Other features and aspects will become apparent from the following detailed description, drawings, and claims.

[0007] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a schematic perspective view of a portion of the active region of the semiconductor device of FIG. 1. FIG. 3 is a schematic plan view of a portion of the semiconductor device surrounded by dashed line F3 of FIG. 1. FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 of FIG. 3. FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 of FIG. 3. FIG. 6 is an enlarged view of a portion of FIG. 4. FIG. 7 is a schematic cross-sectional view of the semiconductor device taken along line F7-F7 of FIG. 3. FIG. 8 is a schematic plan view of a portion of the semiconductor device surrounded by dashed line F8 of FIG. 1. FIG. 9 is a schematic cross-sectional view of the semiconductor device taken along line F9-F9 of FIG. 8. FIG. 10 is a schematic plan view of a semiconductor device according to another example of the present disclosure. FIG. 11 is a schematic cross-sectional view of the semiconductor device taken along line F11-F11 of FIG. 10. FIG. 12 is a schematic cross-sectional view of the semiconductor device taken along line F12-F12 of FIG. 10. FIG. 13 is an enlarged view of a portion of FIG. 11. FIG. 14 is a schematic plan view of a semiconductor device according to another example of the present disclosure. FIG. 15 is a schematic cross-sectional view of the semiconductor device taken along line F15-F15 in FIG. 14. FIG. 16 is an enlarged view of a portion of FIG. 15. FIG. 17 is a schematic cross-sectional view of a semiconductor device according to another example of the present disclosure. FIG. 18 is a schematic cross-sectional view of the semiconductor device shown in FIG. 17 from a different direction. FIG. 19 is a schematic plan view of an exemplary semiconductor device according to a second embodiment of the present disclosure. FIG. 20 is a schematic cross-sectional view of the semiconductor device shown in FIG. 19. FIG. 21 is a schematic cross-sectional view of the semiconductor device shown in FIG. 19. FIG. 22 is an enlarged plan view of a semiconductor device in a case where a contact plug is shifted in the X-axis direction. FIG. 23 is a schematic cross-sectional view of the semiconductor device of FIG. 22. FIG. 24 is an enlarged plan view of a semiconductor device without a complementary region in a case where a contact plug is shifted in the X-axis direction. FIG. 25 is a schematic cross-sectional view of the semiconductor device of FIG. 24. FIG. 26 is a schematic plan view of a semiconductor device according to another example of the present disclosure. FIG. 27 is a schematic plan view of a semiconductor device according to another example of the present disclosure. Fig. 28 is a schematic cross-sectional view of a semiconductor device according to another example of the present disclosure. Fig. 29 is a schematic plan view of an exemplary semiconductor device according to a third embodiment. Fig. 30 is a schematic cross-sectional view of the semiconductor device taken along line F30-F30 in Fig. 29. Fig. 31 is a schematic cross-sectional view of the semiconductor device taken along line F31-F31 in Fig. 29.32 is a schematic cross-sectional view of a semiconductor device when the contact plug is shifted in the X-axis direction. FIG. 33 is a schematic cross-sectional view of a semiconductor device including a first electrode without a recess when the contact plug is shifted in the X-axis direction. FIG. 34 is a schematic plan view of a semiconductor device according to another example of the present disclosure. FIG. 35 is a schematic cross-sectional view of the semiconductor device taken along line F35-F35 in FIG. 34. FIG. 36 is a schematic plan view of a semiconductor device according to another example of the present disclosure. FIG. 37 is a schematic cross-sectional view of the semiconductor device taken along line F37-F37 in FIG.

[0008] DETAILED DESCRIPTION Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout the drawings and detailed description. The drawings may not be to scale, and the relative size, proportions, and depictions of elements in the drawings may be exaggerated for clarity, explanation, and convenience.

[0009] The following detailed description provides a comprehensive understanding of the described methods, devices, and / or systems. Modifications and equivalents of the described methods, devices, and / or systems will be apparent to those skilled in the art. Except for operations that necessarily occur in a specific order, the order of operations is illustrative and may be changed as would be apparent to one skilled in the art. Descriptions of functions and structures well known to those skilled in the art may be omitted.

[0010] Exemplary embodiments may have different forms and are not limited to the described examples, but the described examples are thorough and complete and will convey the full scope of the present disclosure to those skilled in the art.

[0011] First Embodiment An exemplary semiconductor device 10 according to a first embodiment will be described with reference to FIGS. 1 to 9. The semiconductor device 10 may be configured as a semiconductor chip on which an insulated gate bipolar transistor (IGBT) is formed. FIG. 1 is a schematic plan view of the exemplary semiconductor device 10 according to one embodiment. FIG. 2 is a schematic perspective view of a portion of the active region 16 of the semiconductor device 10 of FIG. 1. The emitter electrode 22 is omitted from FIG. 2 to facilitate understanding of the arrangement of the contact plug 64. FIG. 3 is a schematic plan view of a portion of the semiconductor device 10 surrounded by a dashed dotted line F3 of FIG. 1. FIG. 3 corresponds to a cross-sectional view of the semiconductor device 10 taken along the XY plane intersecting the bottom 64B of the contact plug 64. FIG. 4 is a schematic cross-sectional view of the semiconductor device 10 taken along line F4-F4 in FIG. 3. FIG. 5 is a schematic cross-sectional view of the semiconductor device 10 taken along line F5-F5 in FIG. 3. FIG. 6 is a partial enlarged view of FIG. 4. FIG. 7 is a schematic cross-sectional view of the semiconductor device 10 taken along line F7-F7 in FIG. 3. Fig. 8 is a schematic plan view of a portion surrounded by a dashed dotted line F8 of the semiconductor device 10 in Fig. 1. Fig. 9 is a schematic cross-sectional view of the semiconductor device 10 taken along the line F9-F9 in Fig. 8.

[0012] 1 to 9, the Z-axis direction of the mutually orthogonal X, Y, and Z axes is a direction orthogonal to the first surface 12A of the semiconductor layer 12 (see, for example, FIGS. 2 and 4). Note that, as used in this specification, the term "plan view" refers to viewing the semiconductor device 10 from above along the Z-axis direction (from the side of the first surface 12A of the semiconductor layer 12), unless explicitly stated otherwise. Note that in the present disclosure, the Y-axis direction may be referred to as the first direction, and the X-axis direction may be referred to as the second direction.

[0013] 1 to 9, the semiconductor device 10 includes a semiconductor layer 12 and an insulating layer 14 located on the semiconductor layer 12. The semiconductor layer 12 has a first surface 12A and a second surface 12B opposite the first surface 12A (see, for example, FIGS. 4 and 5). The insulating layer 14 may cover the first surface 12A of the semiconductor layer 12. The semiconductor layer 12 may have an outer edge 12C that is rectangular in plan view (see FIG. 1).

[0014] The semiconductor layer 12 may include silicon (Si). In one example, the semiconductor layer 12 may be substantially made of silicon. The insulating layer 14 may be made of silicon oxide (SiO ２ ), silicon nitride (SiN), silicon oxynitride (SiON), and aluminum oxide (Al ２ O ３ ) The insulating layer 14 may consist of a single insulating layer or may include multiple different insulating layers.

[0015] 1, the semiconductor device 10 may include an active region 16 in which an IGBT is formed, and a peripheral region 18 located along an outer edge 12C of the semiconductor layer 12. The peripheral region 18 may surround the active region 16 in a plan view. In the illustrated example, the semiconductor device 10 includes two active regions 16. Note that the arrangement of the active region 16 and the peripheral region 18 can be determined appropriately depending on the desired characteristics of the semiconductor device 10, and is not limited to the illustrated example.

[0016] The semiconductor device 10 may include a gate electrode 20 located on the insulating layer 14 and an emitter electrode 22 located on the insulating layer 14. The gate electrode 20 and the emitter electrode 22 are spaced apart from each other. The emitter electrode 22 may cover at least the active region 16. In the illustrated example, the gate electrode 20 includes a gate pad portion 24, inner gate finger portions 26, and outer gate finger portions 28. The inner gate finger portions 26 are connected to the gate pad portion 24 and extend in the X-axis direction between the two active regions 16. The outer gate finger portions 28 are connected to the gate pad portion 24 and are located in the outer region 18. Each active region 16 may be at least partially surrounded by the inner gate finger portions 26 and the outer gate finger portions 28 in a planar view. In addition, in the illustrated example, the emitter electrode 22 includes an emitter pad portion 30 and an emitter finger portion 32. The emitter pad portion 30 may cover the active region 16. The emitter finger portions 32 may be connected to the emitter pad portion 30 and located in the peripheral region 18. At least a portion of the emitter finger portions 32 may surround the peripheral gate finger portions 28 in a plan view. The peripheral gate finger portions 28 may be located between the emitter pad portion 30 and the emitter finger portions 32. The arrangement of the gate electrode 20 and the emitter electrode 22 can be determined appropriately depending on the desired characteristics of the semiconductor device 10, and is not limited to the example shown in the figure.

[0017] The gate electrode 20 may comprise at least one of aluminum (Al), copper (Cu), an aluminum alloy, a copper alloy, tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The gate electrode may consist of a single metal layer or may include multiple different metal layers.

[0018] The emitter electrode 22 may include at least one of aluminum, copper, an aluminum alloy, a copper alloy, tungsten, molybdenum, nickel, titanium, titanium nitride, tantalum, and tantalum nitride. The emitter electrode 22 may be composed of a single metal layer or may include multiple different metal layers.

[0019] 1 is an example, and it should be understood that a different layout may be adopted depending on the desired characteristics of the semiconductor device 10. For example, the position and size of the active region 16 may be different from the example shown in FIG. 1. Furthermore, the semiconductor device 10 may include elements other than IGBTs.

[0020] 4, 5, and 9, the semiconductor device 10 may include a collector electrode 34 formed on the second surface 12B of the semiconductor layer 12. The collector electrode 34 may include at least one of titanium, nickel, palladium (Pd), gold (Au), silver (Ag), and aluminum. The collector electrode 34 may be composed of a single metal layer, or may include multiple different metal layers.

[0021] The semiconductor layer 12 may include a p-type collector region 36 adjacent to a collector electrode 34. The collector region 36 may include at least a portion of the second surface 12B of the semiconductor layer 12. The collector electrode 34 forms an ohmic contact with the collector region 36. In one example, the p-type impurity concentration of the collector region 36 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ It may be the following:

[0022] The semiconductor layer 12 may include an n-type buffer region 38 located on the collector region 36 and an n-type drift region 40 located on the buffer region 38. The drift region 40 has a lower n-type impurity concentration than the buffer region 38. In one example, the n-type impurity concentration of the buffer region 38 is 1×10 １５ cm －３ 1x10 or more １７ cm －３In one example, the n-type impurity concentration of the drift region 40 may be 1×10 １３ cm －３ 1x10 or more １５ cm －３ It may be the following:

[0023] In this disclosure, n-type may be referred to as the first conductivity type, and p-type may be referred to as the second conductivity type. The n-type impurity may be, for example, phosphorus (P), arsenic (As), etc. The p-type impurity may be, for example, boron (B), aluminum (Al), etc.

[0024] 2 to 7, the semiconductor device 10 includes gate trenches 42 and dummy trenches 44 extending from the first surface 12A into the semiconductor layer 12. Each of the gate trenches 42 and dummy trenches 44 extends in the Y-axis direction in a plan view. The gate trenches 42 and dummy trenches 44 are spaced apart in the X-axis direction in a plan view. In this disclosure, the gate trenches may be referred to as first trenches, and the dummy trenches may be referred to as second trenches.

[0025] The semiconductor device 10 includes a first electrode 46 located in the gate trench 42 and separated from the semiconductor layer 12 by the insulating layer 14, and a second electrode 48 located in the dummy trench 44 and separated from the semiconductor layer 12 by the insulating layer 14. The second electrode 48 is electrically insulated from the first electrode 46.

[0026] The gate trench 42 refers to a trench in which a first electrode 46 is embedded, among the multiple trenches 42, 44 formed in the semiconductor layer 12. The first electrode 46 may be electrically connected to the gate electrode 20 (see FIG. 1).

[0027] The first electrode 46 may be formed of conductive polysilicon. In another example, the first electrode 46 may be formed of any other conductive material. The dummy trench 44 refers to a trench among multiple trenches formed in the semiconductor layer 12, in which the second electrode 48 is embedded. The second electrode 48 may be electrically connected to the emitter electrode 22.

[0028] The second electrode 48 may be formed of conductive polysilicon. Alternatively, the second electrode 48 may be formed of any other conductive material. The insulating layer 14 may include a first insulating layer 50 and a second insulating layer 52 positioned on the first insulating layer 50. The first insulating layer 50 may cover the first surface 12A of the semiconductor layer 12 and the trenches 42 and 44. The first electrode 46 and the second electrode 48 may be embedded in the gate trench 42 and the dummy trench 44, respectively, via the first insulating layer 50. The second insulating layer 52 may cover the first electrode 46 embedded in the gate trench 42 and the second electrode 48 embedded in the dummy trench 44.

[0029] In one example, each trench 42, 44 may have a depth (dimension in the Z-axis direction) of 1 μm or more and 30 μm or less. Also, in one example, each trench 42, 44 may have a width (dimension in the X-axis direction) of 0.1 μm or more and 1 μm or less. In the illustrated example, the sidewalls of each trench 42, 44 extend in the Z-axis direction, but in another example, they may be inclined with respect to the Z-axis direction.

[0030] 3, the ratio of the number of gate trenches 42 to the number of dummy trenches 44 is 1:2. That is, sets each including one gate trench 42 and two dummy trenches 44 are repeatedly arranged in the X-axis direction. Note that the ratio of the number of gate trenches 42 to the number of dummy trenches 44 can be determined appropriately depending on the desired characteristics of the semiconductor device 10, and is not limited to the example shown in the figure.

[0031] In this embodiment, the pitch in the X-axis direction of the multiple trenches 42, 44, including the gate trench 42 and the dummy trench 44, may be constant. Also, the dimension in the X-axis direction of each trench 42, 44 may be the same. In another example, the pitch in the X-axis direction of the multiple trenches 42, 44 may not be constant, and / or the dimension in the X-axis direction of each trench 42, 44 may not be the same.

[0032] 3 to 6, the gate trench 42 and the dummy trench 44 are spaced apart in the X-axis direction in plan view. The semiconductor layer 12 includes a gate-dummy mesa portion 54 defined between the gate trench 42 and the dummy trench 44. Since the semiconductor device 10 includes a plurality of gate trenches 42 and a plurality of dummy trenches 44, the semiconductor layer 12 may include a plurality of gate-dummy mesa portions 54. In the present disclosure, the gate-dummy mesa portion may be simply referred to as a mesa portion.

[0033] 4 to 6, the gate-dummy mesa 54 may include an n-type first region 56A, a p-type second region 58A located on the first region 56A, and an n-type third region 60A located on the second region 58A and including a part of the first surface 12A of the semiconductor layer 12. In other words, at least a part of the surface portion of the gate-dummy mesa 54 may be the third region 60A.

[0034] The first region 56A corresponds to a portion of the carrier storage region 56 located above the drift region 40. The carrier storage region 56 may have a higher n-type impurity concentration than the drift region 40. In one example, the n-type impurity concentration of the carrier storage region 56 is 1×10 １５ cm －３ 1x10 or more １７ cm －３ It may be the following:

[0035] The second region 58A corresponds to a portion of the base region 58 located on the carrier storage region 56. In one example, the p-type impurity concentration of the base region 58 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ It may be the following:

[0036] The third region 60A corresponds to a part of the emitter region 60 located on the base region 58. The emitter region 60 includes a part of the first surface 12A of the semiconductor layer 12. In one example, the n-type impurity concentration of the emitter region 60 is 1×10 １９ cm －３ 1x10 or more ２０ cm －３It may be the following:

[0037] The bottoms of the gate trench 42 and the dummy trench 44 may be adjacent to the drift region 40. Therefore, the gate-dummy mesa 54 may further include a portion of the drift region 40.

[0038] 3, a part of the surface of the gate-dummy mesa 54 may be the second region 58A. Specifically, a part of the region of the gate-dummy mesa 54 adjacent to the contact plug 64 may be the second region 58A.

[0039] In one example, the dimension D1 (see FIG. 5) in the X-axis direction of the upper portion 54A of the gate-dummy mesa portion 54 may be 1 μm or less. More preferably, the dimension D1 may be 0.8 μm or less. The upper portion 54A of the gate-dummy mesa portion 54 is a portion that includes a part of the first surface 12A of the semiconductor layer 12. Note that if the sidewalls of the trenches 42, 44 are inclined with respect to the Z-axis direction, the upper portion 54A may be a relatively narrow portion of the gate-dummy mesa portion 54.

[0040] 2 to 6 , the semiconductor layer 12 may further include a dummy-dummy mesa portion 62 defined between two dummy trenches 44 spaced apart in the X-axis direction in a plan view. Unlike the gate-dummy mesa portion 54, the dummy-dummy mesa portion 62 may not include the emitter region 60. Therefore, a surface portion of the dummy-dummy mesa portion 62 may be the base region 58. In other words, in the dummy-dummy mesa portion 62, the base region 58 may include a portion of the first surface 12A of the semiconductor layer 12.

[0041] The dimension D2 (see FIG. 5) in the X-axis direction of the upper portion 62A of the dummy-dummy mesa portion 62 may be the same as or different from the width of the gate-dummy mesa portion 54. In one example, the dimension D2 may be 1 μm or less. More preferably, the dimension D2 may be 0.8 μm or less.

[0042] 2 to 4, the semiconductor device 10 includes a plurality of contact plugs 64 that penetrate the insulating layer 14 and contact the semiconductor layer 12. The plurality of contact plugs 64 include a row R of contact plugs that contact the gate-dummy mesa portion 54. Each of the contact plugs 64 included in the row R may penetrate the third region 60A of the gate-dummy mesa portion 54. On the other hand, the row R of contact plugs may be separated from the dummy-dummy mesa portion 54.

[0043] The multiple contact plugs 64 may include multiple columns R. In the illustrated example, one column R may be arranged for one gate-dummy mesa portion 54. This means that the contact plugs 64 shown in FIG. 4 are each included in a different column R.

[0044] As shown, the gate trench 42 is located between two gate-dummy mesas 54. Each gate-dummy mesa 54 contacts one row R of contact plugs, and therefore the gate trench 42 is located between two rows R.

[0045] The two gate-dummy mesa portions 54, between which one gate trench 42 is located, can also be referred to as a first mesa portion and a second mesa portion. The two rows R can also be referred to as a first row and a second row of contact plugs. When the first mesa portion is defined between the first trench and the second trench, and the second mesa portion is defined between the first trench and the third trench, the first trench corresponds to the gate trench 42, and the second trench and the third trench correspond to the dummy trench 44. Since the third trench corresponds to the dummy trench 44, the third electrode located in the third trench is electrically connected to the second electrode located in the second trench (the second electrode 48 located in the dummy trench 44). The second row of contact plugs at least partially overlaps the third trench in a plan view and is spaced apart from the first trench.

[0046] 3, the row R of contact plugs at least partially overlaps the dummy trench 44 in a plan view and is separated from the gate trench 42. As shown in FIG. 4, the bottom surfaces of the contact plugs 64 may be located lower than the top surfaces of the second electrodes 48. Therefore, each of the contact plugs 64 included in the row R may be in contact with the second electrode 48.

[0047] The dimension D1 (see FIG. 5) of the upper portion 54A of the gate-dummy mesa portion 54 may be larger than, equal to, or smaller than the dimension D3 (see FIG. 6) of each contact plug 64 in the X-axis direction. Because the row R of contact plugs may at least partially overlap with the dummy trenches 44 in a plan view, the dimension D1 of the upper portion 54A of the gate-dummy mesa portion 54 does not necessarily have to be larger than the dimension D3 of each contact plug 64. For example, making the dimension D1 of the upper portion 54A of the gate-dummy mesa portion 54 equal to or smaller than the dimension D3 of each contact plug 64 may be effective in miniaturizing the gate-dummy mesa portion 54.

[0048] The contact plugs 64 included in the row R are arranged at intervals in the Y-axis direction. In one example, the contact plugs 64 included in the row R may be arranged at regular intervals in the Y-axis direction. In one example, the dimension D4 (see FIG. 7 ) of each contact plug 64 in the Y-axis direction may be 1 μm or more and 10 μm or less. Furthermore, the distance D5 between the contact plugs 64 in the Y-axis direction may be 1 μm or more and 10 μm or less. In one example, the distance D5 may be larger than the dimension D1 in the X-axis direction of the upper portion 54A of the gate-dummy mesa portion 54. The ratio between the dimension D4 and the distance D5 can be determined appropriately depending on the desired characteristics of the semiconductor device 10.

[0049] The contact plug 64 may include at least one of tungsten (W), molybdenum (Mo), nickel (Ni), aluminum (Al), copper (Cu), an aluminum alloy, a copper alloy, titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The contact plug 64 may be composed of a single metal layer or may include multiple different metal layers.

[0050] 2, 3, and 7, the gate-dummy mesa 54 includes a plurality of p-type inbase regions 66. Each of the plurality of inbase regions 66 is in contact with the bottom portion 64B of the corresponding contact plug 64 included in row R. The plurality of inbase regions 66 are arranged at intervals in the Y-axis direction.

[0051] The p-type impurity concentration of the in-base regions 66 is higher than the p-type impurity concentration of the second region 58A. １９ cm －３ 1x10 or more ２０ cm －３ It may be the following:

[0052] As shown in FIGS. 2 , 4 , 6 , and 7 , each of the multiple inbase regions 66 is located between the third region 60A and the first region 56A. Each of the multiple inbase regions 66 is adjacent to the second region 58A. It can also be said that each of the multiple inbase regions 66 is located within the second region 58A (base region 58). Each of the multiple inbase regions 66 may be located within the second region 58A closer to the third region 60A than to the first region 56A. In the illustrated example, each of the multiple inbase regions 66 may be separated from the third region 60A.

[0053] 4, 6, and 7, each of the multiple in-base regions 66 may extend along the bottom portion 64B of the contact plug 64 in the gate-dummy mesa 54 so as to cover the bottom portion 64B of the contact plug 64. As shown in FIGS. 3, 4, and 6, each of the multiple in-base regions 66 may extend across the entire width of the gate-dummy mesa 54 in the X-axis direction.

[0054] 3 and 7, the in-base region 66 may extend around the bottom 64B of the contact plug 64 in the gate-dummy mesa 54. Therefore, the in-base region 66 does not need to be present in a location relatively far from the contact plug 64 as shown in FIG.

[0055] 8 and 9 , in the peripheral region 18, the semiconductor device 10 may include an isolation trench 68 formed in the semiconductor layer 12 and an isolation electrode 70 embedded in the isolation trench 68 with the first insulating layer 50 interposed therebetween. The isolation electrode 70 may be formed of conductive polysilicon. In another example, the isolation electrode 70 may be formed of any other conductive material. The isolation electrode 70 may be electrically connected to the gate electrode 20. Although not shown, the isolation trench 68 may communicate with the gate trench 42 (e.g., at an end of the gate trench 42 in the Y-axis direction).

[0056] The semiconductor layer 12 may include a p-type periphery well region 72 in the periphery region 18. The periphery well region 72 may be formed to surround the active region 16 in a plan view. The p-type impurity concentration of the periphery well region 72 may be higher than the p-type impurity concentration of the base region 58.

[0057] As shown in FIG. 9 , the periphery well region 72 may include a portion of the first surface 12A of the semiconductor layer 12 in the periphery region 18. The depth of the periphery well region 72 from the first surface 12A may be greater than the depth (dimension in the Z-axis direction) of the isolation trench 68. The isolation trench 68 may be formed within the periphery well region 72. The periphery well region 72 may be covered with an insulating layer 14. The insulating layer 14 may include a first well opening 74 and a second well opening 76 that expose the periphery well region 72. The emitter pad portion 30 may be in contact with the periphery well region 72 through the first well opening 74. The emitter finger portion 32 may be in contact with the periphery well region 72 through the second well opening 76.

[0058] The insulating layer 14 may further include a gate opening 78 between the first well opening 74 and the second well opening 76. The semiconductor device 10 may also include a perimeter gate wiring 80 located on the first insulating layer 50. The perimeter gate wiring 80 may be located below the perimeter gate finger portions 28 and above the perimeter well region 72. The perimeter gate finger portions 28 may be in contact with the perimeter gate wiring 80 through the gate opening 78. The perimeter gate wiring 80 may be formed from conductive polysilicon. In another example, the perimeter gate wiring 80 may be formed from any other conductive material.

[0059] (Functions and Effects of the Semiconductor Device According to the Present Embodiment) The functions of the semiconductor device 10 of the present embodiment will be described below. In the semiconductor device 10 of the present embodiment, the semiconductor layer 12 includes a gate-dummy mesa portion 54 defined between the gate trench 42 and the dummy trench 44. The multiple contact plugs 64 include a row R of contact plugs that contact the gate-dummy mesa portion 54. The row R of contact plugs at least partially overlaps the dummy trench 44 in a plan view and is spaced apart from the gate trench 42. The contact plugs 64 included in the row R are arranged at intervals in the Y-axis direction.

[0060] 6, the contact plug 64 in contact with the gate-dummy mesa portion 54 is located closer to the dummy trench 44 than to the gate trench 42. Therefore, it is possible to improve the short-circuit resistance between the first electrode 46 in the gate trench 42 and the contact plug 64 included in the row R.

[0061] Since the row R of contact plugs may at least partially overlap the dummy trenches 44 in plan view, the dimension D1 of the upper portion 54A of the gate-dummy mesa portion 54 does not necessarily need to be larger than the dimension D3 of each contact plug 64. This makes it easy to reduce the dimension D1 of the gate-dummy mesa portion 54 in the X-axis direction.

[0062] 7, the gate-dummy mesa 54 further includes a plurality of p-type inbase regions 66. Each of the plurality of inbase regions 66 is in contact with the bottom 64B of the corresponding contact plug 64 included in the row R. The p-type impurity concentration of the plurality of inbase regions 66 is higher than the p-type impurity concentration of the second region 58A, which suppresses the occurrence of latch-up in the semiconductor device 10 and facilitates operation of the semiconductor device 10 within the reverse bias safe operating area (RBSOA).

[0063] In locations where inbase regions 66 with a relatively high p-type impurity concentration exist, the formation of an inversion layer that functions as a channel of semiconductor device 10 is inhibited. However, because the multiple inbase regions 66 are arranged at intervals in the Y-axis direction, an inversion layer can be formed in locations where no inbase regions 66 exist in second region 58A of gate-dummy mesa 54. As a result, when semiconductor device 10 is turned on, a current path as shown by the arrows in FIG. 7 can be ensured.

[0064] 6, each of the multiple in-base regions 66 extends across the entire width of the gate-dummy mesa 54 in the X-axis direction. As a result, the current path from the third region 60A to the first region 56A can be reliably blocked around the contact plug 64. This reduces the variation in the characteristics of the semiconductor device 10.

[0065] Therefore, according to the semiconductor device 10 of this embodiment, it is possible to reduce the dimension of the mesa portion 54 in the X-axis direction while maintaining or improving the performance of the semiconductor device 10. The semiconductor device 10 of this embodiment has the following advantages.

[0066] (1) The gate trench 42 (first trench) and the dummy trench 44 (second trench) are spaced apart in the X-axis direction (second direction perpendicular to the first direction) in a plan view, and the semiconductor layer 12 includes a gate-dummy mesa portion 54 (mesa portion) defined between the gate trench 42 and the dummy trench 44. The multiple contact plugs 64 include a row R of contact plugs that contact the gate-dummy mesa portion 54. The row R of contact plugs at least partially overlaps the dummy trench 44 in a plan view and is spaced apart from the gate trench 42. The contact plugs 64 included in the row R are arranged at intervals in the Y-axis direction (first direction).

[0067] With this configuration, even if the dimension D1 in the X-axis direction of the gate-dummy mesa portion 54 is relatively small, it is possible to improve the short-circuit resistance between the first electrode 46 in the gate trench 42 and the contact plugs 64 included in row R. Furthermore, because the contact plugs 64 included in row R are arranged at intervals, it is possible to enable proper on-operation of the semiconductor device 10. Therefore, it is possible to miniaturize the dimension in the X-axis direction of the mesa portion 54 while maintaining or improving the performance of the semiconductor device 10.

[0068] (2) The gate-dummy mesa portion 54 (mesa portion) includes a plurality of p-type (second conductivity type) inbase regions 66. The p-type impurity concentration of the plurality of inbase regions 66 is higher than the p-type impurity concentration of the second region 58A. Each of the plurality of inbase regions 66 is in contact with the bottom portion 64B of the corresponding contact plug 64 included in the row R. The plurality of inbase regions 66 are arranged at intervals in the Y-axis direction (first direction). With this configuration, the presence of the plurality of inbase regions 66 suppresses the occurrence of latch-up in the semiconductor device 10 and facilitates operation of the semiconductor device 10 within the reverse bias safe operating area (RBSOA).

[0069] (3) Each of the multiple in-base regions 66 is located between the third region 60A and the first region 56A and extends across the entire width of the gate-dummy mesa portion 54 (mesa portion) in the X-axis direction (second direction). This configuration reliably blocks the current path from the third region 60A to the first region 56A around the contact plug 64. This reduces the variation in the characteristics of the semiconductor device 10.

[0070] (4) Each of the contact plugs 64 included in the row R penetrates the third region 60A. With this configuration, the bottoms 64B of the contact plugs 64 can be positioned relatively low, which further facilitates operation of the semiconductor device 10 within the reverse bias safe operating area (RBSOA).

[0071] (5) The dimension in the X-axis direction (second direction) of the upper portion 54A of the gate-dummy mesa portion 54 (mesa portion) may be equal to or smaller than the dimension in the X-axis direction (second direction) of each of the contact plugs 64 included in the row R. This configuration makes it possible to easily miniaturize the gate-dummy mesa portion 54.

[0072] <Another Arrangement Example of Gate Trenches and Dummy Trenches> Next, a semiconductor device 100 according to another example of the present disclosure will be described with reference to FIGS. 10 to 13. FIG. 10 is a schematic plan view of the semiconductor device 100. FIG. 11 is a schematic cross-sectional view of the semiconductor device 100 taken along line F11-F11 in FIG. 10. FIG. 12 is a schematic cross-sectional view of the semiconductor device 100 taken along line F12-F12 in FIG. 10. FIG. 13 is a partial enlarged view of FIG. 11. Note that in FIGS. 10 to 13, components similar to those in the first embodiment are denoted by the same reference numerals. Further, detailed description of components similar to those in the first embodiment will be omitted.

[0073] 10 to 13, the gate trenches 42 and the dummy trenches 44 are arranged alternately in the X-axis direction. In the semiconductor device 100, no two dummy trenches 44 are adjacent to each other, and therefore the semiconductor layer 12 does not need to include the dummy-to-dummy mesa portion 62 (see FIG. 3, etc.) as described above in relation to the first embodiment. As shown in FIG. 12, the trenches 42, 44 may be arranged at equal intervals (corresponding to the dimension D1 of the upper portion 54A of the gate-to-dummy mesa portion 54).

[0074] 10 , in plan view, two rows R of contact plugs may be arranged to overlap one dummy trench 44. As shown in Fig. 13 , one second electrode 48 can be in contact with the contact plugs 64 included in the two rows R. The two rows R of contact plugs may be arranged close to each other on one second electrode 48.

[0075] 10, 11, and 13, in the semiconductor device 100, the row R of contact plugs may be arranged so as to contact all of the mesa portions, i.e., the gate-dummy mesa portions 54. Therefore, in the semiconductor device 100, the contact plugs 64 can be arranged at a higher density than in the semiconductor device 10 shown in FIG.

[0076] <Example of Contact Plug Contacting Two Mesa Portions> Next, a semiconductor device 200 according to another example of the present disclosure will be described with reference to FIGS. 14 to 16. FIG. 14 is a schematic plan view of the semiconductor device 200. FIG. 15 is a schematic cross-sectional view of the semiconductor device 200 taken along line F15-F15 in FIG. 14. FIG. 16 is a partial enlarged view of FIG. 15. Note that in FIGS. 14 to 16, components similar to those in the first embodiment are denoted by the same reference numerals. Further, detailed description of components similar to those in the first embodiment will be omitted.

[0077] 14 to 16 , in the semiconductor device 200, similar to the semiconductor device 100, the gate trenches 42 and the dummy trenches 44 are alternately arranged in the X-axis direction. The semiconductor device 200 includes a plurality of contact plugs 202 that penetrate the insulating layer 14 and contact the semiconductor layer 12. The plurality of contact plugs 202 includes a row R of contact plugs that contact two gate-dummy mesa portions 54. Each of the contact plugs 202 included in the row R may penetrate the third regions 60A of both of the two gate-dummy mesa portions 54. The row R of contact plugs is located between the two gate trenches 42 in a plan view and is spaced apart from the two gate trenches 42.

[0078] The two gate-dummy mesas 54 contacted by the contact plug row R can also be referred to as the first and second mesas. When the first mesa is defined between the first and second trenches and the second mesa is defined between the second and third trenches, the first and third trenches correspond to the gate trenches 42, and the second trench corresponds to the dummy trench 44. Because the third trench corresponds to the gate trench 42, the third electrode located in the third trench is electrically connected to the first electrode located in the first trench (the first electrode 46 located in the gate trench 42). The contact plug row R contacts both the first and second mesas and is separated from both the first and third trenches.

[0079] 15, the bottom 202B of each contact plug 202 is located on the second electrode 48. The bottom 202B of each contact plug 202 is covered by two in-base regions 66 included in different gate-dummy mesas 54.

[0080] In the semiconductor device 200, the dimension D6 in the X-axis direction of each contact plug 202 (see FIG. 16 ) may be greater than at least the dimension in the X-axis direction of the dummy trench 44. In one example, as shown in FIG. 16 , the pitch D7 in the X-axis direction of the trenches 42, 44 may be smaller than the dimension D6 in the X-axis direction of each contact plug 202.

[0081] In the illustrated example, each contact plug 202 can be arranged to contact two gate-dummy mesas 54, making it even easier to reduce the dimension D1 of the upper portion 54A of the gate-dummy mesa 54.

[0082] <Example of Different Depth Positions of In-Base Region> Next, a semiconductor device 300 according to another example of the present disclosure will be described with reference to FIGS. 17 and 18 . FIG. 17 is a schematic cross-sectional view of the semiconductor device 300. FIG. 18 is a schematic cross-sectional view of the semiconductor device 300 shown in FIG. 17 from a different direction. In FIGS. 17 and 18 , the same components as those in the first embodiment are denoted by the same reference numerals. Further, detailed description of the same components as those in the first embodiment will be omitted.

[0083] 17 and 18 , the gate-dummy mesa 54 of the semiconductor device 300 includes a plurality of p-type inbase regions 302. Each of the plurality of inbase regions 302 is in contact with the bottom portion 64B of the corresponding contact plug 64 included in a row R. The plurality of inbase regions 302 are arranged at intervals in the Y-axis direction.

[0084] The p-type impurity concentration of the plurality of in-base regions 302 is higher than the p-type impurity concentration of the second region 58A. １９ cm －３ 1x10 or more ２０ cm －３ It may be the following:

[0085] Each of the in-base regions 302 is located between the third region 60A and the first region 56A. Each of the in-base regions 302 is adjacent to the second region 58A. Furthermore, each of the in-base regions 302 is adjacent to the third region 60A.

[0086] Each of the multiple in-base regions 302 can extend along the bottom 64B of the contact plug 64 so as to cover the bottom 64B of the contact plug 64. Therefore, the positions of the multiple in-base regions 302 can vary depending on the position of the bottom 64B of the contact plug 64. When the bottom 64B of the contact plug 64 is located relatively high, each of the multiple in-base regions 302 can be adjacent to the third region 60A, as shown in the figure. Conversely, when the bottom 64B of the contact plug 64 is located relatively low, each of the multiple in-base regions 66 can be spaced apart in the Z-axis direction from the third region 60A, as described with reference to FIG. 7 .

[0087] Second Embodiment Next, an exemplary semiconductor device 400 according to a second embodiment of the present disclosure will be described with reference to FIGS. 19 to 21 . FIG. 19 is a schematic plan view of the semiconductor device 400. FIGS. 20 and 21 are schematic cross-sectional views of the semiconductor device 400 shown in FIG. 19 . Note that in FIGS. 19 to 21 , components similar to those in the first embodiment are denoted by the same reference numerals. Further, detailed description of components similar to those in the first embodiment will be omitted.

[0088] 19 to 21, in the semiconductor device 400, the gate-dummy mesa 54 further includes a plurality of p-type complementary regions 402. The p-type impurity concentration of the complementary regions 402 is higher than the p-type impurity concentration of the second region 58A and lower than the p-type impurity concentration of the plurality of in-base regions 66. In one example, the p-type impurity concentration of the plurality of complementary regions 402 is 1×10 １８ cm －３ 1x10 or more １９ cm －３ Each of the complementary regions 402 may at least partially surround one of the in-base regions 66 in plan view. Each of the complementary regions 402 may extend across the entire width of the gate-dummy mesa 54 in the X-axis direction.

[0089] 20 and 21 , each of the complementary regions 402 is located between the third region 60A and the first region 56A. Each of the complementary regions 402 is adjacent to the second region 58A. Each of the complementary regions 402 may be located in the second region 58A closer to the third region 60A than to the first region 56A. In the illustrated example, each of the complementary regions 402 may be adjacent to the third region 60A. Each of the complementary regions 402 may be located above the in-base regions 66.

[0090] 22 to 25, the operation of the semiconductor device 400 will be described. As will be described below, the complementary region 402 of the semiconductor device 400 can function to reduce variations in the characteristics of the semiconductor device 400 that may occur when the patterning of the contact plug 64 is misaligned during the manufacturing process.

[0091] FIG. 22 is an enlarged plan view of the semiconductor device 400 when the contact plugs 64 are shifted in the X-axis direction. FIG. 23 is a schematic cross-sectional view of the semiconductor device 400 of FIG. 22. As shown in FIGS. 22 and 23, the multiple contact plugs 64 are shifted to the left with respect to the trenches 42 and 44. The contact plugs 64 are still in contact with the gate-dummy mesa portion 54, but a relatively large distance D8 and a relatively small distance D9 are created between the gate trench 42 and the contact plug 64 depending on their positional relationship. Therefore, a relatively wide area 404A exists between the gate trench 42 and the contact plug 64, which are separated by the relatively large distance D8, and a relatively narrow area 404B exists between the gate trench 42 and the contact plug 64, which are separated by the relatively small distance D9.

[0092] Since the in-base region 66 is formed along the bottom 64B of the contact plug 64, the position of the in-base region 66 may depend on the position of the contact plug 64. This is because the in-base region 66 is formed by ion implantation through the contact hole filled with the contact plug 64. Therefore, if a positional deviation occurs during the formation of the contact plug 64, the position of the in-base region 66 will also be shifted.

[0093] 22 and 23, the in-base region 66 may extend over the entire length of the relatively narrow area 404B in the X-axis direction, but may extend over only a portion of the length of the relatively wide area 404A in the X-axis direction. In the illustrated example, the in-base region 66 is absent in a portion of the area 404A that is adjacent to the gate trench 42 and relatively far from the contact plug 64.

[0094] On the other hand, the complementary region 402 can be formed to extend across the entire width of the gate-dummy mesa 54 in the X-axis direction. In one example, the complementary region 402 may be formed by ion implantation using a mask prior to the formation of the contact hole for the contact plug 64. Therefore, even if the contact plug 64 is misaligned, the complementary region 402 can extend across the entire length of the relatively wide area 404A in the X-axis direction.

[0095] Next, for comparison, a semiconductor device 401 without a complementary region will be described. Fig. 24 is an enlarged plan view of the semiconductor device 401 when the contact plug 64 is shifted in the X-axis direction. Fig. 25 is a schematic cross-sectional view of the semiconductor device 401 of Fig. 24.

[0096] 24 and 25 , similar to FIGS. 22 and 23 , the multiple contact plugs 64 are shifted to the left with respect to the trenches 42, 44. As a result, a relatively wide area 404A exists between the gate trench 42 and the contact plug 64, which are separated by a relatively large distance D8, and a relatively narrow area 404B exists between the gate trench 42 and the contact plug 64, which are separated by a relatively small distance D9. No in-base region 66 exists in a portion of the area 404A that is adjacent to the gate trench 42 and relatively far from the contact plug 64.

[0097] The semiconductor device 401 does not include a complementary region as described in relation to the semiconductor device 400. Therefore, when the semiconductor device 401 is turned on, a current path (see the arrow shown in FIG. 25 ) from the third region 60A through the area 404A to the first region 56A is provided by the inversion layer formed in the second region 58A. Such a current path, which is unintentionally generated when the contact plug 64 is misaligned, causes variations in the characteristics of the semiconductor device 401.

[0098] On the other hand, in the semiconductor device 400 according to this embodiment, even if the contact plug 64 is misaligned, the complementary region 402 can extend over the entire length of the relatively wide area 404A in the X-axis direction. The presence of the complementary region 402, which has a higher p-type impurity concentration than the second region 58A, can suppress the occurrence of the above-described unintended current path (inversion layer). Therefore, the semiconductor device 400 according to this embodiment can achieve lower characteristic variations while maintaining the same advantages as the first embodiment.

[0099] Modification of Second Embodiment The complementary region as described in relation to the second embodiment can also be applied to a semiconductor device having a different configuration from that shown in FIG.

[0100] 26 is a schematic plan view of a semiconductor device 500 configured by applying complementary regions 502 to the semiconductor device 100 shown in FIG. 26, in the semiconductor device 500, the gate-dummy mesa portion 54 further includes a plurality of p-type complementary regions 502. The p-type impurity concentration of the complementary regions 502 is higher than the p-type impurity concentration of the second region 58A and lower than the p-type impurity concentration of the plurality of in-base regions 66. In one example, the p-type impurity concentration of the plurality of complementary regions 502 is 1×10 １８ cm －３ 1x10 or more １９ cm －３ 21. Each of the complementary regions 502 at least partially surrounds one of the in-base regions 66 in plan view. Each of the complementary regions 502 may extend across the entire width of the gate-dummy mesa 54 in the X-axis direction. The position of the complementary region 502 in the Z-axis direction may be the same as that of the complementary region 402 shown in FIG.

[0101] 27 is a schematic plan view of a semiconductor device 600 configured by applying complementary regions 602 to the semiconductor device 200 shown in FIG. 27, in the semiconductor device 600, the gate-dummy mesa portion 54 further includes a plurality of p-type complementary regions 602. The p-type impurity concentration of the complementary regions 602 is higher than the p-type impurity concentration of the second region 58A and lower than the p-type impurity concentration of the plurality of in-base regions 66. In one example, the p-type impurity concentration of the plurality of complementary regions 602 is 1×10 １８ cm －３ 1x10 or more １９ cm －３ 21. Each of the complementary regions 602 at least partially surrounds one of the in-base regions 66 in plan view. Each of the complementary regions 602 may extend across the entire width of the gate-dummy mesa 54 in the X-axis direction. The position of the complementary region 602 in the Z-axis direction may be the same as that of the complementary region 402 shown in FIG.

[0102] 28 is a schematic cross-sectional view of a semiconductor device 700 configured by applying complementary regions 702 to the semiconductor device 300 shown in FIG. 28. As shown in FIG. 28, in the semiconductor device 700, the gate-dummy mesa portion 54 further includes a plurality of p-type complementary regions 702. The p-type impurity concentration of the complementary regions 702 is higher than the p-type impurity concentration of the second region 58A and lower than the p-type impurity concentration of the plurality of in-base regions 302. In one example, the p-type impurity concentration of the plurality of complementary regions 702 is 1×10 １８ cm －３ 1x10 or more １９ cm －３ The following may be true. Each of the multiple complementary regions 702 at least partially surrounds one of the multiple in-base regions 302 in a plan view. Each of the multiple complementary regions 702 may extend across the entire width of the gate-dummy mesa 54 in the X-axis direction. Each of the multiple complementary regions 702 is located between the third region 60A and the first region 56A. Each of the multiple complementary regions 702 is adjacent to the second region 58A. Each of the multiple complementary regions 702 may be located in the second region 58A closer to the third region 60A than to the first region 56A. In the illustrated example, each of the multiple complementary regions 702 and each of the multiple in-base regions 302 may be adjacent to the third region 60A. Therefore, the multiple complementary regions 702 do not have to be located above the multiple in-base regions 302.

[0103] Based on the same principle as that explained in relation to the second embodiment, the semiconductor devices 500, 600, and 700 can achieve lower characteristic variations while having the same advantages as the first embodiment.

[0104] Third Embodiment Next, an exemplary semiconductor device 800 according to a third embodiment of the present disclosure will be described with reference to FIGS. 29 to 31 . FIG. 29 is a schematic plan view of the semiconductor device 800. FIG. 30 is a schematic cross-sectional view of the semiconductor device taken along line F30-F30 in FIG. 29 . FIG. 31 is a schematic cross-sectional view of the semiconductor device taken along line F31-F31 in FIG. 29 . Note that in FIGS. 29 to 31 , components similar to those in the first embodiment are denoted by the same reference numerals. Further, detailed description of components similar to those in the first embodiment will be omitted.

[0105] 29 to 31 , the semiconductor device 800 includes a first electrode 802 located in the gate trench 42 and separated from the semiconductor layer 12 by the insulating layer 14. The first electrode 802 includes a plurality of recesses 804. As shown in FIG. 31 , the plurality of recesses 804 are recessed from the upper surface 802A of the first electrode 802. The plurality of recesses 804 are aligned in the Y-axis direction such that each recess 804 is adjacent to a corresponding one of the contact plugs 64 included in the row R. As shown in FIG. 29 , the dimension of each recess 804 in the Y-axis direction may be equal to or greater than the dimension of each in-base region 66 in the Y-axis direction. In the illustrated example, the dimension of each recess 804 in the Y-axis direction is slightly larger than the dimension of each in-base region 66 in the Y-axis direction.

[0106] 30 , each recess 804 has a bottom surface 804B located below the interface between the third region 60A and the second region 58A. More preferably, as in the illustrated example, the bottom surface 804B of each recess 804 may be located below the in-base region 66. Each recess 804 may be filled with the second insulating layer 52.

[0107] 32 and 33, the operation of the semiconductor device 800 will be described. As will be described below, the multiple recesses 804 of the first electrode 802 can function to reduce variations in the characteristics of the semiconductor device 800 that may occur when the patterning of the contact plug 64 is misaligned during the manufacturing process.

[0108] 32 is a schematic cross-sectional view of the semiconductor device 800 when the contact plugs 64 are shifted in the X-axis direction. As shown in Fig. 32, the multiple contact plugs 64 are shifted to the left with respect to the trenches 42 and 44. As a result, the distance between the gate trench 42 and the contact plug 64 on the left side of the gate trench 42 is relatively large.

[0109] In locations where the inbase region 66, which has a relatively high p-type impurity concentration, exists, the formation of an inversion layer that functions as a channel of the semiconductor device 10 is inhibited. Typically, the inbase region 66 reliably blocks the current path from the third region 60A to the first region 56A around the contact plug 64. However, as in the example of FIG. 32 , when the multiple contact plugs 64 are shifted to the left relative to the trenches 42 and 44, the inbase region 66 located to the left of the gate trench 42 does not extend across the entire width of the gate-dummy mesa 54 in the X-axis direction. The gate-adjacent region 806 between this inbase region 66 and the gate trench 42 is part of the second region 58A. In the semiconductor device 800, due to the presence of the recess 804 in the first electrode 802, the gate-adjacent region 806 faces the second insulating layer 52, rather than the first electrode 802, via the first insulating layer 50. Therefore, even if a gate voltage is applied to the first electrode 802, an inversion layer cannot be formed in the gate-adjacent region 806.

[0110] Next, for comparison, a semiconductor device 801 including a first electrode 46 without a recess will be described. FIG. 33 is a schematic cross-sectional view of the semiconductor device 801 in which the contact plugs 64 are shifted in the X-axis direction. As shown in FIG. 33 , similar to FIG. 32 , the multiple contact plugs 64 are shifted to the left with respect to the trenches 42 and 44. As a result, the distance between the gate trench 42 and the contact plug 64 located on the left side of the gate trench 42 is relatively large. As a result, the in-base region 66 located on the left side of the gate trench 42 does not extend across the entire width of the gate-dummy mesa portion 54 in the X-axis direction.

[0111] The first electrode 46 of the semiconductor device 801 does not have a recess as described in relation to the semiconductor device 800. The upper surface 46A of the first electrode 46 is located above the interface between the third region 60A and the second region 58A. Therefore, the gate-adjacent region 806 between the in-base region 66 and the gate trench 42 faces the first electrode 46 via the first insulating layer 50. As a result, in the semiconductor device 801, when a gate voltage is applied to the first electrode 46, an inversion layer is formed in the gate-adjacent region 806. Therefore, when the semiconductor device 801 is turned on, the inversion layer formed in the second region 58A provides a current path (see the arrow in FIG. 33 ) from the third region 60A through the gate-adjacent region 806 to the first region 56A. Such a current path, which is unintentionally generated when the contact plug 64 is misaligned, causes variations in the characteristics of the semiconductor device 801.

[0112] On the other hand, in the semiconductor device 800 according to this embodiment, the presence of the recess 804 in the first electrode 802 prevents the gate-adjacent region 806 from facing the first electrode 802 in the X-axis direction. Therefore, even if the contact plug 64 is misaligned, an inversion layer is not formed in the second region 58A. This makes it possible to suppress the occurrence of the unintended current path (inversion layer) described above. Thus, the semiconductor device 800 according to this embodiment can achieve lower characteristic variations while retaining the same advantages as the first embodiment.

[0113] Modification of Third Embodiment The first electrode having a recess as described in relation to the third embodiment can also be applied to a semiconductor device having a different configuration from that shown in FIG.

[0114] Fig. 34 is a schematic plan view of a semiconductor device 900 configured by applying a first electrode 902 having a recess 904 to the semiconductor device 100 shown in Fig. 10. Fig. 35 is a schematic cross-sectional view of the semiconductor device taken along line F35-F35 in Fig. 34.

[0115] 34 and 35 , the semiconductor device 900 includes a first electrode 902 located in the gate trench 42 and separated from the semiconductor layer 12 by the insulating layer 14. The first electrode 902 includes a plurality of recesses 904. The recesses 904 are aligned in the Y-axis direction such that each recess 904 is adjacent to a corresponding one of the contact plugs 64 included in a row R (similar to FIG. 31 described in connection with the third embodiment). As shown in FIG. 34 , the dimension of each recess 904 in the Y-axis direction may be equal to or greater than the dimension of each in-base region 66 in the Y-axis direction.

[0116] 35 , each recess 904 has a bottom surface 904B located below the interface between the third region 60A and the second region 58A. More preferably, as in the illustrated example, the bottom surface 904B of each recess 904 may be located below the in-base region 66. Each recess 904 may be filled with the second insulating layer 52.

[0117] Fig. 36 is a schematic plan view of a semiconductor device 1000 configured by applying a first electrode 1002 having a recess 1004 to the semiconductor device 200 shown in Fig. 14. Fig. 37 is a schematic cross-sectional view of the semiconductor device taken along line F37-F37 in Fig. 36.

[0118] 36 and 37 , the semiconductor device 1000 includes a first electrode 1002 located in the gate trench 42 and separated from the semiconductor layer 12 by the insulating layer 14. The first electrode 1002 includes a plurality of recesses 1004. The recesses 1004 are aligned in the Y-axis direction such that each recess 1004 is adjacent to a corresponding one of the contact plugs 64 included in a row R (similar to FIG. 31 described in connection with the third embodiment). As shown in FIG. 36 , the dimension of each recess 1004 in the Y-axis direction may be equal to or greater than the dimension of each in-base region 66 in the Y-axis direction.

[0119] 37 , each recess 1004 has a bottom surface 1004B located below the interface between the third region 60A and the second region 58A. More preferably, as in the illustrated example, the bottom surface 1004B of each recess 1004 may be located below the in-base region 66. Each recess 1004 may be filled with the second insulating layer 52.

[0120] Based on the same principle as that explained in relation to the third embodiment, the semiconductor devices 900 and 1000 can achieve lower characteristic variations while having the same advantages as the first embodiment.

[0121] Other Modifications The various examples described above have been described with reference to configurations in which the ratio of the number of gate trenches 42 to the number of dummy trenches 44 is 1:2 or 1:1. However, the present disclosure is not limited to these examples. Any number of dummy trenches 44 can be disposed between two gate trenches 42.

[0122] Two gate trenches 42 with any number of dummy trenches 44 disposed between them are referred to as a left gate trench and a right gate trench. In this case, the multiple trenches 42, 44 may include one or more dummy trenches 44 disposed between the left gate trench and the right gate trench. Of the one or more dummy trenches 44, the dummy trench 44 located closest to the left gate trench may at least partially overlap with the row R of contact plugs in a plan view. Similarly, of the one or more dummy trenches 44, the dummy trench 44 located closest to the right gate trench may at least partially overlap with another row R of contact plugs in a plan view.

[0123] One or more of the various examples described herein can be combined to the extent that they are not technically inconsistent. In this specification, "at least one of A and B" should be understood to mean "only A, or only B, or both A and B."

[0124] The term "on" as used in this disclosure can mean both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer can be placed directly on the second layer in contact with the second layer, while in other embodiments, the first layer can be placed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0125] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," and "rear" used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0126] For example, the Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0127] <Supplementary Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the supplementary notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference symbols.

[0128] (Supplementary Note 1) A semiconductor device comprising: a semiconductor layer (12) having a first surface (12A); a first trench (42) and a second trench (44) extending from the first surface (12A) into the semiconductor layer (12); an insulating layer (14) located on the semiconductor layer (12); a first electrode (46) located in the first trench (42) and separated from the semiconductor layer (12) by the insulating layer (14); a second electrode (48) located in the second trench (44) and separated from the semiconductor layer (12) by the insulating layer (14), the second electrode (48) being electrically insulated from the first electrode (46); and a plurality of contact plugs (64) penetrating the insulating layer (14) and contacting the semiconductor layer (12), each of the first trenches (42) and the second trenches (44) extends in a first direction in a plan view, and the first trenches (42) and the second trenches (44) are spaced apart in a second direction perpendicular to the first direction in a plan view; the semiconductor layer (12) includes a mesa portion (54) defined between the first trenches (42) and the second trenches (44); the plurality of contact plugs (64) include a row (R) of contact plugs in contact with the mesa portion (54), the row (R) of contact plugs at least partially overlapping the second trenches (44) in a plan view and being spaced apart from the first trenches (42); and the contact plugs (64) included in the row (R) are arranged at intervals in the first direction.

[0129] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the mesa portion (54) includes: a first region (56A) of a first conductivity type; a second region (58A) of a second conductivity type located on the first region (56A); a third region (60A) of the first conductivity type located on the second region (58A) and including a part of the first surface (12A) of the semiconductor layer (12); and a plurality of inbase regions (66) of a second conductivity type, the plurality of inbase regions (66) having a higher second conductivity type impurity concentration than a second conductivity type impurity concentration of the second region (58A), each of the plurality of inbase regions (66) being in contact with a bottom (64B) of a corresponding contact plug (64) included in the row (R), and the plurality of inbase regions (66) being arranged at intervals in the first direction.

[0130] (Supplementary Note 3) The semiconductor device according to Supplementary Note 2, wherein each of the plurality of in-base regions (66) is located between the third region (60A) and the first region (56A) and extends across the entire width of the mesa portion (54) in the second direction.

[0131] (Supplementary Note 4) The semiconductor device according to Supplementary Note 2, wherein each of the contact plugs (64) included in the row (R) penetrates the third region (60A).

[0132] (Supplementary Note 5) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein each of the contact plugs (64) included in the row (R) is in contact with the second electrode (48).

[0133] (Supplementary Note 6) The semiconductor device according to any one of Supplementary Notes 1 to 5, wherein the contact plugs (64) included in the row (R) are arranged at regular intervals in the first direction.

[0134] (Appendix 7) The semiconductor device according to any one of Appendices 1 to 6, wherein the mesa portion (54) includes an upper portion (54A) including a part of the first surface (12A) of the semiconductor layer (12), and a dimension (D1) in the second direction of the upper portion (54A) of the mesa portion (54) is 0.8 μm or less.

[0135] (Appendix 8) The semiconductor device according to any one of Appendices 1 to 7, wherein the mesa portion (54) includes an upper portion (54A) including a portion of the first surface (12A) of the semiconductor layer (12), and the dimension (D1) in the second direction of the upper portion (54A) of the mesa portion (54) is equal to or less than the dimension (D3) in the second direction of each of the contact plugs (64) included in the row (R).

[0136] (Appendix 9) The semiconductor device according to any one of Appendices 1 to 8, wherein the mesa portion (54) includes an upper portion (54A) including a portion of the first surface (12A) of the semiconductor layer (12), and the spacing (D5) of the contact plugs (64) in the first direction is greater than the dimension (D1) of the upper portion (54A) of the mesa portion (54) in the second direction.

[0137] (Supplementary Note 10) The semiconductor device according to any one of Supplementary Notes 1 to 9, further comprising an emitter electrode (22) located on the insulating layer (14) and connected to the plurality of contact plugs (64).

[0138] (Supplementary Note 11) The semiconductor device according to Supplementary Note 10, wherein the second electrode (48) is electrically connected to the emitter electrode (22).

[0139] (Note 12) The second region (58A) has a second conductivity type impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The second conductivity type impurity concentration of the plurality of in-base regions (66) is 1×10 １９ cm －３ 1x10 or more ２０ cm －３ 3. The semiconductor device according to claim 2, wherein:

[0140] (Supplementary Note 13) The semiconductor device according to Supplementary Note 2, wherein the mesa portion (54) further includes a plurality of complementary regions (402) of a second conductivity type, the impurity concentrations of the second conductivity type of the complementary regions (402) being higher than the impurity concentration of the second conductivity type of the second region (58A) and lower than the impurity concentration of the second conductivity type of the plurality of inbase regions (66), and each of the plurality of complementary regions (402) at least partially surrounding one of the plurality of inbase regions (66) in a planar view.

[0141] (Note 14) The second region (58A) has a second conductivity type impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The impurity concentration of the second conductivity type of the complementary regions (402) is 1×10 １８ cm －３ 1x10 or more １９ cm －３ The second conductivity type impurity concentration of the plurality of in-base regions (66) is 1×10 １９ cm －３ 1x10 or more ２０ cm －３ 14. The semiconductor device according to claim 13, wherein:

[0142] (Appendix 15) The semiconductor device described in Appendix 2, wherein the first electrode (46) includes a plurality of recesses (804) recessed from an upper surface (46A) of the first electrode (46), and the plurality of recesses (804) are aligned in the first direction so that each recess (804) is adjacent to a corresponding one of the contact plugs (64) included in the row (R).

[0143] (Supplementary Note 16) The semiconductor device according to Supplementary Note 15, wherein each recess (804) includes a bottom surface (804B) located below the in-base region (66).

[0144] (Supplementary Note 17) The semiconductor device further includes: a third trench (42) extending from the first surface (12A) into the semiconductor layer (12); and a third electrode (46) located in the third trench (42) and separated from the semiconductor layer (12) by the insulating layer (14), wherein the third electrode (46) is electrically connected to the first electrode (46), the mesa portion (54) is a first mesa portion (54), the third trench (42) extends in the first direction in a plan view, the second trench (44) and the third trench (42) are spaced apart in the second direction in a plan view, and the semiconductor layer (12) includes a second mesa portion (54) defined between the second trench (44) and the third trench (42), 17. The semiconductor device according to any one of claims 1 to 16, wherein the row (R) of contact plugs (202) contacts both the first mesa portion (54) and the second mesa portion (54) and is spaced apart from both the first trench (42) and the third trench (42).

[0145] (Appendix 18) A semiconductor device described in Appendix 17, wherein the pitch (D7) in the second direction between the first trench (42) and the second trench (44) is smaller than the dimension (D6) in the second direction of each of the contact plugs (202) included in the column (R).

[0146] (Supplementary Note 19) The semiconductor device further includes: a third trench (44) extending from the first surface (12A) into the semiconductor layer (12); and a third electrode (48) located in the third trench (44) and separated from the semiconductor layer (12) by the insulating layer (14), wherein the third electrode (48) is electrically connected to the second electrode (48), the mesa portion (54) is a first mesa portion (54), and the row (R) of contact plugs is a first row (R) of contact plugs, the third trench (44) extends in the first direction in a plan view, and the semiconductor layer (12) includes a second mesa portion (54) defined between the first trench (42) and the third trench (44), The semiconductor device according to any one of appendices 1 to 16, wherein the plurality of contact plugs include a second row (R) of contact plugs that contact the second mesa portion (54), the contact plugs included in the second row (R) being arranged at intervals in the first direction, and the second row (R) of contact plugs at least partially overlapping with the third trench (44) in a planar view and being spaced apart from the first trench (42).

[0147] (Supplementary Note 20) The semiconductor device according to any one of Supplementary Notes 1 to 16, wherein the semiconductor device comprises a plurality of trenches (42, 44) extending from the first surface (12A) into the semiconductor layer (12), each of the plurality of trenches (42, 44) extending in the first direction in a plan view, the plurality of trenches (42, 44) including: a left gate trench (42), a right gate trench (42), and one or more dummy trenches (44) arranged between the left gate trench (42) and the right gate trench (42), the first trench (42) being the left gate trench (42), and the second trench (44) being the dummy trench (44) located closest to the left gate trench (42) among the one or more dummy trenches (44).

[0148] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0149] 10, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000... Semiconductor device 12... Semiconductor layer 12A... First surface 12B... Second surface 12C... Outer edge 14... Insulating layer 16... Active region 18... Peripheral region 20... Gate electrode 22... Emitter electrode 24... Gate pad portion 26... Inner gate finger portion 28... Peripheral gate finger portion 30... Emitter pad portion 32... Emitter finger portion 34... Collector electrode 36... Collector region 38... Buffer region 40... Drift region 42... Gate trench (first trench) 44... Dummy trench (second trench) 46, 802, 902, 1002... First electrode 46A... Upper surface 48... Second electrode 50... First insulating layer 52... Second insulating layer 54... Gate-dummy mesa portion (mesa portion) 54A... Upper portion 56... Carrier storage region 56A... First region 58... Base region 58A... Second region 60... Emitter region 60A... Third region 62... Dummy-dummy mesa portion 62A... Upper portion 64, 202... Contact plug 64B, 202B... Bottom portion 66, 302... In-base region 68... Isolation trench 70... Isolation electrode 72... Peripheral well region 74... First well opening 76... Second well opening 78... Gate opening 80... Peripheral gate wiring 402, 502, 602, 702... Complementary region 404A, 404B... Area 802A... Upper surface 804, 904, 1004... Recess 804B, 904B, 1004B... bottom surface 806... gate adjacent region

Claims

a first electrode located in the first trench and separated from the semiconductor layer by the insulating layer; a second electrode located in the second trench and separated from the semiconductor layer by the insulating layer, the second electrode being electrically insulated from the first electrode; and a plurality of contact plugs penetrating the insulating layer and contacting the semiconductor layer, wherein each of the first trench and the second trench extends in a first direction in a plan view, and the first trench and the second trench are separated from each other in a second direction perpendicular to the first direction in a plan view, and the semiconductor layer includes a mesa portion defined between the first trench and the second trench, The semiconductor device, wherein the plurality of contact plugs include a row of contact plugs in contact with the mesa portion, the row of contact plugs at least partially overlapping with the second trench in a planar view and spaced apart from the first trench, and the contact plugs included in the row are arranged at intervals in the first direction.

2. The semiconductor device according to claim 1, wherein the mesa portion includes: a first region of a first conductivity type; a second region of a second conductivity type located on the first region; a third region of a first conductivity type located on the second region and including a part of the first surface of the semiconductor layer; and a plurality of inbase regions of a second conductivity type, the plurality of inbase regions having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second region, each of the plurality of inbase regions being in contact with a bottom of a corresponding contact plug included in the column, and the plurality of inbase regions being arranged at intervals in the first direction.

3. The semiconductor device according to claim 2, wherein each of said plurality of in-base regions is located between said third region and said first region and extends across the entire width of said mesa portion in said second direction.

4. The semiconductor device according to claim 2, wherein each of the contact plugs included in said column penetrates said third region.

5. The semiconductor device according to claim 1, wherein each of the contact plugs included in the column is in contact with the second electrode.

6. The semiconductor device according to claim 1, wherein the contact plugs included in the row are arranged at regular intervals in the first direction.

7. A semiconductor device according to any one of claims 1 to 6, wherein the mesa portion includes an upper portion that includes a part of the first surface of the semiconductor layer, and the dimension of the upper portion of the mesa portion in the second direction is 0.8 μm or less.

8. A semiconductor device according to any one of claims 1 to 7, wherein the mesa portion includes an upper portion that includes a portion of the first surface of the semiconductor layer, and the dimension in the second direction of the upper portion of the mesa portion is less than or equal to the dimension in the second direction of each of the contact plugs included in the column.

9. A semiconductor device according to any one of claims 1 to 8, wherein the mesa portion includes an upper portion that includes a portion of the first surface of the semiconductor layer, and the spacing between the contact plugs in the first direction is greater than the dimension in the second direction of the upper portion of the mesa portion.

10. The semiconductor device according to claim 1, further comprising an emitter electrode located on said insulating layer and connected to said plurality of contact plugs.

11. The semiconductor device according to claim 10, wherein the second electrode is electrically connected to the emitter electrode.

12. The second region has a second conductive type impurity concentration of 1×10 １５ cm －３ Above 1 x 10 １８ cm －３ The second conductivity type impurity concentration of the plurality of in-base regions is 1×10 １９ cm －３ Above 1 x 10 ２０ cm －３ The semiconductor device according to claim 2 , wherein:

13. The semiconductor device according to claim 2, wherein the mesa portion further includes a plurality of complementary regions of a second conductivity type, the impurity concentrations of the second conductivity type of the plurality of complementary regions being higher than the impurity concentration of the second conductivity type of the second region and lower than the impurity concentrations of the second conductivity type of the plurality of in-base regions, and each of the plurality of complementary regions at least partially surrounding one of the plurality of in-base regions in a planar view.

14. The second region has a second conductive type impurity concentration of 1×10 １５ cm －３ Above 1 x 10 １８ cm －３ The second conductivity type impurity concentration of the plurality of complementary regions is 1×10 １８ cm －３ Above 1 x 10 １９ cm －３ The second conductivity type impurity concentration of the plurality of in-base regions is 1×10 １９ cm －３ Above 1 x 10 ２０ cm －３ 14. The semiconductor device according to claim 13, wherein:

15. The semiconductor device described in claim 2, wherein the first electrode includes a plurality of recesses recessed from an upper surface of the first electrode, and the plurality of recesses are aligned in the first direction so that each recess is adjacent to a corresponding one of the contact plugs included in the row.

16. The semiconductor device according to claim 15, wherein each recess includes a bottom surface located below the in-base region.

17. The semiconductor device according to any one of claims 1 to 16, further comprising: a third trench extending from the first surface into the semiconductor layer; and a third electrode located in the third trench and separated from the semiconductor layer by the insulating layer, wherein the third electrode is electrically connected to the first electrode, the mesa portion is a first mesa portion, the third trench extends in the first direction in a planar view, and the second trench and the third trench are separated from each other in the second direction in a planar view, the semiconductor layer includes a second mesa portion defined between the second trench and the third trench, and the row of contact plugs contacts both the first mesa portion and the second mesa portion and is separated from both the first trench and the third trench.

18. The semiconductor device according to claim 17, wherein a pitch between the first trench and the second trench in the second direction is smaller than a dimension in the second direction of each of the contact plugs included in the column.

19. The semiconductor device according to any one of claims 1 to 16, further comprising: a third trench extending from the first surface into the semiconductor layer; and a third electrode located in the third trench and separated from the semiconductor layer by the insulating layer, the third electrode being electrically connected to the second electrode, the mesa portion being a first mesa portion, the row of contact plugs being a first row of contact plugs, the third trench extending in the first direction in a planar view, the semiconductor layer including a second mesa portion defined between the first trench and the third trench, the plurality of contact plugs including a second row of contact plugs contacting the second mesa portion, the contact plugs included in the second row being arranged at intervals in the first direction, and the second row of contact plugs at least partially overlapping the third trench in a planar view and separated from the first trench.

20. The semiconductor device according to any one of claims 1 to 16, comprising a plurality of trenches extending from the first surface into the semiconductor layer, each of the plurality of trenches extending in the first direction in a planar view, the plurality of trenches including: a left side gate trench; a right side gate trench; and one or more dummy trenches disposed between the left side gate trench and the right side gate trench, the first trench being the left side gate trench, and the second trench being a dummy trench among the one or more dummy trenches that is located closest to the left side gate trench.

Images