Silicon carbide substrate, epitaxial substrate, and method for producing semiconductor device

Abstract

This silicon carbide substrate has a main surface. The polytype of the silicon carbide substrate is 4H. The main surface is the {0001} face or a surface inclined with respect to the {0001} face at an off angle of 1° or less. The main surface is composed of an outer edge, an outer peripheral region extending up to 5 mm from the outer edge, and a central region surrounded by the outer peripheral region. The average value of the electrical resistivity in the central region is 1×1010 Ωcm or higher. When the surface density of threading dislocations in square regions with a side length of 1 mm located at intervals of 5 mm in the central region is measured, the value obtained by dividing the number of square regions in which the surface density of threading dislocations is 5000 cm-2 or higher by the total number of square regions is 30% or less.

Description

Silicon carbide substrate, epitaxial substrate, and method for manufacturing semiconductor device

[0001] The present disclosure relates to a silicon carbide substrate, an epitaxial substrate, and a method for manufacturing a semiconductor device. This application claims priority to Japanese Patent Application No. 2023-207580, filed December 8, 2023. The entire contents of this Japanese patent application are incorporated herein by reference.

[0002] Japanese Patent Publication No. 2008-505833 (Patent Document 1) describes a method for producing a ZnO film doped with vanadium and having a viscosity of 1×10 at room temperature. 6 High resistivity substrates having electrical resistivities of Ωcm are disclosed.

[0003] Special Publication No. 2008-505833

[0004] A silicon carbide substrate according to the present disclosure has a primary surface. The polytype of the silicon carbide substrate is 4H. The primary surface is a {0001} plane or a plane inclined relative to the {0001} plane at an off-angle of 1° or less. The primary surface is composed of an outer edge, a peripheral region within 5 mm from the outer edge, and a central region surrounded by the peripheral region. The average electrical resistivity of the central region is 1×10 10 In the central region, when the surface density of threading dislocations is measured in a square region with a side length of 1 mm at intervals of 5 mm, the surface density of threading dislocations is 5000 cm -2 The value obtained by dividing the number of square regions that are equal to or larger than this by the total number of square regions is 30% or less.

[0005] FIG. 1 is a plan view schematic diagram showing the configuration of a silicon carbide substrate according to this embodiment. FIG. 2 is a cross-sectional view schematic diagram taken along line II-II in FIG. 1. FIG. 3 is a plan view schematic diagram showing a region where the areal density of threading dislocations is measured. FIG. 4 is an enlarged schematic view of region IV in FIG. 3. FIG. 5 is a plan view schematic diagram showing the position where electrical resistivity is measured. FIG. 6 is a cross-sectional view schematic diagram showing the relationship between crucible pressure and time in the step of firing a silicon carbide raw material. FIG. 7 is a cross-sectional view schematic diagram showing the step of placing a seed substrate and a silicon carbide raw material in a crucible. FIG. 8 is a cross-sectional view schematic diagram showing the step of growing a silicon carbide crystal. FIG. 9 is a flowchart generally showing a method for manufacturing a semiconductor device according to this embodiment. FIG. 10 is a cross-sectional view schematic diagram showing the step of forming a buffer layer on a silicon carbide substrate. FIG. 11 is a cross-sectional view schematic diagram showing the step of forming an electron transit layer and an electron supply layer. FIG. 12 is a cross-sectional view schematic diagram showing the configuration of a semiconductor device according to this embodiment. FIG. 13 shows the results of the analysis when the surface density of threading dislocations is 5000 cm -2 10 is a graph showing the percentage of square regions having an areal density equal to or greater than the average value of the areal density of threading dislocations, the average value of the areal density of threading dislocations, and the percentage of square regions having an areal density equal to or greater than twice the average value of the areal density of threading dislocations.

[0006] [Problem to be Solved by the Present Disclosure] An object of the present disclosure is to provide a silicon carbide substrate, an epitaxial substrate, and a method for manufacturing a semiconductor device that can improve the yield of semiconductor devices. [Advantages of the Present Disclosure] According to the present disclosure, it is possible to provide a silicon carbide substrate, an epitaxial substrate, and a method for manufacturing a semiconductor device that can improve the yield of semiconductor devices.

[0007] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0008] (1) A silicon carbide substrate according to the present disclosure has a primary surface. The polytype of the silicon carbide substrate is 4H. The primary surface is a {0001} plane or a plane inclined relative to the {0001} plane at an off-angle of 1° or less. The primary surface is composed of an outer edge, a peripheral region within 5 mm from the outer edge, and a central region surrounded by the peripheral region. The average electrical resistivity of the central region is 1×10 10In the central region, when the surface density of threading dislocations is measured in a square region with a side length of 1 mm at intervals of 5 mm, the surface density of threading dislocations is 5000 cm -2 The value obtained by dividing the number of square regions having the above ratio by the total number of square regions is 30% or less. This makes it possible to reduce the proportion of regions where threading dislocations are concentrated. As a result, it is possible to improve the yield of semiconductor devices manufactured using the silicon carbide substrate.

[0009] (2) According to the silicon carbide substrate according to (1) above, the surface density of threading dislocations is 5000 cm -2 The value obtained by dividing the number of square regions equal to or greater than this by the total number of square regions may be 10% or less, thereby further reducing the proportion of regions where threading dislocations are concentrated.

[0010] (3) According to the silicon carbide substrate according to (2) above, the surface density of threading dislocations is 5000 cm -2 The value obtained by dividing the number of square regions that are equal to or greater than this by the total number of square regions may be 5% or greater.

[0011] (4) A silicon carbide substrate according to the present disclosure includes a primary surface. The polytype of the silicon carbide substrate is 4H. The primary surface is a {0001} plane or a plane inclined relative to the {0001} plane at an off-angle of 1° or less. The primary surface is composed of an outer edge, a peripheral region within 5 mm from the outer edge, and a central region surrounded by the peripheral region. The average electrical resistivity of the central region is 1×10 10 When the areal density of threading dislocations is measured in square regions with a side length of 1 mm at intervals of 5 mm in the central region, the value obtained by dividing the number of square regions having an areal density at least twice the average of the areal density of threading dislocations by the number of all square regions is 20% or less. This makes it possible to further reduce the proportion of regions where threading dislocations are concentrated.

[0012] (5) In the silicon carbide substrate according to (4) above, when the areal density of threading dislocations is measured in square regions with a side length of 1 mm at intervals of 5 mm in the central region, the value obtained by dividing the number of square regions having an areal density of threading dislocations at least twice the average areal density by the number of all square regions is 10% or less. This makes it possible to further reduce the proportion of regions where threading dislocations are concentrated.

[0013] (6) In the silicon carbide substrate according to (4) or (5), the average surface density of threading dislocations is 1500 cm -2 More than 3500cm -2 It may be the following:

[0014] (7) In the silicon carbide substrate according to any one of (1) to (5) above, the main surface may have a maximum diameter of 4 inches.

[0015] (8) In the silicon carbide substrate according to any one of (1) to (5) above, the main surface may have a maximum diameter of 6 inches.

[0016] (9) In the silicon carbide substrate according to any one of (1) to (5) above, the off-angle may be equal to or less than 0.5°. This makes it possible to effectively reduce the proportion of regions where threading dislocations are concentrated in a silicon carbide substrate having a small off-angle.

[0017] (10) According to the silicon carbide substrate of any one of (1) to (5) above, the silicon carbide substrate may contain vanadium, which can increase the electrical resistivity.

[0018] (11) An epitaxial substrate according to the present disclosure includes a silicon carbide substrate according to any one of (1) to (5) above and a nitride epitaxial layer on the silicon carbide substrate, thereby reducing the proportion of regions where threading dislocations are concentrated.

[0019] (12) A method for manufacturing a semiconductor device according to the present disclosure includes the steps of preparing a silicon carbide substrate according to any one of (1) to (5) above, forming a nitride epitaxial layer on the silicon carbide substrate, and forming an electrode on the nitride epitaxial layer, thereby reducing the proportion of regions where threading dislocations are concentrated.

[0020] [Details of the Embodiments of the Present Disclosure] Hereinafter, details of the embodiments of the present disclosure will be described with reference to the drawings. Note that the same or corresponding parts in the following drawings are given the same reference numerals, and their description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. Furthermore, for negative indices, in crystallography, a "-" (bar) is placed before the number, but in this specification, a negative sign is placed before the number.

[0021] First, a description will be given of the configuration of silicon carbide substrate 100 according to this embodiment. Fig. 1 is a plan view schematically showing the configuration of silicon carbide substrate 100 according to this embodiment.

[0022] As shown in FIG. 1 , silicon carbide substrate 100 according to this embodiment has a first main surface 1 and an outer peripheral side surface 3. First main surface 1 extends along each of a first direction 101 and a second direction 102. First direction 101 is, for example, the <11-20> direction. Second direction 102 is, for example, the <1-100> direction. Silicon carbide substrate 100 contains an n-type impurity such as nitrogen. Silicon carbide substrate 100 is made of hexagonal silicon carbide. The polytype of the hexagonal silicon carbide is 4H.

[0023] As shown in FIG. 1 , the diameter W1 of the first main surface 1 is, for example, 4 inches. The diameter W1 of the first main surface 1 may be, for example, 6 inches or 8 inches. When viewed along the third direction 103, the diameter W1 is the longest linear distance between two different points on the outer edge 6 of the first main surface 1. In this specification, 4 inches means 99 mm or more and 101.6 mm or less (4 × 25.4 mm). 6 inches means 148.5 mm or more and 152.4 mm or less (6 × 25.4 mm). 8 inches means 198 mm or more and 203.2 mm or less (8 × 25.4 mm).

[0024] The first main surface 1 is composed of an outer edge 6, an outer peripheral region 4, and a central region 5. The outer peripheral region 4 is a region within 5 mm from the outer edge 6. The central region 5 is a region surrounded by the outer peripheral region 4. The central region 5 is continuous with the outer peripheral region 4. In the radial direction of the first main surface 1, a distance W2 between the outer edge 6 and the boundary between the central region 5 and the outer peripheral region 4 is 5 mm.

[0025] As shown in Fig. 1, the outer peripheral side surface 3 has an orientation flat portion 7 and an arc-shaped portion 8. The arc-shaped portion 8 is continuous with the orientation flat portion 7. As shown in Fig. 1, when viewed along a straight line perpendicular to the first main surface 1, the orientation flat portion 7 may extend along a first direction 101.

[0026] The first main surface 1 is a surface tilted in the off direction with respect to the {0001} plane or the {0001} plane. Specifically, the first main surface 1 may be a surface tilted in the off direction with respect to the (0001) plane or the (0001) plane. The first main surface 1 may be a surface tilted in the off direction with respect to the (000-1) plane or the (000-1) plane. The off direction may be, for example, a first direction 101 or a second direction 102.

[0027] The off angle is the tilt angle of first main surface 1 with respect to the {0001} plane. The off angle is, for example, greater than 0° and equal to or less than 1°. The off angle may be, for example, equal to or less than 0.8°, equal to or less than 0.5°, or equal to or less than 0.3°.

[0028] Fig. 2 is a schematic cross-sectional view taken along line II-II in Fig. 1. The cross section shown in Fig. 2 is perpendicular to first main surface 1 and parallel to first direction 101. As shown in Fig. 2, silicon carbide substrate 100 according to this embodiment further has second main surface 2. Second main surface 2 is located on the opposite side of first main surface 1. Outer peripheral side surface 3 is continuous with each of first main surface 1 and second main surface 2.

[0029] Third direction 103 is a direction from second main surface 2 toward first main surface 1. Third direction 103 is perpendicular to each of first direction 101 and second direction 102. In third direction 103, silicon carbide substrate 100 has a thickness of not less than 300 μm and not more than 700 μm, for example.

[0030] The silicon carbide substrate 100 includes threading dislocations 9. The threading dislocations 9 include threading screw dislocations 9 a and threading edge dislocations 9 b. In the central region 5, the areal density of the threading edge dislocations 9 b may be greater than the areal density of the threading screw dislocations 9 a.

[0031] Fig. 3 is a plan view schematic diagram showing a measurement region for the areal density of threading dislocations 9. Fig. 4 is an enlarged schematic diagram of region IV in Fig. 3. The areal density of threading dislocations 9 is measured over the entire central region 5. Specifically, the measurement region for the areal density of threading dislocations 9 is a square region S arranged at intervals of 5 mm in the central region 5. Note that the measurement region for the areal density of threading dislocations 9 is not arranged at the boundary between the central region 5 and the peripheral region 4.

[0032] 3 and 4, the interval (first length W3) between two adjacent square regions S for measuring the areal densities of threading dislocations 9 is 5 mm. When viewed along the third direction, the first length W3 is the distance between the center of a first square region and the center of a second square region adjacent to the first square region.

[0033] As shown in FIG. 3 , the square regions S are arranged along each of the first direction 101 and the second direction 102. One of the square regions S is located at the center P5 of the first main surface 1. A first side of the square region S extends along the first direction 101. A second side of the square region S, which is connected to the first side, extends along the second direction 102. As shown in FIG. 4 , the length of one side of the square region S (second length W4) is 1 mm. The points marked with black circles in FIG. 3 correspond to the centers of the square regions S. As shown in FIG. 3 , when the diameter of the first main surface 1 is 4 inches, the number of square regions S is 241.

[0034] According to the silicon carbide substrate 100 of this embodiment, the areal density of threading dislocations 9 is 5000 cm -2The value obtained by dividing the number of square regions S where the surface density of threading dislocations 9 is 5000 cm or more by the total number of square regions S is 30% or less. -2 The value obtained by dividing the number of square regions S that are equal to or larger than 5000 cm by the total number of square regions S may be 20% or less, 15% or less, or 10% or less. -2 The value obtained by dividing the number of square regions S equal to or greater than this by the total number of square regions S may be 3% or greater, or 5% or greater.

[0035] According to silicon carbide substrate 100 according to this embodiment, the average areal density of threading dislocations 9 in central region 5 is 1500 cm -2 More than 3500cm -2 The average surface density of the threading dislocations 9 is 1800 cm -2 It may be 2000 cm or more. -2 The average surface density of the threading dislocations 9 may be 3200 cm -2 It may be less than 3000 cm -2 The average surface density of the threading dislocations 9 is calculated as the average surface density of the threading dislocations 9 in all the square regions S.

[0036] In the silicon carbide substrate 100 according to this embodiment, the value obtained by dividing the number of square regions S having an areal density of threading dislocations 9 that is twice or more the average value by the number of all square regions S is 20% or less. In the square regions S having an areal density of threading dislocations 9 that is twice or more the average value, threading dislocations 9 that are twice or more the average value are locally present. The value obtained by dividing the number of square regions S having an areal density of threading dislocations 9 that is twice or more the average value by the number of all square regions S may be 15% or less, or may be 10% or less. The value obtained by dividing the number of square regions S having an areal density of threading dislocations 9 that is twice or more the average value by the number of all square regions S may be 3% or more, or may be 5% or more.

[0037] FIG. 5 is a schematic plan view showing the measurement positions of the electrical resistivity. As shown in FIG. 5, the central region 5 includes a center P5, a first position P1, a second position P2, a third position P3, and a fourth position P4. The center P5 is located at the center of a circle along the outer edge 6 of the first main surface 1. As shown in FIG. 1, when viewed along a line perpendicular to the first main surface 1, the first position P1 is spaced a third length W5 from the center P5 in the first direction 101, the second position P2 is spaced a third length W5 from the center P5 in the second direction 102, the third position P3 is spaced a third length W5 from the center P5 in the opposite direction to the first direction 101, and the fourth position P4 is spaced a third length W5 from the center P5 in the opposite direction to the second direction 102. The third length W5 is ¼ of the maximum diameter of the first main surface 1. When the diameter W1 of the first main surface 1 is 100 mm, the third length W5 is 100 mm×¼=25 mm.

[0038] 5 , when viewed along a line perpendicular to the first main surface 1, the center P5 is located midway between the first position P1 and the third position P3 in the first direction 101. The first position P1, the third position P3, and the center P5 are located on a line parallel to the first direction 101. Similarly, when viewed along a line perpendicular to the first main surface 1, the center P5 is located midway between the second position P2 and the fourth position P4 in the second direction 102. The second position P2, the fourth position P4, and the center P5 are located on a line parallel to the second direction 102.

[0039] (Electrical Resistivity) According to silicon carbide substrate 100 according to this embodiment, the average value of electrical resistivity in central region 5 is 1×10 10 The electrical resistivity is measured at the center P5, the first position P1, the second position P2, the third position P3, and the fourth position P4. The average electrical resistivity in the central region 5 is the average value of the electrical resistivities at the above five positions. The average electrical resistivity in the central region 5 is 1×10 10 It may be 5×10 Ωcm or more. 10 It may be Ωcm or more, or 1×10 11 It may be 5×10 Ωcm or more. 11 It may be Ωcm or more, or 1×10 12At any point in the central region 5, the electrical resistivity may be 1×10 12 It may be Ωcm or more.

[0040] The electrical resistivity of silicon carbide substrate 100 is measured using, for example, COREMA-WT, an electrical resistivity measuring device manufactured by SemiMap. The voltage applied to silicon carbide substrate 100 is, for example, 5.0 V. The diameter of the probe is 10 mm. The measurement temperature is room temperature (27° C.).

[0041] (Vanadium Concentration) Silicon carbide substrate 100 according to this embodiment may contain vanadium (V). The average vanadium concentration in central region 5 is, for example, 1.0×10 16 cm -3 Above 3.0 x 10 17 cm -3 The vanadium concentration is measured at the center P5, the first position P1, the second position P2, the third position P3, and the fourth position P4. The average vanadium concentration is the average value of the vanadium concentrations at the above five points. The average vanadium concentration is 5.0 x 10 16 cm -3 Above 1.0 x 10 17 cm -3 It may be the following:

[0042] (Nitrogen Concentration) Silicon carbide substrate 100 according to this embodiment may contain nitrogen (N). The average concentration of nitrogen in central region 5 is, for example, 4.0×10 15 cm -3 Above 2.0 x 10 17 cm -3 The nitrogen concentration is measured at the center P5, the first position P1, the second position P2, the third position P3, and the fourth position P4. The average nitrogen concentration is the average value of the nitrogen concentrations at the above five points. The average nitrogen concentration is 1.0 x 10 16 cm -3 Above 8.0 x 10 16 cm -3 It may be the following:

[0043] The concentrations of vanadium and nitrogen are measured by, for example, secondary ion mass spectrometry (SIMS). For SIMS, for example, an IMS7f secondary ion mass spectrometer manufactured by Cameca Corporation can be used. The measurement conditions for SIMS are, for example, O primary ions, ２ ＋ The measurement conditions can be such that the primary ion energy is 8 keV.

[0044] <Method for Manufacturing Silicon Carbide Substrate> Next, a method for manufacturing silicon carbide substrate 100 according to this embodiment will be described. First, silicon carbide raw material 156 is prepared. Silicon carbide raw material 156 is, for example, a polycrystalline silicon carbide powder. The bulk density of silicon carbide raw material 156 is, for example, 2.0 g / cm 3 Next, silicon carbide raw material 156 is fired in a state where silicon carbide raw material 156 is placed in a crucible (not shown).

[0045] FIG. 6 is a schematic diagram showing the relationship between the pressure in the crucible and time in the firing step of silicon carbide raw material 156. As shown in FIG. 6, silicon carbide raw material 156 is fired at a first pressure C1. The first pressure C1 is, for example, 80 kPa. The firing temperature is, for example, 2150° C. or higher and 2250° C. or lower. The time from first time point T1 to second time point T2 is, for example, 3 hours. Next, the pressure in the crucible is slowly reduced. The pressure in the crucible is reduced from the first pressure C1 to a second pressure C2. The second pressure C2 is, for example, 100 Pa or 500 Pa. The time from second time point T2 to third time point T3 is, for example, 1 hour. Next, silicon carbide raw material 156 is fired at the second pressure C2. The time from third time point T3 to fourth time point T4 is, for example, 10 hours.

[0046] 7 is a cross-sectional view schematically illustrating a step of placing seed substrate 150 and silicon carbide source material 156 in crucible 130. First, crucible 130 is prepared. Crucible 130 is made of graphite. Crucible 130 has a housing portion 132 and a lid portion 131. Lid portion 131 is placed on housing portion 132. Housing portion 132 has a bottom surface 133. Bottom surface 133 faces lid portion 131. A heating portion (not shown) is arranged around the outer circumferential surface of crucible 130. The heating portion may be a resistance heating type or an induction heating type.

[0047] 7 , a silicon carbide raw material 156, a vanadium supply source 154, and porous carbon 160 are placed in the accommodation portion 132. The silicon carbide raw material 156 is placed on the porous carbon 160. The silicon carbide raw material 156 is in contact with both the porous carbon 160 and the accommodation portion 132.

[0048] The porous carbon 160 is in contact with, for example, the storage portion 132. The porous carbon 160 is spaced apart from both the lid portion 131 and the bottom surface 133. The porous carbon 160 is made of a porous material. In other words, the porous carbon 160 has a large number of pores.

[0049] The bulk concentration of the porous carbon 160 is lower than the bulk concentration of the graphite that constitutes the crucible 130. The bulk concentration of the porous carbon 160 is, for example, 1.36 g / cm ３ The bulk concentration of the porous carbon 160 is, for example, 1.3 g / cm ３ 1.4g / cm or more ３ It may be the following:

[0050] The thickness of the porous carbon 160 is, for example, 3 mm or more and 15 mm or less. The concentration of vanadium doped into the silicon carbide crystals 57, which will be described later, is affected by the thickness of the porous carbon 160. If the thickness of the porous carbon 160 is large, the concentration of vanadium doped into the silicon carbide crystals 57 will be low. Conversely, if the thickness of the porous carbon 160 is small, the concentration of vanadium doped into the silicon carbide crystals 57 will be high. Therefore, in order to reduce the in-plane variation in the vanadium concentration, porous carbon 160 with small variation in thickness is used.

[0051] The vanadium supply source 154 is arranged so as to be in contact with the bottom surface 133 of the accommodation portion 132. Specifically, the vanadium supply source 154 is arranged opposite the silicon carbide raw material 156 with respect to the porous carbon 160. From another perspective, the porous carbon 160 is arranged between the silicon carbide raw material 156 and the vanadium supply source 154. The porous carbon 160 faces the vanadium supply source 154. The vanadium supply source 154 contains, for example, vanadium carbide.

[0052] Seed substrate 150 is fixed to lid portion 131 using, for example, an adhesive (not shown). Seed substrate 150 has third main surface 151 and fourth main surface 152. Third main surface 151 faces silicon carbide raw material 156. Fourth main surface 152 faces lid portion 131. Third main surface 151 of seed substrate 150 is arranged to face the surface of silicon carbide raw material 156. As described above, seed substrate 150, silicon carbide raw material 156, and vanadium supply source 154 are arranged in crucible 130.

[0053] 8 is a cross-sectional schematic view showing the growth process of silicon carbide crystal 57. First, the pressure inside crucible 130 is reduced while the temperature of third main surface 151 of seed substrate 150 is lower than the temperature of silicon carbide raw material 156. The pressure of the ambient gas inside crucible 130 is reduced to, for example, 1.0 kPa. As a result, silicon carbide raw material 156 begins to sublimate, and the sublimated silicon carbide gas is recrystallized on third main surface 151 of seed substrate 150.

[0054] Vanadium supply source 154 also sublimates along with silicon carbide raw material 156. The sublimated vanadium gas passes through pores in porous carbon 160 and gaps between the powder constituting silicon carbide raw material 156, and reaches the periphery of seed substrate 150. As silicon carbide crystal 57 grows, silicon carbide crystal 57 is doped with vanadium. As a result, silicon carbide crystal 57 containing vanadium grows on third main surface 151.

[0055] In the step of growing silicon carbide crystal 57, the temperature inside crucible 130 is, for example, not less than 2150° C. and not more than 2250° C. The growth surface of silicon carbide crystal 57 may be curved so as to be convex toward silicon carbide raw material 156. As described above, silicon carbide crystal 57 grows on third main surface 151.

[0056] Next, a step of cutting silicon carbide crystal 57 is performed. For example, using a saw wire, silicon carbide crystal 57 is sliced ​​along a plane perpendicular to the central axis of silicon carbide crystal 57. In this way, a plurality of silicon carbide substrates 100 are obtained.

[0057] <Method of Manufacturing Semiconductor Device> Next, a method of manufacturing the semiconductor device 400 according to this embodiment will be described. Fig. 9 is a flowchart that outlines the method of manufacturing the semiconductor device 400 according to this embodiment. The method of manufacturing the semiconductor device 400 according to this embodiment mainly includes a step (S1) of manufacturing the epitaxial substrate 200 and a step (S2) of forming an electrode on the nitride epitaxial layer 30.

[0058] First, a step (S1) of manufacturing epitaxial substrate 200 is performed. Step (S1) of manufacturing epitaxial substrate 200 includes a step (S10) of preparing silicon carbide substrate 100 and a step (S20) of forming nitride epitaxial layer 30. First, step (S10) of preparing silicon carbide substrate 100 is performed. In step (S10) of preparing silicon carbide substrate 100, silicon carbide substrate 100 according to the present embodiment is prepared (see FIG. 1 ).

[0059] Next, the step (S20) of forming nitride epitaxial layer 30 is performed. Specifically, buffer layer 31 is formed on silicon carbide substrate 100. FIG. 10 is a cross-sectional schematic view showing the step of forming buffer layer 31 on silicon carbide substrate 100. Buffer layer 31 is formed by epitaxial growth on first main surface 1 of silicon carbide substrate 100. Buffer layer 31 is formed by MOCVD (Metal Organic Chemical Vapor Deposition), for example.

[0060] The buffer layer 31 is made of, for example, aluminum gallium nitride (AlGaN). The buffer layer 31 has a thickness of, for example, 150 nm. As a source gas for aluminum (Al), for example, TMA (trimethylaluminum) is used. As a source gas for gallium (Ga), for example, TMG (trimethylgallium) is used. As a source gas for nitrogen (N), for example, ammonia is used.

[0061] Next, the electron transit layer 32 and the electron supply layer 33 are formed. Fig. 11 is a cross-sectional view showing the process of forming the electron transit layer 32 and the electron supply layer 33. First, the electron transit layer 32 is formed on the buffer layer 31 by MOCVD. The electron transit layer 32 is made of, for example, gallium nitride (GaN). The thickness of the electron transit layer 32 is, for example, 1 µm.

[0062] Next, the electron supply layer 33 is formed on the electron transit layer 32. The electron supply layer 33 is formed by, for example, MOCVD. The electron supply layer 33 is made of, for example, AlGaN. The thickness of the electron supply layer 33 is, for example, 20 μm. Two-dimensional electron gas is generated in a portion of the electron transit layer 32 near the interface between the electron transit layer 32 and the electron supply layer 33.

[0063] As described above, the epitaxial substrate 200 is manufactured. As shown in Fig. 11 , the epitaxial substrate 200 includes the silicon carbide substrate 100 and the nitride epitaxial layer 30. The nitride epitaxial layer 30 includes a buffer layer 31, an electron transit layer 32, and an electron supply layer 33. The buffer layer 31 is provided on the silicon carbide substrate 100. The electron transit layer 32 is provided on the buffer layer 31. The electron supply layer 33 is provided on the electron transit layer 32.

[0064] Next, the step (S2) of forming electrodes is performed. First, the source electrode 41 and the drain electrode 42 are formed. Specifically, a first resist pattern (not shown) is formed on the electron supply layer 33. In the first resist pattern, openings are formed in the regions where the source electrode 41 and the drain electrode 42 are to be formed.

[0065] Next, a first metal stack film is formed on the first resist pattern using, for example, a vacuum deposition method. The first metal stack film includes, for example, a titanium (Ti) film and an aluminum (Al) film. Next, the first metal stack film formed on the first resist pattern is removed by lift-off. As a result, the source electrode 41 and the drain electrode 42 made of the first metal stack film are formed on the electron supply layer 33.

[0066] Next, alloying annealing may be performed. Specifically, the source electrode 41 and the drain electrode 42 are annealed. The annealing temperature is, for example, 600° C. This may allow each of the source electrode 41 and the drain electrode 42 to make ohmic contact with the electron supply layer 33.

[0067] Next, the gate electrode 43 is formed. Specifically, a second resist pattern (not shown) is formed on the electron supply layer 33. In the second resist pattern, an opening is formed in the region where the gate electrode 43 is to be formed.

[0068] Next, a second metal stack film is formed on the second resist pattern using, for example, a vacuum deposition method. The second metal stack film includes, for example, a nickel (Ni) film and a gold (Au) film. Next, the second metal stack film formed on the second resist pattern is removed by lift-off. As a result, a gate electrode 43 made of the second metal stack film is formed on the electron supply layer 33.

[0069] 12 is a cross-sectional view showing a configuration of a semiconductor device 400 according to this embodiment. The semiconductor device 400 is, for example, a field-effect transistor, and more specifically, a high electron mobility transistor (HEMT). The semiconductor device 400 mainly includes an epitaxial substrate 200, a gate electrode 43, a source electrode 41, and a drain electrode 42.

[0070] 12 , each of the gate electrode 43, the source electrode 41, and the drain electrode 42 is provided on the epitaxial substrate 200. Specifically, each of the gate electrode 43, the source electrode 41, and the drain electrode 42 is in contact with the electron supply layer 33. The gate electrode 43 may be located between the source electrode 41 and the drain electrode 42.

[0071] Next, the effects of the method for manufacturing silicon carbide substrate 100, epitaxial substrate 200, and semiconductor device 400 according to this embodiment will be described.

[0072] In order to produce silicon carbide crystal 57 with low stress using sublimation, it is necessary to maintain a small temperature difference in the radial direction while maintaining a convex shape in the growth direction. If a temperature difference occurs on the growth surface of silicon carbide crystal 57 during crystal growth, minute irregularities are generated on the growth surface. This causes minute facets (in other words, (000-1) planes) to be generated at multiple locations on the growth surface of silicon carbide crystal 57. If impurities such as vanadium precipitate on the minute facets, these precipitates can become the starting points for the generation of threading dislocations 9. Threading dislocations 9 can also be generated during the process of the generation and annihilation of the minute facets.

[0073] Microfacets tend to be generated in regions where the angle of the growth plane of silicon carbide crystal 57 is close to 0°. Therefore, particularly when producing silicon carbide crystal 57 having an on-plane or a growth plane with a small off-angle, microfacets are generated in many regions of the growth plane. In this case, threading dislocations 9 are formed locally in silicon carbide crystal 57, and the proportion of regions where threading dislocations 9 are concentrated increases.

[0074] As a result of extensive research, the inventors have come to the following findings and have found a way to reduce the proportion of regions where threading dislocations 9 are concentrated. First, the inventors focused on the shape of the surface of silicon carbide raw material 156 after firing. A large number of irregularities existed on the surface of silicon carbide raw material 156 from which silicon carbide crystal 57 with a high proportion of regions where threading dislocations 9 are concentrated was produced. The inventors hypothesized that the irregularities on the surface of silicon carbide raw material 156 are related to the generation of microfacets in silicon carbide crystal 57.

[0075] Therefore, the inventors conducted extensive research into the firing process of silicon carbide raw material 156 so as to prevent the occurrence of irregularities on the surface of silicon carbide raw material 156. As a result, by first firing silicon carbide raw material 156 at a high pressure, then gradually reducing the pressure, and then firing silicon carbide raw material 156 at an even lower pressure, it was possible to obtain silicon carbide raw material 156 in which the occurrence of irregularities on the surface of silicon carbide raw material 156 was suppressed. By using this silicon carbide raw material 156, it was possible to obtain silicon carbide crystal 57 in which the proportion of regions where threading dislocations 9 are concentrated is low.

[0076] According to silicon carbide substrate 100 in accordance with the present embodiment, it is possible to reduce the proportion of regions where threading dislocations 9 are concentrated. Therefore, it is possible to improve the yield of semiconductor devices manufactured using silicon carbide substrate 100.

[0077] (Sample Preparation) First, silicon carbide substrates 100 having a polytype of 4H were fabricated using manufacturing methods A and B. Samples 1 to 3 and 7 to 9 fabricated by manufacturing method A are comparative examples. Samples 4 to 6 and 10 to 12 fabricated by manufacturing method B are examples.

[0078] The difference between manufacturing methods A and B is the firing step of silicon carbide raw material 156. In the firing step of manufacturing method A, silicon carbide raw material 156 was fired for 10 hours under a pressure condition of 100 Pa. On the other hand, in the firing step of manufacturing method B, silicon carbide raw material 156 was first fired for 3 hours under a pressure condition of 80 kPa. Next, the pressure was reduced from 80 kPa to 100 Pa over 1 hour. Next, silicon carbide raw material 156 was fired for 10 hours under a pressure condition of 100 Pa. In each of manufacturing methods A and B, the firing temperature of silicon carbide raw material 156 was 2200°C.

[0079] Next, seed substrate 150 and fired silicon carbide source material 156 were placed in crucible 130 (see FIG. 7 ). Next, silicon carbide crystal 57 was formed on third main surface 151 of seed substrate 150 using a sublimation method (see FIG. 8 ). Next, silicon carbide crystal 57 was sliced ​​using a saw wire, thereby obtaining silicon carbide substrates 100 according to samples 1 to 12.

[0080] (Measurement method) The areal density of threading dislocations 9 was measured in the central region 5 of the silicon carbide substrate 100. The threading dislocations 9 include threading screw dislocations 9a and threading edge dislocations 9b. The measurement regions for the areal density of threading dislocations 9 were square regions S arranged at intervals of 5 mm in the central region 5 (see FIG. 3 ). The interval (first length W3) between two adjacent square regions S was 5 mm. The length of one side of the square region S (second length W4) was 1 mm.

[0081] (Measurement Results) FIG. 13 shows the results of measurements where the surface density of threading dislocations 9 is 5000 cm -2 The average surface density of the threading dislocations 9 and the percentage of square regions having a surface density twice or more than the average surface density of the threading dislocations 9 are shown. -2 The proportion of the square region that is equal to or larger than the surface density of the threading dislocations 9 is 5000 cm -2 The ratio of square regions having an areal density of threading dislocations 9 that is twice or more the average value is calculated by dividing the number of square regions having an areal density of threading dislocations 9 that is twice or more the average value by the number of all square regions.

[0082] In the case of a 4-inch silicon carbide substrate 100, the surface density of threading dislocations 9 is 5000 cm -2 The proportion of square regions having an areal density of threading dislocations 9 equal to or greater than 5000 cm was 34% or more and 56% or less, and the proportion of square regions having an areal density of threading dislocations 9 equal to or greater than twice the average value was 23% or more and 27% or less. On the other hand, in silicon carbide substrate 100 produced by manufacturing method B, the areal density of threading dislocations 9 was 5000 cm -2 The proportion of square regions having a surface density of threading dislocations 9 that was twice the average surface density was 6% or more and 9% or less, and the proportion of square regions having a surface density of threading dislocations 9 that was twice the average surface density was 5% or more and 9% or less.

[0083] In the case of a 6-inch silicon carbide substrate 100, the surface density of threading dislocations 9 is 5000 cm -2 The proportion of square regions having an areal density of threading dislocations 9 equal to or greater than 5000 cm was 45% or more and 64% or less, and the proportion of square regions having an areal density of threading dislocations 9 equal to or greater than twice the average value was 21% or more and 31% or less. On the other hand, in the silicon carbide substrate 100 produced by manufacturing method B, the areal density of threading dislocations 9 was 5000 cm -2 The proportion of square regions having a surface density of threading dislocations 9 equal to or greater than twice the average surface density was 5% or more and 10% or less, and the proportion of square regions having a surface density of threading dislocations 9 equal to or greater than twice the average surface density was 7% or more and 10% or less.

[0084] From the above results, it was confirmed that silicon carbide substrates 100 of samples 4 to 6 and 10 to 12 can reduce the proportion of regions where threading dislocations 9 are concentrated, compared to silicon carbide substrates 100 of samples 1 to 3 and 7 to 9. Therefore, the yield of semiconductor devices manufactured using these silicon carbide substrates 100 can be improved.

[0085] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments, and is intended to include meanings equivalent to the claims and all modifications within the scope thereof.

[0086] 1 First main surface, 2 Second main surface, 3 Outer peripheral side surface, 4 Outer peripheral region, 5 Central region, 6 Outer edge, 7 Orientation flat portion, 8 Arc-shaped portion, 9 Threading dislocation, 9a Threading screw dislocation, 9b Threading edge dislocation, 30 Nitride epitaxial layer, 31 Buffer layer, 32 Electron transit layer, 33 Electron supply layer, 41 Source electrode, 42 Drain electrode, 43 Gate electrode, 50 Growth surface, 56 Main body portion, 57 Silicon carbide crystal, 100 Silicon carbide substrate, 101 First direction, 102 Second direction, 103 Third direction, 130 Crucible, 131 Lid portion, 132 Storage portion, 133 Bottom surface, 150 Seed substrate, 151 Third main surface, 152 Fourth main surface, 154 Vanadium supply source, 156 Silicon carbide raw material, 160 porous carbon, 200 epitaxial substrate, 400 semiconductor device, C1 first pressure, C2 second pressure, P1 first position, P2 second position, P3 third position, P4 fourth position, P5 center, S square area, T1 first point in time, T2 second point in time, T3 third point in time, T4 fourth point in time, W1 diameter, W2 distance, W3 first length, W4 second length, W5 third length.

Claims

1. A silicon carbide substrate having a principal surface, the polytype of the silicon carbide substrate being 4H, the principal surface being a {0001} plane or a plane inclined with respect to the {0001} plane at an off angle of 1° or less, the principal surface being composed of an outer edge, a peripheral region within 5 mm from the outer edge, and a central region surrounded by the peripheral region, and the average electrical resistivity of the central region being 1×10 10 When the surface density of threading dislocations in a square region having a side length of 1 mm and spaced 5 mm apart in the central region is measured, the surface density of threading dislocations is 5000 cm -2 a value obtained by dividing the number of square regions that are equal to or larger than the square region size by the total number of square regions is 30% or less.

2. The surface density of the threading dislocations is 5000 cm -2 2 . The silicon carbide substrate according to claim 1 , wherein a value obtained by dividing the number of square regions that are equal to or larger than this number by the total number of square regions is 10% or less.

3. The surface density of the threading dislocations is 5000 cm -2 3 . The silicon carbide substrate according to claim 2 , wherein a value obtained by dividing the number of square regions that are equal to or greater than this number by the total number of square regions is equal to or greater than 5%.

4. A silicon carbide substrate having a main surface, the polytype of the silicon carbide substrate being 4H, the main surface being a {0001} plane or a plane inclined with respect to the {0001} plane at an off angle of 1° or less, the main surface being composed of an outer edge, a peripheral region within 5 mm from the outer edge, and a central region surrounded by the peripheral region, and the average electrical resistivity of the central region being 1×10 10 and when the areal density of threading dislocations is measured in square regions in the central region having sides each having a length of 1 mm and spaced at intervals of 5 mm, the number of square regions having an areal density that is at least twice the average areal density of threading dislocations divided by the number of all square regions is 20% or less.

5. The silicon carbide substrate according to claim 4, wherein, when the areal density of threading dislocations in square regions in the central region, each of which has a side length of 1 mm and is spaced 5 mm apart, the number of square regions having an areal density at least twice the average value of the areal density of threading dislocations divided by the number of all square regions is 10% or less.

6. The average surface density of the threading dislocations is 1500 cm -2 More than 3500cm -2 The silicon carbide substrate according to claim 4 or 5, wherein:

7. The silicon carbide substrate according to claim 1, wherein the maximum diameter of said main surface is 4 inches.

8. The silicon carbide substrate according to claim 1, wherein the maximum diameter of the main surface is 6 inches.

9. The silicon carbide substrate according to claim 1, wherein the off angle is equal to or less than 0.5°.

10. The silicon carbide substrate according to claim 1, further comprising vanadium.

11. An epitaxial substrate comprising: a silicon carbide substrate according to any one of claims 1 to 10; and a nitride epitaxial layer on the silicon carbide substrate.

12. A method for manufacturing a semiconductor device, comprising the steps of: preparing a silicon carbide substrate according to any one of claims 1 to 10; forming a nitride epitaxial layer on the silicon carbide substrate; and forming an electrode on the nitride epitaxial layer.

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