Signal generation circuit, drive circuit, power conversion device, and vehicle

Abstract

A signal generation circuit according to one embodiment comprises: a delay signal generation unit configured so as to generate at least one delay pulse signal using an input pulse signal common to a first switching element and a second switching element; and a logic synthesis unit configured so as to generate a first control pulse signal and a second control pulse signal for the first switching element and the second switching element by performing different logic synthesis on two signal sets of a plurality of signal sets specified by the at least one delay pulse signal and the input pulse signal. The first control pulse signal is different from the input pulse signal, and the second control pulse signal is different from the input pulse signal and the first control pulse signal.

Description

Signal generating circuit, drive circuit, power conversion device and vehicle

[0001] The present invention relates to a signal generating circuit, a drive circuit, a power conversion device, and a vehicle.

[0002] Patent Document 1 discloses a technology using a parallel circuit of a first switching element that is a Si-IGBT and a second switching element that is a SiC-MOSFET in a switch section that constitutes an inverter (see Patent Document 1). The first switching element and the second switching element are driven by a first switching control signal (gate drive signal) and a second switching control signal (gate drive signal) that are different from each other. In order to generate the different first switching control signal (gate drive signal) and second switching control signal (gate drive signal), an inverter control device equipped with a microcomputer needs to generate and output different switching control source signals for the first switching control signal and the second switching control signal.

[0003] Patent No. 6468363

[0004] [Summary] A signal generation circuit according to the present disclosure includes a delay signal generation unit configured to generate at least one delay pulse signal using a common input pulse signal for a first switching element and a second switching element that have different transition times between an ON state, which is a conductive state, and an OFF state, which is a non-conductive state; and a logic synthesis unit configured to generate a first gate signal for the first switching element and a second gate signal for the second switching element by performing different logic synthesis on two signal sets out of a plurality of signal sets defined by the at least one delay pulse signal and the input pulse signal, wherein the first gate signal is different from the input pulse signal and the second control pulse signal is different from the input pulse signal and the first gate signal.

[0005] FIG. 1 is a schematic diagram of a system configuration of a power conversion device employing a signal generating circuit according to a first embodiment. FIG. 2 is a circuit diagram illustrating a schematic configuration of an example of a switch unit and a drive circuit. FIG. 3 is a time chart of various signals according to the first embodiment. FIG. 4 is a circuit diagram of a circuit used in a double pulse test in Experimental Example 1. FIG. 5 is a graph showing measurement results of gate voltages corresponding to a first gate signal and a second gate signal at turn-on in Experimental Example 1. FIG. 6 is a graph showing measurement results of device currents flowing through the first switching element and the second switching element at turn-on in Experimental Example 1. FIG. 7 is a graph showing measurement results of gate voltages corresponding to a first gate signal and a second gate signal at turn-off in Experimental Example 1. FIG. 8 is a graph showing measurement results of device currents flowing through the first switching element and the second switching element at turn-off in Experimental Example 1. FIG. 9 is a circuit diagram of a drive circuit including a signal generating circuit according to a second embodiment. FIG. 10 is a time chart of various signals in the second embodiment. FIG. 11 is a circuit diagram of a circuit used in a double pulse test in Experimental Example 2. FIG. 12 is a graph showing measurement results of gate voltages corresponding to a first gate signal and a second gate signal at turn-on in Experimental Example 2. FIG. 13 is a graph showing measurement results of device currents flowing through the first switching element and the second switching element at turn-on in Experimental Example 2. FIG. 14 is a graph showing measurement results of gate voltages corresponding to a first gate signal and a second gate signal at turn-off in Experimental Example 2. FIG. 15 is a graph showing measurement results of device currents flowing through the first switching element and the second switching element at turn-off in Experimental Example 2. FIG. 16 is a circuit diagram of a drive circuit including a signal generation circuit according to a third embodiment. FIG. 17 is a time chart of various signals in the third embodiment. FIG. 18 is a circuit diagram for explaining a fourth embodiment. FIG. 19 is a circuit diagram for explaining a fifth embodiment.Fig. 20 is a circuit diagram for explaining a sixth embodiment. Fig. 21 is a diagram for explaining a modified example of the sixth embodiment. Fig. 22 is a circuit diagram for explaining a seventh embodiment. Fig. 23 is a diagram showing an example of the configuration of a vehicle on which a power conversion device is mounted. Fig. 24 is a schematic diagram of an example of a switch unit. Fig. 25 is a schematic diagram of another example of a switch unit.

[0006] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The following description of the preferred embodiments of the present disclosure will be given with reference to the accompanying drawings. In the description of the drawings, the same elements are designated by the same reference numerals, and redundant description will be omitted.

[0007] First Embodiment Fig. 1 is a schematic diagram of a system configuration of a power conversion device to which a signal generation circuit according to a first embodiment is applied. The power conversion device 1 is a device that converts power between direct current and alternating current. The power conversion device 1 is mounted on a vehicle such as a hybrid vehicle or an electric vehicle. The alternating current may be single-phase or multi-phase. Unless otherwise specified below, a configuration will be described in which the power conversion device 1 is mounted on the vehicle and the alternating current is three-phase.

[0008] 1, the power conversion device 1 is disposed between a motor (rotating electric machine) 2 driven by AC and a DC power supply unit 3. The power conversion device 1 is configured to convert DC power from the DC power supply unit 3 into AC power to drive the motor 2. The power conversion device 1 is configured to convert AC power generated in the motor 2 into DC power for regeneration.

[0009] The DC power supply unit 3 includes a high-voltage DC power supply. An example of the rated voltage of the DC power supply unit 3 is 300 V or more and 900 V or less. The DC power supply unit 3 may be configured to be capable of storing electricity. Examples of the DC power supply unit 3 include a secondary battery and an electric double layer capacitor. Examples of the secondary battery include a nickel-metal hydride secondary battery and a lithium-ion secondary battery. The DC power supply unit 3 may be a battery that combines a secondary battery and an electric double layer capacitor. The DC power supply unit 3 may be an all-solid-state battery. The DC power supply unit 3 may include a DC / DC converter.

[0010] The motor 2 functions as a driving power source for a vehicle such as a hybrid vehicle, an electric vehicle, etc. The motor 2 functions as an electric motor and also as a generator.

[0011] The power conversion device 1 includes an inverter circuit 4 and a plurality of drive circuits 5 .

[0012] The inverter circuit 4 has a leg 41u, a leg 41v, and a leg 41w. The leg 41u is a U-phase leg, the leg 41v is a V-phase leg, and the leg 41w is a W-phase leg. The three legs 41u, 41v, and 41w are connected in parallel between a high-potential wiring 6a electrically connected to the positive electrode of the DC power supply unit 3 and a low-potential wiring 6b electrically connected to the negative electrode of the DC power supply unit 3.

[0013] Each of the leg 41u, the leg 41v, and the leg 41w has an upper arm switch unit 20 and a lower arm switch unit 20. Therefore, the inverter circuit 4 shown in Fig. 1 has six switch units 20. The two switch units 20 included in each of the leg 41u, the leg 41v, and the leg 41w are configured to be switchable between an ON state, which is a conductive state, and an OFF state, which is a non-conductive state.

[0014] The two switch sections 20 included in each of the legs 41u, 41v, and 41w are connected in series between the high-potential wiring 6a and the low-potential wiring 6b.

[0015] A node (connection point) 42u between the switch unit 20 of the upper arm and the switch unit 20 of the lower arm of the leg 41u is an AC input / output point, and is electrically connected to a U-phase electrode of the motor 2. A node (connection point) 42v between the switch unit 20 of the upper arm and the switch unit 20 of the lower arm of the leg 41v is an AC input / output point, and is electrically connected to a V-phase electrode of the motor 2. A node (connection point) 42w between the switch unit 20 of the upper arm and the switch unit 20 of the lower arm of the leg 41w is an AC input / output point, and is electrically connected to a W-phase electrode of the motor 2.

[0016] The power conversion device 1 may include a capacitor 43 for smoothing the DC voltage supplied from the DC power supply unit 3 to the inverter circuit 4. The capacitor 43 is connected in parallel to the legs 41u, 41v, and 41w between the high-potential wiring 6a and the low-potential wiring 6b.

[0017] The plurality of drive circuits 5 are provided corresponding to the two switch units 20 included in each of the legs 41u, 41v, and 41w. Therefore, in the configuration shown in Fig. 1, the power conversion device 1 has six drive circuits 5. The six drive circuits 5 drive the switch units 20 based on input pulse signals corresponding to each drive circuit 5 from an external control device 7. An example of the external control device 7 is an ECU (Electronic Control Unit) installed in an automobile.

[0018] In the power conversion device 1, the six switch units 20 have the same configuration, and the six drive circuits 5 also have the same configuration. Therefore, the switch units 20 and the drive circuits 5 will be described using one set of switch unit 20 and drive circuit 5 as an example.

[0019] FIG. 2 is a circuit diagram for explaining a schematic configuration of an example of the switch section 20 and the drive circuit 5. As shown in FIG.

[0020] [Switch Section] The switch section 20 has a first switching element 21 and a second switching element 22. The first switching element 21 and the second switching element 22 are connected in parallel between a node 20a and a node 20b of the switch section 20.

[0021] When the switch section 20 constitutes the upper arm, the node 20a of the switch section 20 of the upper arm is electrically connected to the high-potential wiring 6a, and the node 20b of the switch section 20 of the upper arm is electrically connected to the node 20a of the switch section 20 of the lower arm.

[0022] When the switch section 20 constitutes the lower arm, the node 20a of the switch section 20 of the lower arm is electrically connected to the node 20b of the switch section 20 of the upper arm, and the node 20b of the switch section 20 of the lower arm is electrically connected to the low-potential wiring 6b.

[0023] Each of the first switching element 21 and the second switching element 22 is a semiconductor switching element that can be switched between an ON state, which is a conductive state, and an OFF state, which is a non-conductive state.

[0024] Examples of semiconductor switching elements used for the first switching element 21 and the second switching element 22 include bipolar transistors and unipolar transistors. An example of a bipolar transistor is an insulated gate bipolar transistor (IGBT). An example of a unipolar transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET). The semiconductor switching elements may be power semiconductors. Examples of semiconductor materials for the semiconductor switching elements include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).

[0025] Each of the first switching element 21 and the second switching element 22 may be a semiconductor switching element obtained by combining transistor types and semiconductor materials, for example, the first switching element 21 and the second switching element 22 may be a Si-based IGBT, a Si-based MOSFET, a SiC-based IGBT, or a SiC-based MOSFET.

[0026] The first switching element 21 and the second switching element 22 constituting the switch unit 20 are combined to have different characteristics. In one embodiment, the first switching element 21 and the second switching element 22 have different transition times between the ON state and the OFF state.

[0027] In the following description, unless otherwise specified, the first switching element 21 is a Si-based IGBT (hereinafter referred to as an "Si-IGBT"), and the second switching element 22 is a SiC-based MOSFET (hereinafter referred to as an "SiC-MOSFET"). In this case, the second switching element 22 is a switching element whose transition time between the on state and the off state is shorter than that of the first switching element 21. In other words, the second switching element 22 is a switching element capable of faster switching than the first switching element 21.

[0028] The first switching element 21 may be a bare chip of a Si-IGBT or an element in which the bare chip is housed in a package, and the second switching element 22 may be a bare chip of a SiC-MOSFET or an element in which the bare chip is housed in a package.

[0029] The first switching element 21 has a first main terminal, a second main terminal, and a control terminal. If the first switching element 21 is a Si-IGBT, the first main terminal, the second main terminal, and the control terminal correspond to a collector, an emitter, and a gate. The second switching element 22 has a first main terminal, a second main terminal, and a control terminal. If the second switching element 22 is a SiC-MOSFET, the first main terminal, the second main terminal, and the control terminal correspond to a drain, a source, and a gate.

[0030] As described above, unless otherwise specified, the case will be described in which the first switching element 21 is a Si-IGBT and the second switching element 22 is a SiC-MOSFET, and therefore the first main terminal, second main terminal, and control terminal of the first switching element 21 will be referred to as the collector, emitter, and gate, and the first main terminal, second main terminal, and control terminal of the second switching element 22 will be referred to as the drain, source, and gate.

[0031] The collector of the first switching element 21 and the drain of the second switching element 22 are electrically connected to a node 20a, while the emitter of the first switching element 21 and the source of the second switching element 22 are electrically connected to a node 20b.

[0032] The gate of the first switching element 21 and the gate of the second switching element 22 are electrically connected to the drive circuit 5 .

[0033] The switch unit 20 may include a freewheeling diode 23. The freewheeling diode 23 is connected in anti-parallel to the second switching element 22. Specifically, the cathode of the freewheeling diode 23 is electrically connected to the drain (or node 20a) of the second switching element 22. The anode of the freewheeling diode 23 is electrically connected to the source (or node 20b) of the second switching element 22. A parasitic diode in a SiC-MOSFET may be used as the freewheeling diode 23.

[0034] [Drive Circuit] The drive circuit 5 is a circuit that outputs a first gate signal (first drive pulse signal) for driving the first switching element 21 and a second gate signal (second drive pulse signal) for driving the second switching element 22, based on a common input pulse signal for the first switching element 21 and the second switching element 22. In Fig. 2, the external control device 7 that generates and outputs the input pulse signal is schematically illustrated as a pulse signal source.

[0035] The drive circuit 5 has an input terminal 51 to which an input pulse signal is input, a first output terminal 52 to which a first gate signal is output, and a second output terminal 53 to which a second gate signal is output. The input terminal 51 is electrically connected to the external control device 7. The first output terminal 52 is electrically connected to the gate of the first switching element 21. The second output terminal 53 is electrically connected to the gate of the second switching element 22.

[0036] The drive circuit 5 includes a signal generation circuit 100, a first insulated gate driver IC (first driver) 54a, a first push-pull circuit 55a, a second insulated gate driver IC (second driver) 54b, and a second push-pull circuit 55b. The first insulated gate driver IC 54a and the second insulated gate driver IC 54b are referred to as the first GDIC 54a and the second GDIC 54b.

[0037] The signal generating circuit 100 is a circuit that generates a first control pulse signal for the first switching element 21 and a second control pulse signal for the second switching element 22 using an input pulse signal input to an input terminal 51. The first control pulse signal and the second control pulse signal are different signals that are generated from a common input pulse signal.

[0038] The first GDIC 54a is connected between the first power supply potential line 61 and ground. An example of the first power supply potential supplied to the first power supply potential line 61 is 5 V. The first GDIC 54a outputs a first output pulse signal based on the first control pulse signal. The first output pulse signal is a signal obtained by amplifying the first control pulse signal. In this embodiment, the first output pulse signal is a signal that drives the first push-pull circuit 55a.

[0039] The first GDIC 54a has a function of transmitting signals while isolating the signal generating circuit 100 from the first push-pull circuit 55a and a function of amplifying the first control pulse signal. For example, the first GDIC 54a includes an isolated signal transmission element and an amplifier. Examples of the isolated signal transmission element include a photocoupler, a magnetic coupler using a transformer, or a capacitive coupler using a capacitor. The first GDIC 54a may also include protection circuits such as an undervoltage protection circuit and an overvoltage protection circuit.

[0040] The first push-pull circuit 55a has a first transistor Tr1 and a second transistor Tr2 connected in series between the second power supply potential line 62 and the ground. The first push-pull circuit 55a is a totem-pole output stage in which the first transistor Tr1 and the second transistor Tr2 are connected in series.

[0041] In this embodiment, the first transistor Tr1 is an npn transistor, and the second transistor Tr2 is a pnp transistor. The collector of the first transistor Tr1 is connected to a second power supply potential line 62. An example of the second power supply potential supplied to the second power supply potential line 62 is +18 V. The emitter of the first transistor Tr1 is connected to the emitter of the second transistor Tr2. The collector of the second transistor Tr2 is connected to ground. The gates of the first transistor Tr1 and the second transistor Tr2 are electrically connected to the first GDIC 54a, and a first output pulse signal is input from the first GDIC 54a.

[0042] A node between the emitter of the first transistor Tr1 and the emitter of the second transistor Tr2 is electrically connected to the first output terminal 52 via a first gate resistor 56a. That is, the first gate resistor 56a is disposed on the signal path between the node between the first transistor Tr1 and the second transistor Tr2 connected in series and the first output terminal 52. An example of the resistance value of the first gate resistor 56a is 1 Ω or more and 100 Ω or less.

[0043] In the first push-pull circuit 55a configured as described above, the first transistor Tr1 and the second transistor Tr2 are driven in response to the first output pulse signal from the first GDIC 54a. As a result, a first gate signal is obtained by amplifying the first output pulse signal. The first gate signal is input to the first output terminal 52 via the first gate resistor 56a. Since the first output terminal 52 is electrically connected to the control terminal of the first switching element 21, the first gate signal is input to the gate (control terminal) of the first switching element 21.

[0044] The second GDIC 54b is connected between the first power supply potential line 61 and ground. The second GDIC 54b outputs a second output pulse signal based on the second control pulse signal. The second output pulse signal is a signal obtained by amplifying the second control pulse signal. In this embodiment, the second output pulse signal is a signal that drives the second push-pull circuit 55b.

[0045] The second GDIC 54b has the function of transmitting signals while isolating the signal generating circuit 100 and the second push-pull circuit 55b and the function of amplifying the second control pulse signal. For example, the second GDIC 54b includes an isolated signal transmission element and an amplifier. Examples of the isolated signal transmission element include a photocoupler, a magnetic coupler using a transformer, or a capacitive coupler using a capacitor. The second GDIC 54b may include protection circuits such as an undervoltage protection circuit and an overvoltage protection circuit. Unless otherwise specified, the second GDIC 54b may be the same IC as the first GDIC 54a. However, the second GDIC 54b may be a different IC from the first GDIC 54a.

[0046] The second push-pull circuit 55b has a first transistor Tr1 and a second transistor Tr2 connected in series between the second power supply line 62 and ground. The second push-pull circuit 55b is a totem-pole output stage in which the first transistor Tr1 and the second transistor Tr2 are connected in series. In this embodiment, the first transistor Tr1 and the second transistor Tr2 of the second push-pull circuit 55b are the same as those of the first push-pull circuit 55a. That is, the first transistor Tr1 is an npn transistor, and the second transistor Tr2 is a pnp transistor. The collector of the first transistor Tr1 is connected to the second power supply line 62. The emitter of the first transistor Tr1 is connected to the emitter of the second transistor Tr2. The collector of the second transistor Tr2 is connected to ground. The gates of the first transistor Tr1 and the second transistor Tr2 are electrically connected to the second GDIC 54b, and receive the second output pulse signal from the second GDIC 54b.

[0047] A node between the emitter of the first transistor Tr1 and the emitter of the second transistor Tr2 is electrically connected to the second output terminal 53 via the second gate resistor 56b. That is, the second gate resistor 56b is disposed on the signal path between the node between the first transistor Tr1 and the second transistor Tr2 connected in series and the second output terminal 53. An example of the resistance value of the second gate resistor 56b is the same as that of the first gate resistor 56a. The resistance value of the second gate resistor 56b may be the same as or different from that of the first gate resistor 56a.

[0048] In the second push-pull circuit 55b configured as described above, the first transistor Tr1 and the second transistor Tr2 are driven in response to the second output pulse signal from the second GDIC 54b. As a result, a second gate signal is obtained by amplifying the second output pulse signal. The second gate signal is input to the second output terminal 53 via the second gate resistor 56b. Since the second output terminal 53 is electrically connected to the control terminal of the second switching element 22, the second gate signal is input to the gate (control terminal) of the second switching element 22.

[0049] [Signal Generation Circuit] Next, a detailed description will be given of the signal generation circuit 100 according to an embodiment. The signal generation circuit 100 includes a delay signal generation section 10 and a logic synthesis section 16.

[0050] The delay signal generating section 10 generates a delay pulse signal that is delayed with respect to an input pulse signal. The delay signal generating section 10 has a delay circuit 11 that generates the delay pulse signal.

[0051] The delay circuit 11 is configured to be able to set a resistance value for delaying the rising edge of the input pulse signal and a resistance value for delaying the falling edge of the input pulse signal. The delay circuit 11 has a parallel circuit (resistance unit) 12 in which a first series circuit 13 and a second series circuit 14 are connected in parallel, and a capacitor 15.

[0052] The parallel circuit 12 has a node (first end) 12a and a node (second end) 12b. The node 12a is electrically connected to the input terminal 51. An input pulse signal is input to the node 12a from the external control device 7. The node 12b is electrically connected to the logic synthesis unit 16.

[0053] The first series circuit 13 is configured by connecting a first diode 131 and a first resistor 132 in series. The anode of the first diode 131 is connected to the node 12a. The first resistor 132 is connected between the cathode of the first diode 131 and the node 12b. An example of the forward voltage of the first diode 131 is 0.5 V or more and 1.0 V or less. An example of the resistance value of the first resistor 132 is 10 Ω or more and 10 kΩ or less.

[0054] The second series circuit 14 is configured by connecting a second diode 141 and a second resistor 142 in series. The anode of the second diode 141 is connected to the node 12b. The second resistor 142 is connected between the cathode of the second diode 141 and the node 12a. Examples of the forward voltage of the second diode 141 are the same as those of the first diode 131. The second diode 141 may be the same as or different from the first diode 131. Examples of the resistance value of the second resistor 142 are the same as those of the first resistor 132. The second resistor 142 may be the same as or different from the first resistor 132.

[0055] The capacitor 15 is connected between the node 12b and ground. The capacitance of the capacitor 15 is, for example, 10 pF or more and 10 nF or less.

[0056] In the delay circuit 11, the first series circuit 13 functions as a signal path that delays the rising edge of the input pulse signal, and a delay circuit that delays the rising edge of the input pulse signal is configured by the first series circuit 13 (specifically, the first resistor 132) and the capacitor 15. The delay time for the rising edge is determined by the resistance value of the first resistor 132 and the capacitance of the capacitor 15.

[0057] In the delay circuit 11, the second series circuit 14 functions as a signal path that delays the falling edge of the input pulse signal, and the second series circuit 14 and the capacitor 15 form a delay circuit that delays the falling edge of the input pulse signal. The delay time for the falling edge is determined by the resistance value of the second resistor 142 and the capacitance of the capacitor 15.

[0058] The logic synthesis unit 16 includes an AND circuit 161 for generating a first control pulse signal and an OR circuit 162 for generating a second control pulse signal.

[0059] The AND circuit 161 is electrically connected to the input terminal 51 and the delay signal generating unit 10. A signal set of an input pulse signal and a first delay pulse signal is input to the AND circuit 161. The AND circuit 161 is a logical product circuit that outputs a first control pulse signal by performing a logical product of the input pulse signal and the first delay pulse signal. The AND circuit 161 is electrically connected to the first GDIC 54a, and the first control pulse signal output from the AND circuit 161 is input to the first GDIC 54a.

[0060] The OR circuit 162 is electrically connected to the input terminal 51 and the delay signal generating unit 10. A signal set of an input pulse signal and a first delay pulse signal is input to the OR circuit 162. The OR circuit 162 is a logical OR circuit that performs a logical OR on the input pulse signal and the second delay pulse signal and outputs a second control pulse signal. The OR circuit 162 is electrically connected to the second GDIC 54b, and the second control pulse signal output from the OR circuit 162 is input to the second GDIC 54b.

[0061] 3 is a time chart of various signals in the first embodiment. In FIG. 3, the input pulse signal, the delay pulse signal, the first gate signal, the second gate signal, and the current of the main circuit (hereinafter referred to as "main circuit current") are respectively represented as an input pulse signal S1, a delay pulse signal S2, a first control pulse signal S3, a second control pulse signal S4, and a main circuit current I Ｍ The main circuit current I Ｍ is the current flowing through the switch unit 20. Specifically, the main circuit current IＭ is the current flowing between node 20a and node 20b.

[0062] In FIG. 3, the AND circuit 161 and the OR circuit 162 have threshold voltages (threshold signal levels) for regarding an input signal as High and Low, respectively. ＩＨ and V ＩＬ In the AND circuit 161 and the OR circuit 162, when the input signal is V ＩＨ Once it exceeds V ＩＬ is considered to be in a High state unless the input signal falls below V ＩＬ Once it falls below V ＩＨ It is considered to be in a low state unless it exceeds ＩＨ An example of V is 3V, ＩＬ An example is 2V.

[0063] An example of the operation of the drive circuit 5 and the switch section 20 will be described with reference to FIGS.

[0064] 3, the input pulse signal S1 has a pulse that rises at time t1 and falls at time t3. When the input pulse signal S1 is input to the delay signal generating unit 10, the delay signal generating unit 10 generates a delay pulse signal S2.

[0065] The delay signal generating unit 10 includes a parallel circuit 12 and a capacitor 15. The parallel circuit 12 includes a first series circuit 13 that contributes to delaying the rising edge and a second series circuit 14 that contributes to delaying the falling edge. Therefore, as shown in FIG. 3 , the delay pulse signal S2 rises at time t2, which is a delay time td1 after time t1, and falls at time t4, which is a delay time td2 after time t3.

[0066] "Rising after a delay time from a certain time (referred to as "time α")" means that the signal level gradually increases from time α and exceeds a certain threshold level after the delay time. "Falling after a delay time from a certain time (referred to as "time β")" means that the signal level gradually decreases from time β and falls below a certain threshold level after the delay time.

[0067] In the example shown in FIG. 3, the threshold level that determines the delay time of the rising edge is V, which is the same as the threshold voltage for regarding the signal input to the AND circuit 161 and the OR circuit 162 as High. ＩＨ The threshold level that determines the delay time of the falling edge is V, which is the same as the threshold voltage for regarding the signal input to the AND circuit 161 and the OR circuit 162 as Low. ＩＬ is.

[0068] The delayed pulse signal S2 generated by the delayed signal generating unit 10 is input to the logic synthesis unit 16. The logic synthesis unit 16 has an AND circuit 161 and an OR circuit 162. The AND circuit 161 performs a logical AND on the signal set of the input pulse signal S1 and the delayed pulse signal S2 to generate a first control pulse signal S3. The OR circuit 162 performs a logical OR on the signal set of the input pulse signal S1 and the delayed pulse signal S2 to generate a second control pulse signal S4.

[0069] In the example shown in FIG. 3, the signal level (voltage) of the input pulse signal S1 is equal to or exceeds the threshold voltage V ＩＨ At time t3, the threshold voltage V ＩＬ Therefore, the input pulse signal S1 input to the AND circuit 161 and the OR circuit 162 is in a High state from time t1 to time t3, and thereafter, the input pulse signal S1 again falls below the threshold voltage V ＩＨ The signal level (voltage) of the delayed pulse signal S2 is processed as a signal that is maintained in a low state until it exceeds the threshold voltage V at time t2. ＩＨ At time t4, the threshold voltage V ＩＬ Therefore, the delayed pulse signal S2 input to the AND circuit 161 and the OR circuit 162 is in a High state from time t2 to time t4, and thereafter, the delayed pulse signal S2 again falls below the threshold voltage V ＩＨ is processed as a signal that is maintained in the Low state until the signal exceeds the threshold.

[0070] The first control pulse signal S3 is generated by the logical AND of the input pulse signal S1 and the delayed pulse signal S2. Because of the relationship between the High and Low states of the input pulse signal S1 and the delayed pulse signal S2 in the AND circuit 161, the first control pulse signal S3 is a pulse signal that rises at time t2 and falls at time t3. The second control pulse signal S4 is generated by the logical OR of the input pulse signal S1 and the delayed pulse signal S2. Because of the relationship between the High and Low states of the input pulse signal S1 and the delayed pulse signal S2 in the OR circuit 162, the second control pulse signal S4 is a pulse signal that rises at time t1 and falls at time t4.

[0071] In this way, the signal generating circuit 100 can generate the first control pulse signal S3 and the second control pulse signal S4 with different delay states based on the same input pulse signal S1.

[0072] In the drive circuit 5, the first control pulse signal S3 is input to the first GDIC 54a and output as a first output pulse signal. The first output pulse signal output from the first GDIC 54a is input to the first push-pull circuit 55a and output as a first gate signal. The first gate signal is input to the first output terminal 52 via the first gate resistor 56a. The first output terminal 52 is electrically connected to the gate of the first switching element 21, and therefore the first switching element 21 is driven by the first gate signal.

[0073] The first output pulse signal is an amplified pulse signal of the first control pulse signal, and therefore has a waveform similar to that of the first control pulse signal. The first gate signal is an amplified pulse signal of the first output pulse signal, and therefore has a waveform similar to that of the first output pulse signal. Therefore, the first gate signal has a waveform similar to that of the first control pulse signal S3.

[0074] In the drive circuit 5, the second control pulse signal S4 is input to the second GDIC 54b, and is output as a second output pulse signal. The second output pulse signal output from the second GDIC 54b is input to the second push-pull circuit 55b, and is output as a second gate signal. The second gate signal is input to the second output terminal 53 via the second gate resistor 56b. The second output terminal 53 is electrically connected to the gate of the second switching element 22, and therefore the second switching element 22 is driven by the second gate signal.

[0075] The second output pulse signal has a waveform similar to that of the second control pulse signal S4 because the second control pulse signal S4 is an amplified pulse signal. The second gate signal has a waveform similar to that of the second output pulse signal because the second output pulse signal is an amplified pulse signal. Therefore, the second gate signal has a waveform similar to that of the second control pulse signal S4.

[0076] The first switching element 21 is driven by a first gate signal having a waveform similar to that of the first control pulse signal S3, so it is turned on at time t2 and turned off at time t3. The second switching element 22 is driven by a second gate signal having a waveform similar to that of the second control pulse signal S4, so it is turned on at time t1 and turned off at time t4.

[0077] The timing at which the first switching element 21 and the second switching element 22 turn on is adjusted by the delay time td1. When the resistance value of the first resistor 132 is R1 [Ω] and the capacitance of the capacitor 15 is C [F], the delay time td1 [s] is expressed as the product of the resistance value R1 [Ω] and the capacitance C [F]. Therefore, by adjusting the resistance value R1 and the capacitance C, it is possible to adjust the timing at which the first switching element 21 and the second switching element 22 turn on.

[0078] The timing at which the first switching element 21 and the second switching element 22 turn off is adjusted by the delay time td2. When the resistance value of the second resistor 142 is R2 [Ω], the delay time td2 [s] is expressed as the product of the resistance value R2 [Ω] and the capacitance C [F]. Therefore, by adjusting the resistance value R2 and the capacitance C, it is possible to adjust the timing at which the first switching element 21 and the second switching element 22 turn off.

[0079] The switch unit 20 is configured by connecting a first switching element 21 and a second switching element 22 in parallel. Therefore, when either the first switching element 21 or the second switching element 22 is in the ON state, there is conduction between the node 20a and the node 20b. That is, when either the first switching element 21 or the second switching element 22 is in the ON state, the switch unit 20 is in the ON state. On the other hand, when both the first switching element 21 and the second switching element 22 are in the OFF state, there is no conduction between the node 20a and the node 20b. That is, when both the first switching element 21 and the second switching element 22 are in the OFF state, the switch unit 20 is in the OFF state. Therefore, the switch unit 20 is in the ON state from time t1 to time t4, and as shown in FIG. 3 , the main circuit current I Ｍ is playing.

[0080] As can be seen from the time chart of various signals shown in Fig. 3, the switch unit 20 is driven by the drive circuit 5 having the signal generation circuit 100, and the second switching element 22, which is a SiC-MOSFET, performs the turn-on and turn-off functions of the switch unit 20. Since the transition time between the on state and the off state of a SiC-MOSFET is shorter than that of a Si-IGBT, the transition time for turn-on and turn-off can also be shortened in the switch unit 20. In other words, the switch unit 20 can achieve high-speed switching similar to that of a SiC-MOSFET.

[0081] As can be seen from the time chart of various signals shown in Figure 3, when the switch unit 20 is driven by the drive circuit 5 including the signal generation circuit 100, the first switching element 21, which is a Si-IGBT, is also in the on state from time t2 to time t3. Si-IGBTs have lower conduction loss at high currents than SiC-MOSFETs and are more resistant to overcurrents. Therefore, when the switch unit 20 is turned on and more current begins to flow, the current flows mainly through the first switching element 21, improving the switch unit 20's resistance to overcurrents.

[0082] The switch unit 20 of the power conversion device 1 is configured by connecting a first switching element 21 and a second switching element 22, which have different characteristics, in parallel. Therefore, the configuration of the drive circuit 5 makes it possible to drive the first switching element 21 and the second switching element 22 so as to effectively utilize the respective characteristics of the first switching element 21 and the second switching element 22. Therefore, it is possible to realize a switch unit 20 with better characteristics than when the switch unit 20 is configured with only either the first switching element 21 or the second switching element 22. As a result, the characteristics of the power conversion device 1 including the switch unit 20 are also improved.

[0083] When the switch unit 20 has a first switching element 21 and a second switching element 22 with different characteristics, it is possible to generate different first and second gate signals for the first switching element 21 and the second switching element 22 based on different input pulse signals. In this case, a drive circuit that generates a first gate signal based on an input pulse signal corresponding to the first switching element 21 and a drive circuit that generates a second gate signal based on an input pulse signal corresponding to the second switching element 22 are required. In other words, two drive circuits are required for one switch unit 20. As a result, when the power conversion device 1 has six switch units 20 as shown in FIG. 1 , the number of drive circuits included in the power conversion device 1 is 12. When different first and second gate signals are generated for the first switching element 21 and the second switching element 22 based on different input pulse signals, the external control device 7 is configured to generate different input pulse signals for the switch unit 20 including the first switching element 21 and the second switching element 22. Therefore, for example, an existing external control device 7 cannot be used when the switch section 20 is configured with either the first switching element 21 or the second switching element 22.

[0084] In contrast, the signal generation circuit 100 can generate a first control pulse signal and a second control pulse signal from a common input pulse signal for the first switching element 21 and the second switching element 22. Therefore, the drive circuit 5 including the signal generation circuit 100 can output a first gate signal and a second gate signal for driving the first switching element 21 and the second switching element 22. Therefore, only one drive circuit 5 is required for the switch unit 20. As a result, as shown in FIG. 1 , when the power conversion device 1 has six switch units 20, the number of drive circuits 5 included in the power conversion device 1 is six. Therefore, with a drive circuit 5 including the signal generation circuit 100, the number of drive circuits 5 included in the power conversion device 1 can be reduced compared to when different input pulse signals are used for the first switching element 21 and the second switching element 22. Because the number of drive circuits 5 is reduced, the manufacturing cost of the power conversion device 1 can be reduced.

[0085] Because the signal generating circuit 100 generates the first control pulse signal and the second control pulse signal for the first switching element 21 and the second switching element 22 from a common input pulse signal, it is possible to use an existing external control device 7. Therefore, the switch unit 20 can be easily applied to an existing external control device 7 and a device equipped with the external control device 7 (e.g., a hybrid vehicle, an electric vehicle, etc.). For example, when the switch unit of a power conversion device (or inverter) mounted on a hybrid vehicle, an electric vehicle, etc. is replaced with the switch unit 20, the signal generating circuit 100 can be set in front of an existing GDIC, thereby driving the switch unit 20 without changing the control program for the power conversion device in the ECU.

[0086] The Si-IGBT is a lower-cost device than the SiC-MOSFET, and therefore, compared to a case where all of the switching elements of the switch unit 20 are configured with SiC-MOSFETs, it is possible to reduce the manufacturing costs of the switch unit 20 and the power conversion device 1 including the switch unit 20 while maintaining the characteristics of the SiC-MOSFET.

[0087] The delay circuit 11 includes a parallel circuit 12 and a capacitor 15. The parallel circuit 12 is configured by connecting in parallel a first series circuit 13 that contributes to delaying the rising edge of the input pulse signal and a second series circuit 14 that contributes to delaying the falling edge of the input pulse signal. Therefore, the delay time td1 for the rising edge of the input pulse signal and the delay time td2 for the falling edge of the input pulse signal can be adjusted separately.

[0088] Specifically, as described above, the delay time td1 [s] is expressed as the product of the resistance value R1 [Ω] of the first resistor 132 and the capacitance C [F] of the capacitor 15, and the delay time td2 [s] is expressed as the product of the resistance value R2 [Ω] of the second resistor 142 and the capacitance C [F] of the capacitor 15. In the equations for calculating the delay times td1 and td2, the capacitance C [F] of the capacitor 15 is common, so the delay times td1 and td2 can be adjusted by adjusting the resistance value R1 [Ω] of the first resistor 132 and the resistance value R2 [Ω] of the second resistor 142.

[0089] Next, Experimental Example 1 relating to the signal generating circuit 100 will be described. In Experimental Example 1, a double pulse test was carried out. FIG. 4 is a circuit diagram of the circuit used in the double pulse test used in Experimental Example 1. As shown in FIG. 4, the double pulse test circuit used in Experimental Example 1 had a drive circuit 5 and a switch unit 20. The configurations of the drive circuit 5 and the switch unit 20 were the same as those of the drive circuit 5 and the switch unit 20 described using FIG. 2.

[0090] The resistance value of the first resistor 132 in the first series circuit 13 was 820 Ω. The resistance value of the second resistor 142 in the second series circuit 14 was 820 Ω. The capacitance of the capacitor 15 was 1 nF. The same diode was used for the first and second diodes. The forward voltage of the first and second diodes was 0.6 V. The first GDIC 54a and the second GDIC 54b were the same insulated gate driver IC (BM6108FV-LB manufactured by ROHM Co., Ltd.). The first power supply potential on the first power supply potential line 61 to which the first GDIC 54a and the second GDIC 54b were electrically connected was 5 V. The second power supply potential on the second power supply potential line 62 to which the first push-pull circuit 55a and the second push-pull circuit 55b were electrically connected was 18 V. The resistance values ​​of the first gate resistor 56a and the second gate resistor 56b were 10 Ω. In the AND circuit 161 and the OR circuit 162, the threshold voltage V ＩＨ and V ＩＬ They were 3V and 2V respectively.

[0091] The first switching element 21 of the switch section 20 was a Si-IGBT (MG7213 manufactured by Rohm Co., Ltd.), and the second switching element 22 was a SiC-MOSFET (S4603 manufactured by Rohm Co., Ltd.).

[0092] A node 20a of the switch unit 20 was connected to a power supply potential line 63 via a coil (inductive load) 71. The power supply potential supplied to the power supply potential line 63 was 600 V, and the series circuit of the coil 71 and the switch unit 20 was configured so that a current of 60 A would flow when the switch unit 20 was in the on state. A freewheeling diode 72 was connected in anti-parallel to the coil 71. That is, the cathode of the freewheeling diode 72 was connected to the end of the coil 71 on the power supply potential line 63 side, and the anode of the freewheeling diode 72 was connected to the end of the coil 71 on the node 20a side. A node 20b of the switch unit 20 was connected to ground.

[0093] In Experimental Example 1, a double pulse test was performed using the double pulse test circuit shown in FIG. 4 . Specifically, an input pulse signal was input to the drive circuit 5 from the external control device 7 as a pulse signal source, and the first switching element 21 was driven by a first gate signal output from the first output terminal 52, and the second switching element 22 was driven by a second gate signal output from the second output terminal 53. In the double pulse test, gate voltages corresponding to the first gate signal and the second gate signal were measured, and device currents flowing through the first switching element 21 and the second switching element 22 were also measured. Specifically, the gate-emitter voltage of the first switching element 21 was measured as the gate voltage corresponding to the first gate signal. The gate-source voltage of the second switching element 22 was measured as the gate voltage corresponding to the second gate signal. The collector current was measured as the device current flowing through the first switching element 21. The drain current flowing through the second switching element 22 was measured as the device current flowing through the second switching element 22.

[0094] 5 is a graph showing measurement results of the gate voltage corresponding to the first gate signal and the gate voltage corresponding to the second gate signal at turn-on. The horizontal axis of FIG. 5 represents time (μs), and the vertical axis represents gate voltage (V). The solid line in FIG. 5 represents the first gate voltage for driving the first switching element 21, and the dashed line in FIG. 5 represents the second gate voltage for driving the second switching element 22.

[0095] 6 is a graph showing measurement results of the device current flowing through the first switching element 21 and the device current flowing through the second switching element 22 at turn-on. The horizontal axis of Fig. 6 represents time (μs), and the vertical axis represents the device current (A). The solid line in the graph represents the device current flowing through the first switching element 21, and the dashed line in Fig. 6 represents the device current flowing through the second switching element 22.

[0096] As can be seen from Fig. 5, the gate voltage of the second switching element 22 rose earlier than that of the first switching element 21. Accordingly, as shown in Fig. 6, the second switching element 22 transitioned to the on state before the first switching element 21. As can be seen from Fig. 6, after the first switching element 21 was turned on, the device current flowing through the first switching element 21 was greater than the device current flowing through the second switching element 22.

[0097] 7 is a graph showing measurement results of the gate voltage corresponding to the first gate signal and the gate voltage corresponding to the second gate signal at turn-off. The horizontal axis of FIG. 7 represents time (μs), and the vertical axis represents gate voltage (V). The solid line in FIG. 7 represents the first gate voltage for driving the first switching element 21, and the dashed line in FIG. 7 represents the second gate voltage for driving the second switching element 22.

[0098] 8 is a graph showing measurement results of the device current flowing through the first switching element 21 and the device current flowing through the second switching element 22 at turn-off. The horizontal axis of Fig. 8 represents time (μs), and the vertical axis represents the device current (A). The solid line in Fig. 8 represents the device current flowing through the first switching element 21, and the dashed line in Fig. 8 represents the device current flowing through the second switching element 22.

[0099] As can be seen from Fig. 7, the gate voltage of the first switching element 21 falls earlier than the second switching element 22. Accordingly, as shown in Fig. 8, the first switching element 21 transitions to the off state before the second switching element 22. In other words, the second switching element 22 transitions to the off state after the first switching element 21. As can be seen from Fig. 8, the device current flowing through the first switching element 21 was greater than the device current flowing through the second switching element 22 until the first switching element 21 was turned off.

[0100] 5 to 8, it can be seen that the drive circuit 5 including the signal generation circuit 100 can generate the first gate signal and the second gate signal that drive the first switching element 21 and the second switching element 22 from a common input pulse signal, and can also differentiate the drive timing of the first switching element 21 and the second switching element 22 by the first gate signal and the second gate signal. Furthermore, it can be seen that when the first switching element 21 and the second switching element 22 are both in the on state, the first switching element 21 functions as the main current path in the switch section 20.

[0101] Second Embodiment Fig. 9 is a circuit diagram of a drive circuit including a signal generating circuit according to a second embodiment. Fig. 9 also illustrates a switch unit 20. The configuration of the switch unit 20 is the same as that of the first embodiment. That is, the switch unit 20 is configured by connecting a first switching element 21 and a second switching element 22 in parallel. In the second embodiment, the first switching element 21 is also a Si-IGBT, and the second switching element 22 is also a SiC-MOSFET. The connection relationship between the first switching element 21 and the second switching element 22 is the same as that of the first embodiment, and therefore will not be described again.

[0102] A driving circuit 5A according to the second embodiment differs from the driving circuit 5 mainly in that a signal generating circuit 100A is provided instead of the signal generating circuit 100.

[0103] The drive circuit 5A includes a signal generation circuit 100A, a first GDIC 54a, a first push-pull circuit 55a, a second GDIC 54b, a second push-pull circuit 55b, a first gate resistor 56a, and a second gate resistor 56b.

[0104] The signal generating circuit 100A includes a delay signal generating unit 10A and a logic synthesis unit 16A. The delay signal generating unit 10A generates a first delay pulse signal and a second delay pulse signal having different delay states relative to an input pulse signal. The logic synthesis unit 16A generates a first control pulse signal by performing a logical AND on a signal set of the first delay pulse signals, and generates a second control pulse signal by performing an exclusive OR on a signal set of the second delay pulse signal and the input pulse signal.

[0105] The configurations of the first GDIC 54a, first push-pull circuit 55a, second GDIC 54b, and second push-pull circuit 55b are the same as those in the first embodiment, and therefore will not be described here. The relative positions of the first gate resistor 56a and the second gate resistor 56b are also the same as those in the first embodiment. Therefore, in the drive circuit 5A, the circuit configuration that generates the first gate signal in response to the first control pulse signal generated by the signal generation circuit 100A and the circuit configuration that generates the second gate signal in response to the second control pulse signal generated by the signal generation circuit 100A are the same as those in the first embodiment.

[0106] [Signal Generation Circuit] The delay signal generation section 10A of the signal generation circuit 100A includes a first delay circuit 11A and a second delay circuit 11B.

[0107] (First Delay Circuit) The first delay circuit 11A is configured to be able to set a resistance value for delaying the rising edge of the input pulse signal and a resistance value for delaying the falling edge of the input pulse signal. The first delay circuit 11A has a first parallel circuit (resistance unit) 12A in which a first series circuit 13A and a second series circuit 14A are connected in parallel, and a first capacitor 15a.

[0108] The first parallel circuit 12A has a node (first end) 12c and a node (second end) 12d. The node 12c is electrically connected to the input terminal 51. An input pulse signal is input to the node 12c from the external control device 7. The node 12d is electrically connected to the logic synthesis unit 16A.

[0109] The first series circuit 13A is configured by connecting a first diode 131a and a first resistor 132a in series. The anode of the first diode 131a is connected to the node 12c. The first resistor 132a is connected between the cathode of the first diode 131a and the node 12d. Examples of the forward voltage of the first diode 131a and the resistance value of the first resistor 132a are the same as those of the first diode 131 and the first resistor 132 described in the first embodiment.

[0110] The second series circuit 14A is configured by connecting a second diode 141a and a second resistor 142a in series. The anode of the second diode 141a is connected to the node 12d. The second resistor 142a is connected between the cathode of the second diode 141a and the node 12a. Examples of the forward voltage of the second diode 141a and the resistance value of the second resistor 142a are the same as those of the second diode 141 and the second resistor 142 described in the first embodiment.

[0111] The first capacitor 15a is electrically connected between the node 12d and the ground. An example of the capacitance of the first capacitor 15a is the same as that of the capacitor 15 described in the first embodiment.

[0112] In the first delay circuit 11A, the first series circuit 13A functions as a signal path that delays the rising edge of the input pulse signal, and the first series circuit 13A (specifically, the first resistor 132a) and the first capacitor 15a form a delay circuit that delays the rising edge of the input pulse signal. The delay time for the rising edge is determined by the resistance value of the first resistor 132a and the capacitance of the first capacitor 15a. In other words, the delay time for the rising edge that is applied to the input pulse signal in the first delay circuit 11A is set to Td1. ＯＮ [s], the resistance value of the first resistor 132a is R1a [Ω], and the capacitance of the first capacitor 15a is C1 [F], then Td1 ＯＮ is expressed by the formula (1). ＯＮ = R1a × C1 (1)

[0113] In the first delay circuit 11A, the second series circuit 14A functions as a signal path that delays the falling edge of the input pulse signal, and the second series circuit 14A and the first capacitor 15a form a delay circuit that delays the falling edge of the input pulse signal. The delay time for the falling edge is determined by the resistance value of the second resistor 142a and the capacitance of the first capacitor 15a. In other words, the delay time for the falling edge that is applied to the input pulse signal in the first delay circuit 11A is set to Td1. ＯＦＦ [s] and the resistance value of the second resistor 142a is R2a [Ω], Td1 ＯＦＦ is expressed by the formula (2). ＯＦＦ = R2a × C1 (2)

[0114] The second delay circuit 11B is configured to be able to set a resistance value for delaying the rising edge of the input pulse signal and a resistance value for delaying the falling edge of the input pulse signal. The second delay circuit 11B has a second parallel circuit (resistance unit) 12B in which a third series circuit 13B and a fourth series circuit 14B are connected in parallel, and a second capacitor 15b.

[0115] The second parallel circuit 12B has a node (third terminal) 12e and a node (fourth terminal) 12f. The node 12e is electrically connected to the input terminal 51. An input pulse signal is input to the node 12e from the external control device 7. The node 12f is electrically connected to the logic synthesis unit 16A.

[0116] The third series circuit 13B is configured by connecting a third diode 131b and a third resistor 132b in series. The anode of the third diode 131b is connected to the node 12e. The third resistor 132b is connected between the cathode of the third diode 131b and the node 12f. Examples of the forward voltage of the third diode 131b and the resistance value of the third resistor 132b are the same as those of the first diode 131 and the first resistor 132 described in the first embodiment. The third diode 131b may be the same as or different from the first diode 131a. The third resistor 132b may be the same as or different from the first resistor 132a.

[0117] The fourth series circuit 14B is configured by connecting a fourth diode 141b and a fourth resistor 142b in series. The anode of the fourth diode 141b is electrically connected to the node 12f. The fourth resistor 142b is electrically connected between the cathode of the fourth diode 141b and the node 12e. Examples of the forward voltage of the fourth diode 141b and the resistance value of the fourth resistor 142b are the same as those of the first diode 131 and the first resistor 132 described in the first embodiment. The fourth diode 141b may be the same as or different from the second diode 141a. The fourth resistor 142b may be the same as or different from the second resistor 142a.

[0118] The second capacitor 15b is electrically connected between the node 12f and ground. An example of the capacitance of the second capacitor 15b is the same as that of the capacitor 15 described in the first embodiment. The second capacitor 15b may be the same as or different from the first capacitor 15a.

[0119] In the second delay circuit 11B, the third series circuit 13B functions as a signal path that delays the rising edge of the input pulse signal, and the third series circuit 13B (specifically, the third resistor 132b) and the second capacitor 15b form a delay circuit that delays the rising edge of the input pulse signal. The delay time for the rising edge is determined by the resistance value of the third resistor 132b and the capacitance of the second capacitor 15b. In other words, the delay time for the rising edge that is applied to the input pulse signal in the second delay circuit 11B is set to Td2 ＯＮ [s], the resistance value of the third resistor 132b is R1b [Ω], and the capacitance of the second capacitor 15b is C2 [F], then Td2 ＯＮ is expressed by the formula (3). ＯＮ = R1b × C2 (3)

[0120] In the second delay circuit 11B, the fourth series circuit 14B functions as a signal path that delays the falling edge of the input pulse signal, and the fourth series circuit 14B (specifically, the fourth resistor 142b) and the second capacitor 15b form a delay circuit that delays the falling edge of the input pulse signal. The delay time for the falling edge is determined by the resistance value of the fourth resistor 142b and the capacitance of the second capacitor 15b. In other words, the delay time for the falling edge that is applied to the input pulse signal in the second delay circuit 11B is set to Td2 ＯＦＦ [s] and the resistance value of the fourth resistor 142b is R1b [Ω], Td2 ＯＦＦ is expressed by equation (4). ＯＦＦ = R1b × C2 (4)

[0121] In the second embodiment, the delay time Td1 defined by the formulas (1), (2), (3), and (4) ＯＮ , Td1 ＯＦＦ , Td2 ＯＮ , Td2 ＯＦＦ satisfies the relationships of formulas (5) and (6). ＯＮ <Td2 ＯＮ ... (5) Td1 ＯＦＦ <Td2 ＯＦＦ ...(6) In other words, the resistance value R1a of the first resistor 132a, the resistance value R2a of the second resistor 142a, the capacitance C1 of the first capacitor 15a, the resistance value R1b of the third resistor 132b, the resistance value R2b of the fourth resistor 142b, and the capacitance C2 of the second capacitor 15b are set to satisfy equations (5) and (6).

[0122] (Logic Synthesis Unit) The logic synthesis unit 16A includes an AND circuit 161 for generating a first control pulse signal and an XOR circuit 163 for generating a second control pulse signal.

[0123] The AND circuit 161 is electrically connected to the first delay circuit 11A. A signal set of first delay pulse signals is input to the AND circuit 161. That is, a pair of first delay pulse signals is input to the AND circuit 161 from the delay signal generating unit 10A. The AND circuit 161 is a logical product circuit that performs a logical product on the input first delay pulse signals to output a first control pulse signal. The AND circuit 161 is electrically connected to the first GDIC 54a, and the first control pulse signal output from the AND circuit 161 is input to the first GDIC 54a.

[0124] The XOR circuit 163 is electrically connected to the input terminal 51 and the second delay circuit 11B. A signal set of the input pulse signal and the second delayed pulse signal is input to the XOR circuit 163. The XOR circuit 163 is an exclusive OR circuit that performs an exclusive OR on the input pulse signal and the second delayed pulse signal and outputs a second control pulse signal. The XOR circuit 163 is electrically connected to the second GDIC 54b, and the second control pulse signal output from the XOR circuit 163 is input to the second GDIC 54b.

[0125] 10 is a time chart of various signals in the second embodiment. In FIG. 10, the input pulse signal, the first delay pulse signal, the second delay pulse signal, the first control pulse signal, the second control pulse signal, and the main circuit current are respectively represented as the input pulse signal S1, the first delay pulse signal S2a, the second delay pulse signal S2b, the first control pulse signal S3, the second control pulse signal S4, and the main circuit current I Ｍ The main circuit current I Ｍ is the current flowing through the switch section 20, as in the first embodiment.

[0126] In FIG. 10, the AND circuit 161 and the XOR circuit 163 have threshold voltages (threshold signal levels) for regarding an input signal as High and Low, respectively. ＩＨ and V ＩＬ In the AND circuit 161 and the XOR circuit 163, the input signal is V ＩＨ Once it exceeds V ＩＬis considered to be in a High state unless the input signal falls below V ＩＬ Once it falls below V ＩＨ It is considered to be in a low state unless it exceeds V. ＩＨ An example of V is 3V, ＩＬ An example is 2V.

[0127] The operation of the drive circuit 5A and the switch section 20 will be described with reference to FIGS.

[0128] 10, the input pulse signal S1 has a pulse that rises at time T1 and falls at time T4. When the input pulse signal S1 is input to the delay signal generating unit 10A, the delay signal generating unit 10A generates a first delay pulse signal S2a and a second delay pulse signal S2b.

[0129] The first delay circuit 11A included in the delay signal generating unit 10A includes a first parallel circuit 12A and a first capacitor 15a. The first parallel circuit 12A includes a first series circuit 13A that contributes to delaying the rising edge and a second series circuit 14A that contributes to delaying the falling edge. Therefore, as shown in FIG. 10, the first delay pulse signal S2a is generated from time T1 for a delay time Td1. ＯＮ It rises at time T2 after that, and starts at time T5 with a delay time Td1 ＯＦＦ The meaning of "rising after a delay time from time α" and "falling after a delay time from time β" is the same as in the first embodiment. In the example shown in FIG. 10 , the threshold level that determines the delay time of the rising edge is V, which is the same as the threshold voltage for regarding the signal input to the AND circuit 161 and the XOR circuit 163 as High. ＩＨ The threshold level that determines the delay time of the falling edge is V, which is the same as the threshold voltage for regarding the signal input to the AND circuit 161 and the XOR circuit 163 as Low. ＩＬ is.

[0130] The first delay pulse signal S2a generated by the first delay circuit 11A is input to the logic synthesis unit 16A. Specifically, a pair of first delay pulse signals S2a are input to an AND circuit 161. The AND circuit 161 performs a logical AND operation on the signal set of the first delay pulse signals S2a to generate a first control pulse signal S3.

[0131] In the example shown in FIG. 10, the signal level (voltage) of the first delayed pulse signal S2a is equal to or exceeds the threshold voltage V ＩＨ At time T5, the threshold voltage V ＩＬ Therefore, the first delayed pulse signal S2a input to the AND circuit 161 is in a High state from time T2 to time T5, and thereafter, the first delayed pulse signal S2a is again below the threshold voltage V ＩＨ is processed as a signal that is maintained in the Low state until the signal exceeds the threshold.

[0132] The first control pulse signal S3 is generated by the logical AND of the first delay pulse signals S2a. Due to the relationship between the high and low states of the first delay pulse signal S2a in the AND circuit 161, the first control pulse signal S3 is a pulse signal that rises at time T2 and falls at time T5.

[0133] The second delay circuit 11B included in the delay signal generating unit 10A includes a second parallel circuit 12B and a second capacitor 15b. The second parallel circuit 12B includes a third series circuit 13B that contributes to delaying the rising edge and a fourth series circuit 14B that contributes to delaying the falling edge. Furthermore, in this embodiment, the resistance value R1a of the first resistor 132a, the resistance value R2a of the second resistor 142a, the capacitance C1 of the first capacitor 15a, the resistance value R1b of the third resistor 132b, the resistance value R2b of the fourth resistor 142b, and the capacitance C2 of the second capacitor 15b are set so as to satisfy equations (5) and (6).

[0134] Therefore, as shown in FIG. 10, the second delay pulse signal S2b is generated from time T1 for a delay time Td2. ＯＮ It rises at time T3 after that, and the delay time Td2 ＯＦＦThe meaning of "rising after a delay time from time α" and "falling after a delay time from time β" is the same as in the first embodiment. In the example shown in FIG. 10 , the threshold level that determines the delay time of the rising edge is V, which is the same as the threshold voltage for regarding the signal input to the AND circuit 161 and the XOR circuit 163 as High. ＩＨ The threshold level that determines the delay time of the falling edge is V, which is the same as the threshold voltage for regarding the signal input to the AND circuit 161 and the XOR circuit 163 as Low. ＩＬ is.

[0135] The second delay pulse signal S2b generated by the second delay circuit 11B is input to the logic synthesis unit 16A. Specifically, the second delay pulse signal S2b is input to the XOR circuit 163. The input pulse signal S1 is also input to the XOR circuit 163. The XOR circuit 163 performs an exclusive OR on the signal set of the input pulse signal S1 and the second delay pulse signal S2b to generate the second control pulse signal S4.

[0136] In the example shown in FIG. 10, the signal level (voltage) of the input pulse signal S1 is equal to or exceeds the threshold voltage V ＩＨ At time T4, the threshold voltage V ＩＬ Therefore, the input pulse signal S1 input to the XOR circuit 163 is in a High state from time T1 to time T4, and thereafter, the input pulse signal S1 again falls below the threshold voltage V ＩＨ The signal level (voltage) of the second delayed pulse signal S2b is processed as a signal that is maintained in a low state until it exceeds the threshold voltage V at time T3. ＩＨ At time T6, the threshold voltage V ＩＬ Therefore, the second delayed pulse signal S2b input to the XOR circuit 163 is in a High state from time T3 to time T6, and thereafter, the second delayed pulse signal S2b is again below the threshold voltage V ＩＨ is processed as a signal that is maintained in the Low state until the signal exceeds the threshold.

[0137] The second control pulse signal S4 is generated by the exclusive OR of the signal set of the input pulse signal S1 and the second delay pulse signal S2b. Due to the relationship between the high and low states of the input pulse signal S1 and the second delay pulse signal S2b in the XOR circuit 163, the second control pulse signal S4 is a pulse signal that rises at time T1, falls at time T3, rises again at time T4, and falls at time T6.

[0138] In this way, the signal generating circuit 100A can generate two different control pulse signals, the first control pulse signal S3 and the second control pulse signal S4, based on the same input pulse signal.

[0139] In the drive circuit 5A, the first control pulse signal S3 is input to the first GDIC 54a and output as a first output pulse signal. The first output pulse signal output from the first GDIC 54a is input to the first push-pull circuit 55a and output as a first gate signal. The first gate signal is input to the first output terminal 52 via the first gate resistor 56a. The first output terminal 52 is electrically connected to the gate of the first switching element 21, and therefore the first switching element 21 is driven by the first gate signal.

[0140] The first output pulse signal is an amplified pulse signal of the first control pulse signal, and therefore has a waveform similar to that of the first control pulse signal. The first gate signal is an amplified pulse signal of the first output pulse signal, and therefore has a waveform similar to that of the first output pulse signal. Therefore, the first gate signal has a waveform similar to that of the first control pulse signal S3.

[0141] In the drive circuit 5A, the second control pulse signal S4 is input to the second GDIC 54b, and is output as a second output pulse signal. The second output pulse signal output from the second GDIC 54b is input to the second push-pull circuit 55b, and is output as a second gate signal. The second gate signal is input to the second output terminal 53 via the second gate resistor 56b. The second output terminal 53 is electrically connected to the gate of the second switching element 22, and therefore the second switching element 22 is driven by the second gate signal.

[0142] The second output pulse signal is an amplified pulse signal of the second control pulse signal, and therefore has a waveform similar to that of the second control pulse signal. The second gate signal is an amplified pulse signal of the second output pulse signal, and therefore has a waveform similar to that of the second output pulse signal. Therefore, the second gate signal has a waveform similar to that of the second control pulse signal S4.

[0143] The first switching element 21 is driven by a first gate signal having a waveform similar to that of the first control pulse signal S3, and is therefore turned on at time T2 and turned off at time T5. The second switching element 22 is driven by a second gate signal having a waveform similar to that of the second control pulse signal S4, and is therefore turned on at time T1, turned off once at time T3, turned on again at time T4, and then turned off at time T6. Therefore, the second switching element 22 is in an on state from time T1 to time T3, an off state from time T3 to time T4, and an on state from time T4 to time T6. Of the two on states of the second switching element 22, the on state from time T1 to time T3 is referred to as a first on state, and the on state from time T4 to time T6 after the first on state is referred to as a second on state.

[0144] As described above, the first switching element 21 is turned on at time T2, and therefore the first switching element 21 is turned on between time T1 and time T3 (while the second switching element 22 is in the first on state). ＯＮ and delay time Td2 ＯＮ is realized by satisfying the formula (5).

[0145] As described above, the first switching element 21 is turned off at time T5, and therefore the first switching element 21 is turned off between time T4 and time T5 (while the second switching element 22 is in the second on state). ＯＦＦ and delay time Td2 ＯＦＦ is realized by satisfying the formula (6).

[0146] The switch unit 20 is configured by connecting a first switching element 21 and a second switching element 22 in parallel. Therefore, similar to the first embodiment, when either the first switching element 21 or the second switching element 22 is in the on state, the switch unit 20 is in the on state, and when both the first switching element 21 and the second switching element 22 are in the off state, the switch unit 20 is in the on state. Therefore, the switch unit 20 is in the on state from time T1 to time T6, and as shown in FIG. 10 , the main circuit current I Ｍ is playing.

[0147] 10 , in the configuration of the drive circuit 5A included in the signal generating circuit 100A, the second switching element 22, which is a SiC-MOSTET, is in the ON state from time T1 to time T3, is in the OFF state from time T3 to time T4, and is in the ON state from time T4 to time T6. On the other hand, in the configuration of the drive circuit 5A included in the signal generating circuit 100A, the first switching element 21, which is a Si-IGBT, is in the ON state from time T2 to time T5. Therefore, in this embodiment, the second switching element 22 essentially only performs the function of turning on and off the switch unit 20, and the first switching element 21 essentially functions as a current path when the switch unit 20 is in the ON state.

[0148] The Si-IGBT has smaller conduction loss at high currents than the SiC-MOSFET and is resistant to overcurrent. Therefore, since the current path when the switch unit 20 is in the on state is the first switching element 21 (Si-IGBT), the switch unit 20 has improved resistance to overcurrent. The second switching element 22 (SiC-MOSFET) is responsible for the turn-on and turn-off functions of the switch unit 20, enabling high-speed switching of the switch unit 20.

[0149] The signal generation circuit 100A can generate different first and second control pulse signals from a common input pulse signal for the first switching element 21 and the second switching element 22. As described above, the drive circuit 5A can output a first gate signal for driving the first switching element 21 and a second gate signal for driving the second switching element 22 in response to the first and second control pulse signals. Therefore, the signal generation circuit 100A and the drive circuit 5A have the same effects as those in the first embodiment.

[0150] The set of the drive circuit 5A and the switch unit 20 can be applied to the power conversion device 1 shown in Fig. 1 in place of the set of the drive circuit 5 and the switch unit 20. Since the drive circuit 5A has the same effects as in the first embodiment, the power conversion device 1 to which the set of the drive circuit 5A and the switch unit 20 is applied also has the same effects as in the first embodiment.

[0151] Next, Experimental Example 2 regarding the signal generating circuit 100A will be described. In Experimental Example 2, a double pulse test was carried out. FIG. 11 is a circuit diagram of a circuit used in the double pulse test in Experimental Example 2. As shown in FIG. 11, the double pulse test circuit used in Experimental Example 2 had a drive circuit 5A and a switch unit 20. The configurations of the drive circuit 5A and the switch unit 20 were the same as those of the drive circuit 5A and the switch unit 20 described using FIG. 9.

[0152] The resistance value of the first resistor 132a in the first series circuit 13A was 560Ω. The resistance value of the second resistor 142a in the second series circuit 14A was 820Ω. The capacitance of the first capacitor 15a was 1 nF. The resistance value of the third resistor 132b in the third series circuit 13B was 560Ω. The resistance value of the fourth resistor 142b in the fourth series circuit 14B was 820Ω. The capacitance of the second capacitor 15b was 1 nF. The first diode 131a, the second diode 141a, the third diode 131b, and the fourth diode 141b were the same as the first diode 131 and the second diode 141 in Experimental Example 1. The first GDIC 54a and the second GDIC 54b were the same GDICs as in Experimental Example 1. The first power supply potential in the first power supply potential line 61 to which the first GDIC 54a and the second GDIC 54b are electrically connected is 5 V. The second power supply potential in the second power supply potential line 62 to which the first push-pull circuit 55a and the second push-pull circuit 55b are electrically connected is 18 V. The first gate resistor 56a uses the same gate resistor as the first gate resistor 56a in Experimental Example 1. The second gate resistor 56b uses the same gate resistor as the second gate resistor 56b in Experimental Example 1. In the AND circuit 161 and the XOR circuit 163, the threshold voltage V ＩＨ and V ＩＬ They were 3V and 2V respectively.

[0153] The first switching element 21 of the switch section 20 was a Si-IGBT (MG7213 manufactured by Rohm Co., Ltd.), and the second switching element 22 was a SiC-MOSFET (S4603 manufactured by Rohm Co., Ltd.).

[0154] A node 20a of the switch unit 20 was electrically connected to a power supply potential line 63 via a coil (inductive load) 71. The power supply potential supplied to the power supply potential line 63 was 600 V, and the series circuit of the coil 71 and the switch unit 20 was configured so that a current of 60 A would flow when the switch unit 20 was in the on state. As in Experimental Example 1, a free wheel diode 72 was connected in anti-parallel to the coil 71. A node 20b of the switch unit 20 was connected to ground.

[0155] In Experimental Example 2, a double pulse test was carried out using the double pulse test circuit shown in Fig. 11. Specifically, an input pulse signal was input to drive circuit 5A from external control device 7 as a pulse signal source, and first switching element 21 was driven by a first gate signal output from first output terminal 52, and second switching element 22 was driven by a second gate signal output from second output terminal 53. In the double pulse test, similarly to Experimental Example 1, gate voltages corresponding to the first gate signal and the second gate signal were measured, and device currents flowing through first switching element 21 and second switching element 22 were measured.

[0156] Fig. 12 is a graph showing measurement results of the gate voltage corresponding to the first gate signal and the gate voltage corresponding to the second gate signal at turn-on. The horizontal axis of Fig. 12 represents time (µs), and the vertical axis represents gate voltage (V). The solid line in Fig. 12 represents the first gate voltage for driving the first switching element 21, and the dashed line in Fig. 12 represents the second gate voltage for driving the second switching element 22.

[0157] 13 is a graph showing measurement results of the device current flowing through the first switching element 21 and the device current flowing through the second switching element 22 at turn-on. The horizontal axis of Fig. 13 represents time (μs), and the vertical axis represents the device current (A). The solid line in the graph represents the device current flowing through the first switching element 21, and the dashed line in Fig. 13 represents the device current flowing through the second switching element 22.

[0158] 12, the gate voltage of the second switching element 22 rose earlier than that of the first switching element 21, and the gate voltage of the second switching element 22 fell after the rise of the gate voltage of the first switching element 21. Accordingly, as shown in FIG. 13, the second switching element 22 transitioned to the ON state before the first switching element 21, and after the first switching element 21 turned ON, the second switching element 22 transitioned to the OFF state.

[0159] Fig. 14 is a graph showing measurement results of the gate voltage corresponding to the first gate signal and the gate voltage corresponding to the second gate signal at turn-off. The horizontal axis of Fig. 14 represents time (µs), and the vertical axis represents gate voltage (V). The solid line in Fig. 14 represents the first gate voltage for driving the first switching element 21, and the dashed line in Fig. 14 represents the second gate voltage for driving the second switching element.

[0160] 15 is a graph showing measurement results of the device current flowing through the first switching element 21 and the device current flowing through the second switching element 22 at turn-off. The horizontal axis of Fig. 15 represents time (μs), and the vertical axis represents the device current (A). The solid line in Fig. 15 represents the device current flowing through the first switching element 21, and the dashed line in Fig. 15 represents the device current flowing through the second switching element 22.

[0161] As can be seen from Fig. 14, before the gate voltage of the first switching element 21 falls, the gate voltage of the second switching element 22 is 0 V. Shortly before the gate voltage of the first switching element 21 falls, the second switching element 22 rises, and after the gate voltage of the first switching element 21 falls, the second switching element 22 falls. Accordingly, as shown in Fig. 15, before the first switching element 21 transitions to the off state, the second switching element 22 is in the off state. Shortly before the first switching element 21 transitions to the off state, the second switching element 22 transitions to the on state, and after the first switching element 21 transitions to the off state, the second switching element 22 transitions to the off state.

[0162] From the results shown in FIGS. 13 to 15, it can be seen that in the drive circuit 5A including the signal generation circuit 100A, the second switching element 22 is only responsible for the turn-on and turn-off functions of the switch section 20, and when the switch section 20 is in the on state, the first switching element 21 is responsible for the current path, so that the first gate signal and the second gate signal that drive the first switching element 21 and the second switching element 22 can be generated from a common input pulse signal.

[0163] Third Embodiment In the first and second embodiments, the number of first switching elements and the number of second switching elements included in the switch unit are both 1. However, the number of first switching elements is not limited to 1, and the number of second switching elements is also not limited to 1.

[0164] In the third embodiment, a case will be described in which the switch section includes one first switching element 21 and two second switching elements.

[0165] 16 is a circuit diagram of a drive circuit 5B including a signal generation circuit 100B according to the third embodiment. The drive circuit 5B is a circuit for driving the switch section 20A shown in FIG.

[0166] The switch unit 20A has a first switching element 21, a second-a switching element 22A, and a second-b switching element 22B. In the third embodiment, the first switching element 21 is also a Si-IGBT, and the second-a switching element 22A and the second-b switching element 22B are SiC-MOSFETs. A free wheel diode 23 may be connected in anti-parallel to each of the second-a switching element 22A and the second-b switching element 22B.

[0167] The first switching element 21, the second-a switching element 22A, and the second-b switching element 22B are connected in parallel between the node 20a and the node 20b. Specifically, the collector of the first switching element 21, the drain of the second-a switching element 22A, and the drain of the second-b switching element 22B are electrically connected to the node 20a, and the emitter of the first switching element 21, the source of the second-a switching element 22A, and the source of the second-b switching element 22B are electrically connected to the node 20b.

[0168] The switch unit 20A is applied to the power conversion device 1 shown in FIG.

[0169] The drive circuit 5B differs from the drive circuit 5 mainly in that it has a signal generation circuit 100B instead of the signal generation circuit 100. That is, the drive circuit 5B has a signal generation circuit 100B, a first GDIC 54a, a first push-pull circuit 55a, a seconda GDIC (seconda driver) 541a, a seconda push-pull circuit 551a, a secondb GDIC (secondb driver) 541b, a secondb push-pull circuit 551b, a first gate resistor 56a, a seconda gate resistor 561a, and a secondb gate resistor 561b.

[0170] The signal generating circuit 100B includes a delayed signal generating section 10B and a logic synthesis section 16B.

[0171] The delay signal generating unit 10B generates a first delay pulse signal, a second a delay pulse signal, and a second b delay pulse signal that are different in delay state from the input pulse signal. The second a delay pulse signal is a pulse signal that is delayed with respect to the rising edge of the input pulse signal, and the second b delay pulse signal is a pulse signal that is delayed with respect to the falling edge of the input pulse signal.

[0172] The logic synthesis unit 16B generates the first control pulse signal by performing a logical AND on the signal set of the first delay pulse signals. The logic synthesis unit 16B generates the second a control pulse signal by performing an exclusive OR on the signal set of the input pulse signal and the second a delay pulse signal. The logic synthesis unit 16B generates the second b control pulse signal by performing an exclusive OR on the signal set of the input pulse signal and the second b delay pulse signal.

[0173] The configurations of the first GDIC 54a and the first push-pull circuit 55a are the same as those in the first embodiment, and therefore will not be described. The positional relationship between the first push-pull circuit 55a and the first gate resistor 56a is also the same as in the first embodiment.

[0174] The 2a-GDIC 541a is connected between the first power supply potential line 61 and ground. The 2a-GDIC 541a outputs a 2a-output pulse signal based on the 2a-control pulse signal. The 2a-output pulse signal is a signal obtained by amplifying the 2a-control pulse signal. In this embodiment, the 2a-output pulse signal is a signal that drives the 2a-push-pull circuit 551a.

[0175] The second-a GDIC 541a has a function of transmitting signals while insulating the signal generating circuit 100B from the second-a push-pull circuit 551a and a function of amplifying the second-a control pulse signal. For example, the configuration example of the second-a GDIC 541a is the same as that of the first GDIC 54a.

[0176] The 2a-th push-pull circuit 551a has a first transistor Tr1 and a second transistor Tr2 connected in series between the second power supply potential line 62 and ground. The 2a-th push-pull circuit 551a is a totem-pole output stage in which the first transistor Tr1 and the second transistor Tr2 are connected in series. The first transistor Tr1 and the second transistor Tr2 are an npn transistor and a pnp transistor, respectively.

[0177] The electrical connections between the first transistor Tr1 and the second transistor Tr2, the second power supply potential line 62, and the ground included in the 2a push-pull circuit 551a are the same as those in the first push-pull circuit 55a. The gates of the first transistor Tr1 and the second transistor Tr2 included in the 2a push-pull circuit 551a are electrically connected to the 2a GDIC 541a, and the first output pulse signal is input from the 2a GDIC 541a.

[0178] A node between the emitter of the first transistor Tr1 and the emitter of the second transistor Tr2 is electrically connected to the second output terminal 53a via a second gate resistor 561a, whose resistance value is the same as that of the first gate resistor 56.

[0179] In the 2a push-pull circuit 551a configured as described above, the first transistor Tr1 and the second transistor Tr2 are driven in response to the 2a output pulse signal from the 2a GDIC 541a. As a result, a 2a gate signal (2a drive pulse signal) is obtained by amplifying the 2a output pulse signal. The 2a gate signal is input to the 2a output terminal 53a via the 2a gate resistor 561a. Since the 2a output terminal 53a is electrically connected to the gate of the 2a switching element 22A, the 2a gate signal is input to the gate of the 2a switching element 22A.

[0180] The second b GDIC 541 b is connected between the first power supply potential line 61 and ground. The second b GDIC 541 b outputs a second b output pulse signal based on the second b control pulse signal. The second b output pulse signal is a signal obtained by amplifying the second b control pulse signal. In this embodiment, the second b output pulse signal is a signal that drives the second b push-pull circuit 551 b.

[0181] The second b GDIC 541 b has a function of transmitting signals while insulating the signal generation circuit 100B from the second b push-pull circuit 551 b and a function of amplifying the second b control pulse signal. For example, an example configuration of the second b GDIC 541 b is the same as that of the first GDIC 54 a.

[0182] The 2b push-pull circuit 551b has a first transistor Tr1 and a second transistor Tr2 connected in series between the second power supply potential line 62 and ground. The 2b push-pull circuit 551b is a totem-pole output stage in which the first transistor Tr1 and the second transistor Tr2 are connected in series. The first transistor Tr1 and the second transistor Tr2 are an npn transistor and a pnp transistor, respectively.

[0183] The electrical connections between the first transistor Tr1 and the second transistor Tr2, the second power supply potential line 62, and the ground of the 2b push-pull circuit 551b are the same as those of the first push-pull circuit 55a. The gates of the first transistor Tr1 and the second transistor Tr2 of the 2b push-pull circuit 551b are electrically connected to the 2b GDIC 541b, and the 2b output pulse signal is input from the 2b GDIC 541b.

[0184] A node between the emitter of the first transistor Tr1 and the emitter of the second transistor Tr2 is electrically connected to the second output terminal 53b via a second gate resistor 561b, whose resistance value is the same as that of the second gate resistor 56b.

[0185] In the 2b push-pull circuit 551b configured as described above, the first transistor Tr1 and the second transistor Tr2 are driven in response to the 2b output pulse signal from the 2b GDIC 541b. As a result, a 2b gate signal (2b drive pulse signal) is obtained by amplifying the 2b output pulse signal. The 2b gate signal is input to the 2b output terminal 53b via the 2b gate resistor 561b. Since the 2b output terminal 53b is electrically connected to the gate of the 2b switching element 22B, the 2b gate signal is input to the gate of the 2b switching element 22B.

[0186] [Signal Generation Circuit] The delay signal generation section 10B of the signal generation circuit 100B includes a first delay circuit 11A, a second delay circuit 11C, and a second delay circuit 11D.

[0187] The configuration of the first delay circuit 11A is the same as that of the first delay circuit 11A in the second embodiment, and therefore a description thereof will be omitted.

[0188] The 2a delay circuit 11C includes a 2a parallel circuit 12C in which a third series circuit (3a series circuit) 13B and a fourth diode (3b diode) 141b are connected in parallel, and a second capacitor (2a capacitor) 15b.

[0189] The 2a-th parallel circuit 12C has a node (3a-th terminal) 121a and a node (3b-th terminal) 121b. The node 121a is electrically connected to the input terminal 51. An input pulse signal is input to the node 121a from the external control device 7. The node 121b is electrically connected to the logic synthesis unit 16B.

[0190] The third series circuit 13B has the same configuration as the third series circuit 13B described in the second embodiment. That is, the third series circuit 13B is configured by connecting a third diode (3a diode) 131b and a third resistor (3a resistor) 132b in series. The anode of the third diode 131b is connected to the node 121a. The third resistor 132b is connected between the cathode of the third diode 131b and the node 121b.

[0191] The anode of the fourth diode 141b is connected to the node 121b, and the cathode of the fourth diode 141b is connected to the node 121a.

[0192] The second capacitor 15b is electrically connected between the node 121b and ground.

[0193] In the 2a delay circuit 11C, the third series circuit 13B functions as a signal path that delays the rising edge of the input pulse signal, as described in the second embodiment, and the third series circuit 13B (specifically, the third resistor 132b) and the second capacitor 15b form a delay circuit that delays the rising edge of the input pulse signal. In the 2a parallel circuit 12C, instead of the fourth series circuit 14B, only the fourth diode 141b is connected in parallel to the third series circuit 13B as described above. Therefore, the 2a delay circuit 11C does not have the function of delaying the falling edge of the input pulse signal.

[0194] Therefore, the 2a delay circuit 11C is a circuit that corresponds to the function of delaying the rising edge of the input pulse signal, among the functions of the second delay circuit 11B in the second embodiment. ＯＮ is defined by the formula (3) described in the second embodiment.

[0195] The 2b delay circuit 11D includes a 2b parallel circuit 12D in which a fourth series circuit (3b series circuit) 14B and a third diode (3c diode) 131b are connected in parallel, and a second capacitor (2b capacitor) 15b.

[0196] The 2b parallel circuit 12D has a node (3c terminal) 122a and a node (3d terminal) 122b. The node 122a is electrically connected to the input terminal 51. An input pulse signal is input to the node 122a from the external control device 7. The node 122b is electrically connected to the logic synthesis unit 16B.

[0197] The fourth series circuit 14B has the same configuration as the fourth series circuit 14B described in the second embodiment. That is, the fourth series circuit 14B is configured by connecting a fourth diode (3d diode) 141b and a fourth resistor (3b resistor) 142b in series. The anode of the fourth diode 141b is connected to the node 122b. The fourth resistor 142b is connected between the cathode of the fourth diode 141b and the node 122A.

[0198] The anode of the third diode 131b is connected to the node 122a, and the cathode of the third diode 131b is connected to the node 122b.

[0199] The second capacitor 15b is electrically connected between the node 122b and ground.

[0200] In the 2b delay circuit 11D, the fourth series circuit 14B functions as a signal path that delays the falling edge of the input pulse signal, as described in the second embodiment, and the fourth series circuit 14B (specifically, the fourth resistor 142b) and the second capacitor 15b form a delay circuit that delays the falling edge of the input pulse signal. In the 2b parallel circuit 12D, instead of the third series circuit 13B, only the third diode 131b is connected in parallel to the fourth series circuit 14B as described above. Therefore, the 2b delay circuit 11D does not have the function of delaying the rising edge of the input pulse signal.

[0201] Therefore, the 2b delay circuit 11D is a circuit corresponding to the function of delaying the falling edge of the input pulse signal, among the functions of the second delay circuit 11B in the second embodiment. ＯＦＦ is defined by the formula (4) described in the second embodiment.

[0202] [Logic Synthesis Unit] The logic synthesis unit 16B has an AND circuit 161, a first XOR circuit 163a, and a second XOR circuit 163b.

[0203] The AND circuit 161 is electrically connected to the first delay circuit 11A. A signal set of first delay pulse signals is input to the AND circuit 161. That is, a pair of first delay pulse signals is input to the AND circuit 161 from the first delay circuit 11A. The AND circuit 161 is a logical product circuit that performs a logical product on the input first delay pulse signals to output a first control pulse signal. The AND circuit 161 is electrically connected to the first GDIC 54a, and the first control pulse signal output from the AND circuit 161 is input to the first GDIC 54a.

[0204] The first XOR circuit 163a is electrically connected to the input terminal 51 and the 2a delay circuit 11C. A signal set of an input pulse signal and a 2a delay pulse signal is input to the first XOR circuit 163a. ​​The first XOR circuit 163a is an exclusive OR circuit that performs an exclusive OR on the input pulse signal and the 2a delay pulse signal to output a 2a control pulse signal. The first XOR circuit 163a is electrically connected to the 2a GDIC 541a, and the 2a control pulse signal output from the first XOR circuit 163a is input to the 2a GDIC 541a.

[0205] The second XOR circuit 163b is electrically connected to the input terminal 51 and the 2b delay circuit 11D. A signal set of the input pulse signal and the 2b delayed pulse signal is input to the second XOR circuit 163b. The second XOR circuit 163b is an exclusive OR circuit that outputs a 2b control pulse signal by performing an exclusive OR on the input pulse signal and the 2b delayed pulse signal. The second XOR circuit 163b is electrically connected to the 2b GDIC 541b, and the 2b control pulse signal output from the second XOR circuit 163b is input to the 2b GDIC 541b.

[0206] 17 is a time chart of various signals in the third embodiment. In FIG. 17, the input pulse signal, the first delay pulse signal, the second-a delay pulse signal, the second-b delay pulse signal, the first control pulse signal, the second-a control pulse signal, the second-b control pulse signal, and the main circuit current are respectively represented as the input pulse signal S1, the first delay pulse signal S2a, the second-a delay pulse signal S2b1, the second-b delay pulse signal S2b2, the first control pulse signal S3, the second-a control pulse signal S4a, the second-b control pulse signal S4b, and the main circuit current I Ｍ The main circuit current I Ｍ is the current flowing through the switch section 20A, as in the first embodiment.

[0207] In FIG. 17, the AND circuit 161, the first XOR circuit 163a, and the second XOR circuit 163b have threshold voltages (threshold signal levels) for regarding an input signal as High and for regarding it as Low, respectively, as V ＩＨ and V ＩＬ In the AND circuit 161, the first XOR circuit 163a, and the second XOR circuit 163b, the input signals are V ＩＨ Once it exceeds V ＩＬ is considered to be in a High state unless the input signal falls below V ＩＬ Once it falls below V ＩＨ It is considered to be in a low state unless it exceeds V. ＩＨ An example of V is 3V, ＩＬ An example is 2V.

[0208] In the example shown in FIG. 17, as in the second embodiment, the threshold level that determines the delay time of the rising edge is V, which is the same as the threshold voltage for regarding the signals input to the AND circuit 161, the first XOR circuit 163a, and the second XOR circuit 163b as High. ＩＨ The threshold level that determines the delay time of the falling edge is also V, which is the same as the threshold voltage for regarding the signals input to the AND circuit 161, the first XOR circuit 163a, and the second XOR circuit 163b as Low. ＩＬ is.

[0209] 17, the input pulse signal S1 has a pulse that rises at time T1 and falls at time T4, as in the second embodiment. When the input pulse signal S1 is input to the delay signal generating unit 10B, the delay signal generating unit 10B generates a first delay pulse signal S2a, a second-a delay pulse signal S2b1, and a second-b delay pulse signal S2b2.

[0210] The first delay circuit 11A included in the delay signal generating unit 10B has the same configuration as the first delay circuit 11A described in the second embodiment. Therefore, as shown in FIG. 17, the first delay pulse signal S2a is generated from time T1 for a delay time Td1, as in the second embodiment. ＯＮ It rises at time T2 after time T4 and starts at delay time Td1 ＯＦＦ It falls later at time T5.

[0211] In the example shown in FIG. 17, the signal level (voltage) of the first delayed pulse signal S2a is equal to or exceeds the threshold voltage V ＩＨ At time T5, the threshold voltage V ＩＬ Therefore, in the AND circuit 161, the first delayed pulse signal S2a is in a High state from time T2 to time T5, as in the second embodiment, and thereafter falls below the threshold voltage V ＩＨ is processed as a signal that is maintained in the Low state until the signal exceeds the threshold.

[0212] The first control pulse signal S3 is generated in response to the first delay pulse signal S2a generated by the first delay circuit 11A in the same manner as in the second embodiment. Therefore, the first control pulse signal S3 is a pulse signal that rises at time T2 and falls at time T5, similar to the second embodiment.

[0213] As described above, the second delay circuit 11C provided in the delay signal generating unit 10B is a circuit corresponding to the function of delaying the rising edge of the input pulse signal, which is one of the functions of the second delay circuit 11B in the second embodiment, but does not have the function of delaying the falling edge of the input pulse signal. Therefore, as shown in FIG. 17, the second delay pulse signal S2b1 is generated from time T1 for a delay time Td2. ＯＮ It rises later at time T3 and falls at time T4.

[0214] The 2a-th delay pulse signal S2b1 generated by the 2a-th delay circuit 11C is input to the logic synthesis unit 16B. Specifically, the 2a-th delay pulse signal S2b1 is input to a first XOR circuit 163a. ​​The input pulse signal S1 is also input to the first XOR circuit 163a. ​​The first XOR circuit 163a performs an exclusive OR on the signal set of the input pulse signal S1 and the 2a-th delay pulse signal S2b1 to generate the 2a-th control pulse signal S4a.

[0215] In the example shown in FIG. 17, the signal level (voltage) of the input pulse signal S1 is equal to or exceeds the threshold voltage V ＩＨ At time T4, the threshold voltage V ＩＬ Therefore, in the first XOR circuit 163a, the input pulse signal S1 is in a High state from time T1 to time T4, and thereafter, the input pulse signal S1 again falls below the threshold voltage V ＩＨ The signal level (voltage) of the 2a delayed pulse signal S2b1 is processed as a signal that is maintained in a low state until it exceeds the threshold voltage V ＩＨ At time T4, the threshold voltage V ＩＬ Therefore, in the first XOR circuit 163a, the 2a delayed pulse signal S2b1 is in a High state from time T3 to time T4, and thereafter, the 2a delayed pulse signal S2b1 is again below the threshold voltage V ＩＨ is processed as a signal that is maintained in the Low state until the signal exceeds the threshold.

[0216] The 2a control pulse signal S4a is generated by the exclusive OR of the signal set of the input pulse signal S1 and the 2a delayed pulse signal S2b 1. Due to the relationship between the high and low states of the input pulse signal S1 and the 2a delayed pulse signal S2b 1 in the first XOR circuit 163a, the 2a control pulse signal S4a is a pulse signal that rises at time T1 and then falls at time T3.

[0217] As described above, the 2b delay circuit 11D included in the delay signal generating unit 10B is a circuit that corresponds to the function of delaying the falling edge of the input pulse signal, among the functions of the second delay circuit 11B in the second embodiment, but does not have the function of delaying the rising edge of the input pulse signal. Therefore, as shown in FIG. 17, the 2b delay pulse signal S2b2 rises from time T1 and remains for a delay time Td2 from time T4. ＯＦＦ It falls later at time T6.

[0218] The 2b delay pulse signal S2b2 generated by the 2b delay circuit 11D is input to the logic synthesis unit 16B. Specifically, the 2b delay pulse signal S2b2 is input to a second XOR circuit 163b. The input pulse signal S1 is also input to the second XOR circuit 163b. The second XOR circuit 163b performs an exclusive OR on the signal set of the input pulse signal S1 and the 2b delay pulse signal S2b2 to generate a 2b control pulse signal S4b.

[0219] In the example shown in FIG. 17, the signal level (voltage) of the input pulse signal S1 is equal to or exceeds the threshold voltage V ＩＨ At time T4, the threshold voltage V ＩＬ Therefore, in the second XOR circuit 163b, the input pulse signal S1 is in a High state from time T1 to time T4, and thereafter, the input pulse signal S1 again falls below the threshold voltage V ＩＨ The signal level (voltage) of the 2b delayed pulse signal S2b2 is processed as a signal that is maintained in a low state until it exceeds the threshold voltage V ＩＨ At time T6, the threshold voltage V ＩＬ Therefore, in the second XOR circuit 163b, the 2b delayed pulse signal S2b2 is in a High state from time T1 to time T6, and thereafter, the 2b delayed pulse signal S2b2 is again below the threshold voltage V ＩＨ is processed as a signal that is maintained in the Low state until the signal exceeds the threshold.

[0220] The 2b control pulse signal S4b is generated by the exclusive OR of the signal set of the input pulse signal S1 and the 2b delayed pulse signal S2b2. Due to the relationship between the high and low states of the input pulse signal S1 and the 2b delayed pulse signal S2b2 in the second XOR circuit 163b, the 2b control pulse signal S4b is a pulse signal that rises at time T4 and then falls at time T6.

[0221] In this way, the signal generating circuit 100A can generate the first control pulse signal S3, the second-a control pulse signal S4a, and the second-b control pulse signal S4b based on the same input pulse signal.

[0222] In the drive circuit 5B, the first control pulse signal S3 is input to the first GDIC 54a and output as a first output pulse signal. The first output pulse signal output from the first GDIC 54a is input to the first push-pull circuit 55a and output as a first gate signal. The first gate signal is input to the first output terminal 52 via the first gate resistor 56a. The first output terminal 52 is electrically connected to the gate of the first switching element 21, and therefore the first switching element 21 is driven by the first gate signal.

[0223] The first output pulse signal is an amplified pulse signal of the first control pulse signal, and therefore has a waveform similar to that of the first control pulse signal. The first gate signal is an amplified pulse signal of the first output pulse signal, and therefore has a waveform similar to that of the first output pulse signal. Therefore, the first gate signal has a waveform similar to that of the first control pulse signal S3.

[0224] In the drive circuit 5B, the 2a control pulse signal S4a is input to the 2a GDIC 541a and output as a 2a output pulse signal. The 2a output pulse signal output from the 2a GDIC 541a is input to the 2a push-pull circuit 551a and output as a 2a gate signal. The 2a gate signal is input to the 2a output terminal 53a via the 2a gate resistor 561a. The 2a output terminal 53a is electrically connected to the gate of the 2a switching element 22A, and therefore the 2a gate signal drives the 2a switching element 22A.

[0225] The 2a output pulse signal is an amplified pulse signal of the 2a control pulse signal, and therefore has a waveform similar to that of the 2a control pulse signal. The 2a gate signal is an amplified pulse signal of the 2a output pulse signal, and therefore has a waveform similar to that of the 2a output pulse signal. Therefore, the 2a gate signal has a waveform similar to that of the 2a control pulse signal S4a.

[0226] In the drive circuit 5B, the 2b control pulse signal S4b is input to a 2b GDIC 541b, and is output as a 2b output pulse signal. The 2b output pulse signal output from the 2b GDIC 541b is input to a 2b push-pull circuit 551b, and is output as a 2b gate signal. The 2b gate signal is input to a 2b output terminal 53b via a 2b gate resistor 561b. Since the 2b output terminal 53b is electrically connected to the gate of the 2b switching element 22B, the 2b gate signal drives the 2b switching element 22B.

[0227] The 2b output pulse signal is an amplified pulse signal of the 2b control pulse signal, and therefore has a waveform similar to that of the 2b control pulse signal. The 2b gate signal is an amplified pulse signal of the 2b output pulse signal, and therefore has a waveform similar to that of the 2b output pulse signal. Therefore, the 2b gate signal has a waveform similar to that of the 2b control pulse signal S4b.

[0228] The first switching element 21 is driven by a first gate signal having a waveform similar to that of the first control pulse signal S3, so it turns on at time T2 and turns off at time T5. The second-a switching element 22A is driven by a second-a gate signal having a waveform similar to that of the second-a control pulse signal S4a, so it turns on at time T1 and turns off at time T3. The second-b switching element 22B is driven by a second-b gate signal having a waveform similar to that of the second-b control pulse signal S4b, so it turns on at time T4 and turns off at time T6.

[0229] Because the first switching element 21, the 2-a switching element 22A, and the 2-b switching element 22B are driven as described above, the 2-a control pulse signal S4a and the 2-b control pulse signal S4b are signals for controlling the 2-a switching elements 22A and the 2-b switching elements 22B so that the on-state periods of the 2-a switching elements 22A and the 2-b switching elements 22B are shorter than the on-state period of the first switching element 21 and so that the on-state period of the 2-b switching element 22B occurs after the on-state period of the 2-a switching element 22A. Furthermore, the first control pulse signal S3 is a signal for controlling the first switching element 21 so that the first switching element 21 transitions from the off state to the on state during the on-state period of the 2-a switching element 22A and transitions from the on state to the off state during the on-state period of the 2-b switching element 22B.

[0230] The switch unit 20A is configured by connecting a first switching element 21, a second-a switching element 22A, and a second-b switching element 22B in parallel. Therefore, similar to the first embodiment, when any one of the first switching element 21, the second-a switching element 22A, and the second-b switching element 22B is in the on state, the switch unit 20A is in the on state, and when all of the first switching element 21, the second-a switching element 22A, and the second-b switching element 22B are in the off state, the switch unit 20A is in the off state. Therefore, as shown in FIG. 17 , the main circuit current I Ｍflows from time T1 to time T6.

[0231] The 2a delay circuit 11C included in the delay signal generating unit 10B is a circuit that corresponds to the function of delaying the rising edge of an input pulse signal, which is one of the functions of the second delay circuit 11B in the second embodiment. The 2a switching element 22A is driven in response to a 2a control pulse signal S4a generated based on a 2a delay pulse signal S2b1 from the 2a delay circuit 11C. The 2b delay circuit 11D included in the delay signal generating unit 10B is a circuit that corresponds to the function of delaying the falling edge of an input pulse signal, which is one of the functions of the second delay circuit 11B in the second embodiment. The 2b switching element 22B is driven in response to a 2b control pulse signal S4b generated based on a 2b delay pulse signal S2b2 from the 2b delay circuit 11D.

[0232] Therefore, in the third embodiment, the function of turning on and off the switch unit 20, which was performed by the second switching element 22 in the second embodiment, is shared by the second-a switching element 22A and the second-b switching element 22B. Therefore, the drive circuit 5B and the switch unit 20A have the same effects as those in the second embodiment.

[0233] The set of drive circuit 5B and switch unit 20A can be applied to the power conversion device 1 shown in Fig. 1 in place of the set of drive circuit 5 and switch unit 20. Since the drive circuit 5B and switch unit 20A have the same effects as in the second embodiment, the power conversion device 1 to which the set of drive circuit 5B and switch unit 20A is applied also has the same effects as in the second embodiment.

[0234] (Fourth Embodiment) Another example in which the switch unit has a plurality of first switching elements and a plurality of second switching elements will be described as the fourth embodiment. In the fourth embodiment, the first switching elements are Si-IGBTs and the second switching elements are SiC-MOSFETs. In the fourth embodiment, a configuration in which the switch unit has three first switching elements and three second switching elements will be described. Fig. 18 is a circuit diagram for explaining the fourth embodiment.

[0235] The switch unit 20B according to the fourth embodiment has three first switching elements 21A1, 21A2, and 21A3 and three second switching elements 22C1, 22C2, and 22C3. The three first switching elements 21A1, 21A2, and 21A3 have the same configuration and are Si-IGBTs, as in the first embodiment. The three second switching elements 22C1, 22C2, and 22C3 have the same configuration and are SiC-MOSFETs, as in the first embodiment.

[0236] The three first switching elements 21A1, 21A2, and 21A3 correspond to the first switching element 21 described in the first embodiment. The first switching elements 21A1, 21A2, and 21A3 have the same configuration. Therefore, the configuration of the first switching element 21A1 will be described, and descriptions of the configurations of the first switching elements 21A2 and 21A3 will be omitted.

[0237] The first switching element 21A1 has an element body 211 and a package 212 that houses the element body 211. The element body 211 is a Si-IGBT body (i.e., a bare chip of the Si-IGBT) mounted on a semiconductor substrate. Therefore, the element body 211 has a collector (first main terminal), an emitter (second main terminal), and a gate (control terminal). The first switching element 21A1 has a first terminal 213a, a second terminal 213b, and a third terminal 213c for externally connecting the element body 211 housed in the package 212. The first terminal 213a is electrically connected to the collector of the element body 211. The second terminal 213b is electrically connected to the emitter of the element body 211. The third terminal 213c is electrically connected to the gate of the element body 211.

[0238] The three second switching elements 22C1, 22C2, and 22C3 correspond to the second switching element 22 described in the first embodiment. The second switching elements 22C1, 22C2, and 22C3 have the same configuration. Therefore, the configuration of the second switching element 22C1 will be described, and descriptions of the configurations of the second switching elements 22C2 and 22C3 will be omitted.

[0239] The second switching element 22C1 has an element body 221 and a package 223 that houses the element body 221. The element body 221 is a SiC-MOSFET body (i.e., a bare chip of a SiC-MOSFET) mounted on a semiconductor substrate. Therefore, the element body 221 has a drain (first main terminal), a source (second main terminal), and a gate (control terminal). The second switching element 22C1 has a first terminal 224a, a second terminal 224b, and a third terminal 224c for externally connecting the element body 221 housed in the package 223. The first terminal 224a is electrically connected to the drain of the element body 221. The second terminal 224b is electrically connected to the source of the element body 221. The third terminal 224c is electrically connected to the gate of the element body 221.

[0240] The second switching element 22C1 may have a free wheel diode 222 housed in a package 223. The cathode of the free wheel diode 222 is electrically connected to the drain (or the first terminal 224a) of the element body 221, and the anode of the free wheel diode 222 is electrically connected to the source (or the second terminal 224b) of the element body 221. A parasitic diode included in the SiC-MOSFET body may be used as the free wheel diode.

[0241] The three first switching elements 21A1, 21A2, and 21A3 and the three second switching elements 22C1, 22C2, and 22C3 are connected in parallel between the node 20a and the node 20b.

[0242] The drive circuit 5C that drives the switch section 20B differs from the drive circuit 5 according to the first embodiment mainly in that it has three first output terminals 521a, 521b, and 521c and three second output terminals 531a, 531b, and 531c.

[0243] The drive circuit 5C includes a signal generation circuit 100, a first GDIC 54a, a second GDIC 54b, a first push-pull circuit 55a, a second push-pull circuit 55b, a first gate resistor 56a, and a second gate resistor 56b. The configurations and functions of the signal generation circuit 100, the first GDIC 54a, the second GDIC 54b, the first push-pull circuit 55a, the second push-pull circuit 55b, the first gate resistor 56a, and the second gate resistor 56b are the same as those in the first embodiment, and therefore will not be described again.

[0244] The three first output terminals 521a, 521b, and 521c are electrically connected to the first push-pull circuit 55a via the first gate resistor 56a. Specifically, the three first output terminals 521a, 521b, and 521c are electrically connected to a node between the first transistor Tr1 and the second transistor Tr2 of the first push-pull circuit 55a via the first gate resistor 56a. Therefore, the same first gate signal is input to the first output terminals 521a, 521b, and 521c.

[0245] The first output terminal 521a is electrically connected to the third terminal 213c of the first switching element 21A1. The first output terminal 521b is electrically connected to the third terminal 213c of the first switching element 21A2. The first output terminal 521c is electrically connected to the third terminal 213c of the first switching element 21A3. The same first gate signal is input to the first output terminals 521a, 521b, and 521c, and therefore the same first gate signal is input to the third terminal 213c of each of the first switching elements 21A1, 21A2, and 21A3. In other words, the first switching elements 21A1, 21A2, and 21A3 are driven by the same first gate signal.

[0246] The three second output terminals 531a, 531b, and 531c are electrically connected to the second push-pull circuit 55b via the second gate resistor 56b. Specifically, the three second output terminals 531a, 531b, and 531c are electrically connected to a node between the first transistor Tr1 and the second transistor Tr2 of the second push-pull circuit 55b via the second gate resistor 56b. Therefore, the same second gate signal is input to the second output terminals 531a, 531b, and 531c.

[0247] The second output terminal 531a is electrically connected to the third terminal 224c of the second switching element 22C1. The second output terminal 531b is electrically connected to the third terminal 224c of the second switching element 22C2. The second output terminal 531c is electrically connected to the third terminal 224c of the second switching element 22C3. Since the same second gate signal is input to the second output terminals 531a, 531b, and 531c, the same second gate signal is input to the third terminal 224c of each of the second switching elements 22C1, 22C2, and 22C3. In other words, the second switching elements 22C1, 22C2, and 22C3 are driven by the same second gate signal.

[0248] The signal generation circuit 100 included in the drive circuit 5C is the same as the signal generation circuit 100 described in the first embodiment, and therefore has the same effects as those in the first embodiment. Furthermore, the drive circuit 5C is the same as the drive circuit 5 described in the first embodiment, except that it outputs first gate signals from three first output terminals 521a, 521b, and 521c and outputs second gate signals from three second output terminals 531a, 531b, and 531c. Therefore, the drive circuit 5B also has the same effects as those in the drive circuit 5 described in the first embodiment.

[0249] The first switching elements 21A1, 21A2, and 21A3 included in the switch unit 20B and driven by the first gate signal correspond to the first switching element 21 described in the first embodiment, and the second switching elements 22C1, 22C2, and 22C3 driven by the second gate signal correspond to the second switching element 22 described in the first embodiment. Thus, the switch unit 20B corresponds to a configuration in which three first switching elements 21 and three second switching elements 22 are connected in parallel. Therefore, the switch unit 20B driven by the drive circuit 5A has the same effects as the switch unit 20 described in the first embodiment.

[0250] The set of switch unit 20B and drive circuit 5C described in the fourth embodiment can be applied to the power conversion device 1 shown in Fig. 1 in place of the drive circuit 5 and switch unit 20. As described above, the effects of switch unit 20B and drive circuit 5C are similar to those of switch unit 20 and drive circuit 5 in the first embodiment, and therefore the power conversion device 1 in which the set of switch unit 20B and drive circuit 5C is applied in place of drive circuit 5 and switch unit 20 also has the same effects as those in the first embodiment.

[0251] The switch section 20B has three first switching elements 21A1, 21A2, and 21A3 and three second switching elements 22C1, 22C2, and 22C3, which are connected in parallel, making it easier for a larger current to flow through the switch section 20B.

[0252] Fifth Embodiment A fifth embodiment will be described below, which illustrates yet another example in which the switch unit has a plurality of first switching elements and a plurality of second switching elements. In the fifth embodiment, the first switching elements are Si-IGBTs and the second switching elements are SiC-MOSFETs.

[0253] Fig. 19 is a circuit diagram for explaining the fifth embodiment. Fig. 19 shows a switch section 20C according to the fifth embodiment and a drive circuit 5C for driving the switch section 20C. The drive circuit 5C is the same as that in the fourth embodiment, and therefore a description of the drive circuit 5C will be omitted.

[0254] The switch unit 20C differs from the switch unit 20B described in the fourth embodiment mainly in that the first switching elements 21A1, 21A2, 21A3 and the second switching elements 22C1, 22C2, 22C3 described in the fourth embodiment are housed in a package 200. That is, the switch unit 20C is configured as a semiconductor module (or a switching module) including the first switching elements 21A1, 21A2, 21A3 and the second switching elements 22C1, 22C2, 22C3.

[0255] The package 200 has a first terminal 201, a second terminal 202, a third terminal 203a, a fourth terminal 203b, a fifth terminal 203c, a sixth terminal 204a, a seventh terminal 204b and an eighth terminal 204c for externally connecting the first switching elements 21A1, 21A2, 21A3 and the second switching elements 22C1, 22C2, 22C3 housed within the package 200.

[0256] The first terminal 201 is electrically connected to the node 20a. The second terminal 202 is electrically connected to the node 20b. The first terminal 201 may be the node 20a, and the second terminal 202 may be the node 20b.

[0257] The third terminal 203a is electrically connected to the third terminal 213c of the first switching element 21A1 and is also electrically connected to the first output terminal 521a of the drive circuit 5C, so that the first gate signal from the first output terminal 521a is input to the third terminal 213c of the first switching element 21A1.

[0258] The fourth terminal 203b is electrically connected to the third terminal 213c of the first switching element 21A2 and is also electrically connected to the first output terminal 521b of the drive circuit 5C, so that the first gate signal from the first output terminal 521b is input to the third terminal 213c of the first switching element 21A2.

[0259] The fifth terminal 203c is electrically connected to the third terminal 213c of the first switching element 21A3 and is also electrically connected to the first output terminal 521c of the drive circuit 5C, so that the first gate signal from the first output terminal 521c is input to the third terminal 213c of the first switching element 21A3.

[0260] The sixth terminal 204a is electrically connected to the third terminal 224c of the second switching element 22C1 and is also electrically connected to the second output terminal 531a of the drive circuit 5C, so that the second gate signal from the second output terminal 531a is input to the third terminal 224c of the second switching element 22C1.

[0261] The seventh terminal 204b is electrically connected to the third terminal 224c of the second switching element 22C2 and is also electrically connected to the second output terminal 531b of the drive circuit 5C. Therefore, the second gate signal from the second output terminal 531b is input to the third terminal 224c of the second switching element 22C2.

[0262] The eighth terminal 204c is electrically connected to the third terminal 224c of the second switching element 22C3 and is also electrically connected to the second output terminal 531c of the drive circuit 5C. Therefore, the second gate signal from the second output terminal 531c is input to the third terminal 224c of the second switching element 22C3.

[0263] The switch section 20C described in the fifth embodiment is the same as the switch section 20B according to the fourth embodiment, except that the first switching elements 21A1, 21A2, and 21A3 and the second switching elements 22C1, 22C2, and 22C3 are housed in a package 200. Furthermore, the drive circuit 5C is also the same as that of the fourth embodiment. Therefore, the switch section 20C driven by the drive circuit 5C has the same effects as those of the fourth embodiment.

[0264] The set of the switch unit 20C and the drive circuit 5C can be applied to the power conversion device 1 shown in Fig. 1 in place of the drive circuit 5 and the switch unit 20. The power conversion device 1 in which the set of the switch unit 20C and the drive circuit 5C is applied in place of the set of the drive circuit 5 and the switch unit 20 also has the same effects as those of the fourth embodiment.

[0265] Sixth Embodiment A modified example of the drive circuit will be described as a sixth embodiment. Fig. 20 is a circuit diagram for explaining the sixth embodiment.

[0266] The drive circuit 5D according to the sixth embodiment is a circuit for driving the switch section 20B described in the fourth embodiment. That is, the drive circuit 5D is a modified example of the drive circuit 5C.

[0267] Drive circuit 5D differs from drive circuit 5C described in the fourth embodiment mainly in that a set of a first GDIC, a first push-pull circuit, and a first gate resistor is provided corresponding to each of the three first output terminals 521a, 521b, and 521c, and a set of a second GDIC, a second push-pull circuit, and a second gate resistor is provided corresponding to each of the three second output terminals 531a, 531b, and 531c. Drive circuit 5D will be described focusing on this difference.

[0268] The drive circuit 5D includes a signal generation circuit 100. The configuration and function of the signal generation circuit 100 are the same as those in the first embodiment, and therefore a description thereof will be omitted.

[0269] The drive circuit 5D has a first GDIC 54a1, a first GDIC 54a2, and a first GDIC 54a3 that are electrically connected to the AND circuit 161 and receive the first output pulse signal from the AND circuit 161. The first GDIC 54a1, the first GDIC 54a2, and the first GDIC 54a3 are each connected between the first power supply potential line 61 and ground. The configuration of the first GDIC 54a1, the first GDIC 54a2, and the first GDIC 54a3 is the same as that of the first GDIC 54a described in the first embodiment, and each generates a first output pulse signal from the input first control pulse signal.

[0270] The drive circuit 5D has a first push-pull circuit 55a1 and a first gate resistor 56a1 provided in correspondence with the first GDIC 54a1, a first push-pull circuit 55a2 and a first gate resistor 56a2 provided in correspondence with the first GDIC 54a2, and a first push-pull circuit 55a3 and a first gate resistor 56a3 provided in correspondence with the first GDIC 54a3.

[0271] The first push-pull circuit 55a1, the first push-pull circuit 55a2, and the first push-pull circuit 55a3 are each connected between the second power supply potential line 62 and the ground. The configuration of the first push-pull circuit 55a1, the first push-pull circuit 55a2, and the first push-pull circuit 55a3 is the same as that of the first push-pull circuit 55a described in the first embodiment, and is configured by connecting a first transistor Tr1 and a second transistor Tr2 in series between the second power supply potential line 62 and the ground. The first push-pull circuit 55a1, the first push-pull circuit 55a2, and the first push-pull circuit 55a3 generate a first gate signal from the input first output pulse signal.

[0272] The first gate signal generated by the first push-pull circuit 55a1 is input to the first output terminal 521a via the first gate resistor 56a1. The first gate signal generated by the first push-pull circuit 55a2 is input to the first output terminal 521b via the first gate resistor 56a2. The first gate signal generated by the first push-pull circuit 55a3 is input to the first output terminal 521c via the first gate resistor 56a3.

[0273] An example of the resistance values ​​of the first gate resistor 56a1, the first gate resistor 56a2, and the first gate resistor 56a3 is the same as that of the first gate resistor 56 in the first embodiment. The first gate resistor 56a1, the first gate resistor 56a2, and the first gate resistor 56a3 may be the same gate resistance or may be different from one another.

[0274] The drive circuit 5D has second GDICs 54b1, 54b2, and 54b3 that are electrically connected to the OR circuit 162 and receive the second output pulse signal from the OR circuit 162. The second GDICs 54b1, 54b2, and 54b3 are each connected between the first power supply potential line 61 and ground. The configuration of the second GDICs 54b1, 54b2, and 54b3 is the same as that of the second GDIC 54b described in the first embodiment, and they generate a second output pulse signal from the input second control pulse signal.

[0275] The drive circuit 5D has a second push-pull circuit 55b1 and a second gate resistor 56b1 provided in correspondence with the second GDIC 54b1, a second push-pull circuit 55b2 and a second gate resistor 56b2 provided in correspondence with the second GDIC 54b2, and a second push-pull circuit 55b3 and a second gate resistor 56b3 provided in correspondence with the second GDIC 54b3.

[0276] The second push-pull circuits 55b1, 55b2, and 55b3 are each connected between the second power supply potential line 62 and ground. The configuration of the second push-pull circuits 55b1, 55b2, and 55b3 is the same as that of the second push-pull circuit 55b described in the first embodiment, and is configured by connecting a first transistor Tr1 and a second transistor Tr2 in series between the second power supply potential line 62 and ground. The second push-pull circuits 55b1, 55b2, and 55b3 generate a second gate signal from the input second output pulse signal.

[0277] The second gate signal generated by the second push-pull circuit 55b1 is input to the second output terminal 531a via the second gate resistor 56b1. The second gate signal generated by the second push-pull circuit 55b2 is input to the second output terminal 531b via the second gate resistor 56b2. The second gate signal generated by the second push-pull circuit 55b3 is input to the second output terminal 531c via the second gate resistor 56b3.

[0278] As with the drive circuit 5C, the drive circuit 5D having the above configuration can output first gate signals from the three first output terminals 521a, 521b, and 521c, and can output second gate signals from the three second output terminals 531a, 531b, and 531c. Therefore, the drive circuit 5D can drive the switch section 20B in the same way as the drive circuit 5C. In other words, the drive circuit 5D has the same effects as the drive circuit 5C.

[0279] The set of switch unit 20B and drive circuit 5D described in the sixth embodiment can be applied to the power conversion device 1 shown in Fig. 1 in place of the drive circuit 5 and switch unit 20. The power conversion device 1 in which the set of switch unit 20B and drive circuit 5D described in the sixth embodiment is applied in place of the set of drive circuit 5 and switch unit 20 has the same effects as the fourth embodiment.

[0280] The combination of the GDIC and the push-pull circuit (the GDIC, the push-pull circuit, and the gate resistor) provided in the downstream of the signal generating circuit 100 (specifically, in the downstream of the logic synthesis unit 16) functions as an amplifier of the control pulse signal generated by the signal generating circuit 100.

[0281] In the configuration of the drive circuit 5D, a set of a GDIC, a push-pull circuit, and a gate resistor is provided corresponding to each of the first switching elements 21A1, 21A2, and 21A3, and a set of a GDIC, a push-pull circuit, and a gate resistor is provided corresponding to each of the second switching elements 22C1, 22C2, and 22C3.

[0282] For example, corresponding to the first switching element 21A1, the drive circuit 5D has a first GDIC 54a1, a first push-pull circuit 55a1, and a first gate resistor 56a1. Corresponding to the second switching element 22C1, the drive circuit 5D has a second GDIC 54b1, a second push-pull circuit 55b1, and a second gate resistor 56b1. While the correspondence has been described using the first switching element 21A1 and the second switching element 22C1 as an example, the same applies to the first switching elements 21A2 and 21A3 and the second switching elements 22C2 and 22C3.

[0283] Therefore, in the configuration of drive circuit 5D, the amplification factor when the first gate signal is generated from the first control pulse signal can be adjusted in accordance with each of first switching elements 21A1, 21A2, and 21A3. Similarly, in the configuration of drive circuit 5D, the amplification factor when the second gate signal is generated from the second control pulse signal can be adjusted in accordance with each of second switching elements 22C1, 22C2, and 22C3.

[0284] Fig. 21 is a diagram for explaining a modification of the sixth embodiment. As shown in Fig. 21, the drive circuit 5D can be applied to the switch section 20C described in the fifth embodiment instead of the switch section 20B.

[0285] Seventh Embodiment As the seventh embodiment, a modified example of a signal generation circuit will be described. Fig. 22 is a circuit diagram for explaining the seventh embodiment. A drive circuit 5E shown in Fig. 22 has the same configuration as the drive circuit 5, except that it includes a signal generation circuit 100C instead of the signal generation circuit 100.

[0286] The signal generating circuit 100C includes a delay circuit 11E and a logic synthesis unit 16. The logic synthesis unit 16 is the same as in the first embodiment, and therefore a description thereof will be omitted.

[0287] The delay circuit 11E is composed of a resistor 132c and a capacitor 15c. An example of the resistance value of the resistor 132c is the same as that of the first resistor 132 in the first embodiment. An example of the capacitance of the capacitor 15c is the same as that of the capacitor 15 in the first embodiment.

[0288] A first end of the resistor 132c is electrically connected to the input terminal 51, and a second end (opposite to the first end) of the resistor 132c is electrically connected to a first end of the capacitor 15c. The second end (opposite to the first end) of the capacitor 15c is electrically connected to ground. A node between the resistor 132c and the capacitor 15c is electrically connected to an AND circuit 161 and an OR circuit 162.

[0289] In the above-described delay circuit configuration, a delay signal is generated in which the rising and falling edges of the input pulse signal are delayed by a delay time determined by the resistance value of resistor 132c and the capacitance of capacitor 15c. In the delay circuit 11E configuration, the delay times for the rising and falling edges of the input pulse signal are the same. In other words, the delay circuit 11E does not have the function of individually adjusting the delay time for the rising edge and the delay time for the falling edge of the input pulse signal. The delayed pulse signal generated by the delay circuit 11E is input to an AND circuit 161 and an OR circuit 162.

[0290] The signal generation circuit 100C is the same as the signal generation circuit 100 according to the first embodiment, except that it uses a delay circuit 11E instead of the delay circuit 11. Therefore, like the signal generation circuit 100, the signal generation circuit 100C can generate different first and second control pulse signals from a single input pulse signal.

[0291] The drive circuit 5E is the same as the drive circuit 5 according to the first embodiment, except that it uses a signal generation circuit 100C instead of the signal generation circuit 100. Therefore, like the drive circuit 5, the drive circuit 5E can generate a first gate signal from the first control pulse signal generated by the signal generation circuit 100C, and can generate a second gate signal from the second control pulse signal.

[0292] Therefore, the function and effect of the signal generation circuit 100C and the drive circuit 5E including the signal generation circuit 100C in terms of being able to generate different first control pulse signals and second control pulse signals and their corresponding first gate signals and second gate signals from a single input pulse signal is similar to that of the signal generation circuit 100 and the drive circuit 5 of the first embodiment.

[0293] The effects of driving the switch unit 20 by the drive circuit 5E and the effects of the power conversion device 1 in which the set of the drive circuit 5E and the switch unit 20 is applied instead of the set of the drive circuit 5 and the switch unit 20 shown in FIG. 1 are the same as those in the first embodiment.

[0294] The delay circuit 11E has a simpler configuration than, for example, the delay circuit 11 described in the first embodiment. Therefore, when there is no need to individually adjust the delay times of the rising and falling edges of the input pulse signal, the drive circuit 5C can be easily manufactured by employing the delay circuit 11E.

[0295] Eighth Embodiment As an eighth embodiment, a configuration example of a vehicle X to which the power conversion device 1 shown in Fig. 1 is applied will be described. Fig. 23 is a diagram showing a configuration example of a vehicle on which the power conversion device 1 is mounted.

[0296] The vehicle X includes an engine unit 81 with a generator, an ECU 82, a high-power DC / DC converter 83, a power conversion device 1, a motor 2, a drive device 84, a high-voltage battery 85, a DC / DC converter 86, and a power supply 87. For convenience of illustration, the mounting positions of the components in Fig. 23 differ from the actual positions. The vehicle X shown in Fig. 23 is a so-called series hybrid vehicle.

[0297] The generator-equipped engine section 81 includes a generator, a dedicated engine for generating electricity that drives the generator, and an engine ignition device 81a. Because the energy conversion efficiency of the engine varies greatly depending on the timing of ignition, the ignition timing must be controlled by the ECU 82 in consideration of the rotation angle of the crank that converts the reciprocating motion of the pistons in the cylinders into rotational motion and the required amount of electricity generation. For this reason, an engine ignition device 81a is provided for each cylinder of the engine.

[0298] The high-power DC / DC converter 83 converts DC power generated by the generator of the generator-equipped engine unit 81 into high-voltage DC power. The high-power DC / DC converter 83 supplies the high-voltage DC power to the power conversion device 1 and the high-voltage battery 85. The high-power DC / DC converter 83 can supply discharge power discharged from the high-voltage battery 85 to the power conversion device 1. The high-power DC / DC converter 83 can also charge the high-voltage battery 85 with regenerative power supplied from the power conversion device 1 when the vehicle X decelerates. Therefore, the high-power DC / DC converter 83, or the high-power DC / DC converter 83 and the high-voltage battery 85, function as the DC power supply unit 3 shown in FIG. 1 .

[0299] The power conversion device 1 receives DC power from a high-power DC / DC converter 83 and converts the received DC power into three-phase AC power. The power conversion device 1 is controlled by an ECU 82. Therefore, the ECU 82 functions as the external control device 7 shown in FIG. 1 . FIG. 23 schematically illustrates a configuration example of a vehicle X to which the power conversion device 1 is applied, and therefore illustrates a generator-equipped engine unit 81 and a high-power DC / DC converter 83 interposed between the ECU 82 and the power conversion device 1. However, the ECU 82 only needs to be electrically connected to the drive circuit 5 (see FIG. 1 ) of the power conversion device 1 so that an input pulse signal generated by the ECU 82 is supplied to the drive circuit 5 (see FIG. 1 ) included in the power conversion device 1. Therefore, the input pulse signal may be supplied from the ECU 82 to the power conversion device 1 using a communication line common to the generator-equipped engine unit 81, etc., or the input pulse signal may be supplied from the ECU 82 to the power conversion device 1 using a communication line independent of the generator-equipped engine unit 81, etc.

[0300] The motor 2 has a shaft and rotates the shaft using three-phase AC power supplied from the power conversion device 1 .

[0301] The drive device 84 transmits power generated by the rotation of the shaft of the motor 2 to the drive wheels of the vehicle X. In Fig. 23, the rear wheels of the vehicle X are the drive wheels, but the drive wheels are not limited to the rear wheels. In other words, the front wheels may be the drive wheels, or both the front and rear wheels may be the drive wheels.

[0302] The DC / DC converter 86 receives DC power from the high-power DC / DC converter 83 and converts the received DC power into low-voltage DC power. The power supply 87, which is a low-voltage battery, is charged with the low-voltage DC power output from the DC / DC converter 86. The discharge power discharged from the power supply 87 is supplied to the engine ignition device 81 a and the like.

[0303] The vehicle on which the power conversion device 1 according to the embodiment is mounted is not limited to a hybrid vehicle such as the vehicle X shown in FIG. 23, but may be any vehicle equipped with an engine.

[0304] According to the embodiment described above, it is possible to provide a technique that can generate a first control pulse signal and a second control pulse signal for controlling two switching elements with different characteristics from a single input pulse signal.

[0305] Various embodiments relating to one aspect of the present disclosure have been described above, but these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims.

[0306] In the various embodiments described above, a signal generating circuit included in a driver circuit and multiple GDICs packaged together may be configured as a new GDIC. Alternatively, the driver circuit described in the various embodiments may be used as a new GDIC.

[0307] The switch section may include elements other than the first switching element and the second switching element. For example, as in a switch section 20D shown in Fig. 24 , a freewheeling diode 24 may be connected in parallel to the first switching element 21 and the second switching element 22 between the node 20a and the node 20b. Alternatively, as in a switch section 20E shown in Fig. 25 , a Schottky barrier diode 25 may be connected in parallel to the first switching element 21 and the second switching element 22 between the node 20a and the node 20b.

[0308] The delay signal generating unit is configured to generate at least one delay pulse signal using a common input pulse signal for a first switching element and a second switching element that have different transition times between an on state, which is a conductive state, and an off state, which is a non-conductive state, and the logic synthesis unit is configured to generate a first control pulse signal for the first switching element and a second control pulse signal for the second switching element by performing different logic synthesis on two signal sets out of a plurality of signal sets defined by the at least one delay pulse signal and the input pulse signal.

[0309] In this case, different logic synthesis is performed on two of the multiple signal sets defined by at least one delayed pulse signal and an input pulse signal, so that different first and second control pulse signals can be generated from one input pulse signal.

[0310] Examples of the multiple signal sets defined by at least one delay pulse signal and an input pulse signal include a signal set of a delay pulse signal and an input pulse signal, two identical delay pulse signals, and two input pulse signals. When the delay signal generating unit generates delay pulse signals with different delay states, different delay pulse signals may be adopted as a signal set.

[0311] The logic synthesis unit may be configured to generate a second control pulse signal based on the set of a delay pulse signal and a control pulse signal or a set of delay pulse signals when generating a first control pulse signal based on a set of delay pulse signals and a control pulse signal, and may be configured to generate a second control pulse signal based on the set of delay pulse signals and a control pulse signal when generating a first control pulse signal based on a set of delay pulse signals.

[0312] The logical synthesis may be logical negation in addition to the logical product, logical sum, and exclusive sum shown above. For example, when the logical state of the delayed pulse signal needs to be inverted due to the characteristics of the circuit used, the logical negation can be used. Therefore, the logical synthesis unit may include at least two of an AND circuit, an OR circuit, an XOR circuit, and a NOT circuit, for example.

[0313] From the viewpoint of utilizing the high-speed switching characteristics of the SiC-MOSFET for turning on and off the switch section, the case where the first switching element is an SiC-IGBT and the second switching element is an SiC-MOSFET has been described. However, the first switching element may be an SiC-MOSFET and the second switching element may be an Si-IGBT.

[0314] When the delay circuit included in the delayed signal generating section includes a parallel circuit together with a capacitor, the parallel circuit may be a series circuit of a diode and a resistor, and a parallel circuit of a resistor, as illustrated.

[0315] In the various embodiments (including modified examples) described above, one or more elements of one embodiment may be combined with one or more elements of another embodiment.

[0316] Below, examples of features extracted from the description of this specification and the drawings are shown.

[0317] [A1] (First embodiment, FIG. 2) A signal generation circuit comprising: a delay signal generation unit (10) configured to generate at least one delay pulse signal using a common input pulse signal for a first switching element (21) and a second switching element (22) that have different transition times between an ON state, which is a conductive state, and an OFF state, which is a non-conductive state; and a logic synthesis unit (16) configured to generate a first control pulse signal for the first switching element and a second control pulse signal for the second switching element by performing different logic synthesis on two signal sets out of a plurality of signal sets defined by the at least one delay pulse signal and the input pulse signal, wherein the first control pulse signal is different from the input pulse signal, and the second control pulse signal is different from the input pulse signal and the first control pulse signal.

[0318] [A2] (First embodiment, FIG. 2, Seventh embodiment, FIG. 22) The signal generating circuit according to [A1], wherein the delay signal generating unit has at least one delay circuit (11, 11E) including a resistor (132, 142, 132c) and a capacitor (15, 15c).

[0319] [A3] (First embodiment, FIG. 2) The signal generating circuit according to [A1], wherein the delay signal generating unit has at least one delay circuit (11), and the delay circuit has: a resistor unit (12) having two signal paths connected in parallel and configured to have resistances for delaying the rising edge and the falling edge of the pulse of the input pulse signal; and a capacitor (15).

[0320] [A4] (First embodiment, FIG. 2; Second embodiment, FIG. 9) The signal generation circuit according to any one of [A1] to [A3], wherein the logic synthesis unit has at least two of an AND circuit (161), an OR circuit (162), and an XOR circuit (163) to perform different logic synthesis.

[0321] [A5] The signal generating circuit according to any one of [A1] to [A4], wherein the second switching element is a switching element whose transition time is shorter than that of the first switching element.

[0322] [A6] The signal generating circuit according to any one of [A1] to [A5], wherein the first switching element is an insulated gate bipolar transistor, and the second switching element is a metal oxide semiconductor field effect transistor.

[0323] [A7] The signal generating circuit according to any one of [A1] to [A6], wherein the logic synthesis unit is configured to generate the first control pulse signal and the second control pulse signal so that the second switching element is turned on before the first switching element is turned on, and the second switching element is turned off after the first switching element is turned off.

[0324] [A8] (First embodiment, FIG. 2; Second embodiment, FIG. 9) The signal generation circuit according to [A1], wherein the delay signal generation unit has a delay circuit (11) that generates the delay pulse signal, and the two signal sets are a set of the delay pulse signal and the input pulse signal or a set of the delay pulse signals themselves, and the logic synthesis unit (16, 16A) is configured to: when generating the first control pulse signal based on the set of the delay pulse signal and the input pulse signal, generate the second control pulse signal based on the set of the delay pulse signal and the input pulse signal or the set of the delay pulse signals themselves, and when generating the first control pulse signal based on the set of the delay pulse signals themselves, generate the second control pulse signal based on the set of the delay pulse signal and the input pulse signal.

[0325] [A9] (First embodiment, FIG. 2) The signal generating circuit according to [A8], wherein the delay circuit has a first terminal (12a) to which the input pulse signal is input and a second terminal (12b) electrically connected to the logic synthesis unit, and further has a parallel circuit (12) in which a first series circuit (13) of a first diode (131) and a first resistor (132) and a second series circuit (14) of a second diode (141) and a second resistor (142) are connected in parallel, and a capacitor (15) electrically connected between the second terminal and ground, wherein an anode of the first diode is electrically connected to the first terminal, the first resistor is disposed between a cathode of the first diode and the second terminal, the cathode of the second diode is electrically connected to the second terminal, and the second resistor is disposed between an anode of the second diode and the first terminal.

[0326] [A10] (First embodiment, FIG. 2) The signal generating circuit according to [A9], wherein the logic synthesis unit has: an AND circuit (161) that receives the delayed pulse signal and the input pulse signal as inputs and outputs the first control pulse signal; and an OR circuit (162) that receives the delayed pulse signal and the input pulse signal as inputs and outputs the second control pulse signal.

[0327] [A11] (Third embodiment, FIGS. 16 and 17) The signal generating circuit according to any one of [A1] to [A6], wherein the logic synthesis unit is configured to generate the first control pulse signal and the second control pulse signal so that the first switching element is turned on in a first on state of the two on states of the second switching element, and the first switching element is turned off in a second on state of the two on states of the second switching element that is subsequent to the first on state.

[0328] [A12] (Second embodiment, FIG. 9) The signal generating circuit according to [A1], wherein the delay signal generating unit (10A) has: a first delay circuit (11A) that generates a first delay pulse signal; and a second delay circuit (11B) that generates a second delay pulse signal different from the first delay pulse signal; and the logic synthesis unit (16A) generates the first control pulse signal based on a set of the first delay pulse signals, and generates the second control pulse signal based on a set of the second delay pulse signal and the input pulse signal.

[0329] [A13] (Second embodiment, FIG. 9) The first delay circuit (11B) has a first terminal (12c) to which the input pulse signal is input and a second terminal (12d) electrically connected to the logic synthesis unit, and includes a first parallel circuit (12A) in which a first series circuit (13A) of a first diode (131a) and a first resistor (132a) and a second series circuit (14A) of a second diode (141a) and a second resistor (142a) are connected in parallel, and a first capacitor (15a) electrically connected between the second terminal and ground, wherein an anode of the first diode is connected to the first terminal, the first resistor is disposed between a cathode of the first diode and the second terminal, an anode of the second diode is connected to the second terminal, and the second resistor is disposed between a cathode of the second diode and the first terminal, and the second delay circuit (11B) the signal generating circuit according to [A12], comprising: a third terminal (12e) to which the input pulse signal is input; and a fourth terminal (12f) electrically connected to the logic synthesis unit; a second parallel circuit (12B) in which a third series circuit (13B) of a third diode (131b) and a third resistor (132b) and a fourth series circuit (14B) of a fourth diode (141b) and a fourth resistor (142b) are connected in parallel; and a second capacitor (15b) electrically connected between the fourth terminal and ground, wherein an anode of the third diode is connected to the third terminal, the third resistor is disposed between a cathode of the third diode and the fourth terminal, an anode of the fourth diode is connected to the fourth terminal, and the fourth resistor is disposed between a cathode of the fourth diode and the third terminal.

[0330] [A14] (Second embodiment, FIG. 9) The signal generating circuit according to [A12] or [A13], wherein the logic synthesis unit (16) has: an AND circuit (161) that receives the two first delay pulse signals as input and outputs the first control pulse signal; and an XOR circuit (162) that receives the second delay pulse signal and the input pulse signal as input and outputs the second control pulse signal.

[0331] [A15] (Third embodiment, FIG. 16) The delay signal generating unit (10B) is configured to generate a first delay pulse signal for the first switching element and two second delay pulse signals for the two second switching elements (22A, 22B), The logic synthesis unit (16B) is configured to generate the first control pulse signal and the two second control pulse signals for the two second switching elements by performing logic synthesis on three signal sets out of the plurality of signal sets defined by the first delay pulse signal, the two second delay pulse signals, and the input pulse signal, The logic synthesis unit performs different logic synthesis on at least two of the three signal sets, A second a delay pulse signal out of the two second delay pulse signals is different from the first delay pulse signal and is a signal for a second a switching element out of the two second switching elements, the 2b delay pulse signal of the two second delay pulse signals is different from the first delay pulse signal and the 2a delay pulse signal and is a signal for the 2b switching element of the two second switching elements; the 2a control pulse signal of the two second control pulse signals is a signal for the 2a switching element; the 2b control pulse signal of the two second control pulse signals is a signal for the 2b switching element; the 2a control pulse signal and the 2b control pulse signal are signals for controlling the 2a switching element and the 2b switching element such that an on-state period of the 2a switching element and the 2b switching element is shorter than an on-state period of the first switching element and such that an on-state period of the 2b switching element occurs after an on-state period of the 2a switching element; the first control pulse signal is a signal for controlling the first switching element so as to transition the first switching element from an off state to an on state during a period in which the second a switching element is in an on state, and to transition the first switching element from an on state to an off state during a period in which the second b switching element is in an on state.A signal generating circuit according to any one of [A1] to [A7].

[0332] [A16] (Third embodiment, FIG. 16) The delay signal generating unit (16B) includes: a first delay circuit (11A) that generates the first delay pulse signal; a 2a delay circuit (11C) that generates the 2a delay pulse signal; and a 2b delay circuit (11D) that generates the 2b delay pulse signal, wherein the first delay circuit includes: a first terminal (12c) to which the input pulse signal is input and a second terminal (12d) electrically connected to the logic synthesis unit, and a first parallel circuit (12A) in which a first series circuit (13A) of a first diode (132a) and a first resistor (132a) and a second series circuit (14A) of a second diode (141a) and a second resistor (142a) are connected in parallel; and a first capacitor (15a) electrically connected between the second terminal and ground, wherein the anode of the first diode is connected to the first terminal, the first resistor is disposed between the cathode of the first diode and the second end, the cathode of the second diode is connected to the second end, and the second resistor is disposed between the anode of the second diode and the first end, the 2a delay circuit has a 3a end (121a) to which the input pulse signal is input and a 3b end (121b) electrically connected to the logic synthesis unit, and has a 2a parallel circuit (12C) in which a 3a series circuit (13B) of a 3a diode (131b) and a 3a resistor (132b) and a 3b diode (141b) are connected in parallel, and a 2a capacitor (15b) electrically connected between the 3b end and ground, the anode of the 3a diode is connected to the 3a end, and the 3a resistor is disposed between the cathode of the 3a diode and the 3b end, The cathode of the 3b diode is connected to the 3a terminal, and the anode of the 3b diode is connected to the 3b terminal; and the 2b delay circuit isthe signal generating circuit according to [A15], comprising: a 3c terminal (122a) to which the input pulse signal is input; and a 3d terminal (122b) electrically connected to the logic synthesis unit; a 2b parallel circuit (12D) in which a 3b series circuit (14B) of a 3c diode (141b) and a 3b resistor (142b) and a 3d diode (131b) are connected in parallel; and a 2b capacitor (15b) electrically connected between the 3d terminal and ground; wherein an anode of the 3d diode is connected to the 3c terminal and a cathode of the 3d diode is connected to the 3d terminal; an anode of the 3c diode is connected to the 3d terminal; and the 3b resistor is arranged between the cathode of the 3c diode and the 3c terminal.

[0333] [A17] (Third embodiment, FIG. 16) The signal generating circuit according to [A15] or [A16], wherein the logic synthesis unit (16B) has: an AND circuit (161) that receives as input the first delay pulse signal and the input pulse signal and outputs the first control pulse signal; a first XOR circuit (163a) that receives as input the 2a delay pulse signal and the input pulse signal and outputs the 2a control pulse signal; and a second XOR circuit (163b) that receives as input the 2b delay pulse signal and the input pulse signal and outputs the 2b control pulse signal.

[0334] [A18] (Second embodiment, FIG. 2) A drive circuit comprising: the signal generation circuit (100) according to any one of [A1] to [A14]; a first driver (54a) that generates a first output pulse signal for driving the first switching element in response to the first control pulse signal generated by the signal generation circuit; and a second driver (54b) that generates a second output pulse signal for driving the second switching element in response to the second control pulse signal generated by the signal generation circuit.

[0335] [A19] (Second embodiment, FIG. 2) The drive circuit according to [A18], comprising: a first push-pull circuit (55a) driven by the first output pulse signal to generate a first drive pulse signal for driving the first switching element; and a second push-pull circuit (55b) driven by the second output pulse signal to generate a second drive pulse signal for driving the second switching element.

[0336] [A20] (First embodiment, FIGS. 1 and 2) A power conversion device comprising: an inverter circuit (4) in which two switch units that can be switched between an on state that is a conductive state and an off state that is a non-conductive state have at least one leg (41u, 41v, 41w) connected in series between a high potential wiring (6a) and a low potential wiring (6b), and connection points (42u, 42v, 42w) of the two switch units are AC input / output points; and a drive circuit according to [A18] that is provided for each of the two switch units, wherein each of the two switch units has: the first switching element (21); and the second switching element (22) that is connected in parallel with the first switching element.

[0337] [A21] (Third embodiment, FIG. 16) A drive circuit comprising: a signal generation circuit (100B) according to any one of [A15] to [A17]; a first driver (54a) that generates a first output pulse signal for driving the first switching element in response to the first control pulse signal generated by the signal generation circuit; a second a driver (541a) that generates a second a output pulse signal for driving the second a switching element (22A) in response to the second a control pulse signal generated by the signal generation circuit; and a second b driver (541b) that generates a second b output pulse signal for driving the second b switching element in response to the second b control pulse signal generated by the signal generation circuit.

[0338] [A22] (Third embodiment, FIG. 16) The drive circuit according to [A21], comprising: a first push-pull circuit (55a) driven by the first output pulse signal to generate a first drive pulse signal for driving the first switching element; a second a push-pull circuit (551a) driven by the second a output pulse signal to generate a second a drive pulse signal for driving the second a switching element; and a second b push-pull circuit (551b) driven by the second b output pulse signal to generate a second b drive pulse signal for driving the second b switching element.

[0339] [A23] (FIG. 1) A power conversion device comprising: an inverter circuit (4) in which two switch units that can be switched between an on state that is a conductive state and an off state that is a non-conductive state have at least one leg connected in series between a high potential wiring and a low potential wiring, and a connection point of the two switch units is an AC input / output point; and a drive circuit according to [A21] or [A22] that is provided corresponding to each of the two switch units, wherein each of the two switch units has: the first switching element, and the second a switching element and the second b switching element that are connected in parallel with the first switching element.

[0340] [A24] A vehicle comprising: the power conversion device according to [A20] or [A23]; and a motor driven by the power conversion device.

[0341] REFERENCE SIGNS LIST 1... Power conversion device 2... Motor (rotating electric machine) 4... Inverter circuit 5, 5A, 5B, 5C, 5D, 5E... Drive circuit 6a... High potential wiring 6b... Low potential wiring 10, 10A, 10B... Delay signal generation unit 11, 11E... Delay circuit 11A... First delay circuit 11B... Second delay circuit 11C... 2a delay circuit 11D... 2b delay circuit 12... Parallel circuit (resistance unit) 12A... First parallel circuit (resistance unit) 12B... Second parallel circuit (resistance unit) 12C... 2a parallel circuit 12D... 2b parallel circuit 12a, 12c... Node (first terminal) 12b, 12d... Node (second terminal) 12e... Node (third terminal) 12f... Node (fourth terminal) 13, 13A... First series circuit 13B...Third series circuit (3a-th series circuit) 14, 14A...Second series circuit 14B...Fourth series circuit (3b-th series circuit) 15, 15c, 43...Capacitor 15a...First capacitor 15b...Second capacitor (2a-th capacitor) 15b...Second capacitor (2b-th capacitor) 16, 16A, 16B...Logic synthesis unit 20, 20A, 20B, 20C, 20D, 20E...Switch unit 21, 21A, 21A1, 21A2, 21A3...First switching element 22...Second switching element 22A...2a-th switching element 22B...2b-th switching element 22A1, 22A2, 22A3, 22C1, 22C2, 22C3, 22C4...Second switching element 41u, 41v, 41w...Leg 42u, 42v, 42w...nodes (connection points) 55a, 55a1, 55a2, 55a3...first push-pull circuit 55b, 55b1, 55b2, 55b3...second push-pull circuit 100, 100A, 100B, 100C...signal generating circuit 121a...node (3a terminal) 121b...node (3b terminal) 122a...node (3c terminal) 122b...node (3d terminal) 131, 131a...first diode 131b...third diode (3a diode) 131b...third diode (3c diode) 132...resistor 132a...first resistor 132b...third resistor (3a resistor) 132c...resistor 141, 141a...second diode 141b...fourth diode (3b diode) 141b...fourth diode (3d diode) 142,142a...second resistor 142b...fourth resistor (third b resistor) 161...AND circuit 162...OR circuit 163...XOR circuit 163a...first XOR circuit 163b...second XOR circuit 551a...second a-push-pull circuit 551b...second b-push-pull circuit 54a, 54a1, 54a2, 54a3...first GDIC (first driver) 54b, 54b1, 52b2, 54b3...second GDIC (second driver) 541a...second a-GDIC (second a-driver) 541b...second b-GDIC (second b-driver) S1...input pulse signal S2...delayed pulse signal S2a...first delayed pulse signal S2b...second delayed pulse signal S2b1...second a-delayed pulse signal S2b2...2nd b delayed pulse signal S3...1st control pulse signal S4...2nd control pulse signal S4a...2nd a control pulse signal S4b...2nd b control pulse signal X...vehicle.

Claims

1. A signal generating circuit comprising: a delay signal generating unit configured to generate at least one delay pulse signal using a common input pulse signal for a first switching element and a second switching element having different transition times between an on state, which is a conductive state, and an off state, which is a non-conductive state; and a logic synthesis unit configured to generate a first control pulse signal for the first switching element and a second control pulse signal for the second switching element by performing different logic synthesis on two signal sets out of a plurality of signal sets defined by at least one of the delay pulse signal and the input pulse signal, wherein the first control pulse signal is different from the input pulse signal, and the second control pulse signal is different from the input pulse signal and the first control pulse signal.

2. The signal generating circuit according to claim 1, wherein the delay signal generating section has at least one delay circuit including a resistor and a capacitor.

3. The signal generating circuit according to claim 1, wherein the delay signal generating section has at least one delay circuit, the delay circuit having: a resistor section in which two signal paths are connected in parallel and configured to have resistances for delaying the rising edge and for delaying the falling edge of the pulse of the input pulse signal; and a capacitor.

4. The signal generating circuit according to any one of claims 1 to 3, wherein the logic synthesis section has at least two of an AND circuit, an OR circuit, and an XOR circuit to perform different logic synthesis operations.

5. The signal generating circuit according to any one of claims 1 to 4, wherein the second switching element is a switching element whose transition time is shorter than that of the first switching element.

6. The signal generating circuit according to any one of claims 1 to 5, wherein the first switching element is an insulated gate bipolar transistor, and the second switching element is a metal oxide semiconductor field effect transistor.

7. A signal generating circuit as claimed in any one of claims 1 to 6, wherein the logic synthesis unit is configured to generate the first control pulse signal and the second control pulse signal so that the second switching element is turned on before the first switching element is turned on and the second switching element is turned off after the first switching element is turned off.

8. The signal generating circuit of claim 1, wherein the delay signal generating section has a delay circuit which generates the delayed pulse signal, and the two signal sets are a set of the delayed pulse signal and the input pulse signal or a set of the delayed pulse signals themselves, and the logic synthesis section is configured to, when generating the first control pulse signal based on the set of the delayed pulse signal and the input pulse signal, generate the second control pulse signal based on the set of the delayed pulse signal and the input pulse signal or the set of the delayed pulse signals themselves, and when generating the first control pulse signal based on the set of the delayed pulse signals themselves, generate the second control pulse signal based on the set of the delayed pulse signal and the input pulse signal.

9. The signal generating circuit according to claim 8, wherein the delay circuit has a first end to which the input pulse signal is input and a second end electrically connected to the logic synthesis section, and comprises a parallel circuit in which a first series circuit of a first diode and a first resistor and a second series circuit of a second diode and a second resistor are connected in parallel, and a first capacitor electrically connected between the second end and ground, wherein an anode of the first diode is electrically connected to the first end, the first resistor is disposed between a cathode of the first diode and the second end, a cathode of the second diode is electrically connected to the second end, and the second resistor is disposed between an anode of the second diode and the first end.

10. The signal generating circuit according to claim 9, wherein the logic synthesis unit has: an AND circuit which receives as input the delayed pulse signal and the input pulse signal and outputs the first control pulse signal; and an OR circuit which receives as input the delayed pulse signal and the input pulse signal and outputs the second control pulse signal.

11. A signal generating circuit as claimed in any one of claims 1 to 6, wherein the logic synthesis unit is configured to generate the first control pulse signal and the second control pulse signal so that the first switching element is turned on in a first on state of the two on states of the second switching element, and the first switching element is turned off in a second on state of the two on states of the second switching element that is subsequent to the first on state.

12. The signal generating circuit of claim 1, wherein the delay signal generating section has a first delay circuit that generates a first delay pulse signal, and a second delay circuit that generates a second delay pulse signal different from the first delay pulse signal, and the logic synthesis section generates the first control pulse signal based on a set of the first delay pulse signals, and generates the second control pulse signal based on a set of the second delay pulse signal and the input pulse signal.

13. The first delay circuit has a first terminal to which the input pulse signal is input and a second terminal electrically connected to the logic synthesis unit, and comprises a first parallel circuit in which a first series circuit of a first diode and a first resistor and a second series circuit of a second diode and a second resistor are connected in parallel; and a first capacitor electrically connected between the second terminal and ground, wherein an anode of the first diode is connected to the first terminal, the first resistor is disposed between a cathode of the first diode and the second terminal, an anode of the second diode is connected to the second terminal, and the second resistor is disposed between a cathode of the second diode and the first terminal; the second delay circuit has a third terminal to which the input pulse signal is input and a fourth terminal electrically connected to the logic synthesis unit, and comprises a second parallel circuit in which a third series circuit of a third diode and a third resistor and a fourth series circuit of a fourth diode and a fourth resistor are connected in parallel; and a second capacitor electrically connected between the fourth terminal and ground, 13. The signal generating circuit according to claim 12, wherein an anode of the third diode is connected to the third end, the third resistor is disposed between a cathode of the third diode and the fourth end, an anode of the fourth diode is connected to the fourth end, and the fourth resistor is disposed between a cathode of the fourth diode and the third end.

14. The signal generating circuit according to claim 12 or 13, wherein the logic synthesis unit has: an AND circuit which receives the two first delayed pulse signals as inputs and outputs the first control pulse signal; and an XOR circuit which receives the second delayed pulse signal and the input pulse signal as inputs and outputs the second control pulse signal.

15. The delay signal generating unit is configured to generate a first delay pulse signal for the first switching element and two second delay pulse signals for the two second switching elements; the logic synthesis unit is configured to generate the first control pulse signal and the two second control pulse signals for the two second switching elements by performing logic synthesis on three of the multiple signal sets defined by the first delay pulse signal, the two second delay pulse signals, and the input pulse signal; the logic synthesis unit performs different logic synthesis on at least two of the three signal sets; a 2a delay pulse signal of the two second delay pulse signals is different from the first delay pulse signal and is a signal for the 2a switching element of the two second switching elements; and a 2b delay pulse signal of the two second delay pulse signals is different from the first delay pulse signal and the 2a delay pulse signal and is a signal for the 2b switching element of the two second switching elements; 8. The signal generating circuit according to claim 1, wherein a 2-a control pulse signal of the two second control pulse signals is a signal for the 2-a switching element, and a 2-b control pulse signal of the two second control pulse signals is a signal for the 2-b switching element, and the 2-a control pulse signal and the 2-b control pulse signal are signals for controlling the 2-a switching element and the 2-b switching element such that an on-state period of the 2-a switching element and the 2-b switching element is shorter than an on-state period of the first switching element and a on-state period of the 2-b switching element occurs after the on-state period of the 2-a switching element, and the first control pulse signal is a signal for controlling the first switching element such that the first switching element is transitioned from an off state to an on state during the on-state period of the 2-a switching element and the first switching element is transitioned from an on state to an off state during the on-state period of the 2-b switching element.

16. The delay signal generating section includes a first delay circuit that generates the first delayed pulse signal, a second a delay circuit that generates the second a delayed pulse signal, and a second b delay circuit that generates the second b delayed pulse signal, the first delay circuit having a first end to which the input pulse signal is input and a second end electrically connected to the logic synthesis section, a first parallel circuit in which a first series circuit of a first diode and a first resistor and a second series circuit of a second diode and a second resistor are connected in parallel, and a first capacitor electrically connected between the second end and ground, the anode of the first diode being connected to the first end, the first resistor being disposed between the cathode of the first diode and the second end, the cathode of the second diode being connected to the second end, and the second resistor being disposed between the anode of the second diode and the first end, the 2a delay circuit includes the 2b delay circuit has a 3c terminal to which the input pulse signal is input and a 3d terminal electrically connected to the logic synthesis unit, a 2a parallel circuit in which a 3a series circuit of a 3a diode and a 3a resistor and a 3b diode are connected in parallel, and a 2a capacitor electrically connected between the 3b terminal and ground, wherein an anode of the 3a diode is connected to the 3a terminal, and the 3a resistor is disposed between a cathode of the 3a diode and the 3b terminal, a cathode of the 3b diode is connected to the 3a terminal and an anode of the 3b diode is connected to the 3b terminal, and the 2b delay circuit has a 3c terminal to which the input pulse signal is input and a 3d terminal electrically connected to the logic synthesis unit, a 2b parallel circuit in which a 3b series circuit of a 3c diode and a 3b resistor and a 3d diode are connected in parallel, and a 2b capacitor electrically connected between the 3d terminal and ground, an anode of the 3d diode is connected to the 3c end, a cathode of the 3d diode is connected to the 3d end, and an anode of the 3c diode is connected to the 3d end;The signal generating circuit according to claim 15 , wherein the 3b resistor is disposed between the cathode of the 3c diode and the 3c terminal.

17. The signal generating circuit according to claim 15 or 16, wherein the logic synthesis unit has: an AND circuit which receives as input the first delayed pulse signal and the input pulse signal and outputs the first control pulse signal; a first XOR circuit which receives as input the 2a delayed pulse signal and the input pulse signal and outputs the 2a control pulse signal; and a second XOR circuit which receives as input the 2b delayed pulse signal and the input pulse signal and outputs the 2b control pulse signal.

18. A drive circuit comprising: a signal generating circuit according to any one of claims 1 to 14; a first driver that generates a first output pulse signal for driving the first switching element in response to the first control pulse signal generated by the signal generating circuit; and a second driver that generates a second output pulse signal for driving the second switching element in response to the second control pulse signal generated by the signal generating circuit.

19. The drive circuit of claim 18, comprising: a first push-pull circuit driven by the first output pulse signal to generate a first drive pulse signal for driving the first switching element; and a second push-pull circuit driven by the second output pulse signal to generate a second drive pulse signal for driving the second switching element.

20. A power conversion device comprising: an inverter circuit in which two switch sections that can be switched between an on state, which is a conductive state, and an off state, which is a non-conductive state, have at least one leg connected in series between a high potential wiring and a low potential wiring, and a connection point of the two switch sections is an AC input / output point; and a drive circuit as described in claim 18 that is provided for each of the two switch sections, wherein each of the two switch sections has: the first switching element; and the second switching element that is connected in parallel with the first switching element.

21. A drive circuit comprising: a signal generating circuit according to any one of claims 15 to 17; a first driver that generates a first output pulse signal for driving the first switching element in response to the first control pulse signal generated by the signal generating circuit; a second a driver that generates a second a output pulse signal for driving the second a switching element in response to the second a control pulse signal generated by the signal generating circuit; and a second b driver that generates a second b output pulse signal for driving the second b switching element in response to the second b control pulse signal generated by the signal generating circuit.

22. The drive circuit of claim 21, comprising: a first push-pull circuit driven by the first output pulse signal to generate a first drive pulse signal for driving the first switching element; a seconda push-pull circuit driven by the seconda output pulse signal to generate a seconda drive pulse signal for driving the seconda switching element; and a secondb push-pull circuit driven by the secondb output pulse signal to generate a secondb drive pulse signal for driving the secondb switching element.

23. A power conversion device comprising: an inverter circuit in which two switch sections that can be switched between an on state, which is a conductive state, and an off state, which is a non-conductive state, have at least one leg connected in series between a high potential wiring and a low potential wiring, and a connection point of the two switch sections is an AC input / output point; and a drive circuit as recited in claim 21 provided corresponding to each of the two switch sections, wherein each of the two switch sections has: the first switching element, and the second a switching element and the second b switching element connected in parallel with the first switching element.

24. A vehicle comprising: a power conversion device according to claim 20 or 23; and a motor driven by the power conversion device.

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