Semiconductor device

Abstract

Provided is a semiconductor device capable of improving heat dissipation as a whole thereof and suppressing an increase in on-voltage of an IGBT region.　This semiconductor device comprises: a chip having IGBT regions and diode regions; a lead frame electrically connected to the upper surface of the chip with solder therebetween; and an insulating substrate electrically connected to the lower surface of the chip with solder therebetween. The IGBT regions and the diode regions are alternately arranged in the chip. The cell width of an IGBT region of a part electrically connected to the lead frame with the solder therebetween is wider than the cell width of an IGBT region of another part.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device in which an IGBT region and a diode region are mounted on the same chip.

[0002] A semiconductor device disclosed in Patent Document 1 is known as a reverse conduction IGBT (hereinafter referred to as "RC-IGBT") that has an IGBT (Insulated Gate Bipolar Transistor) region and a diode region connected in antiparallel to the IGBT region mounted on the same chip.

[0003] For example, the abstract of the document lists a solution to the problem of "providing a semiconductor device (semi-hybrid RC-IGBT) in which dedicated IGBT cell regions and diode cell regions are alternately arranged adjacent to each other on a semiconductor substrate, in which snapback in the IGBT cell region can be suppressed without impairing the advantages of high breakdown resistance and low loss." The solution is "a semiconductor device 100 in which a plurality of strip-shaped IGBT cell regions and a plurality of diode cell regions are alternately arranged adjacent to each other, in which the plurality of IGBT cell regions are composed of narrow strip-shaped narrow strip-width regions 10a and at least one wide strip-width region 10b wider than the narrow strip-width region 10a, in which each first region 1a, 1b on the back surface side of the plurality of IGBT cell regions is connected by a bridge region 5a formed of P-type conductivity in the same layer." Also, FIG. 1 and other figures of the same document disclose a semiconductor device in which IGBT cell regions and diode cell regions are alternately arranged, and the IGBT cell region has two regions: a narrow strip width region 10a and a wide strip width region 10b.

[0004] JP 2013-138069 A

[0005] Although not specifically mentioned in Patent Document 1, in an RC-IGBT, the IGBT region is cooled by dissipating Joule heat generated when current is passed through the IGBT region to the adjacent diode region, and the diode region is cooled by dissipating Joule heat generated when current is passed through the diode region to the adjacent IGBT region. Therefore, in an RC-IGBT, if the boundary area between the IGBT region and the diode region is increased by, for example, increasing the number of boundaries between the two regions, the thermal resistance during heat dissipation from one region to the other can be reduced, and the heat dissipation performance of the RC-IGBT as a whole can be improved.

[0006] Here, in the IGBT region of the RC-IGBT, a positive voltage is applied between the collector and emitter, and during the period when the gate voltage is on, carriers (holes) are accumulated in the drift layer to reduce the drift layer resistance, thereby reducing the on-voltage.

[0007] However, if the boundary area between the IGBT region and the diode region is increased to improve the heat dissipation of the RC-IGBT, carriers accumulated in the drift layer of the IGBT region when current is applied to the IGBT region are more likely to be discharged from the body layer of the diode region, and electrons accumulated in the drift layer of the IGBT region are more likely to be discharged from the cathode layer of the diode region. As a result, carrier accumulation in the IGBT region becomes insufficient at the boundary between the IGBT region and the diode region, and the drift layer resistance increases, resulting in a problem of an increase in the on-voltage of the IGBT region.

[0008] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device that can suppress an increase in the on-voltage of the IGBT region while improving the heat dissipation performance of the device as a whole.

[0009] In order to solve the above problems, the semiconductor device of the present invention comprises a chip having an IGBT region and a diode region, a lead frame electrically connected to the top surface of the chip via solder, and an insulating substrate electrically connected to the bottom surface of the chip via solder, wherein the IGBT regions and the diode regions are arranged alternately within the chip, and the cell width of the IGBT region in the portion electrically connected to the lead frame via the solder is wider than the cell width of the IGBT region in other portions.

[0010] According to the semiconductor device of the present invention, it is possible to improve the heat dissipation performance of the entire device and also to suppress an increase in the on-voltage of the IGBT region.

[0011] 1 is a perspective view of the appearance of a semiconductor device according to a first embodiment; 2 is a schematic plan view of a main part of a chip according to a first embodiment, viewed from above; 3 is a cross-sectional view of the semiconductor device according to a first embodiment; 4 is a diagram showing the transfer of Joule heat when current is applied to an IGBT region of the semiconductor device according to a first embodiment; 5 is a schematic plan view of a main part of a chip according to a second embodiment, viewed from above;

[0012] Hereinafter, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

[0013] First, a semiconductor device 100 according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG.

[0014] 1 is a perspective view of the appearance of a semiconductor device 100 of this embodiment. As shown in this figure, the semiconductor device 100 has a chip 1, an insulating substrate 2, and a lead frame 3. Each of these will be described below in turn.

[0015] The insulating substrate 2 is a rigid body in which a desired number and shape of metal wiring 2b are arranged on the upper surface of a ceramic insulating plate 2a. The lower surface of the chip 1 and the upper surface of the metal wiring 2b are electrically connected via solder 4.

[0016] The lead frame 3 is a rigid copper body for carrying a large current, and is equipped with a plurality of terminals 3a that protrude laterally to electrically connect to the upper surfaces of the metal wiring 2b of the insulating substrate 2, and protrusions 3b that protrude downward to electrically connect to the upper surface of the chip 1. The lower surfaces of the terminals 3a of the lead frame 3 and the upper surface of the metal wiring 2b, and the lower surfaces of the protrusions 3b and the upper surface of the chip 1 are electrically connected via solder 4.

[0017] The chip 1 is an RC-IGBT that includes an IGBT region 11 and a diode region 12 connected in antiparallel to the IGBT region 11 within the same chip.

[0018] 2 is a schematic plan view of the main parts of the chip 1, omitting the emitter electrode 15, which will be described later, and the like. As shown in this figure, the chip 1 has an outer peripheral region 13 and a gate pad region 14 in addition to the IGBT region 11 and diode region 12 described above. The dashed lines indicate the portions that come into contact with the protrusions 3b of the lead frame 3 via the solder 4.

[0019] As shown in the figure, cells of the IGBT region 11 and the diode region 12 are alternately arranged inside the peripheral region 13, and a gate pad region 14 is arranged so as to straddle the cells of the multiple IGBT regions 11 and the diode region 12 at the left end of the figure. In addition, the cell width of the IGBT region 11 below the protrusion 3b is wider than the cell width of the IGBT region 11 that does not contact the protrusion 3b. Hereinafter, the former will be referred to as the wide-width IGBT region 11a, and the latter will be referred to as the narrow-width IGBT region 11b. In this embodiment, it is assumed that the widths of the wide-width IGBT regions 11a are equal, the widths of the narrow-width IGBT regions 11b are equal, and the widths of the diode regions 12 are equal, and the cell widths increase in the order of the diode region 12, the narrow-width IGBT region 11b, and the wide-width IGBT region 11a, and the cell width of the wide-width IGBT region 11a is approximately three times (2.5 to 3.5 times) the cell width of the diode region 12.

[0020] 3 is a cross-sectional view of the semiconductor device 100. As shown in the figure, the emitter electrode 15 provided on the upper surface of the chip 1 is electrically and thermally connected to the protrusion 3b of the lead frame 3 via the on-chip solder 4a, and the collector electrode 16 provided on the lower surface of the chip 1 is electrically and thermally connected to the metal wiring 2b of the insulating substrate 2 via the under-chip solder 4b.

[0021] The IGBT region 11 (wide-width IGBT region 11a, narrow-width IGBT region 11b) includes a drift layer 21, a buffer layer 22, a collector layer 23, a body layer 24, an emitter layer 25, a trench 26, a gate electrode 27, and a gate insulating film 28. The drift layer 21 is an n-type semiconductor layer occupying the center of the chip 1 and is the thickest layer. The buffer layer 22 is an n-type semiconductor layer provided below the drift layer 21. The collector layer 23 is a p-type semiconductor layer provided below the buffer layer 22 and is in contact with the upper surface of the collector electrode 16. The body layer 24 is a p-type semiconductor layer provided above the drift layer 21 and is in contact with the lower surface of the emitter electrode 15. The emitter layer 25 is an n-type semiconductor layer provided on the upper surface of the body layer 24 and is in contact with the lower surface of the emitter electrode 15. The trench 26 is a hole that penetrates the body layer 24 and the emitter layer 25 and reaches the drift layer 21. The gate electrode 27 is an electrode disposed in the trench 26. The gate insulating film 28 is an insulating film that covers the outer periphery of the gate electrode 27.

[0022] The diode region 12 has a cathode layer 31 and an emitter insulating film 32 in addition to the drift layer 21, buffer layer 22, body layer 24, and trench 26 described above. The cathode layer 31 is an n-type semiconductor layer provided below the buffer layer 22 and is in contact with the upper surface of the collector electrode 16. The emitter insulating film 32 is an insulating film that covers the outer periphery of the emitter electrode 15 disposed in the trench 26.

[0023] <Heat Dissipation Path of Chip 1> Next, the heat dissipation path of the chip 1 when current is applied to the IGBT region 11 will be described with reference to Figure 4. As shown here, Joule heat generated in the wide IGBT region 11a is dissipated to the left and right diode regions 12, and is also dissipated to the protrusions 3b (lead frame 3) via the on-chip solder 4a, and is then dissipated to the metal wiring 2b (insulating substrate 2) via the under-chip solder 4b. Similarly, Joule heat generated in the narrow IGBT region 11b is dissipated to the left and right diode regions 12, and is also dissipated to the outside of the device (specifically, to the resin mold (not shown) that seals the semiconductor device 100) via the emitter electrode 15, and is then dissipated to the metal wiring 2b (insulating substrate 2) via the under-chip solder 4b.

[0024] 4 , the boundary areas between the left and right diode regions 12 are equal in the wide-width IGBT region 11a and the narrow-width IGBT region 11b, and therefore the left and right boundary areas per unit volume of the wide-width IGBT region 11a are narrower than that of the narrow-width IGBT region 11b. Therefore, compared to the narrow-width IGBT region 11b, the wide-width IGBT region 11a has the following advantages and disadvantages. Specifically, the wide-width IGBT region 11a has a higher carrier accumulation effect than the narrow-width IGBT region 11b, and therefore has the advantage of being able to suppress an increase in on-voltage. However, it has a disadvantage in that the thermal resistance of the heat dissipation path to the diode region 12 is higher than that of the narrow-width IGBT region 11b, and therefore heat dissipation performance is inferior if heat dissipation is limited to the diode region 12.

[0025] However, since the wide-width IGBT region 11a of this embodiment also has a path for dissipating heat to the lead frame 3, which also functions as a heat sink, the existence of this heat dissipation path can improve the above disadvantages and ensure sufficient heat dissipation performance equivalent to that of the narrow-width IGBT region 11b.

[0026] As described above, according to the semiconductor device of this embodiment, it is possible to improve the heat dissipation performance of the entire device and also to suppress an increase in the on-voltage in the IGBT region.

[0027] Second Embodiment Next, a semiconductor device 100 according to a second embodiment of the present invention will be described with reference to Fig. 5. Note that a duplicated description of points common to the first embodiment will be omitted.

[0028] 5 is a schematic plan view of the main part of the chip 1 of this embodiment as seen from above, and similarly to Fig. 2, the emitter electrode 15 and the like are omitted from the illustration. As is obvious from a comparison of Fig. 2 and Fig. 5, whereas the cell width of the diode region 12 in Example 1 is uniform, in this example, the diode region 12 sandwiched between the wide-width IGBT regions 11a is a wide-width diode region 12a having a wide cell width, and the diode region 12 sandwiched between the narrow-width IGBT regions 11b or between the wide-width IGBT region 11a and the narrow-width IGBT region 11b is a narrow-width diode region 12b having a narrow cell width.

[0029] In this way, by making the diode region 12 sandwiched between the wide-width IGBT regions 11a into a wide-width diode region 12a having a wide cell width, the number of boundaries (i.e., boundary area) between the wide-width IGBT regions 11a and the diode region 12 at the portion contacting the protrusion 3b can be further reduced, and therefore the increase in the on-voltage of the IGBT region can be further suppressed than in Example 1.

[0030] REFERENCE SIGNS LIST 100 Semiconductor device 1 Chip 11 IGBT region 11a Wide IGBT region 11b Narrow IGBT region 12 Diode region 12a Wide diode region 12b Narrow diode region 13 Periphery region 14 Gate pad region 15 Emitter electrode 16 Collector electrode 2 Insulating substrate 2a Insulating plate 2b Metal wiring 3 Lead frame 3a Terminal 3b Convex portion 4 Solder 4a Solder on chip 4b Solder under chip

Claims

1. A semiconductor device comprising: a chip having an IGBT region and a diode region; a lead frame electrically connected to the top surface of the chip via solder; and an insulating substrate electrically connected to the bottom surface of the chip via solder, wherein the IGBT regions and the diode regions are arranged alternately within the chip, and the cell width of the IGBT region in a portion electrically connected to the lead frame via the solder is wider than the cell width of the IGBT region in other portions.

2. A semiconductor device according to claim 1, wherein the IGBT regions and the diode regions arranged alternately are surrounded by an outer periphery region, and a gate pad region spanning the IGBT regions and the diode regions is provided inside the outer periphery region.

3. A semiconductor device according to claim 1 or 2, characterized in that the cell width of the IGBT region at the portion electrically connected to the lead frame via the solder is approximately three times the cell width of the diode region at the same portion.

4. A semiconductor device according to claim 1 or 2, characterized in that the cell width of the diode region in the portion electrically connected to the lead frame via the solder is wider than the cell width of the diode region in other portions.

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