Semiconductor device, inverter device, method for manufacturing inverter device, and vehicle

Abstract

This semiconductor device comprises a substrate, a first conductive layer, a first semiconductor element, and a bonding material. The substrate includes a heat dissipation layer. The first conductive layer is bonded to the substrate. The first semiconductor element is bonded to the first conductive layer. The bonding material is positioned on the side opposite to the first conductive layer relative to the substrate in a first direction, and is disposed on the heat dissipation layer. The bonding material includes metal particles. As one embodiment, the semiconductor device further comprises a sealing resin that covers the first semiconductor element.

Description

Semiconductor device, inverter device, inverter device manufacturing method, and vehicle

[0001] The present disclosure relates to a semiconductor device, an inverter device including the semiconductor device, a method for manufacturing the inverter device, and a vehicle equipped with the semiconductor device.

[0002] Conventionally, semiconductor devices equipped with semiconductor elements (such as MOSFETs and IGBTs) having a switching function have been widely known and are mainly used for power conversion. Patent Document 1 discloses an example of such a semiconductor device. The semiconductor device disclosed in this document includes a sealing resin that covers the semiconductor element, a heat dissipation member, and an attachment member. The attachment member is a leaf spring. The sealing resin is attached to the heat dissipation member via the attachment member. The sealing resin is sandwiched between the heat dissipation member and the attachment member.

[0003] In addition to the semiconductor device disclosed in Patent Document 1, there are also cases where a substrate is bonded to a heat dissipation member via a bonding layer. The substrate mounts a semiconductor element and is exposed from the sealing resin. The bonding layer is, for example, a sintered body containing metal particles. In this case, the bonding layer is formed by firing a bonding material containing metal particles. The bonding material is disposed on the heat dissipation member or the substrate. In this case, if a defect such as a defect occurs in the bonded material, there is a risk that the substrate will peel off from the heat dissipation member after the bonding layer is formed by firing.

[0004] International Publication No. 2023 / 047890

[0005] [Summary] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can suppress peeling of a heat dissipation member from a base material when the heat dissipation member and the base material are bonded together.

[0006] A semiconductor device according to a first aspect of the present disclosure includes a substrate including a heat dissipation layer, a first conductive layer bonded to the substrate, a first semiconductor element bonded to the first conductive layer, and a bonding material disposed on the heat dissipation layer and located on the opposite side of the substrate from the first conductive layer in a first direction, the bonding material including metal particles.

[0007] A second aspect of the present disclosure provides an inverter device including a heat dissipation member, a base including a heat dissipation layer facing the heat dissipation member in a first direction, first and second conductive layers located on the opposite side of the base from the heat dissipation member and bonded to the base, a first semiconductor element conductively bonded to the first conductive layer, a second semiconductor element conductively bonded to the second conductive layer, a first signal terminal electrically connected to the first semiconductor element, a second signal terminal electrically connected to the second semiconductor element, a wiring board individually connected to the first signal terminal and the second signal terminal, and a bonding layer bonding the heat dissipation member and the heat dissipation layer, the bonding layer including a sintered body of metal particles.

[0008] A manufacturing method for an inverter device provided by a third aspect of the present disclosure includes a first step, a second step, a third step, a fourth step, a fifth step, and a sixth step. In the first step, a first conductive layer and a second conductive layer are bonded to a base material including a heat dissipation layer so as to be located on the opposite side of the base material from the heat dissipation layer in a first direction. In the second step, a first semiconductor element is conductively bonded to the first conductive layer, and a second semiconductor element is conductively bonded to the second conductive layer. In the third step, a bonding material is disposed on one side of the heat dissipation layer in the first direction. In the fourth step, the bonding material is fired to bond the heat dissipation member and the heat dissipation layer. In the fifth step, a first signal terminal electrically connected to the first semiconductor element and a second signal terminal electrically connected to the second semiconductor element are disposed. In the sixth step, a wiring substrate electrically connected to the first signal terminal and the second signal terminal is disposed. The bonding material includes metal particles.

[0009] A fourth aspect of the present disclosure provides a vehicle including a drive source and a semiconductor device. The semiconductor device is electrically connected to the drive source. The semiconductor device further includes a second conductive layer and a second semiconductor element, in addition to the semiconductor device provided by the first aspect of the present disclosure. The second semiconductor element is electrically connected to the second conductive layer and is electrically connected to the first semiconductor element.

[0010] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0011] FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a plan view corresponding to FIG. 2, seen through the sealing resin. FIG. 4 is a partial enlarged view of FIG. 3. FIG. 5 is a plan view corresponding to FIG. 2, seen through the first conductive member, with the sealing resin and the second conductive member omitted. FIG. 6 is a right side view of the semiconductor device shown in FIG. 1. FIG. 7 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 3. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3. FIG. 10 is a partial enlarged view of a first semiconductor element and its periphery shown in FIG. 9. FIG. 11 is a partial enlarged view of a second semiconductor element and its periphery shown in FIG. 9. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 3. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 3. FIG. 14 is a partial enlarged view of FIG. 10. FIG. 15 is a bottom view of a semiconductor device according to a modified example of the first embodiment of the present disclosure. FIG. 16 is a plan view of an inverter device including the semiconductor device shown in FIG. 1. FIG. 17 is a partially enlarged view of FIG. 16. FIG. 18 is a front view of the inverter device shown in FIG. 16 and corresponds to FIG. 17. FIG. 19 is a cross-sectional view of the inverter device shown in FIG. 16 and corresponds to FIG. 9. FIG. 20 is a partially enlarged view of FIG. 19. FIG. 21 is a circuit block diagram of the inverter device shown in FIG. 16. FIG. 22 is a partially enlarged view of FIG. 21. FIG. 23 is a circuit block diagram of each of a plurality of drive circuits that are elements of the circuit shown in FIG. 21. FIG. 24 is a cross-sectional view illustrating a first step in the manufacturing process of the inverter device shown in FIG. 16. FIG. 25 is a cross-sectional view illustrating a second step in the manufacturing process of the inverter device shown in FIG. 16. FIG. 26 is a cross-sectional view illustrating a third step in the manufacturing process of the inverter device shown in FIG. 16. FIG. 27 is a cross-sectional view illustrating a fourth step in the manufacturing process of the inverter device shown in FIG. 16. Fig. 28 is a cross-sectional view illustrating a fifth step in the manufacturing process of the inverter device shown in Fig. 16. Fig. 29 is a cross-sectional view illustrating a sixth step in the manufacturing process of the inverter device shown in Fig. 16. Fig. 30 is a schematic diagram of a vehicle equipped with the semiconductor device shown in Fig. 1. Fig. 31 is a bottom view of a semiconductor device according to a second embodiment of the present disclosure.Fig. 32 is a cross-sectional view of the semiconductor device shown in Fig. 31 and corresponds to Fig. 9. Fig. 33 is a cross-sectional view of a semiconductor device according to a third embodiment of the present disclosure and corresponds to Fig. 9. Fig. 34 is a partially enlarged view of Fig. 33. Fig. 35 is a bottom view of a semiconductor device according to a fourth embodiment of the present disclosure. Fig. 36 is a cross-sectional view of the semiconductor device shown in Fig. 35 and corresponds to Fig. 9. Fig. 37 is a cross-sectional view illustrating a manufacturing process of an inverter device including the semiconductor device shown in Fig. 35.

[0012] DETAILED DESCRIPTION The present disclosure will be described in detail with reference to the accompanying drawings.

[0013] First Embodiment: A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to Figures 1 to 14. The semiconductor device A10 includes a substrate 11, a first conductive layer 121, a second conductive layer 122, a first power terminal 13, two second power terminals 14, two third power terminals 15, a plurality of first semiconductor elements 21, a plurality of second semiconductor elements 22, a first conductive member 31, a second conductive member 32, a sealing resin 50, and a bonding material 79. The semiconductor device A10 further includes a first signal terminal 161, a second signal terminal 162, a third signal terminal 171, a fourth signal terminal 172, two fifth signal terminals 181, two sixth signal terminals 182, a seventh signal terminal 19, two thermistors 23, a first wiring 61, and a second wiring 62. For ease of understanding, the sealing resin 50 is shown in perspective in Figures 3 and 4. 3, the transmitted sealing resin 50 is indicated by an imaginary line (two-dot chain line). In FIG. 5, for ease of understanding, the first conductive member 31 is transmitted, and the second conductive member 32 and the sealing resin 50 are not shown.

[0014] In the description of the semiconductor device A10, for convenience, the normal direction to a first main surface 121A of a first conductive layer 121 (described later) is referred to as the "first direction z." One direction perpendicular to the first direction z is referred to as the "second direction x." A direction perpendicular to both the first direction z and the second direction x is referred to as the "third direction y."

[0015] The semiconductor device A10 converts DC power input to the first power terminal 13 and two second power terminals 14 into AC power using a plurality of first semiconductor elements 21 and a plurality of second semiconductor elements 22. The converted AC power is input from each of two third power terminals 15 to a power supply target (for example, a motor 89 described below).

[0016] As shown in FIGS. 9 to 11 , the substrate 11 is located on the opposite side of the first semiconductor elements 21 and the second semiconductor elements 22 in the first direction z, with the first conductive layer 121 and the second conductive layer 122 as references. The substrate 11 supports the first conductive layer 121 and the second conductive layer 122. In the semiconductor device A10, the substrate 11 is formed, for example, by active metal brazing (AMB). As shown in FIGS. 9 to 11 , the substrate 11 includes an insulating layer 111, two support layers 112, and a heat dissipation layer 113. The substrate 11 is covered with a sealing resin 50 except for a portion of the heat dissipation layer 113.

[0017] As shown in FIGS. 9 to 11 , the insulating layer 111 includes a portion interposed between the support layer 112 and the heat dissipation layer 113 in the first direction z. The insulating layer 111 is made of a material with relatively high thermal conductivity. For example, the insulating layer 111 is made of ceramics containing aluminum nitride (AlN). The insulating layer 111 may be made of an insulating resin sheet in addition to ceramics. The dimension of the insulating layer 111 in the first direction z is smaller than the dimension of each of the first conductive layer 121 and the second conductive layer 122 in the first direction z.

[0018] 9 to 11 , the two support layers 112 are located between the insulating layer 111 and the first and second conductive layers 121 and 122 in the first direction z. The support layers 112 are spaced apart from each other in the second direction x. The composition of the support layer 112 includes copper (Cu). As shown in FIG. 5 , the support layer 112 is located inward from the periphery of the insulating layer 111 when viewed in the first direction z.

[0019] 9 to 11 , the heat dissipation layer 113 is located on the opposite side of the two support layers 112 from the insulating layer 111 in the first direction z. The heat dissipation layer 113 contains copper. The dimension of the heat dissipation layer 113 in the first direction z is larger than the dimension of the insulating layer 111 in the first direction z. As viewed in the first direction z, the heat dissipation layer 113 is located inward from the periphery of the insulating layer 111. The heat dissipation layer 113 has a heat dissipation surface 113A facing the side opposite to the side facing the insulating layer 111 in the first direction z. The heat dissipation surface 113A is exposed from the sealing resin 50.

[0020] As shown in FIGS. 9 to 11 , the first conductive layer 121 and the second conductive layer 122 are bonded to the substrate 11. The first conductive layer 121 and the second conductive layer 122 contain copper. The first conductive layer 121 and the second conductive layer 122 are spaced apart from each other in the second direction x. As shown in FIGS. 8 and 9 , the first conductive layer 121 has a first main surface 121A facing the first direction z. The first main surface 121A faces the plurality of first semiconductor elements 21. As shown in FIG. 10 , the first conductive layer 121 is bonded to one of the two support layers 112 via a first bonding layer 129. The first bonding layer 129 is, for example, solder. As shown in FIGS. 8 and 9 , the second conductive layer 122 has a second main surface 122A facing the same side as the first main surface 121A in the first direction z. The second main surface 122A faces the plurality of second semiconductor elements 22. As shown in Fig. 11 , the second conductive layer 122 is bonded to the other of the two support layers 112 via a first bonding layer 129.

[0021] As shown in FIGS. 5 and 9 , the multiple first semiconductor elements 21 are bonded to the first main surface 121A of the first conductive layer 121. The multiple first semiconductor elements 21 are arranged along the third direction y. The multiple second semiconductor elements 22 are bonded to the second main surface 122A of the second conductive layer 122. The multiple second semiconductor elements 22 are arranged along the third direction y. The multiple first semiconductor elements 21 and the multiple second semiconductor elements 22 are, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, the multiple first semiconductor elements 21 and the multiple second semiconductor elements 22 may be switching elements such as insulated gate bipolar transistors (IGBTs). Furthermore, the multiple first semiconductor elements 21 may include multiple switching elements and multiple freewheeling diodes individually connected in parallel to these switching elements. Similarly, the second semiconductor elements 22 may also include a plurality of switching elements and a plurality of freewheeling diodes individually connected in parallel to the switching elements. The freewheeling diodes may be, for example, Schottky barrier diodes. In the description of the semiconductor device A10, the first semiconductor elements 21 and the second semiconductor elements 22 are n-channel MOSFETs with a vertical structure. The first semiconductor elements 21 and the second semiconductor elements 22 include a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC).

[0022] As shown in FIGS. 5 and 10, each of the plurality of first semiconductor elements 21 has a first electrode 211 , a second electrode 212 , a first gate electrode 213 and a first detection electrode 214 .

[0023] 10 , the first electrode 211 faces the first main surface 121A of the first conductive layer 121. A current corresponding to the power before being converted by the first semiconductor element 21 flows through the first electrode 211. In other words, the first electrode 211 corresponds to the drain electrode of the first semiconductor element 21. The first electrode 211 is conductively bonded to the first main surface 121A via a conductive bonding layer 29. As a result, the first electrode 211 of each of the multiple first semiconductor elements 21 is electrically connected to the first conductive layer 121. The conductive bonding layer 29 is a sintered body of metal particles containing silver (Ag) or the like. Alternatively, the conductive bonding layer 29 may be solder.

[0024] 10 , the second electrode 212 is located on the opposite side of the first conductive layer 121 from the side facing the first main surface 121A in the first direction z. Therefore, the first electrode 211 and the second electrode 212 are located on opposite sides of each other in the first direction z. A current corresponding to the power converted by the first semiconductor element 21 flows through the second electrode 212. In other words, the second electrode 212 corresponds to the source electrode of the first semiconductor element 21.

[0025] 10 , the first gate electrode 213 is located on the opposite side of the first conductive layer 121 from the side facing the first main surface 121A in the first direction z. Therefore, the first gate electrode 213 is located on the same side as the second electrode 212 in the first direction z. A gate voltage for driving the first semiconductor element 21 is applied to the first gate electrode 213. As shown in FIG. 5 , the area of ​​the first gate electrode 213 is smaller than the area of ​​the second electrode 212 when viewed in the first direction z.

[0026] 5 , the first detection electrode 214 is located on the same side as the second electrode 212 and the first gate electrode 213 in the first direction z. The first detection electrode 214 is located adjacent to the first gate electrode 213 in the third direction y. A voltage equivalent to the voltage applied to the second electrode 212 is applied to the first detection electrode 214. When viewed in the first direction z, the area of ​​the first detection electrode 214 is approximately equal to the area of ​​the first gate electrode 213.

[0027] As shown in FIGS. 5 and 11 , each of the plurality of second semiconductor elements 22 has a third electrode 221 , a fourth electrode 222 , a second gate electrode 223 and a second detection electrode 224 .

[0028] 11 , the third electrode 221 faces the second main surface 122A of the second conductive layer 122. A current corresponding to the power before being converted by the second semiconductor element 22 flows through the third electrode 221. In other words, the third electrode 221 corresponds to the drain electrode of the second semiconductor element 22. The third electrode 221 is conductively bonded to the second main surface 122A via the conductive bonding layer 29. As a result, the third electrode 221 of each of the multiple second semiconductor elements 22 is electrically connected to the second conductive layer 122.

[0029] 11 , the fourth electrode 222 is located on the opposite side of the second conductive layer 122 from the side facing the second main surface 122A in the first direction z. Therefore, the third electrode 221 and the fourth electrode 222 are located on opposite sides of each other in the first direction z. A current corresponding to the power converted by the second semiconductor element 22 flows through the fourth electrode 222. In other words, the fourth electrode 222 corresponds to the source electrode of the second semiconductor element 22.

[0030] 11 , the second gate electrode 223 is located on the opposite side of the second conductive layer 122 from the side facing the second main surface 122A in the first direction z. Therefore, the second gate electrode 223 is located on the same side as the fourth electrode 222 in the first direction z. A gate voltage for driving the second semiconductor element 22 is applied to the second gate electrode 223. As shown in FIG. 5 , the area of ​​the second gate electrode 223 is smaller than the area of ​​the fourth electrode 222 when viewed in the first direction z.

[0031] 5 , the second detection electrode 224 is located on the same side as the fourth electrode 222 and the second gate electrode 223 in the first direction z. The second detection electrode 224 is located on both sides of the second gate electrode 223 in the third direction y. A voltage equivalent to the voltage applied to the fourth electrode 222 is applied to the second detection electrode 224. When viewed in the first direction z, the area of ​​the second detection electrode 224 is approximately equal to the area of ​​the second gate electrode 223.

[0032] As shown in FIGS. 3 and 9 , the first power terminal 13 is located on the opposite side of the second conductive layer 122 from the first conductive layer 121 in the second direction x. The first power terminal 13 is conductively bonded to the first conductive layer 121. This electrically connects the first power terminal 13 to the first electrodes 211 of the first semiconductor elements 21 via the first conductive layer 121. The first power terminal 13 is a P terminal (positive electrode) to which DC power to be converted is input. The first power terminal 13 extends from the first conductive layer 121 in the second direction x. The first power terminal 13 has a covering portion 131 and an exposed portion 132. As shown in FIG. 9 , the covering portion 131 is conductively bonded to the first conductive layer 121 and is covered with sealing resin 50. The exposed portion 132 extends from the covering portion 131 in the second direction x and is exposed to the outside from the sealing resin 50.

[0033] As shown in FIGS. 3 and 8 , each of the two second power terminals 14 is located on the same side as the first power terminal 13 in the second direction x with respect to the first conductive layer 121 and the second conductive layer 122, but is spaced apart from the first conductive layer 121 and the second conductive layer 122. Each of the two second power terminals 14 is electrically connected to the fourth electrodes 222 of the second semiconductor elements 22. The two second power terminals 14 are N terminals (negative electrodes) to which DC power to be converted is input. The second power terminals 14 are spaced apart from each other in the third direction y. The first power terminal 13 is located between the two second power terminals 14 in the third direction y. Each of the two second power terminals 14 has a covering portion 141 and an exposed portion 142. As shown in FIG. 8 , the covering portion 141 is spaced apart from the first conductive layer 121 and is covered with the sealing resin 50. The exposed portion 142 extends from the covered portion 141 in the second direction x and is exposed to the outside from the sealing resin 50 .

[0034] As shown in FIGS. 3 and 8 , each of the two third power terminals 15 is located on the opposite side of the first conductive layer 121 from the second conductive layer 122 in the second direction x. Each of the two third power terminals 15 is conductively bonded to the second conductive layer 122. This electrically connects each of the two third power terminals 15 to the third electrodes 221 of the second semiconductor elements 22 via the second conductive layer 122. AC power converted by the first semiconductor elements 21 and the second semiconductor elements 22 is output from each of the two third power terminals 15. In the semiconductor device A10, the two third power terminals 15 are spaced apart from each other in the third direction y. Each of the two third power terminals 15 includes a covering portion 151 and an exposed portion 152. As shown in FIG. 8 , the covering portion 151 is conductively bonded to the second conductive layer 122 and is covered with a sealing resin 50. The exposed portion 152 extends from the covered portion 151 in the second direction x and is exposed to the outside from the sealing resin 50 .

[0035] 10 , the first wiring 61 is bonded to the first main surface 121A of the first conductive layer 121. The first wiring 61 is located on the opposite side of the plurality of second semiconductor elements 22 with respect to the plurality of first semiconductor elements 21 in the second direction x. The first wiring 61 is electrically connected to the plurality of first semiconductor elements 21 and the first conductive layer 121. As shown in FIGS. 5 and 10 , the first wiring 61 has a first mounting layer 611, a first metal layer 612, two first gate wiring layers 613, a first detection wiring layer 614, a first temperature detection wiring layer 615, and a second detection wiring layer 616.

[0036] 5 , the first mounting layer 611 includes two first gate wiring layers 613, a first detection wiring layer 614, two first temperature detection wiring layers 615, and a second detection wiring layer 616. The first mounting layer 611 is an insulator. The first mounting layer 611 is made of, for example, ceramics. Alternatively, the first mounting layer 611 may be made of an insulating resin sheet.

[0037] 10 , the first metal layer 612 is located on a side facing the first main surface 121A of the first conductive layer 121 in the first direction z, with the first mounting layer 611 as a reference. The first metal layer 612 is bonded to the first mounting layer 611. The first metal layer 612 contains copper. The first metal layer 612 is bonded to the first main surface 121A via a second bonding layer 68. The second bonding layer 68 is, for example, solder.

[0038] 5 and 10 , the two first gate wiring layers 613 are located on the opposite side of the first mounting layer 611 from the first metal layer 612. The two first gate wiring layers 613 are bonded to the first mounting layer 611. Of the two first gate wiring layers 613, one of the first gate wiring layers 613 is conductively bonded to a plurality of first wires 41. The plurality of first wires 41 are individually conductively bonded to the first gate electrodes 213 of the plurality of first semiconductor elements 21. Furthermore, a plurality of sixth wires 46 are conductively bonded to each of the two first gate wiring layers 613. As a result, each of the two first gate wiring layers 613 is electrically connected to the first gate electrodes 213 of the plurality of first semiconductor elements 21.

[0039] 5 and 10 , the first detection wiring layer 614 is located on the opposite side of the first mounting layer 611 from the first metal layer 612. The first detection wiring layer 614 is bonded to the first mounting layer 611. A plurality of second wires 42 are conductively bonded to the first detection wiring layer 614. Furthermore, the plurality of second wires 42 are individually conductively bonded to the first detection electrodes 214 of the plurality of first semiconductor elements 21. As a result, the first detection wiring layer 614 is electrically connected to the first detection electrodes 214 of the plurality of first semiconductor elements 21.

[0040] 5 , the two first temperature detection wiring layers 615 are located on the opposite side of the first mounting layer 611 from the first metal layer 612. The two first temperature detection wiring layers 615 are bonded to the first mounting layer 611. The two first temperature detection wiring layers 615 are adjacent to each other in the third direction y.

[0041] 5 , the second detection wiring layer 616 is located on the opposite side of the first metal layer 612 with respect to the first mounting layer 611. The second detection wiring layer 616 is bonded to the first mounting layer 611. A third wire 43 is conductively bonded to the second detection wiring layer 616. The third wire 43 is further conductively bonded to the first main surface 121A of the first conductive layer 121. This provides electrical continuity between the second detection wiring layer 616 and the first conductive layer 121.

[0042] 11 , the second wiring 62 is bonded to the second main surface 122A of the second conductive layer 122. The second wiring 62 is located on the opposite side of the second semiconductor elements 22 from the first semiconductor elements 21 in the second direction x. The second wiring 62 is electrically connected to the second semiconductor elements 22 and the second conductive layer 122. As shown in FIGS. 5 and 11 , the second wiring 62 includes a second mounting layer 621, a second metal layer 622, two second gate wiring layers 623, a third detection wiring layer 624, two second temperature detection wiring layers 625, and a fourth detection wiring layer 626.

[0043] 5 , the second mounting layer 621 includes two second gate wiring layers 623, a third detection wiring layer 624, two second temperature detection wiring layers 625, and a fourth detection wiring layer 626. The second mounting layer 621 is an insulator. The second mounting layer 621 is made of, for example, ceramics. Alternatively, the second mounting layer 621 may be made of an insulating resin sheet.

[0044] 11 , the second metal layer 622 is located on a side facing the second main surface 122A of the second conductive layer 122 with the second mounting layer 621 as a reference in the first direction z. The second metal layer 622 is bonded to the second mounting layer 621. The second metal layer 622 contains copper. The second metal layer 622 is bonded to the second main surface 122A via a second bonding layer 68.

[0045] 5 and 11 , the two second gate wiring layers 623 are located on the opposite side of the second metal layer 622 with respect to the second mounting layer 621. The two second gate wiring layers 623 are bonded to the second mounting layer 621. A plurality of fourth wires 44 are conductively bonded to one of the two second gate wiring layers 623. The plurality of fourth wires 44 are individually conductively bonded to the second gate electrodes 223 of the second semiconductor elements 22. Furthermore, a plurality of seventh wires 47 are conductively bonded to each of the two second gate wiring layers 623. As a result, each of the two second gate wiring layers 623 is electrically connected to the second gate electrodes 223 of the second semiconductor elements 22.

[0046] 5 and 11 , the third detection wiring layer 624 is located on the opposite side of the second metal layer 622 with respect to the second mounting layer 621. The third detection wiring layer 624 is bonded to the second mounting layer 621. A plurality of fifth wires 45 are conductively bonded to the third detection wiring layer 624. Furthermore, the plurality of fifth wires 45 are individually conductively bonded to the second detection electrodes 224 of the plurality of second semiconductor elements 22. As a result, the third detection wiring layer 624 is electrically connected to the second detection electrodes 224 of the plurality of second semiconductor elements 22.

[0047] 5 , the two second temperature detection wiring layers 625 are located on the opposite side of the second mounting layer 621 from the second metal layer 622. The two second temperature detection wiring layers 625 are bonded to the second mounting layer 621. The two second temperature detection wiring layers 625 are adjacent to each other in the third direction y.

[0048] 5, the fourth detection wiring layer 626 is located on the opposite side of the second mounting layer 621 from the second metal layer 622. The fourth detection wiring layer 626 is bonded to the second mounting layer 621.

[0049] As shown in FIGS. 10 and 11 , each of the multiple sleeves 63 is conductively bonded to either the first wiring 61 or the second wiring 62 via a third bonding layer 69. The third bonding layer 69 is, for example, solder. The multiple sleeves 63 are made of a conductive material such as metal. Each of the multiple sleeves 63 has a cylindrical shape extending in the first direction z. As shown in FIGS. 2 and 9 , each of the multiple sleeves 63 has an end face 631 facing the same side as the first main surface 121A of the first conductive layer 121 in the first direction z. The end face 631 is exposed to the outside from the top surface 51 of the sealing resin 50, which will be described later. The third bonding layer 69 is, for example, solder.

[0050] 4, one of the two thermistors 23 is conductively joined to two first temperature detection wiring layers 615 of the first wiring 61. As shown in FIG. 4, the other of the two thermistors 23 is conductively joined to two second temperature detection wiring layers 625 of the second wiring 62. The two thermistors 23 are used as temperature detection sensors for the semiconductor device A10.

[0051] As shown in FIG. 1 , the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, the two sixth signal terminals 182, and the seventh signal terminal 19 are formed as metal pins extending in the first direction z. These terminals protrude from a top surface 51 of a sealing resin 50 (described later). Furthermore, these terminals are individually press-fitted into a plurality of sleeves 63. As a result, each of these terminals is supported by one of the plurality of sleeves 63 and is electrically connected to one of the first wiring 61 and the second wiring 62.

[0052] 5 and 10 , the first signal terminal 161 is press-fitted into one of the multiple sleeves 63 that is conductively joined to one of the two first gate wiring layers 613 of the first wiring 61. This allows the first signal terminal 161 to be electrically connected to the first gate electrodes 213 of the multiple first semiconductor elements 21 via the two first gate wiring layers 613. A gate voltage for driving the multiple first semiconductor elements 21 is applied to the first signal terminal 161.

[0053] 5 and 11 , the second signal terminal 162 is press-fitted into one of the multiple sleeves 63 that is conductively joined to one of the two second gate wiring layers 623 of the second wiring 62. This allows the second signal terminal 162 to be electrically connected to the second gate electrodes 223 of the multiple second semiconductor elements 22 via the two second gate wiring layers 623. A gate voltage for driving the multiple second semiconductor elements 22 is applied to the second signal terminal 162.

[0054] As shown in Fig. 2 , the third signal terminal 171 is located adjacent to the first signal terminal 161 in the third direction y. As shown in Fig. 5 , the third signal terminal 171 is press-fitted into one of the multiple sleeves 63 that is conductively joined to the first detection wiring layer 614 of the first wiring 61. This allows the third signal terminal 171 to be electrically connected to the first detection electrodes 214 of each of the multiple first semiconductor elements 21 via the first detection wiring layer 614. A voltage equivalent to the voltage applied to the first detection electrodes 214 of each of the multiple first semiconductor elements 21 is applied to the third signal terminal 171.

[0055] As shown in Fig. 2 , the fourth signal terminal 172 is located adjacent to the second signal terminal 162 in the third direction y. As shown in Fig. 5 , the fourth signal terminal 172 is press-fitted into one of the multiple sleeves 63 that is conductively joined to the third detection wiring layer 624 of the second wiring 62. This allows the fourth signal terminal 172 to be electrically connected to the second detection electrodes 224 of each of the multiple second semiconductor elements 22 via the third detection wiring layer 624. A voltage equivalent to the voltage applied to the second detection electrodes 224 of each of the multiple second semiconductor elements 22 is applied to the fourth signal terminal 172.

[0056] As shown in Fig. 2 , the two fifth signal terminals 181 are located on the opposite side of the first signal terminal 161 from the third signal terminal 171 in the third direction y. The two fifth signal terminals 181 are adjacent to each other in the third direction y. As shown in Fig. 5 , the two fifth signal terminals 181 are individually press-fitted into two of the multiple sleeves 63 that are individually conductively joined to the two first temperature detection wiring layers 615 of the first wiring 61. As a result, the two fifth signal terminals 181 are electrically connected to the two thermistors 23 that are conductively joined to the two first temperature detection wiring layers 615 of the two thermistors 23.

[0057] As shown in Fig. 2 , the two sixth signal terminals 182 are located on the opposite side of the second signal terminal 162 from the fourth signal terminal 172 in the third direction y. The two sixth signal terminals 182 are adjacent to each other in the third direction y. As shown in Fig. 5 , the two sixth signal terminals 182 are individually press-fitted into two of the multiple sleeves 63 that are individually conductively joined to the two second temperature detection wiring layers 625 of the second wiring 62. As a result, the two sixth signal terminals 182 are electrically connected to the two thermistors 23 that are conductively joined to the two second temperature detection wiring layers 625 of the two thermistors 23.

[0058] As shown in Fig. 2 , the seventh signal terminal 19 is located on the opposite side of the first signal terminal 161 in the third direction y with respect to the third signal terminal 171. As shown in Fig. 5 , the seventh signal terminal 19 is press-fitted into one of the multiple sleeves 63 that is conductively joined to the second detection wiring layer 616 of the first wiring 61. This provides electrical continuity between the seventh signal terminal 19 and the first conductive layer 121 via the second detection wiring layer 616. A voltage equivalent to the DC power input to the first power terminal 13 and the two second power terminals 14 is applied to the seventh signal terminal 19.

[0059] As shown in FIGS. 5 and 10 , the first conductive member 31 is conductively bonded to the second electrodes 212 of the plurality of first semiconductor elements 21 and the second main surface 122A of the second conductive layer 122. This allows the second electrodes 212 of the plurality of first semiconductor elements 21 to be electrically connected to the second conductive layer 122. The first conductive member 31 contains copper. The first conductive member 31 is a metal clip. As shown in FIG. 5 , the first conductive member 31 has a first main portion 311, a plurality of first bonding portions 312, a plurality of first connecting portions 313, a plurality of second bonding portions 314, and a plurality of second connecting portions 315.

[0060] The first main portion 311 forms a main portion of the first conductive member 31. As shown in Fig. 5 , the first main portion 311 extends in the third direction y. As shown in Fig. 9 , the first main portion 311 straddles between the first conductive layer 121 and the second conductive layer 122.

[0061] As shown in FIG. 10 , the plurality of first bonding portions 312 are individually conductively bonded to the second electrodes 212 of the plurality of first semiconductor elements 21 .

[0062] 5, the multiple first connecting portions 313 are connected to the first main portion 311. In addition, the multiple first connecting portions 313 are individually connected to the multiple first joint portions 312. The multiple first connecting portions 313 are spaced apart from one another in the third direction y. As shown in FIG. 9, when viewed in the third direction y, the multiple first connecting portions 313 are inclined in a direction away from the first main surface 121A of the first conductive layer 121 as they extend from the multiple first joint portions 312 toward the first main portion 311.

[0063] 5 and 9, the multiple second bonding portions 314 are conductively bonded to the second main surface 122A of the second conductive layer 122. The multiple second bonding portions 314 are arranged along the third direction y.

[0064] 5 and 9 , the multiple second connecting portions 315 are connected to the first main portion 311. In addition, the multiple second connecting portions 315 are individually connected to the multiple second bonding portions 314. When viewed in the third direction y, each of the multiple second connecting portions 315 is inclined in a direction away from the second main surface 122A of the second conductive layer 122 as it extends from the multiple second bonding portions 314 toward the first main portion 311.

[0065] 9 , 10 , and 13 , a conductive bonding layer 29 is located between the second electrode 212 of each of the multiple first semiconductor elements 21 and each of the multiple first bonding portions 312. The conductive bonding layer 29 electrically conductively bonds each of the multiple first bonding portions 312 to the second electrode 212 of each of the multiple first semiconductor elements 21. As shown in FIG. 9 , the conductive bonding layer 29 is located between the second main surface 122A of the second conductive layer 122 and the multiple second bonding portions 314. The conductive bonding layer 29 electrically conductively bonds the second main surface 122A to the multiple second bonding portions 314.

[0066] As shown in FIGS. 4 and 11 , the second conductive member 32 is conductively joined to the second electrodes 212 of the plurality of second semiconductor elements 22 and the covering portion 141 of the second power terminal 14. As a result, the second electrodes 212 of the plurality of second semiconductor elements 22 are electrically connected to the second power terminal 14. The second conductive member 32 contains copper. The second conductive member 32 is a metal clip. As shown in FIG. 4 , the second conductive member 32 has two second main portions 321, a plurality of third joint portions 322, a plurality of third connecting portions 323, two fourth joint portions 324, two fourth connecting portions 325, a plurality of intermediate portions 326, and a plurality of cross beam portions 327.

[0067] As shown in Fig. 4, the two second main portions 321 are spaced apart from each other in the third direction y. The two second main portions 321 extend in the second direction x. As shown in Fig. 8, the two second main portions 321 are arranged parallel to the first main surface 121A of the first conductive layer 121 and the second main surface 122A of the second conductive layer 122. The two second main portions 321 are spaced apart from the first main surface 121A and the second main surface 122A more than the first main portion 311 of the first conductive member 31.

[0068] 4 , the intermediate portions 326 are spaced apart from one another in the third direction y and are located between the two second main portions 321 in the third direction y. The intermediate portions 326 extend in the second direction x. The dimension of each of the intermediate portions 326 in the second direction x is smaller than the dimension of each of the two second main portions 321 in the second direction x.

[0069] As shown in FIG. 11 , the plurality of third bonding portions 322 are individually conductively bonded to the fourth electrodes 222 of the plurality of second semiconductor elements 22 .

[0070] 4 and 12 , the multiple third connecting portions 323 are connected to both sides of the multiple third joint portions 322 in the third direction y. Furthermore, the multiple third connecting portions 323 are connected to either one of the two second main portions 321 and the multiple intermediate portions 326. When viewed in the second direction x, each of the multiple third connecting portions 323 is inclined in a direction away from the second main surface 122A of the second conductive layer 122 as it moves from either one of the multiple third joint portions 322 toward either one of the two second main portions 321 or the multiple intermediate portions 326.

[0071] As shown in FIGS. 4 and 8 , the two fourth joint portions 324 are individually conductively joined to the covering portions 141 of the two second power terminals 14 .

[0072] 4 and 8 , the two fourth connecting portions 325 are individually connected to the two second main portions 321 and the two fourth joint portions 324. When viewed in the third direction y, the two fourth connecting portions 325 are inclined in a direction away from the first main surface 121A of the first conductive layer 121 as they move from the two fourth joint portions 324 toward the two second main portions 321.

[0073] As shown in FIGS. 4 and 13 , the multiple cross beam portions 327 are arranged along the third direction y. As viewed in the first direction z, the multiple cross beam portions 327 include regions that individually overlap the multiple first joint portions 312 of the first conductive member 31. Of the multiple cross beam portions 327, the cross beam portion 327 located at the center in the third direction y is connected to the multiple intermediate portions 326 on both sides in the third direction y. Of the multiple cross beam portions 327, the remaining two cross beam portions 327 are connected to one of the two second main portions 321 and one of the multiple intermediate portions 326 on both sides in the third direction y. As viewed in the second direction x, the multiple cross beam portions 327 are convex in the first direction z toward the first main surface 121A of the first conductive layer 121.

[0074] 9 , 11 , and 12 , a conductive bonding layer 29 is located between each of the fourth electrodes 222 of the multiple second semiconductor elements 22 and each of the multiple third bonding portions 322. The conductive bonding layer 29 conductively bonds each of the multiple third bonding portions 322 to each of the multiple second semiconductor elements 22. As shown in FIG. 8 , a conductive bonding layer 29 is located between each of the covering portions 141 of the two second power terminals 14 and the two fourth bonding portions 324. The conductive bonding layer 29 conductively bonds each of the covering portions 141 of the two second power terminals 14 to each of the two fourth bonding portions 324.

[0075] As shown in FIGS. 8 , 9 , 12 , and 13 , the sealing resin 50 covers the first conductive layer 121, the second conductive layer 122, the plurality of first semiconductor elements 21, the plurality of second semiconductor elements 22, the first conductive member 31, and the second conductive member 32. The sealing resin 50 also covers a portion of each of the substrate 11, the first power terminal 13, the third power terminal 15, and the second power terminal 14. The sealing resin 50 has electrical insulation properties. The sealing resin 50 is made of a material containing, for example, a black epoxy resin. As shown in FIGS. 2 and 6 to 9 , the sealing resin 50 has a top surface 51, a bottom surface 52, a first side surface 53, a second side surface 54, and two recesses 55.

[0076] 8 and 9 , top surface 51 faces the same side as first main surface 121A of first conductive layer 121 in first direction z. As shown in Fig. 8 and 9 , bottom surface 52 faces the opposite side from top surface 51 in first direction z. As shown in Fig. 7 , heat dissipation surface 113A of heat dissipation layer 113 of base material 11 is exposed from bottom surface 52.

[0077] 2 and 6 , the first side surface 53 and the second side surface 54 are spaced apart from each other in the second direction x. The first side surface 53 and the second side surface 54 face opposite each other in the second direction x. The exposed portion 132 of the first power terminal 13 and the exposed portion 142 of each of the two second power terminals 14 are exposed to the outside from the first side surface 53. The exposed portion 152 of each of the two third power terminals 15 are exposed to the outside from the second side surface 54.

[0078] 2 and 7 , the two recesses 55 are recessed from the first side surface 53 in the second direction x. The two recesses 55 extend from the top surface 51 to the bottom surface 52 in the first direction z. The two recesses 55 are located on both sides of the first power terminal 13 in the third direction y.

[0079] As shown in FIGS. 8 to 13 , the bonding material 79 is located on the opposite side of the substrate 11 in the first direction z from the first conductive layer 121 and the second conductive layer 122. The bonding material 79 is disposed on the heat dissipation surface 113A of the heat dissipation layer 113 of the substrate 11. The bonding material 79 contains metal particles. The metal particles include silver. Alternatively, the metal particles may include copper. The bonding material 79 is obtained by drying a paste containing the metal particles and a solvent. Alternatively, the bonding material 79 may be a sheet containing the metal particles and a binder.

[0080] 10 and 11, the bonding material 79 is in contact with the heat dissipation surface 113A of the heat dissipation layer 113. As shown in Fig. 7, the bonding material 79 overlaps the entire heat dissipation surface 113A when viewed in the first direction z.

[0081] 14, the bonding material 79 has a bonding surface 79A that faces the same side in the first direction z as the heat dissipation surface 113A of the heat dissipation layer 113. The surface roughness of the bonding surface 79A is smaller than the surface roughness of the heat dissipation surface 113A.

[0082] Next, a semiconductor device A11 according to a modification of the first embodiment of the present disclosure will be described with reference to Fig. 15. Fig. 15 corresponds to Fig. 7 showing the semiconductor device A10. In the semiconductor device A11, the configuration of the bonding material 79 is different from that of the semiconductor device A10.

[0083] As shown in FIG. 15 , the bonding material 79 is located inward from the periphery of the heat dissipation surface 113A of the heat dissipation layer 113 of the base material 11 when viewed in the first direction z.

[0084] Next, an inverter device B including semiconductor devices A10 will be described with reference to FIGS. 16 to 23. Here, FIG. 19 corresponds to FIG. 9 showing the semiconductor device A10. The inverter device B includes three semiconductor devices A10, a heat dissipation member 71, a wiring board 81, and a plurality of support members 82. Furthermore, the inverter device B includes a bonding layer 72 instead of the bonding material 79 for each of the three semiconductor devices A10. The inverter device B is used to drive a motor 89, which will be described later.

[0085] 21 to 24, the configuration of the inverter device B will be described. The heat dissipation member 71 is used to cool the inverter device B. The heat dissipation member 71 contains metal. The heat dissipation member 71 is made of a material containing aluminum (Al), for example.

[0086] As shown in FIGS. 18 and 19 , the heat dissipation member 71 has a base 711 and a heat dissipation portion 712. The base 711 is flat. The base 711 faces the heat dissipation layer 113 of the substrate 11 of each of the three semiconductor devices A10 in the first direction z. As shown in FIG. 16 , the three semiconductor devices A10 are arranged on the base 711 along the third direction y. The heat dissipation portion 712 is connected to the base 711. The heat dissipation portion 712 is located on the opposite side of the base 11 of each of the three semiconductor devices A10 in the first direction z, relative to the base 711. The heat dissipation portion 712 protrudes from the base 711. In the inverter device B, the heat dissipation portion 712 is rectangular parallelepiped-shaped. Alternatively, the heat dissipation portion 712 may be a plurality of fins arranged in a direction perpendicular to the first direction z.

[0087] 19 , the bonding layer 72 bonds the base 711 of the heat dissipation member 71 to the heat dissipation layer 113 of the substrate 11 of each of the three semiconductor devices A10. The bonding layer 72 includes a sintered body of metal particles. The metal particles include silver. Alternatively, the metal particles may include copper. The bonding layer 72 is formed by sintering the bonding material 79 of each of the three semiconductor devices A10 (see the third step S3 described below).

[0088] The wiring board 81 is individually connected to the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, the two sixth signal terminals 182, and the seventh signal terminal 19 of each of the three semiconductor devices A10. As shown in Figures 17 to 19, the wiring board 81 faces the top surface 51 of the sealing resin 50 of each of the three semiconductor devices A10.

[0089] As shown in FIG. 20 , the wiring board 81 has a substrate 811, main wiring 812, rear wiring 813, and internal wiring 814. The substrate 811 has a plurality of through holes 811A penetrating in the first direction z. The main wiring 812 is arranged on the opposite side of the substrate 811 from the sealing resin 50 of each of the three semiconductor devices A10 in the first direction z. The rear wiring 813 is arranged on the opposite side of the substrate 811 from the main wiring 812. The internal wiring 814 is arranged in the plurality of through holes 811A. The internal wiring 814 is connected to the main wiring 812 and the rear wiring 813. The main wiring 812 forms a conductive path between the internal wiring 814 and a control circuit 83 and a plurality of drive circuits 84 provided on the wiring board 81. Details of the control circuit 83 and the plurality of drive circuits 84 will be described later.

[0090] 20 , the first signal terminal 161 of each of the three semiconductor devices A10 has a base 161A and a bulge 161B. One side of the base 161A in the first direction z is press-fitted into one of the multiple sleeves 63 of each of the three semiconductor devices A10. The bulge 161B is provided on the other side of the base 161A in the first direction z. The bulge 161B bulges in a direction perpendicular to the first direction z.

[0091] As shown in FIGS. 17 and 19 , the first signal terminal 161 of each of the three semiconductor devices A10 is press-fitted into one of the through-holes 811A. As a result, as shown in FIG. 20 , the internal wiring 814 arranged in one of the through-holes 811A is pressed into contact with the bulging portion 161B of the first signal terminal 161. This allows the first signal terminal 161 to be electrically connected to the wiring board 81. The second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, the two sixth signal terminals 182, and the seventh signal terminal 19 of each of the three semiconductor devices A10 also have a configuration similar to the base portion 161A and the bulging portion 161B of the first signal terminal 161. Therefore, these signal terminals are press-fitted into one of the through-holes 811A, thereby providing electrical connection to the wiring board 81. This configuration allows the inverter device B to be made more compact.

[0092] 18 , the multiple support members 82 are located between the base 711 of the heat dissipation member 71 and the wiring board 81 in the first direction z. The wiring board 81 is supported by the multiple support members 82. The multiple support members 82 are columnar.

[0093] Next, the circuit of the inverter device B will be described with reference to Figures 21 and 22. A wiring board 81 is provided with a control circuit 83 electrically connected to the main wiring 812, and a plurality of drive circuits 84. The control circuit 83 is a microcomputer including a CPU (Central Processing Unit) and a memory. The control circuit 83 is electrically connected to the plurality of drive circuits 84 and is connected to the outside. The control circuit 83 generates control signals for driving the plurality of drive circuits 84 based on input signals from the outside. The control signals are generated, for example, based on PWM (Pulse Width Modulation) control. The generated control signals are output individually to the plurality of drive circuits 84.

[0094] Each of the plurality of drive circuits 84 generates a drive signal for driving one of the three semiconductor devices A10 based on a control signal input from the control circuit 83. The generated drive signal is output to either a first signal terminal 161 or a second signal terminal 162 of each of the three semiconductor devices A10.

[0095] As shown in FIG. 21 , the multiple drive circuits 84 include three first drive circuits 84A and three second drive circuits 84B. As shown in FIG. 22 , each of the three first drive circuits 84A drives a plurality of first semiconductor elements 21 of one of the three semiconductor devices A10. Each of the three first drive circuits 84A is individually connected to the first signal terminal 161 and the third signal terminal 171 of one of the three semiconductor devices A10. As shown in FIG. 22 , each of the three second drive circuits 84B drives a plurality of second semiconductor elements 22 of one of the three semiconductor devices A10. Each of the three second drive circuits 84B is individually connected to the second signal terminal 162 and the fourth signal terminal 172 of one of the three semiconductor devices A10.

[0096] 21 , the first power terminal 13 of each of the three semiconductor devices A10 is electrically connected to the positive electrode of a DC power supply 88. The two second power terminals 14 of each of the three semiconductor devices A10 are electrically connected to the negative electrode of the DC power supply 88. This allows DC power to be input to each of the three semiconductor devices A10. Then, the multiple drive circuits 84 drive the multiple first semiconductor elements 21 and multiple second semiconductor elements 22 of each of the three semiconductor devices A10, thereby outputting three-phase AC power corresponding to the U phase, V phase, and W phase, respectively, from the two third power terminals 15 of each of the three semiconductor devices A10.

[0097] 21 , the motor 89 is electrically connected to the two third power terminals 15 of each of the three semiconductor devices A10. The motor 89 is a three-phase induction motor. Three-phase AC power is input to the motor 89 from the two third power terminals 15 of each of the three semiconductor devices A10. This drives the motor 89.

[0098] 23, a description will be given of each of the plurality of drive circuits 84. Each of the plurality of drive circuits 84 includes an amplifier circuit 841, a first switch circuit 842, a gate resistor 843, a second switch circuit 844, a current cut-off resistor 845, and an overcurrent detection circuit 846.

[0099] A control signal from the control circuit 83 is input to the amplifier circuit 841. The amplifier circuit 841 amplifies the control signal and generates a drive signal for driving one of the three semiconductor devices A10. The first switch circuit 842 has terminals a, b, and c. Terminals a and b are input sides. Terminal c is output side. In the first switch circuit 842, terminal c is connected to either terminal a or terminal b. Terminal a is connected to the amplifier circuit 841. Terminal b is electrically open. Terminal c is electrically connected to the first signal terminal 161 or the second signal terminal 162 of one of the three semiconductor devices A10 via a gate resistor 843.

[0100] The second switch circuit 844 has terminals d, e, and f. Terminal d is the input side. Terminals e and f are the output side. In the second switch circuit 844, terminal d is connected to either terminal e or terminal f. Terminal d is electrically connected to the first signal terminal 161 or the second signal terminal 162 of one of the three semiconductor devices A10 via a current blocking resistor 845. In each of the multiple drive circuits 84, the gate resistor 843 and the current blocking resistor 845 are connected in parallel to each other with respect to the first signal terminal 161 or the second signal terminal 162 of one of the three semiconductor devices A10. Terminal e is electrically open. Terminal f is grounded. The resistance value r2 of the current blocking resistor 845 is greater than the resistance value r1 of the gate resistor 843.

[0101] The overcurrent detection circuit 846 controls the first switch circuit 842 and the second switch circuit 844. The overcurrent detection circuit 846 includes a current detection resistor 846A and a comparison circuit 846B. One end of the current detection resistor 846A is electrically connected to the third signal terminal 171 or the fourth signal terminal 172 of any of the three semiconductor devices A10. The other end of the current detection resistor 846A is grounded. The voltage across the terminals of the current detection resistor 846A (voltage drop amount) corresponds to the drain-source voltage of each of the multiple first semiconductor elements 21 of any of the three semiconductor devices A10, or the drain-source voltage of each of the multiple second semiconductor elements 22 of any of the three semiconductor devices A10. The voltage across the terminals of the current detection resistor 846A is applied to a comparison circuit 846B. The comparison circuit 846B compares the voltage across the terminals of the current detection resistor 846A with a reference voltage V ０ By comparing the voltage across the current detection resistor 846A with the reference voltage V, the comparison circuit 846B determines whether the first semiconductor elements 21 or the second semiconductor elements 22 of any of the three semiconductor devices A10 are in an overcurrent state. The comparison circuit 846B outputs a determination signal representing the result of the determination. Specifically, when the voltage across the current detection resistor 846A is equal to or greater than the reference voltage V, the comparison circuit 846B determines whether the first semiconductor elements 21 or the second semiconductor elements 22 of any of the three semiconductor devices A10 are in an overcurrent state. ０ If the current is greater than 0.01, it is determined that an overcurrent state exists.

[0102] When there is no overcurrent state (normal state), the terminal d of the second switch circuit 844 is connected to the terminal e. This sets the impedance of the terminal d of the second switch circuit 844 to a sufficiently high state. At the same time, the terminal c of the first switch circuit 842 is connected to the terminal a. This causes the drive signal generated by the amplifier circuit 841 to be output to the first signal terminal 161 or the second signal terminal 162 of any of the three semiconductor devices A10 via the gate resistor 843.

[0103] On the other hand, in an overcurrent state, the terminal c of the first switch circuit 842 is connected to the terminal b. This causes the impedance of the terminal c of the first switch circuit 842 to be sufficiently high. At the same time, the terminal d of the second switch circuit 844 is connected to the terminal f. This causes the terminal d to be grounded.

[0104] Therefore, in an overcurrent state, the first signal terminal 161 or the second signal terminal 162 of any of the three semiconductor devices A10 is grounded via the current-blocking resistor 845. This reduces the gate-source voltage of each of the multiple first semiconductor elements 21 of any of the three semiconductor devices A10, or the gate-source voltage of each of the multiple second semiconductor elements 22 of any of the three semiconductor devices A10. Furthermore, the drain-source short-circuit current (hereinafter referred to as "short-circuit current") of each of the multiple first semiconductor elements 21 of any of the three semiconductor devices A10, or the short-circuit current of each of the multiple second semiconductor elements 22 of any of the three semiconductor devices A10, is blocked. This allows the multiple drive circuits 84 to protect the multiple first semiconductor elements 21 and the multiple second semiconductor elements 22 from overcurrent. The blocking speed of the short-circuit current varies depending on the resistance value r2 of the current-blocking resistor 845. The larger the resistance value r2, the slower the blocking speed of the short-circuit current.

[0105] Here, if the short-circuit current exceeds the short-circuit resistance of each of the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22, the first semiconductor element 21 or the second semiconductor element 22 may be destroyed before the overcurrent protection by the plurality of drive circuits 84 is completed. Therefore, for example, a measure may be taken to provide an internal resistance between the second electrode 212 and the first detection electrode 214 inside each of the plurality of first semiconductor elements 21. This allows the internal resistance to reduce the gate-source voltage when a short-circuit current flows, thereby more reliably preventing the first semiconductor element 21 or the second semiconductor element 22 from being destroyed.

[0106] Next, an example of a method for manufacturing the inverter device B will be described with reference to Figures 24 to 29. In describing the inverter device B, attention will be focused on one of the three semiconductor devices A10. Figures 24 to 29 correspond to Figure 9, which shows the semiconductor device A10.

[0107] First, the first step S1 shown in FIG. 24 is performed. In the first step S1, a first conductive layer 121 and a second conductive layer 122 are bonded to the base material 11, which includes the heat dissipation layer 113, so as to be located on the opposite side of the base material 11 from the heat dissipation layer 113 in the first direction z. The first conductive layer 121 and the second conductive layer 122 are individually bonded to the two support layers 112 of the base material 11 via first bonding layers 129. Furthermore, in the first step S1, the first power terminal 13 is conductively bonded to the first conductive layer 121 by laser welding. At the same time, two third power terminals 15 are conductively bonded to the second conductive layer 122 by laser welding.

[0108] Next, the second step S2 shown in FIG. 25 is performed. In the second step S2, a plurality of first semiconductor elements 21 are conductively bonded to the first conductive layer 121 via the conductive bonding layer 29. At the same time, a plurality of second semiconductor elements 22 are conductively bonded to the second conductive layer 122 via the conductive bonding layer 29. Thereafter, a first conductive member 31 is conductively bonded to the plurality of first semiconductor elements 21 and the second conductive layer 122. Thereafter, two second power terminals 14 are arranged, and the second conductive member 32 is conductively bonded to the plurality of second semiconductor elements 22 and the two second power terminals 14. Thereafter, a first wiring 61 is bonded to the first conductive layer 121. At the same time, a second wiring 62 is bonded to the second conductive layer 122. Further, after that, a sealing resin 50 is formed to cover the first conductive layer 121, the second conductive layer 122, the plurality of first semiconductor elements 21, the plurality of second semiconductor elements 22, the first conductive members 31, and the second conductive members 32. The sealing resin 50 is formed by transfer molding. When forming the sealing resin 50, the heat dissipation surface 113A of the heat dissipation layer 113 of the base material 11 and the end faces 631 of each of the plurality of sleeves 63 are exposed from the sealing resin 50.

[0109] Next, a third step S3 shown in FIG. 26 is performed. In the third step S3, a bonding material 79 is placed on one side of the heat dissipation layer 113 of the base material 11 in the first direction z. The bonding material 79 is in contact with the heat dissipation surface 113A of the heat dissipation layer 113. The bonding material 79 contains metal particles. The metal particles include silver. The bonding material 79 is a paste containing the metal particles and a solvent. The bonding material 79 is placed on the heat dissipation surface 113A by a dispenser or screen printing. The bonding material 79 is then dried to remove the solvent contained in the bonding material 79. Alternatively, the bonding material 79 may be a sheet containing the metal particles. In this case, the sheet is attached to the heat dissipation surface 113A. In the third step S3, as shown in FIG. 14, the surface roughness of the bonding surface 79A of the bonding material 79 is set to be smaller than the surface roughness of the heat dissipation surface 113A.

[0110] 27 is performed. In the fourth step S4, the bonding material 79 is baked to bond the heat dissipation member 71 and the heat dissipation layer 113 of the substrate 11. At this time, the bonding surface 79A of the bonding material 79 contacts the base 711 of the heat dissipation member 71. The bonding material 79 baked in the fourth step S4 becomes the bonding layer 72.

[0111] 28 is then performed. In the fifth step S5, the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, the two sixth signal terminals 182, and the seventh signal terminal 19 are individually press-fitted into the multiple sleeves 63. This results in the arrangement of the first signal terminal 161 that is electrically connected to the first gate electrode 213 of each of the multiple first semiconductor elements 21, and the second signal terminal 162 that is electrically connected to the second gate electrode 223 of each of the multiple second semiconductor elements 22.

[0112] Finally, a sixth step S6 shown in FIG. 29 is performed. In the sixth step S6, the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, the two sixth signal terminals 182, and the seventh signal terminal 19 are individually press-fitted into a plurality of through-holes 811A in the substrate 811 of the wiring substrate 81. Additionally, a plurality of support members 82 are arranged on the base 711 of the heat dissipation member 71, and the wiring substrate 81 is then supported by the plurality of support members 82. This results in the wiring substrate 81 being arranged so as to be individually electrically connected to the first signal terminal 161 and the second signal terminal 162. Through the above steps, the inverter device B is obtained.

[0113] Next, a vehicle C equipped with the semiconductor device A10 will be described with reference to Fig. 30. The vehicle C is, for example, an electric vehicle (EV).

[0114] As shown in Figure 30, vehicle C includes an on-board charger 91, a storage battery 92, and a drive system 93. Power is supplied to the on-board charger 91 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 91 via a wired connection. The on-board charger 91 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 91 is stepped up by the converter and then supplied to the storage battery 92. The stepped-up voltage is, for example, 600V.

[0115] The drive system 93 drives the vehicle C. The drive system 93 includes an inverter 931 and a drive source 932. The semiconductor device A10 constitutes part of the inverter 931. Alternatively, the inverter 931 may include a plurality of the aforementioned inverter devices B. Power stored in the storage battery 92 is supplied to the inverter 931. The power supplied from the storage battery 92 to the inverter 931 is DC power. Unlike the power system shown in FIG. 30 , a step-up DC-DC converter may be further provided between the storage battery 92 and the inverter 931. The inverter 931 converts DC power into AC power. The inverter 931, including the semiconductor device A10, is electrically connected to the drive source 932. The drive source 932 includes an AC motor and a transmission. When AC power converted by the inverter 931 is supplied to the drive source 932, the AC motor rotates, and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotational speed transmitted from the AC motor and then rotates the drive shaft of vehicle C. This drives vehicle C. To drive vehicle C, it is necessary to freely control the rotational speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. Therefore, semiconductor device A10 in inverter 931 is necessary to output AC power whose frequency has been appropriately changed to correspond to the required rotational speed of the AC motor.

[0116] Next, the effects of the semiconductor device A10 will be described.

[0117] The semiconductor device A10 includes a heat dissipation member 71, a substrate 11 including a heat dissipation layer 113, a first conductive layer 121, a first semiconductor element 21, and a bonding material 79. The bonding material 79 is located on the opposite side of the substrate 11 from the first conductive layer 121 in the first direction z and is disposed on the heat dissipation layer 113. The bonding material 79 contains metal particles. This configuration allows the prepared bonding material 79 to be pre-applied on the heat dissipation layer 113, thereby preventing defects such as chipping from occurring in the bonding material 79. As a result, when the bonding material 79 is baked to bond the heat dissipation member 71 and the heat dissipation layer 113 in the fourth step S4 of the manufacturing process of the inverter device B, the bonding between the heat dissipation member 71 and the heat dissipation layer 113 is improved. Therefore, this configuration in the semiconductor device A10 makes it possible to prevent peeling of the substrate 11 from the heat dissipation member 71 when the heat dissipation member 71 and the substrate 11 are bonded together.

[0118] The bonding material 79 has a bonding surface 79A that faces the same side in the first direction z as the heat dissipation surface 113A of the heat dissipation layer 113. The surface roughness of the bonding surface 79A is smaller than the surface roughness of the heat dissipation surface 113A. This configuration improves the bonding state between the heat dissipation member 71 and the heat dissipation layer 113 in the inverter device B.

[0119] In the semiconductor device A11, the bonding material 79 is located inward from the periphery of the heat dissipation surface 113A of the heat dissipation layer 113 when viewed in the first direction z. As a result, in the inverter device B, gaps are formed between the corners of the heat dissipation layer 113 and the heat dissipation member 71 in the first direction z. Here, in the manufacture of the inverter device B, shear stress caused by the heat generated during firing of the bonding material 79 occurs at the interface between the bonding layer 72 and the heat dissipation layer 113. This shear stress tends to concentrate in the corners of the heat dissipation layer 113. Therefore, by adopting this configuration, the shear stress transmitted from the corners of the heat dissipation layer 113 to the bonding layer 72 is reduced, thereby effectively suppressing peeling of the substrate 11 from the heat dissipation member 71.

[0120] Second Embodiment: A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 31 and 32. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Figure 31 corresponds to Figure 7, which shows the semiconductor device A10. Figure 32 corresponds to Figure 9, which shows the semiconductor device A10.

[0121] In the semiconductor device A20, the configuration of the bonding material 79 is different from that of the semiconductor device A10.

[0122] 31 and 32 , the bonding material 79 includes a first portion 791 and a second portion 792 that are spaced apart from each other in the second direction x. As viewed in the first direction z, the plurality of first semiconductor elements 21 overlap the first portion 791. As viewed in the first direction z, the plurality of second semiconductor elements 22 overlap the second portion 792.

[0123] Next, the effects of the semiconductor device A20 will be described.

[0124] The semiconductor device A20 includes a heat dissipation member 71, a substrate 11 including a heat dissipation layer 113, a first conductive layer 121, a first semiconductor element 21, and a bonding material 79. The bonding material 79 is located on the opposite side of the substrate 11 from the first conductive layer 121 in the first direction z, and is disposed on the heat dissipation layer 113. The bonding material 79 includes metal particles. Therefore, with this configuration, the semiconductor device A20 can also suppress peeling of the substrate 11 from the heat dissipation member 71 when the heat dissipation member 71 and the substrate 11 are bonded together. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0125] In semiconductor device A20, bonding material 79 includes first portion 791 and second portion 792 that are spaced apart from each other in second direction x. This configuration can further disperse the shear stress that occurs at the interface between bonding layer 72 and heat dissipation layer 113 due to the heat generated by firing bonding material 79.

[0126] In the above case, when viewed in the first direction z, the first semiconductor element 21 overlaps the first portion 791. With this configuration, when the inverter device B is in use, heat generated from the first semiconductor element 21 can be smoothly conducted from the heat dissipation layer 113 to the heat dissipation member 71 via the bonding layer 72.

[0127] Third Embodiment: A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to Figures 33 and 34. In this figure, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. Figure 33 corresponds to Figure 9, which shows the semiconductor device A10.

[0128] The semiconductor device A30 differs from the semiconductor device A10 in that it further comprises an intermediate layer 78.

[0129] As shown in Figures 33 and 34 , the intermediate layer 78 is located between the heat dissipation surface 113A of the heat dissipation layer 113 of the base material 11 and the bonding material 79. The bonding material 79 is in contact with the intermediate layer 78. The intermediate layer 78 contains silver. Therefore, the intermediate layer 78 and the metal particles contained in the bonding material 79 each contain the same metal element. Furthermore, the metal element contained in the intermediate layer 78 is different from the metal element contained in the heat dissipation layer 113. The intermediate layer 78 is formed, for example, by electrolytic plating.

[0130] 34, the intermediate layer 78 is in contact with the heat dissipation surface 113A of the heat dissipation layer 113. The dimension of the intermediate layer 78 in the first direction z is smaller than the dimension of the bonding material 79 in the first direction z.

[0131] Next, the effects of the semiconductor device A30 will be described.

[0132] The semiconductor device A30 includes a heat dissipation member 71, a substrate 11 including a heat dissipation layer 113, a first conductive layer 121, a first semiconductor element 21, and a bonding material 79. The bonding material 79 is located on the opposite side of the substrate 11 from the first conductive layer 121 in the first direction z, and is disposed on the heat dissipation layer 113. The bonding material 79 includes metal particles. Therefore, with this configuration, even in the semiconductor device A30, when the heat dissipation member 71 and the substrate 11 are bonded together, peeling of the substrate 11 from the heat dissipation member 71 can be suppressed. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A30 achieves the same effects as the semiconductor device A10.

[0133] The semiconductor device A30 further includes an intermediate layer 78 located between the heat dissipation surface 113A of the heat dissipation layer 113 and the bonding material 79. The bonding material 79 is in contact with the intermediate layer 78. The intermediate layer 78 and the metal particles contained in the bonding material 79 each contain the same metal element. This configuration strengthens the bond between the intermediate layer 78 and the bonding layer 72 when the bonding material 79 is fired. Therefore, in the inverter device B, even if the metal element contained in the heat dissipation layer 113 is different from the metal element of the metal particles contained in the bonding material 79, interfacial peeling between the bonding layer 72 and the heat dissipation layer 113 can be suppressed.

[0134] Fourth Embodiment: A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to Figures 35 and 36. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Figure 35 corresponds to Figure 7, which shows the semiconductor device A10. Figure 36 corresponds to Figure 9, which shows the semiconductor device A10.

[0135] The semiconductor device A40 differs from the semiconductor device A10 in that it further includes a protective layer 77.

[0136] As shown in FIGS. 35 and 36 , the protective layer 77 covers the bonding surface 79A of the bonding material 79. The protective layer 77 is an insulator. The protective layer 77 includes, for example, a resin. The protective layer 77 can be peeled off from the bonding surface 79A by hand. The protective layer 77 is resistant to sulfuration. When viewed in the first direction z, the protective layer 77 protrudes beyond the periphery of the bonding surface 79A. The protective layer 77 is in contact with the bottom surface 52 of the sealing resin 50.

[0137] Next, an example of a method for manufacturing an inverter device B including a semiconductor device A40 instead of the semiconductor device A10 will be described with reference to Fig. 37. Fig. 37 corresponds to Fig. 9 showing the semiconductor device A10. In this manufacturing method, the third step S3 described above is different.

[0138] 37 , the third step S3 includes a step of disposing a bonding material 79 on one side in the first direction z of the heat dissipation layer 113 of the base material 11, and then disposing a protective layer 77 to cover the bonding material 79. In the subsequent fourth step S4, the protective layer 77 is removed by peeling before the bonding material 79 is fired.

[0139] Next, the effects of the semiconductor device A40 will be described.

[0140] The semiconductor device A40 includes a heat dissipation member 71, a substrate 11 including a heat dissipation layer 113, a first conductive layer 121, a first semiconductor element 21, and a bonding material 79. The bonding material 79 is located on the opposite side of the substrate 11 from the first conductive layer 121 in the first direction z, and is disposed on the heat dissipation layer 113. The bonding material 79 includes metal particles. Therefore, with this configuration, even in the semiconductor device A40, when the heat dissipation member 71 and the substrate 11 are bonded together, peeling of the substrate 11 from the heat dissipation member 71 can be suppressed. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A40 achieves the same effects as the semiconductor device A10.

[0141] The semiconductor device A40 further includes a protective layer 77 that covers a bonding surface 79A of the bonding material 79. This configuration more reliably prevents damage (such as abrasion) to the bonding material 79 disposed on the heat dissipation layer 113 between the third step S3 and the fourth step S4 of the manufacturing process of the inverter device B.

[0142] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0143] The present disclosure includes embodiments described in the following appendices. Appendix 1. A semiconductor device comprising: a substrate including a heat dissipation layer; a first conductive layer bonded to the substrate; a first semiconductor element bonded to the first conductive layer; and a bonding material located on the opposite side of the substrate in a first direction from the first conductive layer and disposed on the heat dissipation layer, wherein the bonding material contains metal particles. Appendix 2. The semiconductor device according to Appendix 1, further comprising a sealing resin covering the first semiconductor element, wherein the heat dissipation layer has a heat dissipation surface exposed from the sealing resin, and the bonding material is disposed on the heat dissipation surface. Appendix 3. The semiconductor device according to Appendix 2, wherein the bonding material has a bonding surface facing the same side as the heat dissipation surface in the first direction, and wherein the surface roughness of the bonding surface is smaller than the surface roughness of the heat dissipation surface. Appendix 4. The semiconductor device according to Appendix 3, further comprising a protective layer covering the bonding surface. Appendix 5. The semiconductor device according to Appendix 4, wherein the protective layer is an insulator. Appendix 6. The semiconductor device according to Appendix 5, wherein the protective layer protrudes outward beyond the periphery of the bonding surface when viewed in the first direction. Appendix 7. The semiconductor device according to Appendix 6, wherein the protective layer is in contact with the sealing resin. Appendix 8. The semiconductor device according to Appendix 3, wherein the bonding material overlaps the entire heat dissipation surface when viewed in the first direction. Appendix 9. The semiconductor device according to Appendix 3, wherein the bonding material is located inward beyond the periphery of the heat dissipation surface when viewed in the first direction. Appendix 10. The semiconductor device according to Appendix 3, further comprising an intermediate layer located between the heat dissipation surface and the bonding material, the bonding material being in contact with the intermediate layer, and the intermediate layer and the metal particles each containing the same metal element. Appendix 11. The semiconductor device according to Appendix 10, wherein the intermediate layer is in contact with the heat dissipation surface, and the metal element contained in the intermediate layer is different from the metal element contained in the heat dissipation layer. Appendix 12. 12. The semiconductor device according to claim 3, wherein the base material includes an insulating layer located on the opposite side of the heat dissipation layer from the bonding material, and the first conductive layer is bonded to the insulating layer.Appendix 13. The semiconductor device according to Appendix 12, further comprising: a second conductive layer located on the same side of the base as the first conductive layer and bonded to the insulating layer; and a second semiconductor element conductively bonded to the second conductive layer, wherein the first semiconductor element is conductively bonded to the first conductive layer, and the second semiconductor element is in electrical conduction with the first semiconductor element and is covered with the sealing resin. Appendix 14. The semiconductor device according to Appendix 13, wherein the metal particles include silver. Appendix 15. Appendix 16. An inverter device comprising: a heat dissipation member; a base including a heat dissipation layer facing the heat dissipation member in a first direction; first and second conductive layers located on the opposite side of the base from the heat dissipation member and joined to the base; a first semiconductor element conductively joined to the first conductive layer; a second semiconductor element conductively joined to the second conductive layer; a first signal terminal electrically connected to the first semiconductor element; a second signal terminal electrically connected to the second semiconductor element; a wiring board individually connected to the first signal terminal and the second signal terminal; and a bonding layer bonding the heat dissipation member and the heat dissipation layer, wherein the bonding layer includes a sintered body of metal particles. A method for manufacturing an inverter device, comprising: a first step of bonding a first conductive layer and a second conductive layer to a base material including a heat dissipation layer so that the first conductive layer and the second conductive layer are located on an opposite side of the base material from the heat dissipation layer in a first direction; a second step of conductively bonding a first semiconductor element to the first conductive layer and a second semiconductor element to the second conductive layer; a third step of arranging a bonding material on one side of the heat dissipation layer in the first direction; a fourth step of sintering the bonding material to bond the heat dissipation member and the heat dissipation layer; a fifth step of arranging a first signal terminal electrically connected to the first semiconductor element and a second signal terminal electrically connected to the second semiconductor element; and a sixth step of arranging a wiring board electrically connected to the first signal terminal and the second signal terminal, respectively, wherein the bonding material contains metal particles.Supplementary Note 17.A method for manufacturing an inverter device according to Supplementary Note 16, wherein the bonding material is a sheet containing the metal particles, and the third step involves attaching the sheet to the heat dissipation layer.Appendix 18. The method for manufacturing an inverter device according to Appendix 16, wherein the bonding material is a paste containing the metal particles, and in the third step, the paste is applied to the heat dissipation layer and then dried. Appendix 19. The method for manufacturing an inverter device according to any one of Appendixes 16 to 18, wherein the heat dissipation layer has a heat dissipation surface facing opposite to a side on which the first conductive layer and the second conductive layer are located in the first direction, and in the third step, the surface roughness of the bonding material arranged on one side of the heat dissipation layer in the first direction is made smaller than the surface roughness of the heat dissipation surface. Appendix 20. A vehicle comprising: a drive source; and the semiconductor device according to Appendix 13, wherein the semiconductor device is electrically connected to the drive source. Appendix 21. The semiconductor device according to Appendix 5, wherein the protective layer includes a resin. Appendix 22. The semiconductor device according to Appendix 21, wherein the protective layer is peelable from the bonding surface. Appendix 23. The semiconductor device according to Appendix 22, wherein the protective layer is resistant to sulfuration. Appendix 24. The semiconductor device of Appendix 11, wherein a dimension of the intermediate layer in the first direction is smaller than a dimension of the bonding material in the first direction. Appendix 25. The semiconductor device of Appendix 11, wherein the heat dissipation layer contains copper. Appendix 26. The semiconductor device of Appendix 13, wherein the metal particles contain copper. Appendix 27. The semiconductor device of Appendix 13, wherein the bonding material includes a first portion and a second portion spaced apart from each other in a direction perpendicular to the first direction, wherein the first conductive layer overlaps the first portion as viewed in the first direction, and wherein the second conductive layer overlaps the second portion as viewed in the first direction. Appendix 28. The semiconductor device of Appendix 13, further comprising: a first terminal electrically connected to the first conductive layer; and a second terminal electrically connected to the second conductive layer. Appendix 29. The semiconductor device of Appendix 28, wherein the first terminal and the second terminal are exposed from the sealing resin. Appendix 30. 18. The method for manufacturing an inverter device according to claim 17, wherein the metal particles include silver.Supplementary Note 31. The method for manufacturing an inverter device according to Supplementary Note 19, wherein the third step includes a step of arranging the bonding material on one side of the heat dissipation layer in the first direction, and then arranging a protective layer to cover the bonding material, and the fourth step includes removing the protective layer by peeling before firing the bonding material. Supplementary Note 32. A vehicle comprising: a drive source; and the inverter device according to Supplementary Note 15, wherein the inverter device is electrically connected to the drive source.

[0144] A10 to A40: Semiconductor device B: Inverter device C: Vehicle S1 to S6: First step to sixth step 11: Base material 111: Insulating layer 112: Support layer 113: Heat dissipation layer 113A: Heat dissipation surface 121: First conductive layer 121A: First main surface 122: Second conductive layer 122A: Second main surface 129: First bonding layer 13: First power terminal 131: Covered portion 132: Exposed portion 14: Second power terminal 141: Covered portion 142: Exposed portion 15: Third power terminal 151: Covered portion 152: Exposed portion 161: First signal terminal 161A: Base portion 161B: Bulging portion 162: Second signal terminal 171: Third signal terminal 172: Fourth signal terminal 181: Fifth signal terminal 182: Sixth signal terminal 19: Seventh signal terminal 21: First semiconductor element 211: First electrode 212: Second electrode 213: First gate electrode 214: First detection electrode 22: Second semiconductor element 221: Third electrode 222: Fourth electrode 223: Second gate electrode 224: Second detection electrode 23: Thermistor 29: Conductive bonding layer 31: First conductive member 311: First main portion 312: First bonding portion 313: First connecting portion 314: Second bonding portion 315: Second connecting portion 32: Second conductive member 321: Second main portion 322: Third bonding portion 323: Third connecting portion 324: Fourth bonding portion 325: Fourth connecting portion 326: Middle portion 327: Horizontal beam portion 41 to 47: First wire to seventh wire 50: Sealing resin 51: Top surface 52: Bottom surface 53, 54: First side surface, second side surface 55: Recess 61: First wiring 611: First mounting layer 612: First metal layer 613: First gate wiring layer 614: First detection wiring layer 615: First temperature detection wiring layer 616: Second detection wiring layer 62: Second wiring 621: Second mounting layer 622: Second metal layer 623: Second gate wiring layer 624: Third detection wiring layer 625: Second temperature detection wiring layer 626: Fourth detection wiring layer 63: Sleeve 631: End surface 68, 69: Second bonding layerThird bonding layer 71: Heat dissipation member 711: Base 712: Heat dissipation portion 72: Bonding layer 77: Protective layer 78: Intermediate layer 79: Bonding material 79A: Bonding surface 791, 792: First part, second part 81: Wiring board 811: Board 811A: Through hole 812: Main part wiring 813: Back part wiring 814: Internal wiring 82: Support member 83: Control circuit 84: Drive circuit 841: Amplification circuit 842: First switch circuit 843: Gate resistor 844: Second switch circuit 845: Current interruption resistor 846: Overcurrent detection circuit 846A: Current detection resistor 846B: Comparison circuit 91: On-board charger 92: Storage battery 93: Drive system 931: Inverter 932: Drive source z: First direction x: Second direction y: third direction,

Claims

1. A semiconductor device comprising: a substrate including a heat dissipation layer; a first conductive layer bonded to the substrate; a first semiconductor element bonded to the first conductive layer; and a bonding material located on the heat dissipation layer and positioned on the opposite side of the substrate from the first conductive layer in a first direction, wherein the bonding material contains metal particles.

2. The semiconductor device according to claim 1, further comprising a sealing resin covering the first semiconductor element, the heat dissipation layer having a heat dissipation surface exposed from the sealing resin, and the bonding material disposed on the heat dissipation surface.

3. The semiconductor device according to claim 2, wherein the bonding material has a bonding surface facing the same side as the heat dissipation surface in the first direction, and the surface roughness of the bonding surface is smaller than the surface roughness of the heat dissipation surface.

4. The semiconductor device according to claim 3, further comprising a protective layer covering said bonding surface.

5. The semiconductor device according to claim 4, wherein the protective layer is an insulator.

6. The semiconductor device according to claim 5, wherein said protective layer protrudes outward beyond a peripheral edge of said bonding surface when viewed in said first direction.

7. The semiconductor device according to claim 6, wherein the protective layer is in contact with the sealing resin.

8. The semiconductor device according to claim 3, wherein the bonding material overlaps the entire heat dissipation surface when viewed in the first direction.

9. The semiconductor device according to claim 3, wherein the bonding material is located inward from a periphery of the heat dissipation surface when viewed in the first direction.

10. The semiconductor device according to claim 3, further comprising an intermediate layer located between said heat dissipation surface and said bonding material, said bonding material being in contact with said intermediate layer, and said intermediate layer and said metal particles each containing the same metal element.

11. The semiconductor device according to claim 10, wherein the intermediate layer is in contact with the heat dissipation surface, and the metal element contained in the intermediate layer is different from the metal element contained in the heat dissipation layer.

12. The semiconductor device according to any one of claims 3 to 11, wherein the base material includes an insulating layer located on the opposite side of the heat dissipation layer to the bonding material, and the first conductive layer is bonded to the insulating layer.

13. The semiconductor device described in claim 12, further comprising: a second conductive layer located on the same side of the base material as the first conductive layer and bonded to the insulating layer; and a second semiconductor element conductively bonded to the second conductive layer, wherein the first semiconductor element is conductively bonded to the first conductive layer, and the second semiconductor element is electrically connected to the first semiconductor element and is covered with the sealing resin.

14. The semiconductor device according to claim 13, wherein the metal particles include silver.

15. An inverter device comprising: a heat dissipation member; a substrate including a heat dissipation layer facing the heat dissipation member in a first direction; first and second conductive layers located on the opposite side of the substrate from the heat dissipation member and joined to the substrate; a first semiconductor element conductively joined to the first conductive layer; a second semiconductor element conductively joined to the second conductive layer; a first signal terminal electrically connected to the first semiconductor element; a second signal terminal electrically connected to the second semiconductor element; a wiring board individually connected to the first signal terminal and the second signal terminal; and a bonding layer bonding the heat dissipation member and the heat dissipation layer, wherein the bonding layer includes a sintered body of metal particles.

16. A method for manufacturing an inverter device, comprising: a first step of bonding a first conductive layer and a second conductive layer to a substrate including a heat dissipation layer so that the first conductive layer and the second conductive layer are located on the opposite side of the substrate from the heat dissipation layer in a first direction; a second step of conductively bonding a first semiconductor element to the first conductive layer and a second semiconductor element to the second conductive layer; a third step of arranging a bonding material on one side of the heat dissipation layer in the first direction; a fourth step of bonding the heat dissipation member and the heat dissipation layer by firing the bonding material; a fifth step of arranging a first signal terminal conductive to the first semiconductor element and a second signal terminal conductive to the second semiconductor element; and a sixth step of arranging a wiring board individually conductive to the first signal terminal and the second signal terminal, wherein the bonding material contains metal particles.

17. The method for manufacturing an inverter device according to claim 16, wherein the bonding material is a sheet containing the metal particles, and in the third step, the sheet is attached to the heat dissipation layer.

18. The method for manufacturing an inverter device according to claim 16, wherein the bonding material is a paste containing the metal particles, and in the third step, the paste is applied to the heat dissipation layer and then dried.

19. A method for manufacturing an inverter device as described in any one of claims 16 to 18, wherein the heat dissipation layer has a heat dissipation surface facing the opposite side to the side on which the first conductive layer and the second conductive layer are located in the first direction, and in the third step, the surface roughness of the bonding material arranged on one side of the heat dissipation layer in the first direction is made smaller than the surface roughness of the heat dissipation surface.

20. A vehicle comprising: a driving source; and the semiconductor device according to claim 13, wherein the semiconductor device is electrically connected to the driving source.

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