Semiconductor device

Abstract

The present invention suppresses a decrease or variation in a threshold voltage even when a trench pitch is reduced in order to increase a channel density in a trench MOSFET having a vertical channel fin structure. A semiconductor device 1 includes: a plurality of trenches 2 having a long-side direction as a first direction, and a short-side direction as a second direction when seen in plan view, and arranged in the second direction; a source region 3 of a first conductivity type including a fin structure partitioned by the plurality of trenches 2; a channel region 5 of a second conductivity type having a fin structure partitioned by the plurality of trenches 2; and a body region 9 of the second conductivity type. The channel region 5 is connected to the body region 9, and a channel current flows in the channel region 5 vertically. The channel region 5 has a first channel region 5A contacting the lower surface of the source region 3, and a second channel region 5B disposed below the first channel region 5A. The first channel region 5A has a higher impurity concentration of the second conductivity type than the second channel region 5B.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] As one type of trench MOSFET, a trench MOSFET with a vertical channel fin structure has been proposed.

[0003] 7 is a perspective view illustrating a conventional trench MOSFET with a vertical channel fin structure, in which the gate electrode, gate insulating film, interlayer insulating film, source electrode, and drain electrode are not shown.

[0004] 7 has a plurality of trenches 2 arranged in a plane, with the longitudinal direction in a first direction and the lateral direction in a second direction. The trenches 2 shown by dotted lines in the cross section at the front of FIG. 7 are hypothetical positions corresponding to the trenches 2 in order to explain the positional relationship between the other components and the trenches 2.

[0005] The first conductivity type source region 3 includes a region at least a portion of which has a fin structure separated by a plurality of trenches 2. A second conductivity type channel region 5 having a fin structure separated by a plurality of trenches 2 is formed on the lower surface of the source region 3 and in contact with the source region 3. A first conductivity type JFET region 8 is formed below the channel region 5, and a second conductivity type body region 9 is formed on the side of the JFET region 8. The channel region 5 is connected to the body region 9. A first conductivity type drift region 10 is formed below the JFET region 8, and a first conductivity type drain region 11 is formed below the drift region 10.

[0006] 7 has a gate insulating film disposed inside the trench 2 and a gate electrode including a region at least partially disposed inside the trench 2, and a channel current flows vertically (in the depth direction) through the channel region 5. The gate electrodes embedded inside the trench 2 are connected to each other outside the trench 2.

[0007] Incidentally, an example of a patent document related to such technology is Patent Document 1. Although the names of the components and the detailed structure are different, paragraphs 0048 to 0052, FIG. 3, and FIG. 14 to FIG. 18 of Patent Document 1 describe a configuration similar to that shown in FIG. 7 described above.

[0008] Japanese Patent Application Laid-Open No. 2004-207289

[0009] According to the structure of the conventional semiconductor device 1 shown in FIG. 7, the trench pitch can be reduced to increase the channel density, thereby increasing the number of channels, and therefore the on-resistance of the entire semiconductor chip can be reduced.

[0010] 7 , however, when the trench pitch is reduced to increase the channel density and the dimension of the channel region 5 in the second direction (Fin width WF) is reduced, the depletion layers extending from the two gate electrodes sandwiching the channel region 5 become connected inside the channel region 5, resulting in a problem that the threshold voltage (Vth) becomes lower than the intended threshold voltage (Vth) (the threshold voltage (Vth) when the depletion layers are not connected inside the channel region 5). In such a case, if the Fin width WF varies due to manufacturing variations, the threshold voltage (Vth) also varies.

[0011] The problem to be solved by the present invention is to provide a semiconductor device that can suppress a decrease and variation in threshold voltage (Vth) in a trench MOSFET with a vertical channel fin structure, even when the trench pitch is reduced to increase the channel density.

[0012] In order to achieve the above object, a semiconductor device according to the present invention includes: a first conductivity type source region including a plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction in a plan view, the plurality of trenches being arranged in the second direction; a first conductivity type source region including a region having a fin structure at least a portion of which is separated by the plurality of trenches; a second conductivity type channel region in contact with a lower surface of the source region and having a fin structure separated by the plurality of trenches; a gate insulating film disposed inside the trench; a gate electrode including a region at least a portion of which is disposed inside the trench; a first conductivity type JFET region disposed below the channel region; and a second conductivity type body region disposed on a side of the JFET region, wherein ends of bottom surfaces of the plurality of trenches in the first direction are disposed within the body region, the channel region is connected to the body region, and a channel current flows in the channel region in a vertical direction, the channel region including a first channel region in contact with a lower surface of the source region and a second channel region disposed below the first channel region,

[0013] According to the semiconductor device of the present invention, even when the trench pitch is reduced to increase the channel density, it is possible to suppress the decrease and variation in the threshold voltage (Vth).

[0014] 2 is a perspective view of a semiconductor device of Example 1. FIG. 3 is an X1-X1′ cross-sectional view of FIG. 1. FIG. 4 is an X2-X2′ cross-sectional view of FIG. 1. FIG. 5 is a Y1-Y1′ cross-sectional view of FIG. 1. FIG. 6 is an impurity concentration profile with respect to depth in the Z1-Z1′ direction of FIG. 2. FIG. 7 is an X1-X1′ cross-sectional view of a semiconductor device of Example 2, corresponding to FIG. 2 of Example 1. FIG. 8 is a perspective view for schematically explaining the structure of a trench MOSFET with a conventional vertical channel fin structure.

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0016] FIG. 1 is a perspective view of a semiconductor device of Example 1. FIG. 2 is a cross-sectional view taken along X1-X1' in FIG. 1. FIG. 3 is a cross-sectional view taken along X2-X2' in FIG. 1. FIG. 4 is a cross-sectional view taken along Y1-Y1' in FIG. 1. Note that the gate electrode 7, gate insulating film 6, interlayer insulating film 14, source electrode 12, and drain electrode 13 are not shown in FIG.

[0017] The semiconductor device 1 of this embodiment has a plurality of trenches 2, a source region 3 of a first conductivity type, a channel region 5 of a second conductivity type, a gate insulating film 6, a gate electrode 7, a JFET region 8 of the first conductivity type, a body region 9 of the second conductivity type, a drift region 10 of the first conductivity type, and a drain region 11 of the first conductivity type.

[0018] In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this, and the first conductivity type may be p-type and the second conductivity type may be n-type.

[0019] The plurality of trenches 2 have a longitudinal direction in a first direction (the X1-X1' direction in FIG. 1) when viewed in a plan view, and a lateral direction in a second direction (the Y1-Y1' direction in FIG. 1), and are arranged in a plurality in the second direction. Although not shown, a group of trenches each consisting of a plurality of trenches 2 arranged in the second direction is also arranged in a plurality in the first direction. The trenches 2 shown by dotted lines in the cross section at the front of FIG. 1 and the cross section in FIG. 2 are hypothetical positions corresponding to the trenches 2 in order to explain the positional relationship between other components and the trenches 2. The depth of the trenches 2 is shallower than the body region 9 and deeper than the channel region 5.

[0020] The width of trench 2 (length in the first direction) is preferably 0.2 μm or more and 0.6 μm or less. In this example, the width of trench 2 was set to 0.5 μm. The depth of trench 2 is preferably 0.6 μm or more and 1.2 μm or less. In this example, the depth of trench 2 was set to 1.0 μm.

[0021] The first conductivity type source region 3 includes a region having a fin structure, at least a portion of which is separated by a plurality of trenches 2. A second conductivity type channel region 5 having a fin structure separated by a plurality of trenches 2 is formed on the lower surface of the source region 3 and in contact with the source region 3. A first conductivity type JFET region 8 is disposed below the channel region 5, and a second conductivity type body region 9 is disposed on the side of the JFET region 8. The channel region 5 is connected to the body region 9. Therefore, the width (length in the first direction) of the channel region 5 is the width (length in the first direction) of the trench 2 minus the overlap width between the trench 2 and the body region 9. The width (length in the first direction) of the channel region 5 is also the same as the JFET width WJ, which is the width (length in the first direction) of the JFET region 8.

[0022] In this embodiment, the source region 3 has a bottom surface depth of 0.3 μm and a first conductivity type impurity concentration of 1×10 ２０ cm －３ The depth of the bottom surface of the channel region 5 is set to 0.6 μm. Therefore, the thickness of the channel region 5 is 0.3 μm. The body region 9 can be formed by ion implantation using aluminum as a P-type impurity, for example. The depth of the bottom surface of the body region 9 is preferably 1.2 μm or more and 2.0 μm or less. The concentration of the second conductivity type impurity in the body region 9 is 1×10 １８ cm －３ was set to a certain extent.

[0023] A drift region 10 of the first conductivity type is arranged below the JFET region 8. The drift region 10 is also arranged below the body region 9. In addition, a drain region 11 of the first conductivity type, which has a higher impurity concentration than the drift region 10, is arranged below the drift region 10.

[0024] The drift region 10 is, for example, a SiC epitaxial layer formed on a SiC wafer, and has a size of 1×10 １４ cm －３ That's it, 1 x 10 １７ cm －３It is desirable that the thickness of the N-type impurity layer is 5 μm or more and 100 μm or less. In this embodiment, the concentration is 1×10 １６ cm －３ The drift region 10 determines the breakdown voltage in the off state. In this example, the breakdown voltage is set to 1200 V. The drain region 11 is, for example, a SiC wafer, and has a thickness of 1×10 １８ cm －３ It is desirable that the thickness of the insulating film be 50 μm or more and 500 μm or less. In this embodiment, the thickness is set to 150 μm.

[0025] A gate insulating film 6 is disposed inside the trench 2. At least a part of a gate electrode 7 is also disposed inside the trench 2. The gate electrodes 7 disposed inside the trench 2 are connected to each other outside the trench 2.

[0026] The gate insulating film 6 is made of, for example, SiO ２ In this example, the thickness was set to about 50 nm. ２ It is desirable to introduce nitrogen near the interface to improve interface characteristics. The gate electrode 7 can be made of, for example, polysilicon containing a high concentration of N-type dopant.

[0027] In the semiconductor device 1 of this embodiment, a channel current flows vertically (in the depth direction) in the channel region 5 of the fin structure by inputting and controlling a gate drive signal to the gate electrode 7 inside the trench 2. In other words, the semiconductor device 1 is a trench MOSFET with a vertical channel fin structure. Therefore, the number of channels can be increased by reducing the trench pitch and increasing the channel density, thereby reducing the on-resistance of the entire semiconductor chip.

[0028] 3 , in the semiconductor device 1 of this embodiment, the ends of the bottom surfaces of the plurality of trenches 2 in the first direction are located within the body region 9. This results in a structure in which three-dimensional corners of the trenches 2 are located within the body region 9. Therefore, even when a high voltage is applied, the concentration of the electric field is alleviated at the three-dimensional corners of the trenches 2, where the electric field is likely to concentrate and breakdown of the gate insulating film 6 is likely to occur, and breakdown of the gate insulating film 6 can be suppressed.

[0029] Furthermore, in the semiconductor device 1 of this embodiment, the width (length in the first direction) of the gate electrode 7 disposed inside the trench 2 is preferably set to be longer than the width (length in the first direction) of the JFET region 8 (JFET width WJ). The width of the gate electrode 7 is calculated by subtracting the thickness of the gate insulating film (two thicknesses, one in the first direction and the other in the first direction) from the width (length in the first direction) of the trench 2. The end of the bottom surface of the gate electrode 7 in the first direction in the trench 2 is preferably disposed within the body region 9. As a result, the three-dimensional corners of the trench 2 and the gate electrode 7 are located within the body region 9. This alleviates the electric field concentration at the three-dimensional corners of the trench 2, where an electric field is likely to concentrate and breakdown of the gate insulating film 6 is likely to occur, even when a high voltage is applied, thereby suppressing breakdown of the gate insulating film 6.

[0030] In the semiconductor device 1 of this embodiment, when a high voltage is applied between the drain and source, a depletion layer begins to spread laterally from the body region 9 on both sides of the JFET region 8, and when an even higher voltage is applied, the depletion layer closes and pinches off. This ensures a sufficient breakdown voltage. The first conductivity type impurity concentration of the JFET region 8 is desirably set higher than the first conductivity type impurity concentration of the drift region 10. This reduces the resistance of the JFET region 8 and the on-resistance. However, this is not limitative, and the first conductivity type impurity concentration of the JFET region 8 may be set to the same as the first conductivity type impurity concentration of the drift region 10.

[0031] In a trench MOSFET with a vertical channel fin structure, when the trench pitch is reduced to increase the channel density and the dimension of the channel region 5 in the second direction (the Fin width WF shown in FIG. 4 ) is reduced, the depletion layers extending from the two gate electrodes 7 sandwiching the channel region 5 become connected inside the channel region 5, resulting in a problem that the threshold voltage (Vth) becomes lower than the intended threshold voltage (Vth) (the threshold voltage (Vth) when the depletion layers are not connected inside the channel region 5). This is because, when the gate voltage is increased, an inversion layer (channel) is normally formed in the channel region 5 when the maximum depletion layer width is reached. However, when the Fin width WF becomes smaller than a predetermined value, the depletion layers become connected before the maximum depletion layer width is reached, resulting in a lower threshold voltage (Vth) than the intended threshold voltage (Vth). In such a case, the smaller the Fin width WF, the smaller the threshold voltage (Vth). Therefore, if the Fin width WF varies due to manufacturing variations, the threshold voltage (Vth) will vary.

[0032] Therefore, in the semiconductor device 1 of this embodiment, the channel region 5 includes a first channel region 5A in contact with the underside of the source region 3 and a second channel region 5B disposed below the first channel region 5A. The first channel region 5A has a higher second-conductivity-type impurity concentration than the second channel region 5B. By increasing the second-conductivity-type impurity concentration of the first channel region 5A disposed closer to the source region 3, the depletion layer in the first channel region 5A is less likely to expand. As a result, even when the fin width WF is small, the depletion layer is prevented from connecting before reaching its maximum depletion layer width as the gate voltage is increased, thereby maintaining the intended threshold voltage (Vth). Therefore, according to the semiconductor device 1 of this embodiment, even when the trench pitch is reduced to increase the channel density, the decrease and variation in threshold voltage (Vth) can be suppressed.

[0033] The occurrence of the problem of the threshold voltage (Vth) reduction described above is related to the second conductivity type impurity concentration of the first channel region 5A and the dimension in the second direction (Fin width WF) of the first channel region 5A. Therefore, in the semiconductor device 1 of this embodiment, the second conductivity type impurity concentration of the first channel region 5A and the dimension in the second direction (Fin width WF) of the first channel region 5A may be set to values ​​such that the depletion layers extending from the two gate electrodes 7 sandwiching the first channel region 5A do not connect inside the first channel region 5A even when a predetermined threshold voltage (Vth) is applied to the gate electrode 7. To achieve this, the second conductivity type impurity concentration of the first channel region 5A is set to 5×10 １７ cm －３ If the concentration of the second conductivity type impurity in the first channel region 5A is too high, the threshold voltage (Vth) becomes too high. １８ cm －３ In this embodiment, the impurity concentration of the second conductivity type in the first channel region 5A is preferably 5×10 １７ cm －３ The Fin width WF is preferably set to about 0.2 μm or more and 0.6 μm or less. In this embodiment, the Fin width WF is set to 0.5 μm. In this embodiment, the depth of the lower surface of the first channel region 5A is set to 0.4 μm, and the depth of the lower surface of the second channel region 5B is set to 0.6 μm. Therefore, the thickness of the first channel region 5A is 0.1 μm, and the thickness of the second channel region 5B is 0.2 μm. These thicknesses are merely examples and are not limited to these.

[0034] Furthermore, if the second conductivity type impurity concentration in the channel region 5 is low as in the conventional case, when the second conductivity type impurity is ion-implanted into the body region 9, it spreads in the lateral direction in FIG. 2 , which may lead to variations in the JFET width WJ and the width of the channel region 5. Furthermore, it is thought that the second conductivity type impurity concentration in the channel region 5 may be locally concentrated due to the lateral spreading. When the second conductivity type impurity concentration is locally concentrated, the threshold voltage (Vth) increases in that portion. Furthermore, if the width (length in the first direction) of the trench 2 is reduced to increase density while the second conductivity type impurity concentration in the channel region 5 is low as in the conventional case, the proportion of the portion inside the channel region 5 where the second conductivity type impurity concentration is locally concentrated increases due to the lateral spreading, which may have a significant impact on the variation in the threshold voltage (Vth). In contrast to this, by increasing the concentration of the second conductivity type impurities in the first channel region 5A as in this embodiment, when the second conductivity type impurities are ion-implanted into the body region 9, the second conductivity type impurities are less likely to spread laterally in the first channel region 5A, which has the effect of making the threshold voltage (Vth) less likely to fluctuate.

[0035] Furthermore, since the first channel region 5A having a high concentration of second conductivity type impurities is located close to the source region 3, there is also the effect that the barrier lowering of the channel region 5 due to the drain voltage (Drain-induced barrier lowering (DIBL), a phenomenon in which the threshold voltage decreases when the drain voltage is high) is less likely to occur. This is because the barrier is more likely to lower when the concentration is low, and the concentration near the source region 3 has a particularly large effect.

[0036] The semiconductor device 1 of this embodiment also has a source electrode 12 arranged on the front side, a drain electrode 13 arranged on the back side, an interlayer insulating film 14, and a contact region 4 of the second conductivity type.

[0037] The source electrode 12 is an electrode made of a metal such as aluminum.

[0038] The drain electrode 13 is an electrode formed of, for example, a laminated metal film (for example, titanium / nickel / gold), and is electrically connected to the drain region 11 .

[0039] The interlayer insulating film 14 is formed between the mutually connected portions of the gate electrodes 7 and the source region 3. The interlayer insulating film 14 is also formed so as to cover the upper and side portions of the mutually connected portions of the gate electrodes 7.

[0040] The contact region 4 is provided between the body region 9 and the source electrode 12, and has a higher concentration of second-conductivity-type impurities than the body region 9. By providing the contact region 4, the second-conductivity-type body region 9 and the source electrode 12 can be connected with lower resistance than by connecting them via the first-conductivity-type source region 3 or by connecting them directly to the body region 9. Note that the contact region 4 is not essential, and the source electrode 12 and the body region 9 may be connected directly without providing the contact region 4.

[0041] Regarding the impurity concentration, in this embodiment, as an example, the JFET region 8 is illustrated as n, the body region 9 and the first channel region 5A as p, the second channel region 5B as low concentration p-, the drift region 10 as low concentration n-, the source region 3 and the drain region 11 as high concentration n+, and the contact region 4 as high concentration p+, but the impurity concentration may be changed within a range that can realize the intended operation in this embodiment.

[0042] The semiconductor device 1 of this embodiment can be formed using, for example, an n+ type SiC substrate, but is not limited to this and may also be formed using a Si substrate, etc. Furthermore, for portions of this specification where no special description is given regarding the manufacturing method, the semiconductor device can be manufactured using a general semiconductor device manufacturing method, such as forming an n+ type drain region 11 on an n+ type SiC substrate and forming an n- type drift region 10 by epitaxial growth, and so detailed description thereof will be omitted.

[0043] Fig. 5 shows the impurity concentration profile with respect to depth in the Z1-Z1' direction of Fig. 2. The vertical axis represents the impurity concentration IC, which is shown on a log scale, and the horizontal axis represents the depth DP.

[0044] FIG. 5 shows the impurity concentration profiles of the source region 3, the first channel region 5A, the second channel region 5B, and the JFET region 8. As shown in FIG. 5, the peak depth of the second conductivity type impurity concentration of the first channel region 5A is preferably deeper than the junction position between the source region 3 and the first channel region 5A (the intersection point between the profile of the source region 3 and the profile of the first channel region 5A in FIG. 5). If the peak of the second conductivity type impurity concentration of the first channel region 5A exists within the source region 3, the intersection would occur to the right of the peak in FIG. 5, which would tend to shift the intersection position and thus shift the effective channel concentration of the first channel region 5A. Therefore, by employing the present embodiment, the peak impurity concentration of the first channel region 5A can be stabilized, thereby reducing variations in threshold voltage (Vth).

[0045] The second embodiment is a modification of the first embodiment, and differs from the first embodiment in the configuration of the body region 9 .

[0046] FIG. 6 is a cross-sectional view of the semiconductor device of the second embodiment taken along the line X1-X1' corresponding to FIG. 2 of the first embodiment.

[0047] In the semiconductor device 1 of this embodiment, the body region 9 includes a first body region 9A disposed on a side of the channel region 5 and a second body region 9B disposed at a position deeper than the bottom surface of the channel region 5. The first body region 9A has a lower second-conductivity-type impurity concentration than the second body region 9B. The second-conductivity-type impurity concentration of the first body region 9A is preferably equal to or lower than the second-conductivity-type impurity concentration of the second channel region 5B. As an example, FIG. 6 illustrates a case where the second-conductivity-type impurity concentration of the first body region 9A is equal to the second-conductivity-type impurity concentration of the second channel region 5B, and the second-conductivity-type impurity concentration of the second body region 9B is equal to the second-conductivity-type impurity concentration of the body region 9 of the first embodiment.

[0048] According to this embodiment, the second-conductivity-type impurity concentration in the first body region 9A is lower than that in Example 1, and therefore, when the second-conductivity-type impurity is ion-implanted into the first body region 9A, it is possible to suppress the second-conductivity-type impurity concentration in the channel region 5 from partially increasing due to the lateral spread in the lateral direction of FIG. 6 , compared to Example 1, and as a result, it is possible to make the threshold voltage (Vth) less likely to fluctuate than in Example 1. Furthermore, the second body region 9B has a high second-conductivity-type impurity concentration similar to that in Example 1, and the ends of the bottom surfaces of the plurality of trenches 2 in the first direction are disposed within the second body region 9B. Therefore, similar to Example 1, the concentration of the electric field is alleviated even when a high voltage is applied at the three-dimensional corner portions of the trenches 2 where the electric field is likely to concentrate and the breakdown of the gate insulating film 6 is likely to occur.

[0049] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied.

[0050] 1: Semiconductor device 2: Trench 3: Source region 4: Contact region 5: Channel region 5A: First channel region 5B: Second channel region 6: Gate insulating film 7: Gate electrode 8: JFET region 9: Body region 9A: First body region 9B: Second body region 10: Drift region 11: Drain region 12: Source electrode 13: Drain electrode 14: Interlayer insulating film IC: Impurity concentration DP: Depth WJ: JFET width WF: Fin width

Claims

a gate electrode including a region at least a portion of which is disposed inside the trench; a JFET region of the first conductivity type disposed below the channel region; and a body region of the second conductivity type disposed to one side of the JFET region, wherein ends of bottom surfaces of the plurality of trenches in the first direction are disposed within the body region, the channel region is connected to the body region, and a channel current flows vertically through the channel region, the channel region having a first channel region in contact with a bottom surface of the source region and a second channel region disposed below the first channel region, 2. A semiconductor device according to claim 1, characterized in that the second conductivity type impurity concentration of the first channel region and the dimension of the first channel region in the second direction are set to values ​​such that depletion layers extending from the two gate electrodes sandwiching the first channel region do not connect inside the first channel region even when a predetermined threshold voltage is applied to the gate electrodes.

3. In the method according to claim 2, the second conductive type impurity concentration of the first channel region is 5×10 １７ cm －３ That's it, 2 x 10 １８ cm －３ A semiconductor device characterized in that:

4. A semiconductor device according to claim 3, wherein the dimension of said first channel region in said second direction is 0.2 um or more and 0.6 um or less.

5. A semiconductor device according to claim 1, wherein the peak depth of the second conductivity type impurity concentration in said first channel region is deeper than the junction position between said source region and said first channel region.

6. A semiconductor device according to claim 1, wherein the body region has a first body region arranged on the side of the channel region and a second body region arranged at a position deeper than the bottom surface of the channel region, and the first body region has a lower concentration of second conductivity type impurities than the second body region.

7. A semiconductor device according to claim 6, wherein the concentration of the second conductive type impurity in said first body region is equal to or lower than the concentration of the second conductive type impurity in said second channel region.

8. A semiconductor device according to claim 1, comprising: a drift region of a first conductivity type arranged below the JFET region; and a drain region of the first conductivity type arranged below the drift region and having a higher impurity concentration than the drift region.

9. The semiconductor device according to claim 1, wherein the gate electrodes disposed inside the trench are connected to each other outside the trench.

10. A semiconductor device according to claim 1, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

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