Power device and preparation method thereof, and electronic equipment

Abstract

The invention relates to a power device and a preparation method thereof, and electronic equipment. The power device comprises a substrate, an epitaxial layer, and a source region, a base region and a first shielding region which are located in the epitaxial layer and are sequentially arranged along a first direction towards the substrate through a first surface, the second shielding regions are arranged at intervals along a second direction parallel to the first surface, penetrate through the first shielding regions along the first direction and extend into the epitaxial layer; the grid electrodes are located between the adjacent second shielding areas, are arranged at intervals in the second direction and extend into the first shielding areas in the first direction; a first preset distance is formed between the adjacent grids, and a second preset distance is formed between the bottom surface and the bottom surface of the first shielding region; the invention provides a trench gate MOSFET design with four channels in a unit cell based on the characteristic that the gate-oxide electric field at the bottom of a fully-surrounded structure trench is small, so that the channel density in the unit cell is improved, and the trench gate MOSFET with high reliability and low high-pass resistance is realized.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technologies, and particularly to a power device, a preparation method thereof, and an electronic device. Background Art

[0002] The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a widely used and high-performance power device, which has advantages such as fast switching speed, low loss, and simple drive circuit.

[0003] The existing trench-gate silicon carbide (SiC) MOSFET device structure is highly sought after due to its advantages such as high mobility of the trench-gate crystal plane, small cell size, and high channel density. However, at the same time, there is a problem that the electric field gathers at the trench hanging corner, which affects the reliability of the gate oxide. To effectively avoid the risk of dielectric layer breakdown caused by excessive electric field concentration at the bottom of the trench gate, the industry usually injects P-type columns in the bottom and its surrounding areas of the trench to construct a shielding area to relieve the electric field intensity borne by the trench dielectric layer.

[0004] However, the introduction of the shielding area will inevitably increase the on-resistance of the device, which has a negative impact on the conductivity of the device. Summary of the Invention

[0005] Based on this, in view of the technical problems in the prior art, it is necessary to provide a power device, a preparation method thereof, and an electronic device, which can at least improve the gate oxide reliability of the device and reduce its specific on-resistance while ensuring the cell size.

[0006] In a first aspect, the present application provides a power device, including: a substrate, an epitaxial layer, and a source region, a base region, and a first shielding region that are arranged in sequence along a first direction toward the substrate via a first surface within the epitaxial layer;

[0007] A second shielding region is arranged at intervals along a second direction parallel to the first surface, and penetrates the first shielding region along the first direction and extends into the epitaxial layer;

[0008] A gate is located between adjacent second shielding regions. The gates are arranged at intervals along the second direction and extend along the first direction into the first shielding region; there is a first preset distance between adjacent gates, and there is a second preset distance between the bottom surface of the gate and the bottom surface of the first shielding region.

[0009] In the power device of the above embodiment, by setting a double shielding structure (the first shielding region and the second shielding region) to share the electric field intensity in the longitudinal direction (the first direction) and the transverse direction (the second direction), the internal electric field distribution is optimized, and the electric field concentration near the gate or the base region is reduced, thereby improving the breakdown voltage.

[0010] Meanwhile, the setting of the dual-conductive channel structure increases the number of current channels in the power device cell. On the basis of the above structure, the on-resistance is further reduced. By reasonably setting the first preset spacing between the dual-conductive channel structures, the current distribution is dispersed by increasing the conductive channel density per unit area, reducing the current density of a single conductive channel, and reducing the local temperature rise. The second preset spacing can prevent the formation of a conductive channel in the first shielding region when the device is in the on state, reduce the impact of the electric field on the gate, and achieve a balanced optimization of the device on-state characteristics, breakdown voltage, and reliability.

[0011] In some embodiments, the range of the first preset spacing is: 0.4 μm - 0.6 μm;

[0012] The range of the second preset spacing is: 20 nm - 80 nm.

[0013] In some embodiments, the first shielding region has a first preset thickness and a first doping concentration;

[0014] The range of the first preset thickness is 50 nm - 150 nm;

[0015] The range of the first doping concentration is: 2e16 cm -3 -2e17 cm -3 .

[0016] In some embodiments, the second shielding region has a second doping concentration, and the second doping concentration gradually increases in the direction close to the first surface.

[0017] In some embodiments, the gate has a rounded arc surface.

[0018] In some embodiments, the power device includes at least one of the following features:

[0019] The spacing range between adjacent second shielding regions is 1.1 μm - 1.6 μm;

[0020] The width range of the first trench and the second trench is 0.3 μm - 0.5 μm;

[0021] The gate sidewall crystal plane is (11 - 20)(-1 - 120) or (1 - 100)(-1100).

[0022] In some embodiments, the power device further includes: a current spreading region, located between adjacent second shielding regions and connected to the second shielding regions, with the top surface in contact with the bottom surface of the first shielding region and the bottom surface lower than the bottom surface of the second shielding region.

[0023] The epitaxial layer has the same conductivity type as the base region and the current spreading region, and different conductivity types from the source region, the first shielding region, and the second shielding region.

[0024] In a second aspect, the present application further provides a method for manufacturing a power device for manufacturing the power device according to any one of the above embodiments, including: providing a substrate; the top surface of the substrate includes an epitaxial layer;

[0025] forming a source region, a base region, and a first shielding region arranged in sequence along a first direction toward the substrate via a first surface within the epitaxial layer;

[0026] forming a second shielding region within the epitaxial layer, the second shielding region being arranged at intervals along a second direction parallel to the first surface and penetrating the first shielding region along the first direction and extending into the epitaxial layer;

[0027] forming gates located between adjacent second shielding regions, the gates being arranged at intervals along the second direction and extending along the first direction into the first shielding region; there is a first preset distance between adjacent gates, and there is a second preset distance between the bottom surface of the gates and the bottom surface of the first shielding region.

[0028] In the manufacturing method of the above embodiment, compared with the traditional method of separately forming a shielding region by ion implantation at the bottom of the trench, the first shielding region is prepared synchronously with the source region and the base region, and penetrates the epitaxial layer along the second direction and is connected to the second shielding region. While ensuring the shielding effect, it is beneficial for the first shielding region to be short-circuited with the source region.

[0029] In addition, by precisely controlling the first preset distance and the second preset distance related to the gate manufacturing, it is avoided that the first shielding region forms a conductive channel when the device is in the on state, reducing the impact of the electric field on the gate, and realizing the balanced optimization of the electrical performance, thermal management, and process feasibility of the device.

[0030] In some embodiments, the manufacturing method includes at least one of the following features:

[0031] The range of the first preset distance is: 0.4 μm - 0.6 μm;

[0032] The range of the second preset distance is: 20 nm - 80 nm;

[0033] The first shielding region has a first preset thickness and a first doping concentration; and the range of the first preset thickness is 50 nm - 150 nm; the range of the first doping concentration is: 2e16 cm -3 -2e17 cm -3 .

[0034] In a third aspect, the present application further provides an electronic device, including the power device according to any one of the above embodiments; or a power device manufactured by the manufacturing method described in the above embodiments.

[0035] Since the power device manufacturing method and the electronic device of the above embodiments are based on the same inventive concept as the power device provided by the present invention, the manufacturing method for manufacturing such a power device and the electronic device including such a power device have all the advantages of the manufacturing method provided by the present invention, and thus will not be elaborated herein one by one.

[0036] The power device, its manufacturing method, and the electronic device provided by this application have the following unexpected technical effects:

[0037] The first shielding region and the source region and the base region adopt a synchronous manufacturing process, and are connected to the second shielding region through the epitaxial layer penetration, optimizing the internal electric field distribution in both the longitudinal and transverse directions. On the basis of making the electric field distribution more uniform, electrical short-circuiting is improved by means of structural interconnection. The first preset distance and the second preset distance related to the gate are precisely controlled to avoid the risk of adjacent gate short-circuit caused by process errors such as lithography alignment deviation, and to suppress the increase in leakage current caused by local electric field distortion.

[0038] In addition, by setting a double conductive channel structure, the number of current conduction channels in the cell is increased, and the multi-channel shunt effect is used to reduce the current density of a single channel, reduce the conduction loss, and improve the thermal management performance. Description of the Drawings

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0040] Figure 1 It is a schematic structural diagram of a trench-gate SIC MOSFET device in the prior art;

[0041] Figure 2 It is a cross-sectional schematic diagram of a power device provided in an embodiment;

[0042] Figure 3 For Figure 2 It is a schematic diagram of the position of the rounded arc surface in the gate shown;

[0043] Figure 4 It is a flowchart of a manufacturing method provided in an embodiment;

[0044] Figure 5 It is a cross-sectional schematic diagram of the substrate structure in step S20 of the manufacturing method provided in an embodiment;

[0045] Figure 6 It is a cross-sectional schematic diagram of the obtained structure after forming the source region, the base region, and the first shielding region in step S40 of the manufacturing method provided in an embodiment;

[0046] Figure 7 In step S60 of the preparation method provided in an embodiment, after forming the second shielding region, it is a schematic cross-sectional view of the obtained structure;

[0047] Figure 8 It is Figure 7 After forming the current spreading region, it is a schematic cross-sectional view of the obtained structure;

[0048] Figure 9 In step S802 of the preparation method provided in an embodiment, after forming the first trench and the second trench, it is a schematic cross-sectional view of the obtained structure;

[0049] Figure 10 In step S804 of the preparation method provided in an embodiment, after forming the gate oxide layer, it is a schematic cross-sectional view of the obtained structure;

[0050] Figure 11 In step S806 of the preparation method provided in an embodiment, after forming the gate conductive layer, it is a schematic cross-sectional view of the obtained structure;

[0051] Figure 12 It is Figure 11 After finally forming the back metal layer, it is a schematic cross-sectional view of the obtained structure.

[0052] Explanation of reference numerals:

[0053] 1. Initial substrate; 10. Substrate; 11. Buffer layer; 20. Epitaxial layer; 21. First shielding region; 22. Base region; 23. Source region; 24. Second shielding region; 25. Current spreading region; 301. First trench; 302. Second trench; 30. Gate; 31. Gate oxide layer; 32. Gate conductive layer; 12. Dielectric layer; 13. Contact layer; 14. Front metal layer; 15. Passivation layer; 16. Back metal layer. Detailed implementation manners

[0054] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0056] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type or portion discussed below may be referred to as the second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0057] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as a 90-degree rotation or other orientation), and the spatial descriptors used herein are to be interpreted accordingly.

[0058] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "includes" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from being present or added. At the same time, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0059] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, such that variations in the shapes shown can be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present application should not be limited to the specific shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0060] In an embodiment of the present application, the epitaxial layer may include a first surface on the front side and a back side opposite to the front side, i.e., a second surface. Ignoring the flatness of the first surface and the second surface, a direction towards the substrate is defined to include a first direction perpendicular to the first surface of the substrate and a second direction parallel to the first surface. Among them, the first direction and the second direction are perpendicular to each other. In an embodiment of the present application, the first direction is defined as the Y-axis direction, and the second direction is defined as the X-axis direction.

[0061] Currently, the industry mainly forms protection for the gate oxide layer by introducing various shielding layer structures during device design, specifically covering two major types: symmetric shielding structures and asymmetric shielding structures. The typical implementation method of the symmetric shielding structure is: after the gate trench is formed, an ion implantation process is performed on the bottom of the trench to add a shielding region at the bottom of the gate oxide layer. However, as Figure 1 shown in (1), the shielding region is concentrated at the bottom of the trench gate, which is not conducive to short-circuiting with the source electrode. The floating shielding region cannot fully exert its protective effect on the trench gate dielectric. At the same time, parasitic triode conduction is likely to occur under extreme working conditions, causing device failure; as Figure 1 shown in (2), for the asymmetric shielding structure, the shielding regions on both sides of the gate are asymmetric. The gate trench is embedded in the shielding region at the bottom. Although the short-circuit problem of the symmetric shielding structure is solved, only one-sided channel conduction occurs, reducing the channel density within the cell.

[0062] Therefore, how to increase the channel density within a unit cell while achieving high reliability has become one of the technical problems that need to be urgently solved by those skilled in the art.

[0063] Please refer to Figure 2, In view of this, an embodiment of the present application provides a power device, aiming to increase the channel density within a unit cell and achieve high reliability and low on-resistance. The power device includes: a substrate 10, an epitaxial layer 20, and a source region 23, a base region 22, and a first shielding region 21 that are sequentially arranged within the epitaxial layer 20 along a first direction (OY direction) toward the substrate 10 via a first surface 20a;

[0064] A second shielding region 24 is arranged at intervals along a second direction (OX direction) parallel to the first surface, and penetrates through the first shielding region along the first direction (OY direction) and extends into the epitaxial layer 20;

[0065] A gate 30 is located between adjacent second shielding regions 24. The gates 30 are arranged at intervals along the second direction (OX direction) and extend into the first shielding region 21 along the first direction (OY direction); there is a first preset distance between adjacent gates 30, and there is a second preset distance between the bottom surface of the gate 30 and the bottom surface of the first shielding region 21.

[0066] Further, in some embodiments, the power device further includes:

[0067] A current spreading region 25 is located between adjacent second shielding regions 24 and is connected to the second shielding regions 24. The top surface is in contact with the bottom surface of the first shielding region 21, and the bottom surface is lower than the bottom surface of the second shielding region 24. The epitaxial layer 20 has the same conductivity type as the base region 22 and the current spreading region 25, and different conductivity types from the source region 23, the first shielding region 21, and the second shielding region 24.

[0068] Among them, the doping concentration of the current spreading region 25 is greater than that of the epitaxial layer 20, which promotes faster diffusion of electrons in the direction of the drift region and reduces the resistance of the JFET region.

[0069] Please continue to refer to Figure 2 , in some embodiments, the range of the first preset distance is: 0.4 μm - 0.6 μm, such as 0.4 μm, 0.5 μm, or 0.6 μm, etc.; the range of the second preset distance is: 20 nm - 80 nm, such as 20 nm, 40 nm, 60 nm, or 80 nm, etc.

[0070] Since the spacing of the double conductive channels is too small or process errors (such as lithography alignment deviation) may cause short circuits between adjacent gates or local electric field distortion, which instead increases leakage current. In the above embodiments, by precisely controlling the first preset distance to be within the range of 0.4 μm - 0.6 μm, it is possible to balance the process implementation difficulty while increasing the density of conductive channels per unit area, avoid device performance degradation caused by unreasonable spacing design, and provide guarantee for the reliability and process compatibility of the device structure.

[0071] In addition, the dual-conductive channel structure can introduce a total of four conductive channels on both sides of the gate to disperse the current distribution, reduce the current density of a single conductive channel, thereby avoiding local overheating problems caused by excessive current concentration, and reducing performance losses caused by high temperature to a certain extent.

[0072] Furthermore, the thickness (dimension along the OY direction) and doping concentration of the first shielding region 21 are limited. The range of the first preset thickness of the first shielding region 21 is 50 nm - 150 nm, such as 50 nm, 100 nm, or 150 nm, etc. The range of the first doping concentration is: 2e16 cm -3 -2e17 cm -3 , such as 2e16 cm -3 , 1e17 cm -3 or 2e17 cm -3 etc. Among them, the first shielding region 21, the epitaxial layer 20, and the base region 22 form a JFET region. The thickness of the first shielding region 21 is closely related to its shielding effect and the resistance of the JFET region. Therefore, it is necessary to reasonably set the thickness of the first shielding region 21 to balance the breakdown voltage and the specific on-resistance.

[0073] Among them, a protection preset distance (second preset spacing) of 20 nm - 80 nm can ensure sufficient space at the bottom of the gate; the thickness of the first shielding region 21 is between 50 nm - 150 nm, while maintaining the doping concentration of the first shielding region 21 between 2e16 cm -3 and 5e17 cm -3 together can prevent the formation of a conductive channel between the gate and the source.

[0074] Please continue to refer to Figure 2 , furthermore, in some embodiments, the second shielding region 24 has a second doping concentration, and the second doping concentration gradually increases along the direction close to the first surface (YO direction, the opposite direction of the OY direction). The range of the second doping concentration is 2e16 cm -3 -1e18 cm -3 , such as 2e16 cm -3 , 1e17 cm -3 or 1e18 cm -3 etc. The doping concentration is high near the first surface 20a for source contact.

[0075] Considering the lateral diffusion of the second shielding region 24 and the formation of a JFET region between the second shielding region 24 and the epitaxial layer 20, which affects the conduction characteristics, in some embodiments, the size between adjacent second shielding regions 24 is limited to 1.1 μm - 1.6 μm, such as 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, or 1.6 μm, etc.

[0076] In the above embodiments, the second shielding region 24 and the epitaxial layer 20 form a semi-superjunction structure. When withstanding voltage, the P-type second shielding region and the N-type epitaxial layer 20 deplete each other to withstand high voltage. Acting together with the first shielding region 21, the electric field intensity at the bottom and corners of the gate trench is reduced, protecting the gate oxide layer 31.

[0077] In addition, the adjacent second shielding region 24 and the epitaxial layer 20 form another JET region. By reasonably increasing the spacing of the second shielding regions 24, the resistance value of the JFET region can be effectively reduced, thereby reducing the overall on-resistance of the device. At the same time, the setting of the first shielding region 21 can make up for the weakening of the protection effect of the gate oxide layer 31 caused by the increase in the spacing of the second shielding regions 24, thus maintaining reliable protection of the gate oxide layer 31 while optimizing the on-state characteristics.

[0078] Please continue to refer to Figure 2 , in some embodiments, the depth range (dimension in the OY direction) of the gate 30 is 0.8 μm - 1 μm, such as 0.8 μm, 0.9 μm or 1 μm; the width range is 0.5 μm - 0.7 μm, such as 0.5 μm, 0.6 μm or 0.7 μm, etc., and the sidewall crystal plane is (11 - 20)(-1 - 120).

[0079] Furthermore, the gate 30 has a rounded arc surface. Among them, the ratio range of the radius R1 of the rounded arc surface at the bottom of the gate 30 to the width W (dimension in the OX direction) of the gate 30 is 0.3 - 0.4, and the ratio range of the radius R2 of the rounded arc surface at the top of the gate 30 to the width of the gate 30 is 0.6 - 0.7. The specific position of the rounded arc surface is as Figure 3 shown. In the above embodiments, the rounded arc surface can relieve the electric field concentration caused by the curvature effect and at the same time remove the epitaxial layer 20 damaged by etching near the gate 30.

[0080] Figure 4 is a flowchart of a method for manufacturing a power device according to an embodiment of the present application. Referring to Figure 4 , this manufacturing method is used to manufacture the power device as described in any one of the above embodiments, including:

[0081] Step S20: Provide a substrate 10, and the top surface of the substrate 10 includes an epitaxial layer 20.

[0082] Step S40: Form source regions 23, base regions 22, and first shielding regions 21 in the epitaxial layer 20 that are arranged in sequence along a first direction (OY direction) toward the substrate 10 via a first surface 20a.

[0083] Step S60: Form second shielding regions 24 in the epitaxial layer 20. The second shielding regions 24 are arranged at intervals along a second direction (OX direction) parallel to the first surface 20a, and penetrate the first shielding regions 21 along the first direction (OY direction) and extend into the epitaxial layer 20.

[0084] Step S80: Form gates 30 located between adjacent second shielding regions 24. The gates 30 are arranged at intervals along the second direction (OX direction) and extend into the first shielding region 21 along the first direction (OY direction); there is a first preset distance between adjacent gates, and there is a second preset distance between the bottom surface and the bottom surface of the first shielding region 21.

[0085] Among them, the power device obtained after steps S20 - S80 can be referred to Figure 11 . For the convenience of understanding this application, Figure 11 An example of a power device prepared by using the preparation method provided in this application. There can be other suitable examples of power devices prepared by using the preparation method provided in this application, and this application does not limit them here.

[0086] For the above steps, specific descriptions are made with reference to the accompanying drawings.

[0087] Please refer to Figure 5 . In the step S20 extension step, it further includes: providing an initial substrate 1, and sequentially forming a buffer layer 11 and an epitaxial layer 20 along the YO direction (the opposite direction of the OY direction) on the top surface of the initial substrate 1.

[0088] Exemplarily, the initial substrate 1 and the buffer layer 11 are used to form a substrate 10, and the thickness range of the substrate 10 is 0.5μm - 3μm, such as 0.5μm, 1μm, 2μm, or 3μm, etc. The thickness and specific doping concentration of the epitaxial layer 20 are selected according to the product design voltage and are used as the drift region of the power device. It should be understood that the above data mentioned in this application are only examples and are adjusted according to the actual case in the actual embodiment, and are not limited to the above data.

[0089] Exemplarily, in the embodiment mentioned in this application, the materials of both the substrate 10 and the epitaxial layer 20 are silicon carbide (SiC).

[0090] Please refer to Figure 6 . Specifically in step S40: Perform an ion implantation process three times from top to bottom (via the first surface 20a) in the epitaxial layer 20 to form the first shielding region 21, the base region 22, and the source region 23. In an embodiment where the substrate 10 includes an N-type substrate, P-type ions can be implanted to form the first shielding region 21 and the base region 22, and N-type ions can be implanted to form the source region 23; correspondingly, by analogy with the above method, only the "P" and "N" in each step of the above method need to be interchanged.

[0091] Among them, in some embodiments, the first shielding region has a first preset thickness and a first doping concentration; the range of the first preset thickness is 50nm - 150nm, and the range of the first doping concentration is: 2e16cm-3 -2e17 cm -3 。

[0092] Please refer to Figure 7 , in step S60, it specifically includes: using high-energy implantation of P-type ions in different doses to form second shielding regions 24 arranged at intervals along the OX direction.

[0093] Please refer to Figure 8 , in some embodiments, before step S80, it further includes: using a high-energy ion implantation process or Channeling IMP to form a current spreading region 25 in the epitaxial layer 20 between adjacent second shielding regions 24; the top surface of the current spreading region 25 is in contact with the bottom surface of the first shielding region 21, and the bottom surface is lower than the bottom surface of the second shielding region 24.

[0094] Please refer to Figures 9 - 11 , in some embodiments, step S80 further includes:

[0095] Please refer to Figure 9 , step S802: Using dry etching to form a first trench 301 and a second trench 302 that extend from the first surface 20a into the epitaxial layer 20 to the first shielding region 21 between adjacent second shielding regions 24, and it is necessary to ensure that the bottom of the above trenches does not penetrate the first shielding region 21, and perform a rounding process on the above trenches formed by etching.

[0096] Among them, the width range of the first trench and the second trench is 0.3 μm - 0.5 μm, such as 0.3 μm, 0.4 μm or 0.5 μm, etc.

[0097] Please refer to Figure 10 , step S804: Using one or more of the deposition processes to form a gate oxide layer 31 covering the inner surfaces of the first trench 301 and the second trench 302. Among them, the material of the gate oxide layer 31 may include but is not limited to silicon dioxide (SiO2), aluminum oxide (Al2O3). The thickness of the gate oxide layer 31 is specifically set according to the requirements of the driving voltage, and in this embodiment, the thickness of the gate oxide layer 31 is not limited.

[0098] Please refer to Figure 11 , step S806: After filling polysilicon in the first trench 301 and the second trench 302 using any one of the deposition methods, etching or chemical mechanical polishing (CMP) is used to remove the polysilicon material outside the first trench 301 and the second trench 302 to form a gate conductive layer 32.

[0099] It should be understood that although Figure 4The steps in the flowchart are sequentially shown according to the indication of the arrows, but these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless otherwise clearly stated in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 4 At least a part of the steps in Figure 4 may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0100] Please refer to Figure 12 , after step S80, it further includes: depositing and forming a dielectric layer 12 on the top surface of the gate 30, and forming a contact layer 13 of the source region 23 through a photolithography mask; combining photolithography and using metal meshing to form a front metal layer 14 on the top surface of the contact layer 13; depositing a passivation layer 15 on the top surface of the front metal layer 14 for protecting the power device; finally, reducing the thickness of the substrate 10 by wafer thinning and forming a back metal layer 16 on the back surface of the substrate 10.

[0101] Among them, the material of the dielectric layer 12 may include but is not limited to undoped silicate glass, borophosphate glass, silicon nitride (SiN);

[0102] Among them, the material of the contact layer 13 may include but is not limited to titanium silicon alloy, cobalt silicon alloy;

[0103] Among them, the material of the front metal layer 14 may include but is not limited to aluminum (Al), copper (Cu);

[0104] Among them, the material of the passivation layer 15 at least includes silicon nitride (SiN), polyimide, and the passivation layer 15 is removed at the place where metal contact is required, and the specific pattern is related to the layout.

[0105] Among them, the material of the back metal layer 16 may include but is not limited to nickel (Ni), titanium (Ti), silver (Ag).

[0106] In some embodiments, the present application further provides an electronic device, including the power device described in any one of the above embodiments; or a power device prepared by the preparation method described in the above embodiments.

[0107] In the electronic device configured with the above power device, the double shielding region structure can reduce the chip area through parameter optimization (such as reducing the drift region thickness), meet the development requirements of miniaturized and highly integrated devices; the balance of breakdown and conduction performance is improved, and the long-term reliability (such as electromigration resistance) is significantly enhanced;

[0108] The power device, its manufacturing method, and the electronic device provided by the present application have the following unexpected technical effects:

[0109] Through the double shielding structure (the first shielding region and the second shielding region), the internal electric field distribution is optimized in the longitudinal direction (the first direction) and the transverse direction (the second direction), making the electric field distribution more uniform and increasing the breakdown voltage. The double conductive channel structure with the first preset spacing and the second preset spacing can increase the number of current conduction channels in the cell, utilize the multi-channel shunt effect to reduce the current density of a single channel, reduce the on-resistance, and improve the thermal management performance. At the same time, it avoids the formation of a conductive channel in the first shielding region in the on-state, improving the trade-off relationship between the specific on-resistance, breakdown voltage, and reliability.

[0110] In the manufacturing method, the first shielding region, the source region, and the base region adopt a synchronous manufacturing process, and are connected to the second shielding region through the epitaxial layer penetration. While maintaining the shielding effectiveness, electrical shorting is improved through structural interconnection. By precisely controlling the first preset spacing and the second preset spacing related to the gate, the risk of adjacent gate short circuit caused by process errors such as lithography alignment deviation is avoided, and the increase in leakage current caused by local electric field distortion is suppressed, realizing the collaborative optimization of the device electrical performance, thermal stability, and process compatibility.

[0111] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0112] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A power device, characterized in that, Comprising: a substrate, an epitaxial layer, and a source region, a base region, and a first shielding region that are sequentially arranged in a first direction toward the substrate via a first surface within the epitaxial layer; a second shielding region that is arranged at intervals in a second direction parallel to the first surface and penetrates the first shielding region in the first direction and extends into the epitaxial layer; gate electrodes that are located between adjacent second shielding regions, the gate electrodes are arranged at intervals in the second direction and extend in the first direction into the first shielding region; there is a first preset distance between adjacent gate electrodes, and there is a second preset distance between the bottom surface and the bottom surface of the first shielding region.

2. The power device according to claim 1, characterized in that, The range of the first preset distance is: 0.4 μm - 0.6 μm; The range of the second preset distance is: 20 nm - 80 nm.

3. The power device according to claim 2, wherein The first shielding region has a first preset thickness and a first doping concentration; The range of the first preset thickness is 50 nm - 150 nm; The range of the first doping concentration is: 2e16 cm -3 -2e17 cm -3 .

4. The power device according to claim 3, wherein, The second shielding region has a second doping concentration, and the second doping concentration gradually increases in a direction close to the first surface.

5. The power device according to any one of claims 1-4, characterized in that The gate electrode has a rounded arc surface.

6. The power device according to any one of claims 1-4, characterized in that, Comprising at least one of the following features: The distance between adjacent second shielding regions ranges from 1.1 μm - 1.6 μm; The width range of the gate electrode is 0.3 μm - 0.5 μm; The gate sidewall crystal plane is (11 - 20)(-1 - 120).

7. The power device according to any one of claims 1-4, characterized in that, Further comprising: a current spreading region that is located between adjacent second shielding regions and is connected to the second shielding region, the top surface is in contact with the bottom surface of the first shielding region, and the bottom surface is lower than the bottom surface of the second shielding region; The epitaxial layer has the same conductivity type as the base region and the current spreading region, and different conductivity types from the source region, the first shielding region, and the second shielding region.

8. A method for manufacturing a power device, characterized in that, For manufacturing the power device according to any one of claims 1 - 7, comprising: providing a substrate; the top surface of the substrate includes an epitaxial layer; forming a source region, a base region, and a first shielding region that are sequentially arranged in a first direction toward the substrate via a first surface within the epitaxial layer; forming a second shielding region within the epitaxial layer, the second shielding region is arranged at intervals in a second direction parallel to the first surface and penetrates the first shielding region in the first direction and extends into the epitaxial layer; forming gate electrodes that are located between adjacent second shielding regions, the gate electrodes are arranged at intervals in the second direction and extend in the first direction into the first shielding region; there is a first preset distance between adjacent gate electrodes, and there is a second preset distance between the bottom surface and the bottom surface of the first shielding region.

9. The preparation method according to claim 8, wherein Comprising at least one of the following features: The range of the first preset distance is: 0.4 μm - 0.6 μm; The range of the second preset distance is: 20 nm - 80 nm; The first shielding region has a first preset thickness and a first doping concentration; and The range of the first preset thickness is 50 nm - 150 nm; The range of the first doping concentration is: 2e16 cm -3 - 2e17 cm -3 .

10. An electronic device, characterized in that, Comprising: the power device according to any one of claims 1 - 7; or the power device manufactured by the manufacturing method according to claim 8.

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