Devices for LED pixel circuitry including high-k dielectric materials and methods of forming the same

Abstract

A method includes forming a feature on a substrate. A deposition process is performed for depositing a high-K dielectric layer on a top and sidewalls of the feature. Performing the deposition process includes performing one or more deposition cycles at a process temperature ranging from about 50°C to about 200°C. The metal-containing precursor includes a core metal and a ligand. Molecules of the metal-containing precursor are adsorbed on the top and sidewalls of the feature to provide a highly uniform dielectric layer having step a coverage of at least 90%.

Description

DEVICES FOR LED PIXEL CIRCUITRY INCLUDING HIGH-K DIELECTRIC MATERIALS AND METHODS OF FORMING THE SAMECROSS-REFERENCE TO RELATED APPLICATION

[0001] This Application claims priority to and the benefit of U.S. Provisional Application No. 63 / 608,142 filed December 8, 2023, and which is incorporated by reference herein for all purposes.TECHNICAL FIELD

[0002] This disclosure generally relates to thin film transistors (TFTs) and capacitors used in pixel circuitry for organic light emitting diodes (OLEDs) and micro-light emitting diodes (micro-LEDs) including high-K dielectric materials and methods of forming high-K dielectric layers in such devices.BACKGROUND

[0003] Large panel displays are used for many display applications. Large panel organic light emitting diode (OLED(s)) displays and micro light emitting diode (micro-LED(s)) displays include thousands of pixel circuits formed on a substrate which is typically a glass or a polymeric substrate and which, in some cases, can be flexible, bendable, or stretchable depending on the desired end application. Such OLED displays and micro-LED displays include an array of pixels, each pixel defining an active pixel area and circuitry for driving the active pixel area to emit light (red, blue, or green) that, when combined with the emitted light from other pixels, form an image on the display. For both OLED and micro-LED displays, the pixel circuit is a thin-film transistor (TFT) driver circuit formed in the backplane of the display. These driver circuits are sometimes referred to as a pixel circuit, a pixel driver circuit, a backplane driver circuit, or a backplane driver.

[0004] FIG. 1 is a basic schematic diagram of a simple pixel circuit for a light emitting diode (LED). The circuit is formed in the backplane of the device. As shown in FIG. 1, the exemplary circuit includes a switching TFT (TFTi), a driving TFT (TFT2), a thin film capacitor (Cs), and a diode (LED). The diode can be either an OLED or a micro-LED. Each transistor includes a source, a drain and a dielectric gate electrode. Each thin film capacitor in the driver circuit includes two conductive terminals (electrodes) separated by a dielectric.SUMMARY

[0005] This disclosure generally relates to thin film transistors (TFTs) and capacitors used in pixel circuits for organic light emitting diodes (OLEDs) and micro-light emitting diodes (micro-LEDs) including high-K dielectric materials and methods of forming high-K dielectric layers in such devices.

[0006] Some embodiments, as described herein, relate to a method is provided including forming a feature of a LED pixel circuit device on a substrate, the feature having a top surface and first and second side walls, each of the first and second sidewalls having a surface; introducing the substrate including the feature into a deposition chamber; heating the substrate including the feature to a temperature less than 150 °C; and forming a high-K dielectric layer via an atomic layer deposition process. The atomic layer deposition process includes: (1) introducing a metal-containing precursor over the substrate, wherein the metal-containing precursor comprises a core metal and a ligand, wherein molecules of the metal-containing precursor are adsorbed on the top surface and the surfaces of the first and second sidewalls of the feature; (2) introducing an oxy gen-containing co-reactant over the substrate, wherein molecules of the oxygen-containing co-reactant react with the molecules of the metal-containing precursor to form a portion of the high-K dielectric layer, and 3) repeating steps (1) and (2) until the high-K dielectric layer has a desired thickness. According to the various embodiments, the high-K dielectric layer is a conformal layer and provides a step coverage of at least 90% over a feature. The feature on which the high-K dielectric layer is formed can have an aspect ratio of up to 20:1 . Tn some embodiments, the high-K dielectric layer has a step coverage over the feature of at least 90% and a uniformity that varies by less than 5% over surfaces having a dimension of up to 3300 mm.

[0007] Some embodiments, as described herein relate to a device including: a substrate; a feature formed on the substrate, the feature having at least a top surface and first and second side walls; and a high-K dielectric layer. The feature can have an aspect ratio of up to 20:1, and the substrate can be a glass substrate or a flexible substrate. According to the various embodiments, the high-K dielectric layer is a conformal layer and provides a step coverage of at least 90% over the feature. In some embodiments, the high-K dielectric layer has a step coverage over the feature of at least 90% and a uniformity that varies by less than 5% over surfaces having a dimension of up to 3300 mm.

[0008] In some embodiments, the feature can be a thin film transistor. In one embodiment a gate electrode is formed over the high-K dielectric layer. In another embodiment, the gate electrode is formed on the substrate and the high-K dielectric layer is formed over the gate electrode.

[0009] In still other embodiments, the device can include first and second opposing electrodes of a capacitor defining a gap, wherein a high-K dielectric material fills the gap-

[0010] The preceding summary of the present disclosure is not intended to describe each embodiment of the present disclosure. The details of one or more embodiments of the disclosure are also set forth in the description below. Other features, objects,and advantages of the disclosure will be apparent from the description and from the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To assist in understanding the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0012] FIG. 1 is a circuit diagram of an exemplary pixel circuit for a OELD or microLED device;

[0013] FIG. 2A is a schematic diagram of a cross-section of an exemplary bottom gate thin film transistor;

[0014] FIG. 2B is a schematic diagram of a cross-section of exemplary top gate thin film transistor;

[0015] FIG. 3 is a schematic diagram of a cross-section of part of an exemplary pixel circuit including a thin film transistor and a capacitor;

[0016] FIGS. 4A, 4B, and 4C are schematic, cross-sectional views of a process for manufacturing a transistor, according to an embodiment of this disclosure;

[0017] FIGS. 5A and 5B are schematic, cross-sectional views of a process for manufacturing a capacitor, according to an embodiment of this disclosure; and

[0018] FIG. 6 is a flowchart of a process for depositing a high-K dielectric layer, according to an embodiment of this disclosure.

[0019] While the disclosure is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail below. It is to be understood, however, that the intention is not to limit the disclosure to the embodiment(s) described. On the contrary, the disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure as defined by the appended claims.DETAILED DESCRIPTION

[0020] The following detailed description should be read with reference to the drawings. The detailed description and the drawings, which are not necessarily to scale, depict illustrative embodiments and are not intended to limit the scope of the invention. The illustrative embodiments depicted are intended only as exemplary. Selected features of any illustrative embodiment may be incorporated into an additional embodiment unless clearly stated to the contrary.

[0021] As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the content clearly dictates otherwise. As used in this specification and the appended claims, the term “or” is generally employed in its sense including “and / or” unless the content clearly dictates otherwise.

[0022] As used herein, “have”, “having”, “include”, “including”, “comprise”, “comprising” or the like are used in their open-ended sense, and generally mean “including, but not limited to.” It will be understood that the terms “consisting of’ and “consisting essentially of” are subsumed in the term “comprising,” and the like.

[0023] The term “about” generally refers to a range of numbers that is considered equivalent to the recited value (e.g., having the same function or result). In many instances, the term “about” may include numbers that are rounded to the nearest significant figure.

[0024] The term “high-K dielectric” refers to materials having a dielectric constant greater than 8.

[0025] Numerical ranges expressed using endpoints include all numbers subsumed within that range (e.g. 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.80, 4 and 5).

[0026] All scientific and technical terms used herein have meanings commonly used in the art unless otherwise specified.

[0027] Applications such as augmented reality / virtual reality (AR / VR), in-vehicle displays, smart medical applications, and the like increasingly demand displays having high dynamic ranges and ultra-high resolutions. For pixel circuits currently used to form the LEDs used in large panel displays for such applications, the achievable pixel pitch, which is the vertical and horizonal distance between individual LED pixels on an LED display and indicative of pixel density, is limited due to poor step coverage provided by films deposited using existing physical vapor deposition (PVD) and plasma-enhanced chemical vapor deposition (PECVD) processes used toform the TFTs and the capacitor(s) in the pixel circuit. Poor step coverage results in current leakage which may cause the image on the display to flicker or stick. For ultra-high resolution displays having a high pixel per inch (PPI), a thin and conformal gate dielectric layer with low leakage current will be required for the TFTs utilized in the pixel circuit. Additionally, to achieve a high dynamic range, a high storage capacitor which can store more charge and provide ample electrical charge to turn the illuminant unit on-off quickly compared with a low storage capacitor will be needed.

[0028] To achieve a thin dielectric layer with better leakage current to meet TFT gate dielectric layer requirements and to provide increased charge storage capability for capacitors utilized in the pixel circuits for large panel display applications, a high-K dielectric material other than silicon dioxide (S1O2) and having a dielectric constant greater than 8 is needed. However, for the large panel display industry, due to process flow integration limitations and the nature of some of the substrates utilized (e.g. polymeric substrates), the selected high-K dielectric material(s) need to be suitable for deposition using a low temperature deposition process (i.e. deposition temperatures at or below 150 °C). Thus, a process that is capable of forming highly conformal layers of a high-K dielectric material to provide a step coverage of at least 90% for features having an aspect ratio of up to 20: 1 at low deposition temperatures is needed to fabricate the TFTs and capacitors used in the pixel circuits for large panel displays to enable the high resolutions and high dynamic ranges demanded by the next generation displays.

[0029] The various embodiments described herein generally relate to thin film transistors (TFTs) and capacitors used in pixel circuitry for organic light emitting diodes (OLEDs) and micro-light emitting diodes (micro-LEDs) used in large panel display devices including high-K dielectric materials and methods of forming high-K dielectric layers (i.e., dielectric layers formed from a dielectric material having a dielectric constant greater than 8) in such thin film transistors and capacitors. In particular, the high-K dielectric materials are deposited via atomic layer deposition (ALD) at temperatures less than 150 °C (low temperature ALD process).

[0030] FIG. 2A, FIG. 2B, and FIG. 3 are schematic, cross-sectional views of exemplary transistors and a transistor together with a capacitor that may be used to form a pixel circuit such as the pixel circuit shown in FIG. 1.

[0031] FIG. 2A provides a schematic, cross-sectional view of an exemplary bottom gate thin film transistor 20 which can form a part of a pixel circuit for driving a pixel 22. As can be seen in FIG. 2A, a gate electrode 24 is formed on a substrate 26. In some cases, as shown, an insulative layer (not shown) can be optionally disposed between the substrate 26 and the gate electrode 24. A dielectric layer 28 is disposed over the gate electrode 24A such that it is in contact with a top surface 30 and the sidewalls 32, 34 of the gate electrode 24 and also in contact with the underlying substrate 26 and / or optional insulator layer, if present. Also visible in the schematic diagram of FIG. 2A, is the passivation layer 36, source 38, drain 40, channel 42, and etch stop layer 44.

[0032] FIG. 2B provides a schematic, cross-sectional view of an exemplary top gate thin film transistor 50 which can form a part of a pixel circuit including pixel 52. As can be seen in FIG. 2B, the gate electrode 54 is formed on top of the dielectric layer 56 (hence, the term “top gate”). The dielectric layer 56 is formed on the substrate 58 and over the channel 60. A passivation layer 66 is formed over the gate electrode 54 and the dielectric layer 56. The source 62 and drain 64 extend through the passivation layer 66 and the dielectric layer 56 to contact the substrate 58. In some cases, an insulative layer can be optionally disposed between the substrate 58 and the dielectric layer 56 and the channel 60.

[0033] FIG. 3 is a schematic diagram of a cross-section of part of an exemplary pixel circuit including a thin film transistor 70 and a capacitor 72 formed on a substrate 78 and connected to a pixel 74. As can be seen in the diagram, thin film transistor 70 is a top gate thin film transistor in which gate electrode 76a is disposed on top of the dielectric layer 80. Additionally, the thin film transistor 70 includes a channel 82, a source 84, and a drain 86. A passivation layer 88 extends over electrodes 76a, 76b and over the dielectric layer 80. The dielectric layer 80 extends over the channel 82 and capacitor electrode 75.

[0034] Substrates 26, 58, and 78 may comprise glass or a polymeric material and, if a polymeric material, can be flexible such that it is bendable or stretchable.

[0035] FIGS. 4A, 4B, and 4C are schematic, cross-sectional views illustrating a process for manufacturing a thin film transistor (TFT), such as TFTs 20, 50, and / or 70 as described above with reference to FIGS. 2A, 2B and 3 following the method of FIG. 6. TFTs manufactured according to the method of FIG. 6 include at least one high-Kdielectric layer 106 and can be used in a pixel circuit of a LED for large panel display applications. While the TFT shown in FIGS. 4A-4C is a bottom gate TFT, it will be generally understood that the method of FIG. 6 can also be used to form a top gate TFT as well as other TFT types incorporating a dielectric layer, and more particularly a high- K dielectric layer.

[0036] As depicted by FIGS. 4A-4C, TFT 100 is formed on a substrate 102 and can form a part of a larger integrated circuit formed on that same substrate. The substrate 102 may comprise glass or a polymeric material and, if a polymeric material, can be flexible such that it is bendable or stretchable.

[0037] In FIG. 4A, a gate electrode 104 is formed over the substrate 102. The gate electrode 104 may be also referred to as a metal gate simply as a gate. The gate electrode 104 may comprise one or more conductive materials. In some embodiments, the conductive material(s) may be a metallic material such as aluminum, copper, and the like.

[0038] In some embodiments, the gate electrode 104 may be formed by blanket depositing a suitable metallic material over the substrate 102 and patterning the deposited metallic material to remove undesired portions of the deposited metallic material. The deposition process used to from the gate electrode 104 may be a physical vapor deposition (PVD) process. The patterning process may be a suitable wet etching process, a suitable dry etching process, an ion milling process, a laser drilling process, or the like.

[0039] In other embodiments, the gate electrode 104 also may be formed by depositing a sacrificial layer over the substrate, patterning the sacrificial layer to form an opening therein, filling the opening with a suitable metallic material, and removing the sacrificial layer. The sacrificial layer may comprise an insulating material or a photoresist. The patterning process may be a suitable wet etching process, a suitable dry etching process, an ion milling process, a laser drilling process, or the like. The filling process may be a suitable deposition process, such as PVD, plating, or the like.

[0040] Regardless of the process used to form the gate electrode 104, the gate electrode 104 may have a width W1 and a height Hl. In some embodiments, an aspect ratio Hl AVI of the gate electrode 104 can range from about 1: 1 to about 20:1, from about 2:1 to about 15: 1, from about 1: 1 to about 10: 1, from 2:1 to about 10: 1, or from about 2:1 to about 5:1.

[0041] In FIG. 4B, a dielectric material is deposited over the substrate 102 and along a top surface and the sidewalls of the gate electrode 104 to form a dielectric layer 106. In some embodiments, the substrate 102 with the gate electrode 104 formed thereon may be introduced into a deposition chamber 110 and the dielectric layer 106 may be deposited using an atomic layer deposition (ALD) process as described in greater detail with reference to FIG. 6.

[0042] The dielectric layer 106 can include a high-K dielectric material having a dielectric constant of at least 8 making it a high-K dielectric layer. The high-K dielectric material can include a metal oxide material, a metal silicate material, or the like formed from an organo metallic precursor including a core metal and a ligand. The core metal may be any one of Al, Ti, Ta, Hf, Zr, La, Lu, Sc, Y, Gd, Dy, or the like. The ligand can include alkylamides, alkyls, cyclopentadienyls, tetrakis(dimethylamino), tetrakis(diethylamino), tetrakis(ethylmethylamino), tert-butoxide, isopropoxide or the like. Exemplary high-K dielectric materials having a dielectric constant of at least 8 formed from such precursors may include, but are not limited to AI2O3, TaOv TiCh, ZrO2, HfO2,Y2O3, HfSiO4, La2O3, LaA103, La2HF2O7, GDScO3, DyScO3, or mixtures thereof. In one embodiment, the dielectric material forming the dielectric layer 106 can include AI2O3, HfO2, ZrO2, or a mixture of A12O3, HfO2and ZrO2. In another embodiment, the dielectric material forming the dielectric layer 106 can include Ta2Os. In still yet another embodiment, the dielectric material forming the dielectric layer 106 can include La2O3.

[0043] The dielectric layer 106 is formed such that it has a first thickness Tl on the top of the gate electrode 104 and a second thickness T2 on the sidewalls of the gate electrode 104. In some embodiments, a ratio of T2 / T1 is in a range from about 0.9 to about 1. The thickness of the deposited layer can be measured by ellipsometry. A blanket thickness across the surfaces of the feature on which the layer is deposited is used to determine uniformity. In some embodiments, a dielectric layer 106 formed according to the method of FIG. 6 can have a uniformity that varies by less than 5%, less than 3%, or less than 2% for surfaces having a dimension of up to 3300 mm.

[0044] By using the ALD process 300 of FIG. 6 for depositing the dielectric layer 106, a step coverage of the dielectric layer 106 can be improved as compared to if the dielectric layer 106 was formed using a PVD or PECVD process. In some cases, step coverage 106 of a dielectric layer formed using the ALD process 300, as describedherein with reference to FIG. 6, can be greater than 90%, greater than 95%, greater than 98%, or, some cases, greater than 99.5%. More particularly, step coverage 106 of a dielectric layer formed on a feature having an aspect ratio ranging from about 1 : 1 to about 20:1 using the ALD process 300, as described herein with reference to FIG. 6, can be greater than 90%, greater than 95%, greater than 98%, or, some cases, greater than 99.5%. Step coverage can be measured from SEM or TEM images of the structure or feature including the deposited layer such as dielectric layer 106.

[0045] In some embodiments, following the deposition process, the dielectric layer 106 can be patterned to form a gate dielectric 108. The patterning process removes portions of the dielectric layer 106 that are deposited on and are in physical contact with the substrate 102 as shown in FIG. 4C. The patterning process may comprise a suitable wet etching process, a suitable dry etching process, an ion milling process, a laser drilling process, or the like.

[0046] FIGS. 5A and 5B provide schematic, cross-sectional views of a process for manufacturing a capacitor 200 including a high-K dielectric layer. The capacitor 200 can form part of an integrated circuit that is formed on a substrate 202. More particularly, the capacitor 200 can be a part of a pixel circuit of a LED used in large panel display applications. In such embodiments, the substrate 202 may be glass or a polymeric material and, if a polymeric material, can be flexible such that it is bendable or stretchable.

[0047] In FIG. 5A, electrodes 204 and 206 are formed over the substrate 202. The electrodes 204 and 206 are spaced apart such that there is a gap 208 between the electrodes 204 and 206. The electrodes 204 and 206 may be configured as plates or electrodes of the capacitor 200. The electrodes 204 and 206 may comprise one or more conductive materials. In some embodiments, the conductive materials may be metallic materials such as aluminum, copper, and the like.

[0048] In some embodiments, the electrodes 204 and 206 may be formed by blanket depositing a suitable metallic material over the substrate 202 and patterning the deposited metallic material to remove undesired portions of the deposited metallic material. The deposition process may be a PVD process. The patterning process may be a suitable wet etching process, a suitable dry etching process, an ion milling process, a laser drilling process, or the like.

[0049] In other embodiments, the electrodes 204 and 206 may be formed by depositing a sacrificial layer over the substrate, patterning the sacrificial layer to form openings therein, filling the openings with a suitable metallic material, and removing the sacrificial layer. The sacrificial layer may comprise an insulating material or a photoresist. The patterning process may be a suitable wet etching process, a suitable dry etching process, an ion milling process, a laser drilling process, or the like. The filling process may be a suitable deposition process, such as PVD, plating, or the like. The gap 208 has a width W2 and a height H2. An aspect ratio, H2:W2, can range from can range from about 1 : 1 to about 20:1, from about 2: 1 to about 15: 1, from about 1: 1 to about 10:1, from 2: 1 to about 10:1, or from about 2: 1 to about 5: 1.

[0050] In FIG. 5B, a dielectric material is deposited over the substrate 202 and within the gap 208 (see FIG. 5A) between the electrodes 204 and 206 to form the dielectric layer 210. In some embodiments, the substrate 202 with the electrodes 204 and 206 formed thereon may be introduced into a deposition chamber 212 and the dielectric layer 210 may be deposited using an atomic layer deposition process (ALD) process as described in greater detail with reference to FIG. 6.

[0051] The dielectric layer 210 may comprise a high-K dielectric material having a dielectric constant of at least 8 making it a high-K dielectric layer. The high-K dielectric material can be a metal oxide material, a metal silicate material, or the like formed from an organo metallic precursor including a core metal and a ligand. The core metal may be any one of Al, Ti, Ta, Hf, Zr, La, Lu, Sc, Y, Gd, Dy, or the like. The ligand can include alkylamides, alkyls, cyclopentadienyls, tetrakis(dimethylamino), tetrakis(diethyl amino), tetrakis(ethylmethylamino), tert- butoxide, isopropoxide, or the like. Exemplary high-K dielectric materials having a dielectric constant of at least 8 formed from such precursors may include, but are not limited to, Ta2O5, TiO2, ZrO2, A12O3, HfO2, Y2O3, HfSiO4, La2O3, LaA103, La2HF2O?, GDSCO3, DyScO3, or mixtures thereof. In one embodiment, the high-K dielectric material forming the dielectric layer 106 can include A12O3, HfO2, ZrO2, or a mixture of A12O3, HfO2and ZrO2. In another embodiment, the dielectric material forming the dielectric layer 210 can include Ta2O In still yet another embodiment, the dielectric material forming the dielectric layer 210 can include La2O3.

[0052] By using the process 300 of FIG. 6 for depositing the dielectric layer 210 shown in FIG. 2B, a filling performance of the dielectric layer 210 is improved. By improvingthe filling performance, formation of voids in the dielectric layer 210 is reduced or avoided as determined by TEM.

[0053] FIG. 6 is a flowchart of a process 300 for depositing a high-K dielectric layer in the formation of a TFT or capacitor such as described herein. The TFT and / or capacitor may form a part of a pixel circuit of an FED used in large panel displays. The process 300 may be used to form dielectric layer 28 (FIG. 2A), 56 (FIG. 2B), and 80 (FIG. 3). The process 300 may be also used to form the dielectric material in the space between the electrodes of capacitor 72 shown in FIG. 3. In the illustrated embodiment, the process 300 is an atomic layer deposition (AED) process. In other embodiments, the process can be a plasma assisted AED process.

[0054] The process 300 starts with step 302, when a substrate is introduced into a deposition chamber. The substrate may comprise one or more features formed thereon. In some embodiments, the one or more features may be a gate electrode of a transistor such as, for example, gate electrodes 24, 54, 76a, or 76b of FIGS. 2A-3 and / or electrodes of a capacitor (e.g., electrodes 204 and 206 of FIGS. 5B). The process 300 may be performed at a process temperature (sometimes referred to as a susceptor set point) ranging from about 50°C to about 200°C, from about 50 °C to 150 °C, from about 50 °C to 120 °C, from about 50 °C to 100 °C, or from about 50 °C to 90 °C. In some embodiments, the process temperature is less than 150 °C. Depending on the deposition tool used to perform the process, the process temperature may cause the substrate to be heated to a substrate temperature at or below the process temperature. For example, the selected process temperature may cause the substrate to be heated to a temperature ranging from about 50°C to about 200°C, from about 50 °C to about 180 °C, from about 50 °C to 150 °C, from about 50 °C to 120 °C, from about 50 °C to 100 °C, or from about 50 °C to 90 °C. The process pressure can range from about 100 mTorr to about 20000 mTorr. By using a low process temperature as described above, the process 300 may be integrated into a process flow for manufacturing micro-LED displays, OLED displays, and any other type of LED displays for which a low process temperature may be desired.

[0055] In step 304, a deposition cycle is performed on the substrate. In some embodiments, the deposition cycle comprises steps 306, 308, 310, and 312. In step 306, a first precursor is introduced in the deposition chamber over the substrate. The first precursor may be a metal-containing precursor, such as an organo-metallic precursor.The metal-containing precursor includes a core metal and a ligand. The core metal may comprise Al, Ti, Ta, Hf, Zr, La, Lu, Sc, Y, Gd, Dy, or the like. The ligand may comprise alkylamides, alkyls, cyclopentadienyls, tetrakis(dimethylamino), tetrakis(diethylamino), tetrakis(ethylmethylamino), tert-butoxide, isopropoxide, or the like. In some embodiments, the precursor is introduced into the deposition chamber with a flow rate in a range from 10 seem to 10000 seem. Molecules of the precursor are adsorbed on the exposed surface of the substrate and exposed surfaces of the one or more features.

[0056] Exemplary precursors suitable for forming the high-K dielectric layer as described herein according to the various embodiments can include, but are not limited to, tetrakis(dimethylamino)titanium (TDMAT), tetrakis(dimethylamino)hafnium (TDMAH), trimethylaluminum, tetrakis(dimethylamino)zirconium (TDMAZ), and dimethylaluminum isopropoxide (DM Al). In one embodiment, the precursor used to form a high-K dielectric layer can be dimethylaluminum isopropoxide (DMAI).

[0057] In step 308, a first purge process is performed to remove un-adsorbed molecules of the first precursor from the deposition chamber. The purge process is performed by introducing an inert gas into the chamber and then evacuating the chamber. In step 310, a co-reactant is introduced in the deposition chamber over the substrate. The co-reactant may be an oxygen-containing co-reactant. The oxygen-containing co-reactant may comprise an oxygen-containing gas such as O2, H2O, O3, or the like. In some embodiments, the co-reactant is introduced into the deposition chamber at a flow rate ranging from 50 seem to 10000 seem. Molecules of the co-reactant react with molecules of the metal precursor deposited onto the surface of the substrate or exposed surface of the one or more features to form a dielectric layer from the deposited high-K dielectric material. In the illustrated embodiment, the dielectric layer is a high-K dielectric material including a high-K metal oxide material such as, for example, AI2O3, HI'CL, ZrCL, or mixtures thereof. In step 312, a second purge process is performed to remove unreacted molecules of the metal precursor and co-reactant together with any volatile reaction byproducts from the deposition chamber. Steps 304-312 are repeated until a desired thickness of the dielectric layer is achieved (Step 314)

[0058] Upon achieving the desired thickness of the high-K dielectric layer, the process 300 ends. In some embodiments, a thickness of the high-K dielectric layer may be in arange from about 10 A to about 2000 A depending on the overall panel design and application.

[0059] In some embodiments, the process 300 may be a plasma-assisted ALD process (PE-ALD). In such embodiments, a plasma is introduced into the deposition chamber over the substrate. The gas plasma may have a power in a range from about 1 kW to about 30 kW at an RF frequency of 13.56 MHz, 27.1 MHz, or higher. A PE-ALD process may be used to increase the deposition rate thereby increasing productivity and throughput.

[0060] The scope of this disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments described or illustrated herein that a person having ordinary skill in the art would comprehend. The scope of this disclosure is not limited to the example embodiments described or illustrated herein. Moreover, although this disclosure describes and illustrates respective embodiments herein as including particular components, elements, feature, functions, operations, or steps, any of these embodiments may include any combination or permutation of any of the components, elements, features, functions, operations, or steps described or illustrated anywhere herein that a person having ordinary skill in the art would comprehend. Furthermore, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Additionally, although this disclosure describes or illustrates particular embodiments as providing particular advantages, particular embodiments may provide none, some, or all of these advantages.

Claims

CLAIMS:

1. A method comprising: forming a feature of a LED pixel circuit device on a substrate, the feature having a top surface and first and second sidewalls, each of the first and second sidewalls having a surface; introducing the substrate including the feature into a deposition chamber; heating the substrate including the feature to a temperature less than 150 °C; and forming a high-K dielectric layer via an atomic layer deposition process including(a) introducing a metal-containing precursor over the substrate, wherein the metal-containing precursor comprises a core metal and a ligand, wherein molecules of the metal-containing precursor are adsorbed on the top surface and the surfaces of the first and second sidewalls of the feature,(b) introducing an oxygen-containing co-reactant over the substrate, wherein molecules of the oxygen-containing co-reactant react with the molecules of the metal-containing precursor to form a portion of the high-K dielectric layer, and(c) repeating steps (a) and (b) until the high-K dielectric layer has a desired thickness, wherein the high-K dielectric layer is a conformal layer and provides a step coverage of at least 90% over the feature.

2. The method of claim 1, wherein the high-K dielectric layer has a uniformity that varies by less than 5% over surfaces having a dimension of up to 3300 mm.

3. The method of claim 1, wherein the high-K dielectric layer provides a step coverage of at least 95% over the feature.

4. The method of claim 1, wherein the substrate including the feature is heated to a temperature ranging from 50°C to 150 °C.

5. The method of claim 1, wherein the substrate including the feature is heated to a temperature ranging from 50°C to 120 °C.

6. The method of claim 1, The method of claim 1, wherein the substrate including the feature is heated to a temperature ranging from 50°C to 100 °C.

7. The method of claim 1 , wherein the core metal comprises Al, Ti, Ta, Hf, Zr, La, Lu, Sc, Y, Gd, or Dy.

8. The method of claim 7, wherein the ligand comprises alkylamides, alkyls, cyclopentadienyls, tetrakis(dimethylamino), tetrakis (diethylamino), tetrakis(ethylmethylamino), tert-butoxide, or isopropoxide.

9. The method of claim 1, wherein the high-K dielectric layer comprises AI2O3 Ta2O5, TiO2, ZrO2, HfO2, Y2O3, HfSiO4, La2O3, LaA103, La2HF2O7, GDScO3, DyScO3, or mixtures thereof.

10. The method of claim 1, wherein the high-K dielectric layer comprises A12O3, HfO2, ZrO2, or mixtures thereof.

11. The method of claim 1 , wherein the dielectric layer comprises T a2Os.

12. The method of claim 1, wherein the dielectric layer comprises A12O3.

13. The method of claim 1 , wherein the high-K dielectric layer comprises a lanthanum-containing dielectric material having a dielectric constant greater than 8.

14. The method of claim 1, wherein the substrate comprises glass.

15. The method of claim 1, wherein the substrate is flexible.

16. The method of claim 1, wherein the device is a thin film transistor and the feature is a channel and wherein the method further comprises forming a gate electrode over the high-K dielectric layer.

17. The method of claim 1, wherein the device is a thin film transistor and the feature is a gate electrode formed on the substrate and wherein the high-K dielectric layer is formed over the gate electrode.

18. The method of claim 1 , wherein the substrate further comprises first and second opposing electrodes of a capacitor defining a gap and wherein the method further comprises filling the gap with the high-K dielectric material.

19. The method of claim 1 , wherein an aspect ratio of the feature ranges 1 : 1 to 20: 1.

20. The method of claim 1 , wherein: the dielectric layer has a first thickness on the top surface of the feature and a second thickness on the surfaces of the first and second sidewalls of the feature; and a ratio of the second thickness to the first thickness ranges from 0.9 to 1.

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