Preparation method for hybrid passivated back-contact cell with partial mask layer removed

Abstract

The present disclosure relates to the technical field of back-contact cells, and in particular, to a preparation method for a hybrid passivated back-contact cell with partial mask layer removed, comprising the following steps: S1, providing a double-sided polished silicon wafer; S2, sequentially forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer obtained in S1; S3, performing first etching on the first semiconductor layer to form second semiconductor opening areas spaced apart; S4, texturing and cleaning; S5, removing part of the mask layer to reduce the thickness D of the mask layer formed in S2; S6, forming a second semiconductor layer on the back surface obtained in S5; and S7, using laser to perform second etching on a polished area on the back surface of the silicon wafer obtained in S6, to form first semiconductor opening areas. According to the present disclosure, by removing partial thickness of the mask layer, the adhesion between the mask layer and the second semiconductor layer can be enhanced, and the passivation effect of the second semiconductor layer is improved, thereby improving the cell yield and the cell conversion efficiency; moreover, the process steps are simplified, reducing the device cost.

Description

A method for preparing a combined passivation back contact battery by removing part of the mask layer

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application number 2023117147996, filed with the Chinese Patent Office on December 14, 2023, entitled “A method for preparing a combined passivated back contact battery by removing part of the mask layer,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure belongs to the technical field of back-contact batteries, and particularly relates to a method for preparing a combined passivation back-contact battery by removing part of a mask layer. Background Art

[0004] At present, the back contact battery process generally includes: S101, double-sided polishing of silicon wafers; S102, coating a protective mask layer on the back of the silicon wafer; S103, texturing and cleaning the silicon wafer to form a velvet surface opposite the protective mask layer, and then removing the protective mask layer to form a silicon wafer with a single-sided texturing and single-sided polishing structure; S104, sequentially coating a first semiconductor layer and a mask layer on the back of the silicon wafer, the first semiconductor layer comprising an intrinsic amorphous or microcrystalline silicon layer and an N-type doped amorphous or microcrystalline silicon layer; S105, laser or etching an opening on the back of the silicon wafer to form a second semiconductor opening area; S106, cleaning the silicon wafer to remove the first semiconductor layer in the second semiconductor opening area; S107, silicon wafer A front passivation layer and an anti-reflection layer are formed in sequence on the light-receiving surface, and a second semiconductor layer is formed on the back surface, wherein the second semiconductor layer comprises an intrinsic amorphous or microcrystalline silicon layer and a P-type doped amorphous or microcrystalline silicon layer; S108, openings are formed on the back surface of the silicon wafer by laser or etching to form first semiconductor opening areas that are arranged alternately with the second semiconductor opening areas; S109, the silicon wafer is cleaned to remove the mask layer in the first semiconductor opening areas; S110, a conductive film layer is deposited on the back surface of the silicon wafer; S111, an insulating groove is formed between the first semiconductor opening area and the second semiconductor opening area by laser or etching; S112, metal electrodes are formed on the first semiconductor opening area and the second semiconductor opening area of ​​the silicon wafer.

[0005] In the conventional back-contact cell process described above, a back-contact cell requires the preparation of a silicon wafer with a polished backside and textured frontside, resulting in a lengthy manufacturing process. Furthermore, in the prior art, during step S106, when the first semiconductor layer is removed, the mask layer may warp at the edge of the second semiconductor opening, thereby affecting the cell's passivation performance. Furthermore, during step S107, when the second semiconductor layer is formed on the backside, significant adhesion issues exist between the mask layer and the second semiconductor layer.

[0006] It should be noted that this part of the present disclosure only provides background technology related to the present disclosure and does not necessarily constitute prior art or public known technology.

[0007] Summary of the Invention

[0008] The purpose of the present disclosure is to overcome the defect of the prior art that the poor adhesion between the mask layer and the second semiconductor layer in the back contact battery affects the battery performance, and to provide a preparation method for a combined passivation back contact battery by removing part of the mask layer. In the preparation method of the combined passivation back contact battery, by removing part of the thickness of the mask layer, the adhesion between the mask layer and the second semiconductor layer can be improved, the passivation effect of the second semiconductor layer can be improved, and then the battery yield and battery conversion efficiency can be improved; at the same time, the process steps are simplified and the equipment cost is reduced.

[0009] To achieve the above objectives, the present disclosure provides a method for preparing a combined passivation back contact cell by removing part of the mask layer, comprising the following steps:

[0010] S1, provide double-sided polished silicon wafers;

[0011] S2. Forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer obtained in S1, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer;

[0012] S3, performing a first etching on the first semiconductor layer in a predetermined area on the back side of the silicon wafer obtained in S2 to form second semiconductor opening areas distributed at intervals;

[0013] S4, forming a textured surface in the second semiconductor opening region on the back side and on the front side simultaneously through texturing and cleaning;

[0014] S5, then removing part of the mask layer to reduce the thickness D of the mask layer formed in S2, wherein the thickness d of the removed mask layer satisfies: 50%≤d / D<100%;

[0015] S6, forming a second semiconductor layer on the back surface obtained in S5, wherein the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer;

[0016] S7. Use laser to perform a second etching on the polished area on the back side of the silicon wafer obtained in S6 to form a first semiconductor opening area.

[0017] In some preferred embodiments of the present disclosure, 50%≤d / D≤97%.

[0018] In some preferred embodiments of the present disclosure, D is 50-110 nm.

[0019] In some preferred embodiments of the present disclosure, the thickness of the mask layer retained in S5 is T, T=Dd, and the ratio of T to the thickness of the first doped polycrystalline layer is 1:1.1-100.

[0020] In some preferred embodiments of the present disclosure, the ratio of T to the thickness of the first doped polycrystalline layer and the intrinsic amorphous silicon layer is 1:1.1-100:0.08-5.

[0021] The mask layer formed by S2 can be a single-layer structure or a multi-layer composite mask layer.

[0022] In some preferred embodiments of the present disclosure, the mask layer formed by S2 is at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0023] In some other preferred embodiments of the present disclosure, the mask layer formed by S2 is a composite mask layer formed by at least one selected from amorphous silicon, polycrystalline silicon and at least one selected from silicon nitride, silicon oxide, and silicon oxynitride, and the film thickness of at least one selected from silicon nitride, silicon oxide, and silicon oxynitride in the composite mask layer is t, 70%≤t / D≤100%.

[0024] In some preferred embodiments of the present disclosure, 50%≤d / t≤100%, where t is the thickness of at least one film selected from silicon nitride, silicon oxide, and silicon oxynitride in the mask layer.

[0025] In some specific preferred embodiments of the present disclosure, the mask layer in S2 is silicon nitride and has a thickness of 50-90 nm.

[0026] In some preferred embodiments of the present disclosure, the mask layer in S2 is a composite mask layer formed by sequentially arranged amorphous silicon and silicon nitride, wherein the thickness of the amorphous silicon is 3-20 nm, and the thickness of the silicon nitride is 50-90 nm.

[0027] In some preferred embodiments of the present disclosure, in S5, the method for removing part of the mask layer is a solution etching method, and the conditions of the solution etching method include: the etching solution used is an aqueous solution containing hydrofluoric acid, the concentration of hydrofluoric acid is 2wt%-10wt%, the processing temperature is 20℃-30℃, and the reaction time is 60-500s.

[0028] In some preferred embodiments of the present disclosure, the method for preparing a combined passivation back contact cell by removing part of the mask layer further comprises:

[0029] S6 further includes the step of forming a front passivation layer and an anti-reflection layer on the front surface of the silicon wafer;

[0030] S8, forming a conductive film layer on the back side of the silicon wafer obtained in S7;

[0031] S9, performing a third etching on the conductive film layer on the back side of the silicon wafer obtained in S8 to form an insulating trench between the first semiconductor opening region and the second semiconductor opening region;

[0032] S10, forming metal electrodes respectively at the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer obtained in S9.

[0033] In some preferred embodiments of the present disclosure, the laser in S7 is an ultraviolet or green laser with a pulse width of less than 100 ns.

[0034] In some preferred embodiments of the present disclosure, the width of the first semiconductor opening region is 100-300 μm.

[0035] In some preferred embodiments of the present disclosure, the width of the second semiconductor opening region is 400-800 μm. Beneficial effects:

[0036] The present disclosure utilizes the above-mentioned technical solution, particularly after the post-texturing cleaning method, to remove a portion of the mask layer, and to control the thickness d of the removed mask layer to satisfy the following conditions: 50% ≤ d / D < 100%. Combined with a combined passivation structure, the second semiconductor layer and the first semiconductor layer can be separated by a suitably thin mask layer while ensuring that the mask layer has sufficient thickness to allow for damage-free openings during the first etching step S3 and provide sufficient protection during the texturing cleaning step S4. This ensures good insulation between the first and second semiconductor layers, avoids leakage between the first and second semiconductor layers, and prevents warping of the mask layer at the edge of the second semiconductor opening region, thereby improving the passivation effect of the second semiconductor layer and the adhesion between the mask layer and the second semiconductor layer, thereby improving battery yield and battery conversion efficiency. Furthermore, the process steps are simplified and equipment costs are reduced. Under the same conditions, if the mask layer is left too thick when removed, warping of the mask layer at the edge of the second semiconductor opening region will still occur, thereby affecting the passivation of the second semiconductor layer and, in turn, battery performance. Moreover, the second etching with laser in conjunction with S7 to form the first semiconductor opening area can significantly improve product yield and battery conversion efficiency compared to the conventional mask etching method.

[0037] In the preferred embodiment of the present invention, during the second etching process of S7 after thinning the mask layer, laser is used to remove the second semiconductor layer and the retained mask layer at one time without damaging the first semiconductor layer. Compared with the conventional mask etching method, the process flow is simplified, and the equipment for a cleaning process is eliminated, thereby reducing the equipment cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0039] FIG1 is a process flow chart of a specific embodiment of a method for preparing a combined passivation back contact cell by removing part of the mask layer disclosed herein;

[0040] FIG2 is a schematic structural diagram of a back-contact battery disclosed herein.

[0041] Explanation of the accompanying symbols: 1. silicon wafer, 2.1. tunneling oxide layer, 2.2. first doped polycrystalline layer, 3. mask layer, 4.1. intrinsic amorphous silicon layer, 4.2. second doped amorphous silicon layer, 5. conductive film layer, 6. metal electrode, 7. front passivation layer, 8. anti-reflection layer. DETAILED DESCRIPTION

[0042] In this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this disclosure, "plurality" means two or more, unless otherwise specifically specified.

[0043] In the present disclosure, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0044] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0045] The present disclosure provides a method for preparing a combined passivation back contact cell by removing part of a mask layer, comprising the following steps:

[0046] S1, provide double-sided polished silicon wafers;

[0047] S2. Forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer obtained in S1, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer;

[0048] S3, performing a first etching on the first semiconductor layer in a predetermined area on the back side of the silicon wafer obtained in S2, removing the first semiconductor layer and the mask layer in the predetermined area, and forming second semiconductor opening areas distributed at intervals;

[0049] S4, forming a textured surface in the second semiconductor opening region on the back side and on the front side simultaneously through texturing and cleaning;

[0050] S5, then removing part of the mask layer to reduce the thickness D of the mask layer formed in S2, wherein the thickness d of the removed mask layer satisfies: 50%≤d / D<100%;

[0051] S6, forming a second semiconductor layer on the back surface obtained in S5, wherein the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer;

[0052] S7. Use laser to perform a second etching on the polished area on the back side of the silicon wafer obtained in S6 to remove the second semiconductor layer and the mask layer retained in the corresponding area to form a first semiconductor opening area.

[0053] The silicon wafer described in S1 of the present disclosure may be a Czochralski single crystal silicon wafer or a cast single crystal silicon wafer, and its conductivity type may be, for example, N-type or P-type. Those skilled in the art may also perform conventional cleaning in S1 according to actual needs.

[0054] In some preferred embodiments of the present disclosure, 50%≤d / D≤97%, more preferably 70%≤d / D≤97%.

[0055] In some preferred embodiments of the present disclosure, D is 50-110 nm.

[0056] In some preferred embodiments of the present disclosure, the thickness of the mask layer retained in S5 is T, T=Dd, and the ratio of T to the thickness of the first doped polycrystalline layer is 1:1.1-100, preferably 1:1-20, further preferably 1:3.5-20, and further preferably 1:6-15. With the preferred embodiment of the present disclosure, the ratio of the thickness of the retained mask layer to the thickness of the first doped polycrystalline layer is appropriate, which is more conducive to maximizing the good insulation function between the first semiconductor layer and the second semiconductor layer, effectively avoiding leakage between the first semiconductor layer and the second semiconductor layer, and preventing the mask layer from warping at the edge of the second semiconductor opening area, thereby improving the passivation effect of the second semiconductor layer and significantly improving the adhesion between the mask layer and the second semiconductor layer, thereby further improving the battery yield and battery conversion efficiency.

[0057] In some preferred embodiments of the present disclosure, the ratio of T to the thickness of the first doped polycrystalline layer and the intrinsic amorphous silicon layer is 1:1.1-100:0.08-5, preferably 1:1-20:0.3-3, and more preferably 1:3.5-20:0.5-2. The preferred embodiment of the present disclosure further avoids leakage between the first and second semiconductor layers, improves adhesion between the mask layer and the second semiconductor layer, and enhances the passivation effect of the second semiconductor layer, thereby further improving battery yield and battery conversion efficiency.

[0058] On the basis of satisfying the above thickness ratio, those skilled in the art can select the thickness of the tunnel oxide layer and the intrinsic amorphous silicon layer from the prior art. For example, the thickness of the tunnel oxide layer is 1-2 nm, and the thickness of the intrinsic amorphous silicon layer is 5-15 nm.

[0059] The mask layer formed by S2 can be a single-layer structure or a multi-layer composite mask layer.

[0060] In some preferred embodiments of the present disclosure, the mask layer formed by S2 is at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0061] In some other preferred embodiments of the present disclosure, the mask layer formed by S2 is a composite mask layer formed by at least one selected from amorphous silicon and polycrystalline silicon and at least one selected from silicon nitride, silicon oxide, and silicon oxynitride. The composite mask layer is preferably formed by stacking various layers.

[0062] Further preferably, the thickness of the film layer of at least one selected from silicon nitride, silicon oxide, and silicon oxynitride in the composite mask layer is t, and 70%≤t / D≤100%.

[0063] In some preferred embodiments of the present disclosure, 50% ≤ d / t ≤ 100%, where t is the thickness of the at least one selected from silicon nitride, silicon oxide, and silicon oxynitride film in the mask layer. In this preferred embodiment, the composite mask layer can etch more than half or all of the at least one selected from silicon nitride, silicon oxide, and silicon oxynitride film, leaving the at least one selected from amorphous silicon and polycrystalline silicon underneath, which further enhances the insulation function between the first semiconductor layer and the second semiconductor layer.

[0064] In some specific preferred embodiments of the present disclosure, the mask layer in S2 is silicon nitride and has a thickness of 50-90 nm.

[0065] In some preferred embodiments of the present disclosure, the mask layer in S2 is a composite mask layer formed by sequentially arranged amorphous silicon and silicon nitride, wherein the thickness of the amorphous silicon is 3-20 nm, and the thickness of the silicon nitride is 50-90 nm.

[0066] In the present disclosure, one of the first doped polycrystalline layer and the second doped silicon layer is N-type and the other is P-type. The second doped silicon layer can be a doped amorphous or microcrystalline silicon layer. The doping concentration and thickness of the first doped polycrystalline layer and the second doped silicon layer can be selected from the range of the prior art according to actual needs. For example, the thickness of the first doped polycrystalline layer is 70-300nm, and the effective doping concentration is 1e19-1e21cm -3 The thickness of the second doped silicon layer is 5-20nm, and the effective doping concentration is 1e19-1e21cm -3 .

[0067] The methods for forming the first semiconductor layer and the second semiconductor layer disclosed in the present invention can be carried out according to the prior art, as long as corresponding film layers with the required thickness and doping concentration can be formed.

[0068] The predetermined area in S3 can be set by a person skilled in the art based on the pattern of the second semiconductor opening region. The first etching method in S3 can be conventional, such as laser or mask etching, preferably laser. The laser can be ultraviolet or green laser with a pulse width of less than 100 ns. The width of the second semiconductor opening region can be, for example, 400-800 μm.

[0069] The texturing cleaning conditions described in S4 of the present disclosure may be carried out with reference to those in the prior art, and may include, for example, a texturing solution comprising a mixed solution of alkali (preferably potassium hydroxide and / or sodium hydroxide), a texturing additive, and water, wherein the alkali content is 1% to 5% by weight, and the texturing additive content is 0.5% to 1% by weight; a texturing time of 8 to 20 minutes, and a texturing temperature of 75° C. to 85° C. The texturing additive may be a commercially available product in the art or may be prepared.

[0070] In some preferred embodiments of the present disclosure, in S5, the method for removing part of the mask layer is a solution etching method, which can make the retained mask layer more uniform without damaging the first semiconductor layer.

[0071] Further preferably, the solution etching method comprises: an aqueous solution containing hydrofluoric acid, a hydrofluoric acid concentration of 2wt%-10wt%, a treatment temperature of 20°C-30°C, and a reaction time of 60-500s. This preferred solution can be performed in the same equipment as the texturing and cleaning in S4, further reducing equipment costs.

[0072] The hydrofluoric acid-containing aqueous solution disclosed in the present invention may or may not contain other solutes. For example, the other solutes may be at least one of ammonium fluoride, hydrochloric acid, phosphoric acid, sulfuric acid, acetic acid, etc. The content of other solutes can be selected according to actual needs and effects, as long as it is conducive to removing part of the mask layer and making the retained mask layer more uniform without damaging the first semiconductor layer; specifically, it can be a BOE etching solution.

[0073] The preparation method of the combined passivation back contact cell in the present disclosure may also include other conventional film layer preparation steps, such as other steps for preparing an interdigitated back contact cell. In some preferred embodiments of the present disclosure, the preparation method of the combined passivation back contact cell with partial removal of the mask layer further includes: S6 also includes the step of forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer. The types and thicknesses of the front passivation layer and the anti-reflection layer can be selected with reference to the ranges in the prior art. The front passivation layer can be, for example, a single-layer amorphous silicon passivation layer, or a combination layer of an amorphous silicon passivation layer and an amorphous silicon doped layer or a microcrystalline doped layer. Those skilled in the art can select according to their needs. This disclosure will not be elaborated here.

[0074] Further preferably, in S6, a second semiconductor layer is first formed on the back side of the silicon wafer, and then a front passivation layer and an anti-reflection layer are formed. This is more conducive to avoiding the influence of bypass plating of the front passivation layer and the anti-reflection layer.

[0075] It should be pointed out in the present disclosure that the first semiconductor opening region and the second semiconductor opening region formed in S7 are arranged at intervals so that metal electrodes of different polarities can be deposited on the surfaces of the openings.

[0076] In some preferred embodiments of the present disclosure, the laser in S7 is an ultraviolet or green laser with a pulse width of less than 100 ns. In the present disclosure, because the mask layer retained in S5 is relatively thin, the laser can remove the second semiconductor layer and the mask layer retained in the corresponding region at once without damaging the first semiconductor layer, further improving battery performance.

[0077] In some preferred embodiments of the present disclosure, the width of the first semiconductor opening region is 100-300 μm.

[0078] In some preferred embodiments of the present disclosure, the method for preparing a combined passivation back contact cell by removing part of the mask layer further comprises: S8, forming a conductive film layer on the back side of the silicon wafer obtained in S7.

[0079] The formation method, type, and thickness of the conductive film layer disclosed herein can all be determined by reference to prior art techniques. For example, the conductive film layer can be formed using physical vapor deposition (PVD) or activated plasma deposition (RPD). The thickness of the conductive film layer can be, for example, 40-80 nm. The conductive film layer can be made of an indium oxide-based film doped with at least one of tin, tungsten, titanium, and zinc, or a zinc oxide-based film doped with aluminum and / or boron.

[0080] In some preferred embodiments of the present disclosure, the method for preparing a combined passivated back-contact cell with a portion of the mask layer removed further includes: S9, performing a third etching on the conductive film layer on the back side of the silicon wafer obtained in S8 to form an insulating trench between the first semiconductor opening region and the second semiconductor opening region. The third etching can be performed using mask etching or laser etching. The width of the insulating trench can be, for example, 20-100 μm, and the resistance between the first semiconductor opening region and the second semiconductor opening region after etching is greater than 1 kΩ.

[0081] In some preferred embodiments of the present disclosure, the method for preparing a combined passivated back-contact cell with partial mask layer removal further includes: S10, forming metal electrodes at the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer obtained in S9. The metal electrodes can be formed, for example, by screen printing. It is understood that the polarity of the metal electrodes at the first semiconductor opening region and the second semiconductor opening region are different.

[0082] The embodiments of the present disclosure are described in detail below, which are exemplary and only used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0083] Example 1

[0084] A method for preparing a combined passivated back contact cell, as shown in FIG1 , comprises the following steps:

[0085] S1, provide double-sided polished silicon wafer 1:

[0086] The N-type single crystal silicon wafer 11 is double-sided polished and cleaned, and the silicon wafer 1 is a Czochralski single crystal silicon wafer 1 .

[0087] S2. Forming a first semiconductor layer and a mask layer 3 in sequence on the back side of the S1 silicon wafer 1. The first semiconductor layer includes a tunneling oxide layer 2.1 and an N-type first doped polycrystalline layer 2.2 in sequence on the back side.

[0088] The thickness of the tunnel oxide layer 2.1 is 2 nm, the thickness of the first doped polycrystalline layer 2.2 is 80 nm, and the effective doping concentration is 1e20 cm -3 .

[0089] The mask layer 3 is a single layer of silicon nitride, and the thickness D of the silicon nitride is 60 nm.

[0090] S3, performing a first etching on the first semiconductor layer in a predetermined area on the back side of the S2 silicon wafer 1, removing the mask layer 3 and a portion of the first semiconductor layer in the predetermined area, and forming second semiconductor opening regions W1 distributed at intervals;

[0091] The first etching is performed using a laser method, wherein the laser is an ultraviolet laser with a pulse width of 10 ns. The width of the formed second semiconductor opening region W1 is 500 μm.

[0092] S4, forming a textured surface in the second semiconductor opening region W1 on the back surface and the front surface simultaneously through texturing and cleaning;

[0093] The texturing solution used is a mixed solution of potassium hydroxide, a texturing additive, and water, wherein the mass percentage of potassium hydroxide is 2% and the mass percentage of the texturing additive is 1%. The texturing time is 10 minutes and the texturing temperature is 80°C.

[0094] S5, removing part of the mask layer 3;

[0095] The method for removing part of the mask layer 3 is a solution etching method, the solution is a mixed solution of hydrofluoric acid and water, the concentration is 5wt%, the processing temperature is 28°C, and the reaction time is 300s; the removal of part of the mask layer 3 reduces the thickness D of the mask layer 3 formed by S2, wherein the thickness d of the removed mask layer 3 satisfies: d / D=80%.

[0096] S6. First, a second semiconductor layer is formed on the back surface. The second semiconductor layer includes an intrinsic amorphous silicon layer 4.1 and a P-type second doped amorphous silicon layer 4.2 formed in sequence on the back surface. Then, a front passivation layer 7 (specifically, an amorphous silicon passivation layer and an N-type amorphous silicon doped layer) and an anti-reflection layer 8 are formed on the front surface of the silicon wafer 1 in S5.

[0097] The thickness of the intrinsic amorphous silicon layer 4.1 is 10 nm, the thickness of the second doped amorphous silicon layer 4.2 is 15 nm, and the effective doping concentration is 1e19 cm -3 .

[0098] S7, performing a second etching on the polished area on the back side of the silicon wafer 1 in S6 to remove the second semiconductor layer and the retained mask layer 3 in the corresponding area, thereby forming a first semiconductor opening area W2;

[0099] The second etching is performed by laser, which is a green laser with a pulse width of 10ns. The width W2 of the formed first semiconductor opening region is 300μm. In the present disclosure, since the mask layer 3 is kept thin, the laser can remove the second semiconductor layer and the mask layer 3 at one time without damaging the first semiconductor layer.

[0100] S8, forming a conductive film layer 5 on the back side of the silicon wafer 1 in a fully covering manner in S7;

[0101] A transparent conductive film layer 5 is deposited on the back of the silicon wafer 11 by physical vapor deposition (PVD). The thickness of the conductive film layer 5 is 50 nm. The material of the conductive film layer 5 can be a tin-doped indium oxide-based film.

[0102] S9. Using mask etching, perform a third etching on the back side of the S8 silicon wafer 1 to form an insulating groove W3; the width Wg of the insulating groove W3 is 100 μm, and after etching, the resistance between the first semiconductor opening region and the second semiconductor opening region is greater than 1 kΩ.

[0103] S10. Using screen printing technology, metal electrodes 6 are formed at the first semiconductor opening area and the second semiconductor opening area on the back side of the silicon wafer 1 respectively; the resulting back contact battery structure is shown in FIG2 .

[0104] Example 2

[0105] The method of Example 1 is referred to, except that the thickness d of the mask layer removed in S5 satisfies: d / D=50%. To meet the removal thickness d, the process parameters need to be adjusted accordingly: the concentration of the mixed solution of hydrofluoric acid and water is 5wt%, the processing temperature is 28°C, and the reaction time is 180s.

[0106] Example 3

[0107] The method of Example 1 was followed, except that the mask layer in S2 was a composite mask layer formed of an amorphous silicon layer and a silicon nitride layer disposed in sequence, the amorphous silicon layer having a thickness of 10 nm and the silicon nitride layer having a thickness of 60 nm. In S5, all of the silicon nitride layer in the mask layer was removed, retaining the underlying amorphous silicon layer. Accordingly, the reaction time required to remove all of the silicon nitride layer was adjusted to 375 seconds.

[0108] Example 4

[0109] The method of Example 3 is referred to, except that in S5, the silicon nitride layer in the mask layer is partially removed and the removal thickness is 40 nm. To meet the removal thickness d, the process parameters need to be adjusted accordingly: the concentration of the mixed solution of hydrofluoric acid and water is 5 wt %, the processing temperature is 28° C., and the reaction time is 250 s.

[0110] Example 5

[0111] The method of Example 1 is referred to, except that the thickness of the first doped polycrystalline layer is adjusted to 70 nm in S2, so that the ratio of the thickness of the mask layer retained in S5 to the thickness of the first doped polycrystalline layer is 1:5.8.

[0112] Example 6

[0113] The method of Example 1 is referred to, except that the thickness of the intrinsic amorphous silicon layer is adjusted to 5 nm in S6, so that the ratio of the thickness of the mask layer retained in S5 to the thickness of the intrinsic amorphous silicon layer is 1:0.4.

[0114] Comparative Example 1

[0115] The method of Example 1 is referred to, except that the second etching in S7 adopts a conventional mask etching method, specifically including: forming a protective mask layer in the entire back area except the first semiconductor opening area to be etched, then etching with an etching solution (specifically a mixed solution of nitric acid, hydrofluoric acid and water, with the mass concentrations of nitric acid and hydrofluoric acid being 60% and 10%, respectively) at 25° C. for 3 minutes. After etching, the retained mask layer is removed with a mixed solution of hydrofluoric acid and water (with the same concentration as the corresponding solution in S5), and finally the protective mask layer is removed with an alkaline solution (specifically a sodium hydroxide aqueous solution with a mass concentration of 2%).

[0116] Comparative Example 2

[0117] The method of Example 1 is referred to, except that S5 is not performed, and subsequent steps such as S6 are performed directly after S4.

[0118] Comparative Example 3

[0119] The method of Example 1 is referred to, except that the mask layer is completely removed in S5, and the process parameters need to be adjusted accordingly: the concentration of the mixed solution of hydrofluoric acid and water is 5 wt %, the processing temperature is 28° C., and the reaction time is 375 s.

[0120] Test Case

[0121] The back contact cells prepared in the above embodiments and comparative examples were subjected to different preparation process index parameters, and IV tests were performed on the prepared back contact cells. The process cycle, yield and conversion efficiency among the process index parameters were extracted and compared, with the results shown in Table 1.

[0122] Table 1

[0123] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present disclosure can significantly improve the product yield while ensuring the battery conversion efficiency, which is beneficial to improving product reliability and reducing product costs.

[0124] Furthermore, according to the comparison between Example 1 and Example 2, Example 3 and Example 4, and Example 1 and Examples 5-6, respectively, it can be seen that the preferred scheme of removing part of the mask layer of appropriate thickness or the preferred scheme of retaining the mask layer thickness with an appropriate ratio of the specific layer can further take into account the improvement of both product yield and battery conversion efficiency.

[0125] The preferred embodiments of the present disclosure are described in detail above, but the present disclosure is not limited thereto. Within the technical concept of the present disclosure, various simple variations of the technical solution of the present disclosure may be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as disclosed by the present disclosure and fall within the scope of protection of the present disclosure. Industrial Applicability

[0126] The present disclosure provides a method for preparing a combined passivation back contact battery by removing part of the mask layer. In the preparation method of the combined passivation back contact battery, by removing part of the thickness of the mask layer, the adhesion between the mask layer and the second semiconductor layer can be improved, the passivation effect of the second semiconductor layer can be improved, and thus the battery yield and battery conversion efficiency can be improved; at the same time, the process steps are simplified and the equipment cost is reduced.

Claims

1. A method for preparing a combined passivation back contact cell by removing part of the mask layer, characterized in that: The following steps are involved: S1, provide double-sided polished silicon wafers; S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer obtained in S1, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer; S3, performing a first etching on the first semiconductor layer in a preset area on the back side of the silicon wafer obtained in S2 to form second semiconductor opening areas distributed at intervals; S4, forming a velvet surface in the second semiconductor opening region on the back side and on the front side simultaneously through velvet cleaning; S5, then removing part of the mask layer to reduce the thickness D of the mask layer formed in S2, wherein the thickness d of the removed mask layer satisfies: 50%≤d / D<100%; S6, then forming a second semiconductor layer on the back surface obtained in S5, the second semiconductor layer comprising an intrinsic amorphous silicon layer and a second doped silicon layer; S7. Use laser to perform a second etching on the polished area on the back side of the silicon wafer obtained in S6 to form a first semiconductor opening area.

2. The method for preparing a combined passivation back contact cell by removing part of the mask layer according to claim 1, characterized in that: 50%≤d / D≤97%, and / or, D is 50-110 nm.

3. The method for preparing a combined passivation back contact cell by removing part of the mask layer according to claim 1, characterized in that: The thickness of the mask layer retained in S5 is T, T=Dd, and the ratio of T to the thickness of the first doped polycrystalline layer is 1:1.1-100.

4. The method for preparing a combined passivation back contact cell by removing part of the mask layer according to claim 3, characterized in that: The ratio of T to the thickness of the first doped polycrystalline layer and the intrinsic amorphous silicon layer is 1:1.1-100:0.08-5.

5. The method for preparing a combined passivation back contact cell by removing part of the mask layer according to claim 1, characterized in that: The mask layer formed by S2 is at least one of silicon nitride, silicon oxide, and silicon oxynitride; and / or, The mask layer formed by S2 is a composite mask layer formed by at least one selected from amorphous silicon, polycrystalline silicon and at least one selected from silicon nitride, silicon oxide, and silicon oxynitride. The film layer thickness of at least one selected from silicon nitride, silicon oxide, and silicon oxynitride in the composite mask layer is t, 70%≤t / D≤100%.

6. The method for preparing a combined passivation back contact cell by removing part of the mask layer according to claim 5, characterized in that: 50%≤d / t≤100%, where t is the thickness of at least one film selected from silicon nitride, silicon oxide, and silicon oxynitride in the mask layer.

7. The method for preparing a combined passivation back contact cell by removing part of the mask layer according to claim 1, characterized in that: The mask layer in S2 is silicon nitride and has a thickness of 50-90 nm; or, The mask layer in S2 is a composite mask layer formed by sequentially arranged amorphous silicon and silicon nitride, wherein the thickness of the amorphous silicon contained therein is 3-20 nm, and the thickness of the silicon nitride contained therein is 50-90 nm.

8. The method for preparing a combined passivation back contact cell by removing part of the mask layer according to claim 1, characterized in that: In S5, the method for removing part of the mask layer is a solution etching method, and the conditions of the solution etching method include: the etching solution used is an aqueous solution containing hydrofluoric acid, the concentration of hydrofluoric acid is 2wt%-10wt%, the processing temperature is 20℃-30℃, and the reaction time is 60-500s.

9. The method for preparing a combined passivation back contact cell by removing part of the mask layer according to claim 1, characterized in that: The method for preparing a combined passivation back contact cell by removing part of the mask layer also includes: S6 also includes the step of forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer; S8, forming a conductive film layer on the back side of the silicon wafer obtained in S7; S9, performing a third etching on the conductive film layer on the back side of the silicon wafer obtained in S8 to form an insulating groove between the first semiconductor opening region and the second semiconductor opening region; S10, forming metal electrodes at the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer obtained in S9.

10. The method for preparing a combined passivation back contact cell by removing part of the mask layer according to claim 1, characterized in that: The laser in S7 is an ultraviolet or green laser, and the pulse width is less than 100 ns; and / or, The width of the first semiconductor opening region is 100-300 μm, and the width of the second semiconductor opening region is 400-800 μm.

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