Solar cell module and double-side-textured topcon structured cell thereof

Abstract

A solar cell module and a double-side-textured TOPCon structured cell thereof, belonging to the technical field of solar cells. The solar cell module comprises a plurality of TOPCon structured cells which are connected in series, and further comprises a support and a connecting member, the support being arranged on one side of the solar cell module, and the connecting member being arranged on the side of the support away from the solar cell module. Each TOPCon structured cell is a double-side-textured TOPCon structured cell, the first side of a silicon wafer thereof close to an emitter being of a first textured structure, and the second side of the silicon wafer close to a tunnel oxide layer being of a second textured structure; and the first textured structure and the second textured structure all comprise a plurality of tetragonal-pyramidal textured protrusions arranged at equal intervals, the average size of tetragonal pyramids of the first textured structure being smaller than the average size of tetragonal pyramids of the second textured structure. The solar cell module can maintain the passivation effect while improving the light trap effect, and avoid electricity leakage on back sides of cells.

Description

A solar cell module and its double-sided velvet-coated TOPCon structure battery Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell assembly and a double-sided textured TOPCon structure cell thereof. Background Art

[0002] With conventional energy sources becoming increasingly depleted, solar energy is undoubtedly the most widespread, cleanest, and most promising alternative energy source among current sustainable energy sources. Its development and utilization are therefore particularly important. Solar power generation devices, also known as photovoltaic cells or solar cells, generate electricity based on the photovoltaic effect of a semiconductor PN junction, directly converting solar energy into batteries. Currently, conventional batteries are limited by materials, processes, and equipment, leaving little room for efficiency improvements. Solar cells, by reducing costs and increasing efficiency, can achieve grid parity, ultimately becoming a truly large-scale renewable energy source.

[0003] High-efficiency crystalline silicon solar cells, with their low cost, high efficiency, and mature manufacturing processes, account for over 90% of the photovoltaic market and are the mainstay of photovoltaic power generation. Improving cell efficiency is a perpetual pursuit in the photovoltaic industry. Tunnel oxide passivated contact (TOPCon) solar cells have attracted widespread attention in the industry due to their excellent passivation performance and low manufacturing cost. The tunnel oxide passivated contact solar cell (TOPCon) is a new type of passivated contact solar cell first proposed by the Fraunhofer Institute for Solar Energy in Germany at the 28th European PVSEC Photovoltaic Conference in 2013. A 1-2 nm thick tunnel oxide layer is first deposited on the back of the cell, followed by a layer of doped polysilicon. Together, these two form a passivated contact structure, providing excellent interface passivation for the back of the silicon wafer.

[0004] In order to improve the current density and electrical performance of TOPCon cells, the light trapping ability of the cells can be greatly improved by texturing on both sides of the silicon substrate. For example, Chinese patent CN115863456A discloses a perovskite / TOPCon stacked solar cell, which includes a perovskite top cell and a TOPCon bottom cell. The TOPCon bottom cell includes a silicon substrate, wherein the silicon substrate has a double-sided inverted pyramid velvet structure, and the double-sided inverted pyramid velvet structure includes a bottom inverted pyramid structure and a top inverted pyramid structure. The angle between the side wall of the bottom inverted pyramid structure and the plane of the silicon substrate is 6° to 25°.

[0005] This application uses double-sided texturing of a silicon substrate to improve battery performance. However, the texturing surface on the side close to the tunneling oxide layer has large fluctuations, resulting in unstable thickness, which is not conducive to the adhesion of the tunneling oxide layer. After the electrode is formed, a good tunneling contact cannot be formed, resulting in low conversion efficiency.

[0006] Summary of the Invention

[0007] The content of this application is used to briefly introduce concepts that will be described in detail in the detailed description section below. The content of this application is not intended to identify key features or essential features of the technical solution for which protection is sought, nor is it intended to limit the scope of the technical solution for which protection is sought.

[0008] Some embodiments of the present application propose a solar cell module and a double-sided textured TOPCon structure cell thereof to solve the technical problems mentioned in the above background technology section.

[0009] As a first aspect of the present application, some embodiments of the present application provide a solar cell assembly, comprising a plurality of TOPCon structure cells connected in series, and further comprising a bracket and a connector, wherein the bracket is disposed on one side of the solar cell assembly, and a connector is disposed on a side of the bracket away from the solar cell assembly, wherein the TOPCon structure cell is a double-sided textured TOPCon structure cell;

[0010] The connecting member includes a fixed portion and a rotating portion, the fixed portion is fixedly connected to the bracket, a rotating groove is provided on the fixed portion, and the rotating portion includes a rotating shaft, the rotating shaft extends into the rotating groove so that the rotating portion is rotatably connected to the fixed portion about a first rotating axis as a rotating axis;

[0011] The TOPCon structure battery cell comprises:

[0012] An emitter, a silicon wafer, a tunneling oxide layer and a doped conductive layer, wherein the emitter, the silicon wafer, the tunneling oxide layer and the doped conductive layer are arranged in sequence, a first passivation layer is provided on the side of the emitter away from the silicon wafer, a second passivation layer is provided on the side of the first passivation layer, the first surface of the silicon wafer close to the emitter has a first velvet structure, and the second surface of the silicon wafer close to the tunneling oxide layer has a second velvet structure, the first velvet structure and the second velvet structure both comprise a number of equidistantly arranged square pyramidal velvet protrusions, and the average size of the square pyramids of the first velvet structure is smaller than the average size of the square pyramids of the second velvet structure.

[0013] Furthermore, the tip of the square pyramid velvet protrusion of the second velvet structure is configured as an arc-shaped structure.

[0014] Furthermore, the bottom between two adjacent square pyramid velvet protrusions of the second velvet structure is formed into an arc-shaped structure.

[0015] Furthermore, the average slope of the square pyramid velvet protrusions of the first velvet structure is greater than the average slope of the square pyramid velvet protrusions of the second velvet structure.

[0016] Furthermore, the surface that simultaneously passes through the axes of two adjacent square pyramidal velvet protrusions of the second velvet structure is defined as the projection surface of the two square pyramidal velvet protrusions of the second velvet structure passed through, and the angle range of the side tangent projections of the two adjacent square pyramidal velvet protrusions of the second velvet structure on the projection surface is greater than or equal to 120°.

[0017] Furthermore, the silicon wafer is N-type single crystal silicon.

[0018] Furthermore, the emitter is a P-type emitter.

[0019] Furthermore, the emitter is an emitter having a Suichuan oxide layer and a P+ polysilicon layer structure.

[0020] Furthermore, the first passivation layer is an aluminum oxide layer.

[0021] Furthermore, the second passivation layer is a silicon nitride layer.

[0022] Furthermore, a third passivation layer is provided on a side of the doped conductive layer away from the tunneling oxide layer.

[0023] Furthermore, the third passivation layer is a silicon nitride layer.

[0024] Furthermore, the tunneling oxide layer is a silicon oxide layer.

[0025] Furthermore, the doped conductive layer is a polysilicon layer.

[0026] Furthermore, the doped conductive layer is a stacked structure of multiple polysilicon layers.

[0027] Furthermore, it also includes a front electrode and a back electrode, and the front electrode and the back electrode are respectively arranged on both sides of the silicon wafer.

[0028] Furthermore, the back electrode is a silver electrode.

[0029] Furthermore, the front electrode is a silver electrode or a silver-aluminum electrode.

[0030] As a second aspect of the present application, some embodiments of the present application provide the above-mentioned double-sided texturized TOPCon structure cell suitable for the solar cell module.

[0031] As a third aspect of the present application, some embodiments of the present application provide a solar cell assembly comprising the above-mentioned double-sided texturized TOPCon structure cell.

[0032] The beneficial effect of the present application is to provide a solar cell assembly and a double-sided textured TOPCon structure cell thereof, which can maintain the passivation effect while increasing the light trap effect and preventing leakage on the back of the cell.

[0033] The specific beneficial effects are as follows:

[0034] 1. The velvet structure on the back of the battery is relatively smooth, which ensures the uniformity of the thickness of the tunnel oxide layer, effectively prevents local leakage of the battery itself, and also ensures the passivation effect, preventing unnecessary dopants from the polysilicon layer from being doped into the silicon wafer.

[0035] 2. The velvet structure on the back of the battery is relatively smooth to prevent the tunneling oxide layer from forming gaps on the contact surface with the silicon wafer during coating, thereby affecting the battery performance.

[0036] 3. The velvet structure on the back of the battery is relatively smooth, which reduces the thickness of the doped conductive layer and effectively increases the current. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings constituting a part of this application are used to provide a further understanding of this application and make other features, purposes and advantages of this application more apparent. The drawings and descriptions of the exemplary embodiments of this application are used to explain this application and do not constitute an improper limitation on this application.

[0038] In addition, throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the elements and components are not necessarily drawn to scale.

[0039] In the attached figure:

[0040] FIG1 is a schematic diagram of the front structure of a battery assembly according to an embodiment of the present application;

[0041] FIG2 is a schematic diagram of the back structure of a battery assembly according to an embodiment of the present application;

[0042] FIG3 is a schematic diagram of the overall structure of a double-sided textured TOPCon structure battery according to an embodiment of the present application;

[0043] FIG4 is a schematic structural diagram of a second velvet structure according to an embodiment of the present application;

[0044] FIG5 is a schematic diagram of incident light at a first textured structure according to an embodiment of the present application.

[0045] The meanings of the specific reference numerals in the figure are: 10, TOPCon structure battery cell; 100, emitter; 200, silicon wafer; 210, first velvet structure; 220, second velvet structure; 230, protrusion; 300, tunneling oxide layer; 400, doped conductive layer; 500, first passivation layer; 600, second passivation layer; 700, third passivation layer; 800, front electrode; 900, back electrode; 20, bracket; 30, connector; 31, fixing part; 31a, rotation groove; 32, rotating part; 32a, rotation axis; L1, first rotation axis. DETAILED DESCRIPTION

[0046] The present disclosure may be more readily understood by reference to the following description in conjunction with the accompanying drawings and examples, all of which constitute a part of this disclosure. It should be understood that the present disclosure is not limited to the specific products, methods, conditions, or parameters described and / or illustrated herein. Further, the terms used herein are for the purpose of describing specific embodiments by way of example only and are not intended to be limiting unless otherwise indicated.

[0047] It should also be understood that, for the sake of clarity, certain features of the present disclosure may be described herein in the context of separate embodiments, but may also be provided in combination with each other in a single embodiment. That is, unless clearly incompatible or specifically not included, each separate embodiment is considered to be combinable with any other embodiment, and the combination is considered to represent another different embodiment. Conversely, for the sake of simplicity, various features of the present disclosure described in the context of a single embodiment may also be provided individually or in any sub-combination. Finally, although a particular embodiment may be described as part of a series of steps or part of a more general structure, each step or sub-structure itself may also be considered to be an independent embodiment.

[0048] Unless otherwise indicated, it should be understood that each individual element in a list and each combination of individual elements in that list will be interpreted as a different embodiment. For example, a list of embodiments expressed as "A, B, or C" should be interpreted to include embodiments "A," "B," "C," "A or B," "A or C," "B or C," or "A, B, or C."

[0049] In this disclosure, the singular forms of the articles "a," "an," and "the" also include the corresponding plural reference, and a reference to a specific value includes at least that specific value unless the context clearly dictates otherwise. Thus, for example, a reference to "a substance" is a reference to at least one of that substance and equivalents thereof.

[0050] Terms including ordinal numbers such as "first" and "second" may be used to explain various components or fluids, but these components and fluids are not limited by these terms. Therefore, without departing from the teachings of the present disclosure, these terms are only used to distinguish the component / fluid from another component / fluid.

[0051] When items are described by using conjunction terms such as “… and / or…”, the description should be understood to include any one of the associated listed items and all combinations of one or more thereof; for example, A and / or B should be interpreted as including an embodiment that includes “A” but not “B”, an embodiment that includes “B” but not “A”, and an embodiment that includes both “A” and “B”.

[0052] In general, the use of the term "about" indicates an approximate value that can vary depending on the desired properties obtained by the disclosed subject matter and will be interpreted in a context-dependent manner based on function. Therefore, one of ordinary skill in the art will be able to interpret a certain degree of difference on a case-by-case basis. In some cases, the number of important figures used when expressing a particular value can be a representative technique for determining the difference allowed by the term "about". In other cases, a gradient in a range of values ​​can be used to determine the range of differences allowed by the term "about". Further, all ranges in this disclosure are inclusive and combinable, and reference to a value stated in a range includes every value within that range.

[0053] Throughout the specification of this application document, when a part is described as “including” a certain constituent element, unless otherwise clearly described to the contrary, it does not mean that other constituent elements are excluded, but rather that other constituent elements may be included.

[0054] Throughout the specification of the present invention, when a certain step is described as being "above" or "before" other steps, it not only includes situations where a certain step has a direct time series relationship with other steps, but also includes situations where there is an indirect time series relationship where the time series of the order of two steps is changed, such as a mixing step after each step. The same rights apply.

[0055] Throughout the specification of the present invention, when it is recorded as "according to any embodiment of the ... aspect of the ... object of the present invention...", unless otherwise clearly stated to the contrary, it does not mean that the constituent elements of the scheme described before and after it are excluded, but that other constituent elements may also be included.

[0056] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs; and the terms used herein include any and all combinations of one or more of the associated listed items.

[0057] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0058] As shown in Figures 1 and 2, a solar cell assembly of the present application includes a plurality of TOPCon structure cells 10 connected in series, a bracket 20, and a connector 30. The bracket 20 is provided on one side of the solar cell assembly, and the connector 30 is provided on the side of the bracket 20 away from the solar cell assembly. The connector 30 includes a fixed portion 31 and a rotating portion 32. The fixed portion 31 is fixedly connected to the bracket 20. The fixed portion 31 is provided with a rotating groove 31a. The rotating portion 32 includes a rotating shaft 32a. The rotating shaft 32a extends into the rotating groove 31a so that the rotating portion 32 is rotatably connected to the fixed portion 31 with the first rotating axis L1 as the rotating axis 32a.

[0059] Specifically, a solar cell module consists of a frame, TOPCon structured cells, a cover, packaging materials, electrical connectors, and a junction box. The solar cell module is made up of TOPCon structured cells connected in series and parallel via electrical connectors, then sealed with a cover and packaging materials. A frame is then added around the perimeter, and a junction box is installed to transmit the current generated within the PV module to external circuits.

[0060] Electrical connectors, also known as photovoltaic welding ribbons or welding ribbons, are used to electrically connect to the electrodes of TOPCon structure cells to collect the current converted by the TOPCon structure cells. They are components that realize the electrical performance connection between the TOPCon structure cells inside the solar cell module and are the core electrical connection components in the solar cell module. The quality of the electrical connectors directly affects the efficiency of the solar cell module in collecting electricity. In some embodiments, the electrical connectors include interconnecting ribbons and bus ribbons. The interconnecting ribbons are used to connect the cells in series. An interconnecting ribbon is welded on the back of each cell, so that several cells are welded together in series to form a cell string. The bus ribbon is a carrier for connecting the cell strings. The bus ribbon connects the cell strings in series together, and finally leads to the positive and negative poles and connects to the junction box. In some embodiments, the interconnecting ribbons and the bus ribbons are both tin-coated copper ribbons.

[0061] More specifically, the bracket 20 is arranged on one side of the cover and fixedly connected to the cover. A connector 30 is also provided on one side of the bracket 20. The connector 30 is used to connect the solar cell assembly to the external environment. In order to enable the solar cell assembly to convert solar energy into electrical energy at the most appropriate angle, the connector 30 can adjust the angle and position of the solar cell assembly.

[0062] Specifically, the connecting member 30 includes a fixed portion 31 and a rotating portion 32. The fixed portion 31 is also provided with an arc groove. The fixed portion 31 can rotate with the second axis as the rotating axis to adapt to the relative angle between the rotating portion 32 and the bracket 20. The rotating portion 32 is provided with a connecting groove for connecting an external pillar. Therefore, the rotating portion 32 can adjust its angle with the solar cell assembly according to the actual terrain conditions, making the solar cell assembly easy to install while ensuring that it can convert solar energy into electrical energy at the optimal orientation angle.

[0063] As shown in Figures 3 to 5, in a specific embodiment, the TOPCon structure cell 10 is a double-sided textured TOPCon structure cell, which includes an emitter 100, a silicon wafer 200, a tunneling oxide layer 300 and a doped conductive layer 400. The emitter 100, the silicon wafer 200, the tunneling oxide layer 300 and the doped conductive layer 400 are stacked in sequence. The emitter 100 is provided with a first passivation layer 500 on the side away from the silicon wafer 200. The first passivation layer A second passivation layer 600 is provided on one side of the silicon wafer 200. The first surface of the silicon wafer 200 near the emitter 100 has a first velvet structure 210, and the second surface of the silicon wafer 200 near the tunneling oxide layer 300 has a second velvet structure 220. The first velvet structure 210 and the second velvet structure 220 both include a plurality of equally spaced square pyramidal velvet protrusions 230. The average slope of the square pyramidal velvet protrusions 230 of the first velvet structure 210 is greater than the average slope of the square pyramidal velvet protrusions 230 of the second velvet structure 220. That is, the first velvet structure 210 and the second velvet structure 220 both include a plurality of equally spaced square pyramids, and the average size of the square pyramids of the first velvet structure 210 is smaller than the average size of the square pyramids of the second velvet structure 220.

[0064] Specifically, the TOPCon structure cell is stacked from top to bottom with an emitter 100, a silicon wafer 200, a tunneling oxide layer 300, and a doped conductive layer 400. The first passivation layer 500 is an aluminum oxide layer, the second passivation layer 600 is a silicon nitride layer, and the doped conductive layer 400 is provided with a third passivation layer 700 on the side away from the tunneling oxide layer 300. The third passivation layer 700 is a silicon nitride layer, and the doped conductive layer 400 is a polycrystalline silicon layer. The emitter 100 is provided on the first side of the silicon wafer 200. In this application, the terms "top" and "bottom", "top surface" and "bottom surface" or "bottom" and "top" or "front" and "back" refer to the direction from the light-receiving front to the back of the solar cell, with the side closer to the light-receiving front being called "top" and the side closer to the back being called "bottom". The tunneling oxide layer 300 is arranged on the back side of the silicon wafer 200, providing good surface passivation for the back side of the silicon wafer 200. The tunneling oxide layer 300 can allow majority carriers (electrons) to tunnel into the doped conductive layer 400 while blocking the recombination of minority carriers (holes). Then, the majority carriers are laterally transmitted in the doped conductive layer 400 and collected by the metal, thereby greatly reducing the metal contact recombination current and improving the open circuit voltage and short circuit current of the battery. A layer of metal is deposited thereon as an electrode to realize a passivated contact structure without the need for openings.

[0065] The square pyramidal velvet protrusions refer to a first velvet structure on the front of the silicon wafer that is a "pointed" protrusion, a second velvet protrusion on the bottom of the silicon wafer that has an arc-shaped top surface, and an arc-shaped structure between the two second velvet structures. The protrusions on the front of the silicon wafer are more "dense" than those on the back. When sunlight hits the velvet protrusions on the front of the silicon wafer, due to their greater density, more sunlight is captured and enters the interior of the silicon wafer. Once inside the silicon wafer, the sunlight moves to the back of the silicon wafer. The back of the silicon wafer has a relatively "flat" velvet protrusion structure, which can effectively reflect sunlight. Therefore, the sunlight undergoes multiple reflections inside the silicon wafer, increasing the silicon wafer's absorption of sunlight and improving its photoelectric conversion capacity.

[0066] More specifically, a first passivation layer 500 is provided on the side of the emitter 100 away from the silicon wafer 200, and a second passivation layer 600 is provided on the side of the doped conductive layer 400 away from the tunneling oxide layer 300. The passivation layer can effectively improve the cell efficiency. The key factor that restricts further improvement of the efficiency of traditional crystalline silicon (c-Si) solar cells is the loss caused by carrier recombination at the interface between the metal electrode and the silicon wafer 200, resulting in a high Jo load current.

[0067] More specifically, the first surface of the silicon wafer 200, near the front, has a first textured structure 210, and the second surface, near the bottom, has a second textured structure 220. Silicon wafer 200 is cleaned with a hydrofluoric acid solution to remove the natural oxide layer on the surface. Subsequently, silicon wafer 200 is placed in an alkaline solution for a textured treatment, forming a number of square pyramidal textured protrusions 230 on the surface of silicon wafer 200, known as a pyramid texture. This pyramid texture reduces the reflectivity of incident solar light on the surface of silicon wafer 200, increases its absorption of sunlight, and, to a certain extent, improves the photoelectric conversion efficiency of the TOPCon cell.

[0068] Specifically, the concentration of the alkali solution and treatment conditions vary at different stages of the double-sided texturing process. During the main "thinning" stage, a 12% high-concentration KOH solution is used to treat the silicon wafer at 80°C for 12 minutes, resulting in a 130μm N-type silicon wafer 200. The KOH concentration is then reduced to 4%, the treatment temperature is lowered to 70°C, and a small amount of additives is added to the wafer for 100 seconds to complete the double-sided texturing of the silicon wafer 200. The reflectivity of both surfaces is approximately 12%.

[0069] In another feasible embodiment, an inverted pyramid textured structure can be formed on the bottom and top surfaces of the silicon substrate using a copper metal catalytic etching method. The copper metal catalytic etching method includes using a plating solution having a copper nitrate concentration of approximately 40 mol / L, a HF concentration of approximately 5 mol / L, and a hydrogen peroxide concentration of approximately 0.8 mol / L at approximately 30°C for approximately 5 minutes.

[0070] Since the pyramid velvet surface has a certain angle with the incident angle of sunlight, it allows sunlight to re-enter the battery after reflection, which can increase the amount of sunlight entering the battery. According to the principle of light trapping, when light is incident on a slope at a certain angle, the light will be reflected to a slope at another angle, forming secondary or multiple absorption, thereby increasing the light absorption rate, and ultimately increasing the photocurrent density, effectively improving the photoelectric conversion efficiency of the battery.

[0071] More specifically, the slope of the square pyramid velvet protrusions 230 of the first velvet structure 210 is greater than the slope of the square pyramid velvet protrusions 230 of the second velvet structure 220. That is, the square pyramid velvet protrusions 230 of the first velvet structure 210 are arranged more densely on the silicon wafer 200 than the square pyramid velvet protrusions 230 of the second velvet structure 220. In other words, the number of the square pyramidal velvet protrusions 230 of the first velvet structure 210 on the front side of the silicon wafer 200 is greater than the number of the square pyramidal velvet protrusions 230 of the second velvet structure 220. Therefore, the light incident from the front side of the battery passes through the silicon wafer 200 itself and is more easily reflected by the square pyramidal velvet protrusions 230 of the second velvet structure 220 on the back side, which is more "flatter" than the square pyramidal velvet protrusions 230 of the first velvet structure 210. Therefore, the movement path of light in the silicon wafer 200 can be increased, thereby effectively improving the photoelectric conversion efficiency of the battery.

[0072] In a specific embodiment, the tips of the square pyramid suede protrusions 230 of the second suede structure 220 are configured as an arc structure, and the bottoms between two adjacent square pyramid suede protrusions 230 of the second suede structure 220 are configured as an arc structure.

[0073] Specifically, the velvet structure on the bottom surface of the silicon wafer 200 is smoother than the velvet structure on the top surface. The tunneling oxide layer 300 is arranged on the bottom surface of the silicon wafer 200. The tunneling oxide layer 300 itself is relatively thin (0.9 nanometers to 3 nanometers). Therefore, the relatively smooth silicon wafer 200 can make the tunneling oxide layer 300 better fit with the silicon wafer 200, effectively preventing the possible gap between the contact surface of the tunneling oxide layer 300 and the silicon wafer 200 during coating, thereby affecting the battery performance of the TOPCon battery. At the same time, it can also reduce the surface area of ​​the silicon wafer and reduce the area that needs passivation.

[0074] More specifically, the relatively flat velvet surface on the bottom surface ensures better thickness uniformity of the tunnel oxide layer 300, effectively preventing local leakage in TOPCon structured cells and preventing unwanted dopants from the polysilicon layer from being introduced into the silicon wafer 200. Because the thickness uniformity of the tunnel oxide layer 300 is ensured, the thickness of the tunnel oxide layer 300 can be reduced to a certain extent, thereby increasing the current of the TOPCon structured cell. This also ensures that the electrodes disposed on the back side of the silicon wafer 200 do not directly contact or come too close to the back side of the silicon wafer 200. The uniformity error range referred to here is between 0.1 and 0.3 nanometers.

[0075] In a specific embodiment, the surface that simultaneously passes through the axes of the two adjacent square pyramid velvet protrusions 230 of the second velvet structures 220 is defined as the projection surface of the two square pyramid velvet protrusions 230 of the second velvet structures 220 passed through, and the angle range of the side tangent projection of the two adjacent square pyramid velvet protrusions 230 of the second velvet structures 220 on the projection surface is greater than or equal to 120°.

[0076] In other words, the back side of the silicon wafer 200 has a plurality of equally spaced square pyramidal velvet protrusions 230 of the second velvet structure 220. An arc-shaped structure is present between any two adjacent square pyramidal velvet protrusions 230 of the second velvet structure 220 on the back side of the silicon wafer 200, and the angle between the two surfaces tangent to the arc of the arc structure on the projection plane is greater than or equal to 120 degrees. This ensures that the square pyramidal velvet protrusions 230 of the second velvet structure 220 on the bottom side of the silicon wafer 200 are smoother than the square pyramidal velvet protrusions 230 of the first velvet structure 210 on the top side of the silicon wafer 200, resulting in a more uniform thickness of the tunnel oxide layer 300.

[0077] In a specific embodiment, the silicon wafer 200 is N-type single crystal silicon. The N-type silicon substrate does not form boron-oxygen complexes when exposed to light, which reduces light-induced degradation and thermally assisted light-induced degradation to a certain extent. The emitter 100 is a P-type emitter, which uses a P+ layer formed by diffusing boron elements into the silicon wafer 200 to form a PN junction, and is deposited using PECVD low temperature. The P-type polysilicon layer includes an intrinsic layer that is deposited by the reaction of SiH4, H2 and B2H6 to play a protective role, and a poly Si film is doped in the intrinsic layer. The emitter is an emitter having a Suichuan oxide layer and a P+ polysilicon layer structure.

[0078] In one specific embodiment, the tunneling oxide layer 300 is a silicon oxide layer. Utilizing the quantum tunneling effect, it allows electrons to pass smoothly while preventing holes from recombinating. The fully passivated surface eliminates the silicon / metal contact interface, facilitating an increase in the open-circuit voltage (Voc). Carriers are collected over the entire surface, reducing lifetime sensitivity and improving the fill factor (FF). Blocking minority carriers while allowing majority carriers to pass freely and unimpeded reduces recombination. This suppresses carrier recombination on the surface of the silicon wafer 200, improving the minority carrier lifetime and the open-circuit voltage of the battery. The selective carrier collection and passivation contact structure can be applied to the entire surface of the battery, eliminating the need for openings to form localized passivation contacts. This not only simplifies the manufacturing process but also allows carriers to be transported in a single dimension, eliminating the need for additional lateral transport, thereby achieving a higher fill factor.

[0079] Specifically, an ultrathin silicon oxide tunneling layer is formed on the back surface using low-pressure chemical vapor deposition (LPCVD). Polycrystalline silicon is deposited on the ultrathin silicon oxide tunneling layer and phosphorus-doped using a pulsed laser. Subsequently, a silicon nitride antireflection layer (third passivation layer 700) is deposited on the back surface of the silicon wafer 200 using plasma-enhanced chemical vapor deposition (PECVD). The doped conductive layer is a stack of multiple polycrystalline silicon layers.

[0080] In a specific embodiment, the double-sided textured TOPCon structure battery further includes a front electrode 800 and a back electrode 900, which are respectively disposed on both sides of the silicon wafer 200. The back electrode 900 is a silver electrode. The front electrode 800 is a silver electrode or an aluminum electrode.

[0081] Specifically, metal electrodes are prepared by screen printing or sintering on the front and back sides of the silicon wafer 200. The above-mentioned electrode material configuration can obtain better conductivity and connection tension between the silicon wafer 200, thereby improving the structural stability of the battery while improving the conductive effect.

[0082] In a specific embodiment, the above structure can improve the passivation effect of the second velvet structure 220, and can also be used in a stacked solar cell structure. The relatively flat surface of the velvet can better form structural contact with other cells such as perovskite cells, thereby ensuring the process stability of the perovskite cell and improving the cell power generation efficiency.

[0083] The above description is only an illustration of some preferred embodiments of the present disclosure and the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the above-mentioned inventive concept. For example, the above-mentioned features are replaced with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims

1. A double-sided TOPCon structure battery, characterized in that: The invention comprises: an emitter (100), a silicon wafer (200), a tunneling oxide layer (300) and a doped conductive layer (400), wherein the emitter (100), the silicon wafer (200), the tunneling oxide layer (300) and the doped conductive layer (400) are sequentially stacked and arranged, a first passivation layer (500) is provided on a side of the emitter (100) away from the silicon wafer (200), a second passivation layer (600) is provided on a side of the first passivation layer (500), and the silicon wafer (200) is disposed on a first passivation layer (600). ) has a first velvet structure (210) on the first surface close to the emitter (100), and has a second velvet structure (220) on the second surface close to the tunneling oxide layer (300), the first velvet structure (210) and the second velvet structure (220) both comprising a plurality of equidistantly arranged square pyramidal velvet protrusions (230), the average size of the square pyramids of the first velvet structure (210) being smaller than the average size of the square pyramids of the second velvet structure (220).

2. The double-sided textured TOPCon structure battery according to claim 1, characterized in that: The tip of the square pyramid velvet protrusion (230) of the second velvet structure (220) is configured as an arc-shaped structure.

3. The double-sided textured TOPCon structure battery according to claim 2, characterized in that: The bottom between the square pyramid velvet protrusions (230) of two adjacent second velvet structures (220) is formed into an arc-shaped structure.

4. The double-sided textured TOPCon structure battery according to claim 3, characterized in that: The average slope of the square pyramid velvet protrusions (230) of the first velvet structure (210) is greater than the average slope of the square pyramid velvet protrusions (230) of the second velvet structure (220).

5. The double-sided textured TOPCon structure battery according to any one of claims 1 to 4, characterized in that: The plane that simultaneously passes through the axes of the two adjacent square pyramid velvet protrusions (230) of the second velvet structures (220) is defined as the projection plane of the two square pyramid velvet protrusions (230) of the second velvet structures (220) passed through, and the angle range of the side tangent projection of the square pyramid velvet protrusions (230) of the two adjacent second velvet structures (220) on the projection plane is greater than or equal to 120°.

6. The double-sided textured TOPCon structure battery according to claim 5, characterized in that: The silicon wafer (200) is N-type single crystal silicon; and / or, the emitter (100) is a P-type emitter; The emitter (100) is an emitter having a tunneling oxide layer and a P+ polysilicon layer structure.

7. The double-sided textured TOPCon structure battery according to claim 6, characterized in that: The first passivation layer (500) is an aluminum oxide layer; and\or, the second passivation layer (600) is a silicon nitride layer.

8. The double-sided textured TOPCon structure battery according to claim 7, characterized in that: A third passivation layer (700) is provided on a side of the doped conductive layer (400) away from the tunneling oxide layer (300).

9. The double-sided textured TOPCon structure battery according to claim 8, characterized in that: The third passivation layer (700) is a silicon nitride layer; and / or, the tunneling oxide layer (300) is a silicon oxide layer.

10. The double-sided textured TOPCon structure battery according to claim 9, characterized in that: The doped conductive layer (400) is a polysilicon layer.

11. The double-sided textured TOPCon structure battery according to claim 10, characterized in that: The doped conductive layer (400) is a stacked structure of multiple polysilicon layers.

12. The double-sided textured TOPCon structure battery according to claim 5, characterized in that: It also includes a front electrode (800) and a back electrode (900), wherein the front electrode (800) and the back electrode (900) are respectively arranged on both sides of the silicon wafer (200).

13. The double-sided textured TOPCon structure battery according to claim 12, characterized in that: The back electrode (900) is a silver electrode; and\or, the front electrode (800) is a silver electrode or an aluminum electrode.

14. A solar cell module, characterized in that: It comprises a plurality of double-sided textured TOPCon structure cells as described in any one of claims 1 to 13 connected in series, and also comprises a bracket (20) and a connector (30), wherein the bracket (20) is arranged on one side of the solar cell assembly, and a connector (30) is provided on the side of the bracket (20) away from the solar cell assembly, wherein the TOPCon structure cell sheet (10) is a double-sided textured TOPCon structure cell; the connector (30) comprises a fixed part (31) and a rotating part (32), wherein the fixed part (31) is fixedly connected to the bracket (20), a rotating groove (31a) is provided on the fixed part (31), and the rotating part (32) comprises a rotating shaft (32a), and the rotating shaft (32a) extends into the rotating groove (31a) so that the rotating part (32) is rotatably connected to the fixed part (31) with a first rotating axis (L1) as the rotating axis.

15. A solar cell module, characterized in that: It comprises a double-sided textured TOPCon structure battery as described in claim 1.

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