Pixel array and readout method therefor, and image sensor

Abstract

The present disclosure relates to the technical field of infrared light. Provided are a pixel array and a readout method therefor, and an image sensor, which are used for improving the readout speed of pixel information. The pixel array comprises: a plurality of pixel columns, wherein for each of the plurality of pixel columns, the pixel column comprises Y pixels; the pixel column comprises a plurality of pixel groups, one of the plurality of pixel groups comprises adjacent y pixels or one pixel among the Y pixels, and 2≤y<Y / 2; an odd-numbered pixel group among the plurality of pixel groups is electrically connected to a first readout bus, and an even-numbered pixel group among the plurality of pixel groups is electrically connected to a second readout bus; the pixel column comprises a plurality of synchronization pixel groups, one of the plurality of synchronization pixel groups comprises an odd-numbered pixel group and an even-numbered pixel group which are adjacent among the plurality of pixel groups, information of a plurality of pixels in one of the plurality of synchronization pixel groups is read out by the first readout bus and the second readout bus, and the plurality of synchronization pixel groups are sequentially read out; and the information of the pixels being read out refers to the pixels being connected to the corresponding first readout bus or second readout bus.

Description

Pixel array, readout method thereof, and image sensor CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to Chinese patent applications No. 202311736461.0 filed on December 15, 2023 and No. 202311753745.0 filed on December 19, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of infrared light technology, and in particular to a pixel array and a readout method thereof, and an image sensor. Background Art

[0003] With the rapid development of communication technology and people's pursuit of color and display practicality of display devices, display devices are developing towards multi-function and digitalization. Specifically, modern display devices are developing towards high density, high resolution, energy saving, high brightness, color, and large screen.

[0004] High resolution is a key performance indicator for image sensors. The higher the resolution, the larger the pixel array required. A larger pixel array requires longer pixel information processing time and a slower frame rate. For image sensors that require fast response times, high resolution and high frame rate are two conflicting indicators. Summary of the Invention

[0005] The embodiments of the present application provide a pixel array, a readout method, and an image sensor. The pixel array is used to increase the speed of pixel information readout and reduce the difficulty of circuit design.

[0006] In a first aspect, the present application provides a pixel array, comprising: a plurality of pixel columns; wherein, for each of the plurality of pixel columns, the pixel column comprises Y pixels; wherein the pixel column comprises a plurality of pixel groups, wherein one pixel group in the plurality of pixel groups comprises y adjacent pixels or one pixel among the Y pixels, 2≤y<Y / 2; wherein the odd-numbered pixel groups in the plurality of pixel groups are electrically connected to a first readout bus, and the even-numbered pixel groups in the plurality of pixel groups are electrically connected to a second readout bus. ; wherein, the column of pixels includes a plurality of synchronous pixel groups, one synchronous pixel group among the plurality of synchronous pixel groups includes adjacent odd-numbered pixel groups and even-numbered pixel groups among the plurality of synchronous pixel groups, information of a plurality of pixels in one synchronous pixel group among the plurality of synchronous pixel groups is read out by the first readout bus and the second readout bus, and the plurality of synchronous pixel groups are read out in sequence; wherein, the information of the pixel is read out when the pixel is connected to the corresponding first readout bus or the second readout bus.

[0007] Some embodiments of the present application provide a pixel array capable of reading information from two pixels, accelerating pixel readout and reducing circuit design complexity. Specifically, this increases frame rates at high resolutions. Furthermore, for integrating pixel processing circuits, this can further increase the upper limit of the integration time, thereby improving performance.

[0008] In some embodiments, the plurality of pixel groups are X1 pixel groups, where Y / y=X1, and X1 is an integer; or the plurality of pixel groups are (X2+1) pixel groups, where Y / y=X2+X3, and the remaining X3 pixels are the last pixel group in the (X2+1) pixel groups.

[0009] In some embodiments, information of multiple pixels in a synchronous pixel group among the multiple synchronous pixel groups is read out, including: information of a pixel in the odd-numbered pixel group and information of a pixel in the even-numbered pixel group are read out simultaneously.

[0010] In some embodiments, one of the Y pixels includes a pixel resistor, a first selection switch, a second selection switch and a short-circuit switch; wherein the first selection switch is configured to connect the pixel resistor to its corresponding first readout bus or the second readout bus, and the second selection switch is configured to connect the pixel resistor to the reset end; wherein the short-circuit switch is connected in parallel with the pixel resistor and is configured to be able to short-circuit the pixel resistor; the pixel resistors of the Y pixels are connected in series in sequence; when the first selection switch and the second selection switch corresponding to a pixel are closed and the short-circuit switch is disconnected, the information of the pixel is read out.

[0011] In some embodiments, the first end of the first selected sub-switch is electrically connected to the first readout bus or the second readout bus, the second end of the first selected sub-switch is electrically connected to the first end of the pixel resistor, the second end of the pixel resistor is electrically connected to the first end of the second selected sub-switch, and the second end of the second selected sub-switch is electrically connected to the reset end.

[0012] In some embodiments, during the phase in which information of two pixels in a synchronous pixel group is read out, the short-circuit switches of the two pixels read out last time remain open.

[0013] In some embodiments, every two adjacent pixels among the Y pixels form a pixel group; the odd-numbered pixel group is electrically connected to the first readout bus, and the even-numbered pixel group is electrically connected to the second readout bus; starting from the first pixel group, every adjacent odd-numbered pixel group and even-numbered pixel group is a synchronous pixel group, and the information of each pixel in a synchronous pixel group is read out; and multiple synchronous pixel groups are read out in sequence.

[0014] In some embodiments, each of the Y pixels is a pixel group; the odd-numbered pixel group is electrically connected to the first readout bus, and the even-numbered pixel group is electrically connected to the second readout bus; starting from the first pixel group, each adjacent odd-numbered pixel group and even-numbered pixel group is a synchronous pixel group, and the information of each pixel in a synchronous pixel group is read out; and multiple synchronous pixel groups are read out in sequence.

[0015] In a second aspect, some embodiments of the present application provide a method for reading out a pixel array, wherein the pixel array includes multiple columns of pixel columns, wherein, for each column of the multiple columns of pixel columns, the column of pixel columns includes Y pixels; wherein the column of pixel columns includes multiple pixel groups, and one pixel group in the multiple pixel groups includes adjacent y pixels or one pixel among the Y pixels, 2≤y<Y / 2; wherein the odd-numbered pixel groups in the multiple pixel groups are electrically connected to a first readout bus, and the even-numbered pixel groups in the multiple pixel groups are electrically connected to a second readout bus; wherein the column of pixel columns includes multiple synchronous pixel groups, and one synchronous pixel group in the multiple synchronous pixel groups includes adjacent odd-numbered pixel groups and even-numbered pixel groups in the multiple pixel groups; the readout stage of the pixel array includes a first readout stage to an Nth readout stage arranged in sequence, wherein N=M / 2, and M is the number of rows of the pixel array.

[0016] The readout method includes: in each readout stage from the first readout stage to the Nth readout stage, information of two pixels in a synchronous pixel group is read out by the first readout bus and the second readout bus respectively; reading out the multiple synchronous pixel groups in sequence, wherein information of each pixel in each synchronous pixel group in the multiple synchronous pixel groups is read out; wherein the information of the pixel is read out, and the pixel is connected to the corresponding first readout bus or the second readout bus.

[0017] The beneficial effects that can be achieved by the pixel array readout method provided in some embodiments of the present application are the same as the beneficial effects that can be achieved by a pixel array provided by the above technical solution, and will not be repeated here.

[0018] In some embodiments, the information of two pixels in a synchronous pixel group is read out by the first readout bus and the second readout bus respectively, including: the information of a pixel in the odd-numbered pixel group in the synchronous pixel group is read out by one of the first readout bus and the second readout bus; at the same time, the information of a pixel in the even-numbered pixel group in the synchronous pixel group is read out by the other of the first readout bus and the second readout bus.

[0019] In some embodiments, one of the Y picture elements includes a picture element resistor, a first selected sub-switch, a second selected sub-switch, and a short-circuit switch.

[0020] In the first readout stage, the first selected sub-switches and the second selected sub-switches of the two pixels in the first synchronous pixel group are closed, and the short-circuit switches of the two pixels are disconnected. The first selected sub-switches and the second selected sub-switches of the other pixels except the two pixels read out in the first readout stage are disconnected, and the short-circuit switches of the other pixels are closed.

[0021] In each readout stage from the second readout stage to the Nth readout stage, the first selected sub-switches and the second selected sub-switches of the two pixels in the synchronous pixel group corresponding to the readout stage are closed; the first selected sub-switches and the second selected sub-switches of the other pixels except the two pixels read out in the readout stage are all disconnected, and except for the short-circuit switches of the two pixels read out in the readout stage and the two pixels read out in the previous readout stage, the short-circuit switches of the other pixels are closed.

[0022] In some embodiments, in each of the readout stages from the first readout stage to the Nth readout stage, the first selected sub-switch is closed before the second selected sub-switch, and the closing time of the first selected sub-switch is equal to the closing time of the second selected sub-switch.

[0023] In some embodiments, the readout method includes: synchronously reading out multiple synchronized pixel groups in the same row among the multiple pixel columns.

[0024] In a third aspect, some embodiments of the present application provide an image sensor comprising a pixel array, a first readout circuit, a second readout circuit, and an analog-to-digital conversion circuit.

[0025] The pixel array is configured to collect infrared signals; the first readout circuit includes multiple first readout buses, and the second readout circuit includes multiple second readout buses; the first readout circuit and the second readout circuit are configured to convert the infrared signals into detection signals and output the detection signals as analog signals; the analog-to-digital conversion circuit is electrically connected to the first readout circuit and the second readout circuit.

[0026] In some embodiments, the first readout circuit includes a first pixel bias resistor, the second readout circuit includes a second pixel bias resistor, and the first pixel bias resistor and the second pixel bias resistor are located on the same side of the pixel array.

[0027] In some embodiments, the first readout circuit includes multiple first readout sub-circuits, and the second readout circuit includes multiple second readout sub-circuits; each of the first readout sub-circuits is electrically connected to a first readout bus connected to a column of pixel columns, and each of the second readout sub-circuits is electrically connected to a second readout bus connected to a column of pixel columns.

[0028] The beneficial effects that can be achieved by the image sensors provided by some embodiments of the present application are the same as the beneficial effects that can be achieved by a pixel array provided by the above technical solution, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a circuit diagram of a pixel array in a related technology provided by some embodiments of the present application.

[0030] FIG2 is a schematic structural diagram of a pixel array in a related technology provided in some embodiments of the present application.

[0031] FIG3 is a schematic structural diagram of a pixel array provided in some embodiments of the present application.

[0032] FIG4 is a circuit diagram of a pixel array provided in some embodiments of the present application.

[0033] FIG5 is a timing diagram of reading a pixel array provided in some embodiments of the present application.

[0034] FIG6 is a circuit diagram of another pixel array provided in some embodiments of the present application.

[0035] FIG7 is a circuit diagram of another pixel array provided in some embodiments of the present application.

[0036] FIG8 is a schematic structural diagram of an image sensor provided in some embodiments of the present application.

[0037] FIG9 is a circuit diagram of a readout circuit provided in some embodiments of the present application. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0039] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0040] With the rapid development of communication technology and people's pursuit of color and display practicality, display devices are moving towards multifunctionality and digitalization. Specifically, modern display devices are developing towards high density, high resolution, energy efficiency, high brightness, color, and large screen sizes. High resolution has become a key performance indicator for image sensors. The higher the resolution, the larger the pixel array required. The larger the pixel array, the longer the pixel information processing time and the slower the frame rate. For image sensors that require fast response, high resolution and high frame rate are two conflicting requirements.

[0041] 1 , the pixel array 50 includes a pixel resistor Rs, a first selected sub-switch ROW_SEL, a second selected sub-switch ROW_SEL_D, and a short-circuit switch ROW_SEL_SHORT. <1> When connected to the readout circuit, the first first selector switch ROW_SEL <1> and the first and second selected sub-switch ROW_SEL_D <1> The switch is closed, the first short-circuit switch ROW_SEL_SHORT <1> disconnected, and the first pixel resistor RS <1> One end of the first selected sub-switch ROW_SEL <1> The other end is connected to the readout circuit TS, and the other end is connected to the first and second selection sub-switch ROW_SEL_D <1> The first pixel resistor Rs <1> is read out; the second pixel resistor is connected to the readout circuit when the second first selector switch ROW_SEL <2> and the second second selector switch ROW_SEL_D <2> The switch is closed, the second short circuit switch ROW_SEL_SHORT <2> The switch is open, and the second pixel resistor RS <2> One end selects the switch ROW_SEL through the second first selection sub-switch <2> The other end is connected to the readout circuit TS, and the second selector switch ROW_SEL_D <2> The second pixel resistor Rs <2> is read out; and so on.

[0042] The sensor's photosensitive area consists of many pixels arranged in a one- or two-dimensional matrix, where a pixel is a single photosensitive unit. The image sensor's resolution is determined by the number of pixels in the matrix's horizontal and vertical dimensions. Specifically, the number of pixels in the image sensor equals the resolution. A photosensitive unit can be represented by the pixel resistor Rs in Figure 1. The readout circuit Ts reads the pixel resistors row by row and column by column, with the readout speed being the frame rate. A larger pixel array contains more information in the image, but the readout speed is slower. A smaller pixel array contains less information in the image, but the readout speed is faster. In other words, a higher readout speed results in lower resolution, while a higher resolution results in a slower readout speed.

[0043] At the same time, refer to Figure 2, which shows the connection method between the pixel array and the readout circuit in the related art. The readout circuit in the related art adopts an upper and lower placement scheme. The readout circuit of this scheme, except for the bias resistor, and the bias resistor in the readout circuit are distributed in the upper and lower areas of the entire pixel array. Due to the manufacturing process, the farther the distance between the pixel array and the bias resistor, the greater the deviation between the readout pixel information and the actual pixel information. Therefore, in the final image, the pixel points read out by the upper and lower readout circuits will show obvious upper and lower stratification, which is not conducive to the extraction of fixed pattern noise (FPN).

[0044] Based on this, some embodiments of the present application provide a pixel array 100. As shown in FIG3 , the pixel array 100 includes a plurality of pixel columns 11. Each pixel column 11 includes Y pixels, and each pixel column 11 is electrically connected to a first readout bus TS_UP and a second readout bus TS_DN.

[0045] Each y adjacent pixels in the Y pixels form a pixel group 20, or each pixel in the plurality of pixels forms a pixel group 20. The odd-numbered pixel groups are electrically connected to the first readout bus TS_UP, and the even-numbered pixel groups are electrically connected to the second readout bus TS_DN. Here, 2≤y<Y / 2.

[0046] For example, a pixel is a pixel group. The first pixel group is electrically connected to the first readout bus TS_UP, that is, the first pixel is electrically connected to the first readout bus TS_UP; the second pixel group is electrically connected to the second readout bus TS_DN, that is, the second pixel is electrically connected to the second readout bus TS_DN; the third pixel group is electrically connected to the first readout bus TS_UP, that is, the third pixel is also electrically connected to the first readout bus TS_UP; the fourth pixel group is electrically connected to the second readout bus TS_DN, that is, the fourth pixel is also electrically connected to the second readout bus TS_DN; and so on.

[0047] If two adjacent pixels in a plurality of pixels form a pixel group, that is, two pixels form a pixel group, the first pixel group is electrically connected to the first readout bus TS_UP, that is, the first pixel and the second pixel are electrically connected to the first readout bus TS_UP; the second pixel group is electrically connected to the second readout bus TS_DN, that is, the third pixel and the fourth pixel are electrically connected to the second readout bus TS_DN; and so on.

[0048] Starting from the first pixel group, each adjacent odd-numbered pixel group and even-numbered pixel group is a synchronous pixel group 30, and information of multiple pixels in a synchronous pixel group is read out by the first readout bus and the second readout bus; and multiple synchronous pixel groups are read out in sequence.

[0049] Among them, the information of multiple pixels in a synchronous pixel group is read out by the first readout bus and the second readout bus, which means that the information of some pixels in the multiple pixels is read out by the first readout bus, and the information of another part of the pixels is read out by the second readout bus.

[0050] Exemplarily, the information of some pixels in a synchronous pixel group and the information of another part of pixels can be synchronously read out by the first readout bus and the second readout bus respectively. "Synchronous readout" includes that the information of some pixels in a synchronous pixel group and the information of another part of pixels can be read out simultaneously by the first readout bus and the second readout bus respectively, and it can also include that some pixels start to be read out by the first readout bus first, and after the first readout bus has started to read out, the other part of pixels start to be read out by the second readout bus, that is, the first readout bus and the second readout bus start to read out successively, and there is a small time difference between the start time of reading.

[0051] In one embodiment, reading out information of multiple pixels in a synchronous pixel group 30 includes: simultaneously reading out information of a pixel in an odd-numbered pixel group and information of a pixel in an even-numbered pixel group.

[0052] For example, one pixel constitutes a pixel group 20. The first pixel group and the second pixel group constitute the first synchronous pixel group, and the information of the first pixel and the second pixel of the first synchronous pixel group are read out. The third pixel group and the fourth pixel group constitute the second synchronous pixel group. After the first synchronous pixel group is read out, the information of the third pixel and the fourth pixel of the second synchronous pixel group are read out, and so on, until each synchronous pixel group is read out in sequence. In the entire pixel array, it is equivalent to reading out the information of each pixel in the pixel array 100 two rows at a time from top to bottom. For example, the information of the first row of pixels and the second row of pixels is read out, followed by the information of the third row of pixels and the fourth row of pixels, followed by the information of the fifth row of pixels and the sixth row of pixels, and so on, until the information of the pixels in the Y-1th row and the Yth row of pixels are read out.

[0053] If every two adjacent pixels in a plurality of pixels constitute a pixel group 20, that is, two pixels constitute a pixel group 20. The first pixel group and the second pixel group constitute a first synchronous pixel group. The information of the first pixel and the third pixel of the first synchronous pixel group are read out. After the information of the first pixel and the third pixel are read out, the information of the second pixel and the fourth pixel are read out. The third pixel group and the fourth pixel group constitute a second synchronous pixel group. After the first synchronous pixel group is read out, the information of the fifth pixel and the seventh pixel of the second synchronous pixel group is read out. After the information of the fifth pixel and the seventh pixel are read out, the information of the sixth pixel and the eighth pixel are read out. And so on. Each synchronous pixel group 30 is read out in sequence. In the entire pixel array, it is equivalent to reading out the information of each pixel in the pixel array 100 from top to bottom. For example, the information of the first row of pixels and the information of the third row of pixels are read out, then the information of the second row of pixels and the information of the fourth row of pixels are read out, then the information of the fifth row of pixels and the information of the seventh row of pixels are read out, then the information of the sixth row of pixels and the information of the eighth row of pixels are read out, and so on, until the information of the Y-3 row of pixels and the information of the Y-1 row of pixels are read out, and the information of the Y-2 row of pixels and the information of the Y row of pixels are read out.

[0054] The information of the pixel is read out, and the pixel is connected to the corresponding first readout bus TS_UP or second readout bus TS_DN.

[0055] It should be noted that the odd-numbered pixel groups are electrically connected to the first readout bus TS_UP, and the even-numbered pixel groups are electrically connected to the second readout bus TS_DN. This electrical connection simply means that the pixel groups are connected to the first readout bus TS_UP or the second readout bus TS_DN, but there is no electrical continuity between the pixel groups and the first readout bus TS_UP or the second readout bus TS_DN. Pixel information can only be transmitted to the first readout bus TS_UP when there is electrical continuity between the pixel and the corresponding first readout bus TS_UP, and pixel information can only be transmitted to the second readout bus TS_DN when there is electrical continuity between the pixel and the corresponding second readout bus TS_DN.

[0056] In some embodiments, if only one pixel group remains, a synchronous pixel group cannot be formed; after the pixel information of the previous synchronous pixel group is read out, the pixel group can be connected to the first readout bus TS_UP and the pixel information is read out.

[0057] For example, if Y=10 and y=2, each pixel column includes 10 pixels. Every two adjacent pixels in the 10 pixels form a pixel group, for a total of five pixel groups. Every adjacent odd-numbered pixel group and even-numbered pixel group form a synchronous pixel group, for a total of two synchronous pixel groups. Ultimately, only one pixel group remains, which can be electrically connected to the first readout bus TS_UP.

[0058] Some embodiments of the present disclosure provide a pixel array in which each pixel column is electrically connected to a first readout bus TS_UP and a second readout bus TS_DN. Information of multiple pixels in a synchronized pixel group is read out using both the first and second readout buses. In other words, information of multiple pixels in a synchronized pixel group is read out using two readout buses (corresponding to two readout circuits). For example, information of two pixels can be read out simultaneously. This speeds up the readout of pixel information and reduces circuit design complexity, thereby increasing the frame rate at high resolution. Furthermore, for an integrating pixel processing circuit, the upper limit of the integration time can be further increased, thereby improving processing performance. In addition, since every y adjacent pixels among the Y pixels form a pixel group 20, 2≤y<Y / 2, the two pixels read out synchronously are confined to a smaller area. Compared with the method of dividing the pixel array into two upper and lower arrays in Figure 2, the solution disclosed in the present invention can speed up the pixel information reading speed while reducing the deviation of pixel information caused by process deviation and layout routing, while improving the performance of the sensor. Moreover, the difference in the readout circuit is reflected between adjacent odd and even rows, which is more conducive to the extraction of fixed pattern noise.

[0059] In one embodiment, each pixel column includes X1 pixel groups, where Y / y=X1, and X1 is an integer; or, each pixel column includes (X2+1) pixel groups, where Y / y=X2 plus X3, and the remaining X3 pixels serve as the last pixel group.

[0060] That is, when Y / y=X1 and X1 is an integer, it means that Y is divisible by y, and when Y / y=X2 with a remainder of X3, it means that Y is not divisible by y. That is, when Y / y=X1 and X1 is an integer, it means that Y is divisible by y, and when Y / y=X2 with a remainder of X3, it means that Y is not divisible by y.

[0061] For example, if Y = 12 and y = 2, then X1 = 6, meaning each pixel column includes 12 pixels. Within the 12 pixels, every two adjacent pixels form a pixel group, for a total of six pixel groups. Odd-numbered pixel groups are electrically connected to the first readout bus, and even-numbered pixel groups are electrically connected to the second readout bus. Starting from the first pixel group, every adjacent odd-numbered pixel group and even-numbered pixel group form a synchronized pixel group. The information of multiple pixels within a synchronized pixel group is read out via the first and second readout buses, and these synchronized pixel groups are read out sequentially. A total of three synchronized pixel groups are read out sequentially.

[0062] If Y = 11 and y = 2, then X2 = 5 and X3 = 1, meaning each column of pixels includes 11 pixels. Within these 11 pixels, every two adjacent pixels form a pixel group, for a total of five pixel groups. The remaining pixel serves as the final pixel group, so the 11 pixels comprise six pixel groups. The odd-numbered pixel groups are electrically connected to the first readout bus, and the even-numbered pixel groups are electrically connected to the second readout bus. Starting from the first pixel group, each adjacent odd-numbered pixel group and even-numbered pixel group form a synchronous pixel group. The information of multiple pixels within a synchronous pixel group is read out by the first and second readout buses, and the multiple synchronous pixel groups are read out sequentially. The two synchronous pixel groups are read out sequentially: the information of multiple pixels in the fifth pixel group is read out by the first readout bus, and the information of one pixel in the sixth pixel group is read out by the second readout bus.

[0063] In one embodiment, reading out information of multiple pixels in a synchronous pixel group 30 includes: simultaneously reading out information of a pixel in an odd-numbered pixel group and information of a pixel in an even-numbered pixel group.

[0064] For example, a pixel constitutes a pixel group 20. The first and second pixel groups constitute the first synchronous pixel group, and the information of the first and second pixels of the first synchronous pixel group are read out simultaneously. The third and fourth pixel groups constitute the second synchronous pixel group, and after the first synchronous pixel group is read out, the information of the third and fourth pixels of the second synchronous pixel group is read out simultaneously. This process is repeated in this way, and each synchronous pixel group is read out in sequence.

[0065] If every two adjacent pixels in a plurality of pixels constitute a pixel group 20, that is, two pixels constitute a pixel group 20. The first pixel group and the second pixel group constitute a first synchronous pixel group. The information of the first pixel and the third pixel of the first synchronous pixel group are read out simultaneously. After the information of the first pixel and the third pixel are read out, the information of the second pixel and the fourth pixel are read out simultaneously. The third pixel group and the fourth pixel group constitute a second synchronous pixel group. After the first synchronous pixel group is read out, the information of the fifth pixel and the seventh pixel of the second synchronous pixel group are read out simultaneously. After the information of the fifth pixel and the seventh pixel are read out, the information of the sixth pixel and the eighth pixel are read out simultaneously. In summary, and so on, each synchronous pixel group 30 is read out in sequence.

[0066] That is to say, the pixel array can read out information of two pixels at the same time, further accelerating the pixel readout speed.

[0067] As shown in FIG4 , pixel column 11 is electrically connected to a reset terminal. Pixel 10 includes a pixel resistor Rs, a first selection switch ROW_SEL, a second selection switch ROW_SEL_D, and a short-circuit switch ROW_SEL_SHORT. The first selection switch ROW_SEL is configured to connect the pixel resistor Rs to its corresponding first readout bus TS_UP or second readout bus TS_DN, and the second selection switch ROW_SEL_D is configured to connect the pixel resistor Rs to the reset terminal VDET.

[0068] The short-circuit switch is connected in parallel with the pixel resistor Rs and is configured to short-circuit the pixel resistor Rs; the pixel resistors Rs of multiple pixels in each pixel column 11 are connected in series in sequence; when the first selection switch ROW_SEL and the second selection switch ROW_SEL_D are turned on and the short-circuit switch ROW_SEL_SHORT is turned off, the pixel information is read out.

[0069] As shown in FIG4 , a first end of the first selected sub-switch is electrically connected to the first readout bus TS_UP or the second readout bus TS_DN, a second end of the first selected sub-switch is electrically connected to the first end of the pixel resistor Rs, a second end of the pixel resistor Rs is electrically connected to the first end of the second selected sub-switch, and a second end of the second selected sub-switch is electrically connected to the reset end VDET.

[0070] In some embodiments, the voltage value of the reset terminal VDET is 0.

[0071] It should be noted that the pixel being read out refers to the pixel resistance Rs being read out. <1> Refers to the first pixel resistance, Rs <2> Refers to the second pixel resistor, and so on.

[0072] 4 and 5, one pixel is a pixel group 20. That is, the first pixel group includes the first pixel resistor Rs <1> , the first selected sub-switch ROW_SEL <1> 、The first and second selection sub-switch ROW_SEL_D <1> and the first short-circuit switch ROW_SEL_SHORT <1> ; The second pixel group includes the second pixel resistor Rs <2> , the second first selected sub-switch ROW_SEL <2> , the second second selection sub-switch ROW_SEL_D <2> and the second short-circuit switch ROW_SEL_SHORT <2> ; The third pixel group includes the third pixel resistor Rs <3> , the third first selected sub-switch ROW_SEL <3> , the third second selection sub-switch ROW_SEL_D <3> and the third short-circuit switch ROW_SEL_SHORT <3> ; The fourth pixel group includes the fourth pixel resistor Rs <4> , the fourth first selected sub-switch ROW_SEL <4> , the fourth second selected sub-switch ROW_SEL_D <4> and the fourth short-circuit switch ROW_SEL_SHORT <4> .

[0073] That is, the first pixel group is electrically connected to the first readout bus TS_UP; the second pixel group is electrically connected to the second readout bus TS_DN; the third pixel group is electrically connected to the first readout bus TS_UP; the fourth pixel group is electrically connected to the second readout bus TS_DN. The same applies to the subsequent pixel groups.

[0074] As mentioned above, starting from the first pixel group, each adjacent odd-numbered pixel group and even-numbered pixel group is a synchronous pixel group. For example, the first pixel group and the second pixel group are the first synchronous pixel group, and the third pixel group and the fourth pixel group are the second synchronous pixel group.

[0075] FIG5 is a timing diagram of the first readout bus pixel array readout. In the first time period, the first first selected sub-switch ROW_SEL <1> and the first and second selected sub-switch ROW_SEL_D <1> The first short-circuit switch ROW_SEL_SHORT is turned on. <1> Disconnect, the first pixel resistor Rs <1> is read out.

[0076] In the second time period, the third first selection sub-switch ROW_SEL <3> And the third second selected sub switch ROW_SEL_D <3> The third short-circuit switch ROW_SEL_SHORT is turned on. <3> Open, the first short-circuit switch ROW_SEL_SHORT <1> Keep it open, the other selected switches are open, the other short-circuit switches are closed, and the third pixel resistor Rs <3> is read out.

[0077] Similarly, in a time period, the corresponding selected switch is closed, the other selected switches are opened, and the corresponding short-circuit switch is opened. The corresponding short-circuit switch in the previous time period also remains opened, and the other short-circuit switches are closed.

[0078] Similarly, the timing diagram for pixel array readout of the second readout bus is the same as the above timing diagram:

[0079] In the first time period, the second first selection sub-switch ROW_SEL <2> and the second second selector switch ROW_SEL_D <2> The second short-circuit switch ROW_SEL_SHORT is turned on. <2> Disconnect, the second pixel resistor Rs <2> is read out.

[0080] In the second time period, the fourth first selection sub-switch ROW_SEL <4> and the fourth second selected sub-switch ROW_SEL_D <4> The fourth short-circuit switch ROW_SEL_SHORT is turned on. <4> Open, the second short-circuit switch ROW_SEL_SHORT <2> Keep it open, the other selected switches are open, the other short-circuit switches are closed, and the fourth pixel resistor Rs <4> is read out.

[0081] As shown in FIG6 , in some embodiments, K adjacent pixels in the figure are a pixel group. The adjacent K pixels refer to K pixels that are adjacent in sequence. That is, the first pixel group includes the first pixel resistor Rs <1> , the first selected sub-switch ROW_SEL <1> 、The first and second selection sub-switch ROW_SEL_D <1> , the first short-circuit switch ROW_SEL_SHORT <1> , the second pixel resistor Rs <2> , the second first selected sub-switch ROW_SEL <2> , the second second selection sub-switch ROW_SEL_D <2> , the second short-circuit switch ROW_SEL_SHORT <2> ...the Kth pixel resistor, the Kth first selected sub-switch, the Kth second selected sub-switch, and the Kth short-circuit switch; the second pixel group includes the K+1th pixel resistor, the K+1th first selected sub-switch, the K+1th second selected sub-switch, the K+1th short-circuit switch...the 2Kth pixel resistor, the 2Kth first selected sub-switch, the 2Kth second selected sub-switch, and the 2Kth short-circuit switch. Where K is an even number.

[0082] That is, the first pixel group is electrically connected to the first readout bus TS_UP, the second pixel group is electrically connected to the second readout bus TS_DN, and the subsequent pixel groups are electrically connected in the same manner.

[0083] As mentioned above, starting from the first pixel group, each adjacent odd-numbered pixel group and even-numbered pixel group is a synchronous pixel group. For example, the first pixel group and the second pixel group are the first synchronous pixel group, and the third pixel group and the fourth pixel group are the second synchronous pixel group.

[0084] It should be noted that the proposed resistor connection method can be expanded to read out K rows of pixel resistors using the first readout circuit and K rows of pixel resistors using the second readout circuit, where K is ≤ half the number of pixel array rows. The smaller the value of K, the easier it is to extract fixed pattern noise information. The larger the value of K, the greater the deviation caused by the readout bus TS routing in the two resistor readout circuits, and the more difficult it is to extract the difference information between the readout circuits.

[0085] As shown in FIG. 7 , FIG. 7 is another pixel array circuit diagram provided by some embodiments of the present application. Pixel 10 includes a pixel resistor Rs, a select switch ROW, and a short-circuit switch ROW_SEL_SHORT. The select switch ROW is configured to connect the pixel resistor Rs to its corresponding first readout bus TS_UP or second readout bus TS_DN, and also to connect the pixel resistor Rs to the reset terminal VDET.

[0086] The short-circuit switch is connected in parallel with the pixel resistor Rs and is configured to short-circuit the pixel resistor Rs; the pixel resistors Rs of multiple pixels in each pixel column 1 are connected in series in sequence; when the selected switch ROW is turned on and the short-circuit switch is turned off, the pixel information is read out.

[0087] As shown in FIG7 , the selection switch ROW includes a first selection sub-switch ROW_SEL and a second selection sub-switch ROW_SEL_D. A first end of the first selection sub-switch ROW_SEL is electrically connected to the first readout bus TS_UP or the second readout bus TS_DN, a second end of the first selection sub-switch ROW_SEL is electrically connected to the second end of the pixel resistor Rs, a first end of the pixel resistor Rs is electrically connected to the first end of the second selection sub-switch ROW_SEL_D, and a second end of the second selection sub-switch ROW_SEL_D is electrically connected to the reset terminal VDET. A first end of the short-circuit switch ROW_SEL_SHORT is electrically connected to the first end of the second selection sub-switch ROW_SEL_D, and a second end of the short-circuit switch ROW_SEL_SHORT is electrically connected to the second end of the pixel resistor Rs.

[0088] 5 , each time information of two pixels is read out, the short-circuit switches of the two pixels read out last time remain disconnected.

[0089] For example, in the third first selector switch ROW_SEL <3> And the third second selected sub switch ROW_SEL_D <3> Close, the third short-circuit switch ROW_SEL_SHORT <3> Disconnected, at this time, the first short-circuit switch ROW_SEL_SHORT <1> Still remains open until the third first selected sub-switch ROW_SEL <3> Open, the first short-circuit switch ROW_SEL_SHORT <1> This can prevent errors in the read pixels when reading new pixels.

[0090] In other embodiments, the value of y can be 2, 3, 4, Y / 8, Y / 4, etc. Different values ​​of y will eventually form different grouping methods, but the corresponding readout scheme of each group can still adopt the scheme described in the above embodiment.

[0091] Some embodiments of the present application provide a method for reading out a pixel array, which is applied to the above-mentioned pixel array.

[0092] The readout phase of the pixel array includes a plurality of readout phases arranged in sequence, wherein the plurality of readout phases include a first readout phase to an Nth readout phase, where N=M / 2, and M is the number of rows of the pixel array.

[0093] The readout method includes: in each readout phase, information of two pixels is read out by a first readout bus and a second readout bus respectively.

[0094] Starting from the first pixel group, each adjacent odd-numbered pixel group and even-numbered pixel group is a synchronous pixel group, and information of multiple pixels in a synchronous pixel group is read out; and multiple synchronous pixel groups are read out in sequence.

[0095] The information of the pixel is read out, and the pixel is connected to the corresponding first readout bus or second readout bus.

[0096] In some embodiments, reading out information of multiple pixels in a synchronous pixel group includes: simultaneously reading out information of a pixel in an odd-numbered pixel group and information of a pixel in an even-numbered pixel group.

[0097] The pixel column is electrically connected to the ground terminal; the pixel includes a pixel resistor, a first selected sub-switch, a second selected sub-switch and a short-circuit switch.

[0098] In the first readout stage, the first selected sub-switches and the second selected sub-switches of the two pixels corresponding to the first readout stage are closed, and the short-circuit switches of the two pixels corresponding to the first readout stage are disconnected. The first selected sub-switches and the second selected sub-switches of the other pixels except the two pixels read out in the first readout stage are disconnected, and the short-circuit switches are closed.

[0099] For example, the first selected sub-switch ROW_SEL in FIG5 <1> and the second second selector switch ROW_SEL_D <1> Close, the first short-circuit switch ROW_SEL_SHORT <1> The timing diagram corresponding to the disconnection belongs to the first readout phase.

[0100] In each readout stage from the second readout stage to the Nth readout stage, the first selected sub-switches and the second selected sub-switches of the two pixels corresponding to the readout stage are closed, and the short-circuit switches of the two pixels corresponding to the readout stage are disconnected; the first selected sub-switches and the second selected sub-switches of the other pixels except the two pixels read out in the readout stage are disconnected, and the short-circuit switches of the other pixels except the two pixels read out in the readout stage and the two pixels read out in the previous readout stage are closed.

[0101] For example, the subsequent timing diagrams in FIG. 5 belong to the second to Nth readout stages.

[0102] 5 , the pixel resistance is read only when both the first selected sub-switch ROW_SEL and the second selected sub-switch ROW_SEL_D are closed in the T1 period.

[0103] In some embodiments, during each readout phase, the first selected sub-switch ROW_SEL is closed before the second selected sub-switch ROW_SEL_D, and the closing duration of the first selected sub-switch ROW_SEL is equal to the closing duration of the second selected sub-switch ROW_SEL_D. This can make the readout circuit more stable.

[0104] Some embodiments of the present application provide a pixel array readout method that uses two readout circuits to simultaneously read pixels, thereby increasing the pixel readout speed. This increases the frame rate at high resolution. Furthermore, for integrating pixel processing circuits, the upper limit of the integration time can be further increased, thereby improving performance.

[0105] As shown in FIG. 8 , some embodiments of the present application provide an image sensor 200 , which includes a pixel array 100 , a first readout circuit TS1 , a second readout circuit TS2 , and an analog-to-digital conversion circuit 40 .

[0106] Pixel array 100 is configured to collect infrared signals. A first readout circuit TS1 includes multiple first readout buses TS_UP, and a second readout circuit TS2 includes multiple second readout buses TS_DN. The first and second readout circuits TS1 and TS2 are configured to convert the infrared signals into detection signals and output the detection signals as analog signals. An analog-to-digital conversion circuit 40 is electrically connected to the first and second readout circuits TS1 and TS2.

[0107] As shown in FIG9 , the first readout circuit includes a first pixel bias resistor Rd1, and the second readout circuit includes a second pixel bias resistor Rd2. The first pixel bias resistor Rd1 and the second pixel bias resistor Rd2 are located on the same side of the pixel array (see FIG3 ). For example, the first pixel bias resistor Rd1 and the second pixel bias resistor Rd2 are located on the same side of the pixel array extending direction.

[0108] The underlying components of the first readout circuit and the second readout circuit can be arranged in a cross-matching manner, thereby avoiding output differences caused by using two readout circuits and improving the performance of the sensor.

[0109] In some embodiments, the first readout circuit includes multiple first readout sub-circuits, and the second readout circuit includes multiple second readout sub-circuits; each first readout sub-circuit is electrically connected to a first readout bus TS_UP connected to a column of pixel columns 11, and each second readout sub-circuit is electrically connected to a second readout bus TS_DN connected to a column of pixel columns 11.

[0110] Each readout sub-circuit includes a bias resistor.

[0111] Some embodiments of the present application provide an image sensor that collects infrared signals through a pixel array. Two readout circuits quickly convert the infrared signals into detection signals and output the detection signals as analog signals. An analog-to-digital conversion circuit receives the analog signals and ultimately converts the collected infrared signals into images.

[0112] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A pixel array, characterized in that: include: A plurality of pixel columns; wherein, for each of the plurality of pixel columns, The pixel column includes Y pixels; The pixel column includes a plurality of pixel groups, and one pixel group in the plurality of pixel groups includes y adjacent pixels or one pixel in the Y pixels, and 2≤y<Y / 2; The odd-numbered pixel groups among the plurality of pixel groups are electrically connected to the first readout bus, and the even-numbered pixel groups among the plurality of pixel groups are electrically connected to the second readout bus; The column of pixels includes a plurality of synchronous pixel groups, one of the plurality of synchronous pixel groups includes an odd-numbered pixel group and an even-numbered pixel group adjacent to each other in the plurality of pixel groups, information of a plurality of pixels in one of the plurality of synchronous pixel groups is read out by the first readout bus and the second readout bus, and the plurality of synchronous pixel groups are read out in sequence; The information of the pixel is read out when the pixel is connected to the corresponding first readout bus or the second readout bus.

2. The pixel array according to claim 1, characterized in that: The plurality of pixel groups is X1 pixel groups, wherein Y / y=X1, and X1 is an integer; or The plurality of pixel groups are (X2+1) pixel groups, wherein Y / y=X2*X3, and the remaining X3 pixels are the last pixel group in the (X2+1) pixel groups.

3. The pixel array according to claim 1, characterized in that: Information of a plurality of pixels in one of the plurality of synchronous pixel groups is read out, including: The information of one pixel in the odd-numbered pixel group and the information of one pixel in the even-numbered pixel group are read out simultaneously.

4. The pixel array according to claim 1, characterized in that: One of the Y pixels includes a pixel resistor, a first selected switch, a second selected switch and a short-circuit switch; The first selection switch is configured to conduct the pixel resistor to the first readout bus or the second readout bus corresponding to the pixel resistor, and the second selection switch is configured to conduct the pixel resistor to the reset terminal; The short-circuit switch is connected in parallel with the pixel resistor and is configured to be able to short-circuit the pixel resistor; The pixel resistors of the Y pixels are connected in series in sequence; When the first selected switch and the second selected switch corresponding to a pixel are closed and the short-circuit switch is opened, information of the pixel is read out.

5. The pixel array according to claim 4, characterized in that: The first end of the first selected sub-switch is electrically connected to the first readout bus or the second readout bus, the second end of the first selected sub-switch is electrically connected to the first end of the pixel resistor, the second end of the pixel resistor is electrically connected to the first end of the second selected sub-switch, and the second end of the second selected sub-switch is electrically connected to the reset end.

6. The pixel array according to claim 4 or 5, characterized in that: During the phase in which information of two pixels in a synchronous pixel group is read out, the short-circuit switches of the two pixels read out last time remain open.

7. The pixel array according to claim 1, characterized in that: Every two adjacent pixels in the Y pixels form a pixel group; the odd-numbered pixel group is electrically connected to the first readout bus, and the even-numbered pixel group is electrically connected to the second readout bus; Starting from the first pixel group, each adjacent odd-numbered pixel group and even-numbered pixel group is a synchronous pixel group, and information of each pixel in a synchronous pixel group is read out; and a plurality of the synchronous pixel groups are read out in sequence.

8. The pixel array according to claim 1, characterized in that: Each of the Y pixels is a pixel group; the odd-numbered pixel groups are electrically connected to the first readout bus, and the even-numbered pixel groups are electrically connected to the second readout bus; Starting from the first pixel group, each adjacent odd-numbered pixel group and even-numbered pixel group is a synchronous pixel group, and information of each pixel in a synchronous pixel group is read out; and a plurality of the synchronous pixel groups are read out in sequence.

9. A method for reading a pixel array, characterized in that: The pixel array includes a plurality of pixel columns, wherein for each of the plurality of pixel columns, the pixel column includes Y pixels; wherein the pixel column includes a plurality of pixel groups, one of the plurality of pixel groups includes adjacent y pixels or one pixel among the Y pixels, 2≤y<Y / 2; wherein the odd-numbered pixel groups among the plurality of pixel groups are electrically connected to a first readout bus, and the even-numbered pixel groups among the plurality of pixel groups are electrically connected to a second readout bus; wherein the pixel column includes a plurality of synchronous pixel groups, one of the plurality of synchronous pixel groups includes adjacent odd-numbered pixel groups and even-numbered pixel groups among the plurality of pixel groups; The readout stage of the pixel array includes a first readout stage to an Nth readout stage arranged in sequence, wherein N=M / 2, and M is the number of rows of the pixel array; The reading method comprises: In each readout stage from the first readout stage to the Nth readout stage, information of two pixels in a synchronous pixel group is read out by the first readout bus and the second readout bus respectively; Reading out the plurality of synchronous pixel groups in sequence, wherein information of each pixel in each synchronous pixel group in the plurality of synchronous pixel groups is read out; The information of the pixel is read out when the pixel is connected to the corresponding first readout bus or the second readout bus.

10. The reading method according to claim 9, characterized in that: The information of two pixels in a synchronous pixel group is read out by the first readout bus and the second readout bus respectively, comprising: The information of a pixel in the odd-numbered pixel group in the synchronous pixel group is read out by one of the first read-out bus and the second read-out bus; and the information of a pixel in the even-numbered pixel group in the synchronous pixel group is read out by the other of the first read-out bus and the second read-out bus.

11. The reading method according to claim 9, characterized in that: One of the Y pixels includes a pixel resistor, a first selected sub-switch, a second selected sub-switch and a short-circuit switch; The reading method comprises: In the first readout stage, the first selected sub-switches and the second selected sub-switches of the two pixels in the first synchronous pixel group are closed, and the short-circuit switches of the two pixels are opened, and the first selected sub-switches and the second selected sub-switches of the other pixels except the two pixels read out in the first readout stage are opened, and the short-circuit switches of the other pixels are closed; In each readout stage from the second readout stage to the Nth readout stage, the first selected sub-switches and the second selected sub-switches of the two pixels in the synchronous pixel group corresponding to the readout stage are closed; the first selected sub-switches and the second selected sub-switches of the other pixels except the two pixels read out in the readout stage are opened, and the short-circuit switches of the two pixels read out in the readout stage and the two pixels read out in the previous readout stage are opened, and the short-circuit switches of the other pixels are closed.

12. The reading method according to claim 11, characterized in that: In each of the readout stages from the first readout stage to the Nth readout stage, the first selected sub-switch is closed before the second selected sub-switch, and the closing time length of the first selected sub-switch is equal to the closing time length of the second selected sub-switch.

13. The reading method according to any one of claims 9 to 12, characterized in that: The readout method comprises: synchronously reading out a plurality of synchronous pixel groups in the same row of the plurality of pixel columns.

14. An image sensor, characterized in that: include: The pixel array according to any one of claims 1 to 8, wherein the pixel array is configured to collect infrared signals; a first readout circuit and a second readout circuit, wherein the first readout circuit includes a plurality of the first readout buses, and the second readout circuit includes a plurality of the second readout buses; the first readout circuit and the second readout circuit are configured to convert the infrared signal into a detection signal and output the detection signal as an analog signal; An analog-to-digital conversion circuit is electrically connected to the first readout circuit and the second readout circuit.

15. The image sensor according to claim 14, characterized in that: The first readout circuit includes a first pixel bias resistor, and the second readout circuit includes a second pixel bias resistor. The first pixel bias resistor and the second pixel bias resistor are located on the same side of the pixel array.

16. The image sensor according to claim 14, characterized in that The first readout circuit includes a plurality of first readout sub-circuits, and the second readout circuit includes a plurality of second readout sub-circuits; Each of the first readout sub-circuits is electrically connected to a first readout bus connected to a column of pixel columns, and each of the second readout sub-circuits is electrically connected to a second readout bus connected to a column of pixel columns.

Images