Semiconductor package and electronic power module comprising a plurality of such semiconductor packages

Abstract

The invention relates to a semiconductor package (212, 215, 220) for an electronic power module (202), comprising a ceramic substrate (600) having a ceramic layer (800) between a lower copper layer (805) and an upper copper layer (810), comprising two first load terminals (300, 305) each having a leadframe (615, 620), wherein one of the first load terminals (300) is assigned to at least one first power semiconductor (335) and the other first load terminal (305) is assigned to at least one second power semiconductor (350), and wherein the relevant power semiconductor (335, 350) is arranged between the upper copper layer (810) of the ceramic substrate (600) and the leadframe (615, 620) of the associated first load terminal (300, 305) and is electrically connected to them, comprising a second load terminal (310), which is electrically connected to the upper copper layer (810), and comprising a control terminal (605), which is electrically connected to signal pins (325, 330) for controlling the semiconductor package (212, 215, 220) and, via connecting elements (610), to the power semiconductors (335, 350). Furthermore, the invention relates to an electronic power module (202) for a motor controller (200), an electrical drive axle (100) and a motor vehicle (105).

Description

[0001] Semiconductor package and electronic power module with several such

[0002] Semiconductor packages

[0003] The present invention relates to a semiconductor package for an electronic power module and to an electronic power module for an engine control system comprising a plurality of such semiconductor packages. Furthermore, the invention relates to an electric drive axle comprising such a power module and to a motor vehicle.

[0004] For example, DE 10 2009 044 659 A1 discloses a power semiconductor module comprising a lead frame, a power semiconductor element, and a cylindrical conductor. A portion of the lead frame, the power semiconductor element, and the cylindrical conductor are each sealed with a compression-molding resin, with terminal portions of the lead frame protruding from peripheral side portions of the power semiconductor module, and an opening of the cylindrical conductor being exposed on an upper surface of the power semiconductor module.

[0005] One object of the invention is to provide a compact semiconductor package that can achieve improved performance within a given package size. The invention achieves this object by means of the subject matter of the independent claims. Subclaims specify preferred embodiments.

[0006] A semiconductor package according to the invention for an electronic power module comprises a ceramic substrate which has a ceramic layer between a lower copper layer and an upper copper layer, two first load connections, each with a leadframe, wherein one of the first load connections is assigned to at least one first power semiconductor and the other first load connection is assigned to at least one second power semiconductor, and wherein the respective power semiconductor is arranged between the upper copper layer of the ceramic substrate and the leadframe of the associated first load connection and is electrically connected to these, a second load connection which is electrically connected to the upper copper layer, a control connection which is electrically connected to signal pins for controlling the semiconductor package and via connecting elements to the power semiconductors. The semiconductor package is designed as a discrete individual package of an electronic power orPower modules are to be understood. The semiconductor package can be used in a half-bridge of a motor control system, with two semiconductor packages forming a half-bridge. Several half-bridges, preferably three half-bridges, can be provided in a separately controllable manner to operate an electric machine of a motor vehicle. The semiconductor package is used to switch current, particularly for consumers in the several tens of kW range, especially for electric machines, e.g., for a motor vehicle.

[0007] By providing two first load terminals and assigning at least one power semiconductor or chip to each first load terminal, the number of power semiconductors on a given area of ​​the ceramic substrate can be increased. In other words, the packing density of the semiconductor package is maximized. By appropriately arranging the first load terminals, the second load terminal, and the power semiconductors, i.e., by selecting a suitable topology for the semiconductor package, current symmetry can also be achieved. The semiconductor package is current-symmetrical if the current flow within the semiconductor package is evenly distributed. This means that the current in different paths or branches of a circuit is always the same. Current symmetry ensures that the circuit functions properly and no undesirable effects occur.Furthermore, a semiconductor package described herein improves electrical testability, which can increase yield. Furthermore, the heat dissipation of the power semiconductors can be optimized, particularly through heat spreading.

[0008] The ceramic substrate can be an AMB (Active Metal Brazing) substrate, a DBC (Direct Copper Bonding) substrate, or a DPC (Direct Plated Copper) substrate. The ceramic layer is an electrical insulation layer. The ceramic layer is made of aluminum oxide or silicon nitride, for example. The lower copper layer of the ceramic substrate is designed to be connected to a heat sink. In other words, the lower copper layer is designed for cooling connection. The lower copper layer is understood to be the back or underside of the package, which is, for example, integrally connected to a heat sink. The heat sink is preferably part of a power module.

[0009] The load terminals can be formed from a single sheet of metal and stamped and formed into a lead frame, then brought into their final shape by stamping and forming. After stamping and forming the sheet, bonding the sheet to the ceramic substrate, and subsequent encapsulation, a remaining frame, which may be fixed during production, can be separated from the load terminals to separate them.

[0010] The first load terminals are designed to electrically connect a busbar to the power semiconductors of the semiconductor package. Together, the first load terminals form the AC terminal, or the "source" side of the semiconductor package. By providing two first load terminals, the power supply can be divided and routed specifically into the semiconductor package. This allows the semiconductor package to be made more compact, and current symmetry can be achieved due to the identical number of corresponding power semiconductors per first load terminal. This increases the power density while maintaining a compact design. The second load terminal forms the DC plus terminal, or the "drain" side, of the semiconductor package.

[0011] The load connections can have a plurality of legs, connectors and / or arms connected in one piece. One connection leg of each load connection, i.e. a leg that serves as a connection element for the external connection of the semiconductor package and has a contact surface, can be arranged three-dimensionally in space such that the contact surfaces of all load connections are arranged in a common plane, in particular on an upper side of the semiconductor package. This can improve the connection to the semiconductor package. The first load connections comprise lead frames, i.e. connection or guide frames, which are shaped such that a busbar connected to the first load connections is arranged at least indirectly on the respective power semiconductor. The respective lead frame conducts the electrical energy present at the first load connection to the associated power semiconductor. If a plurality of first orsecond power semiconductors are provided, the respective leadframe can be designed such that the electrical energy is distributed evenly to all first or second power semiconductors via cross-connectors or branches.

[0012] The control terminal is understood as the gate driver of the semiconductor package. The control terminal comprises a signal substrate with a ceramic layer arranged between a lower copper layer facing the ceramic substrate and an upper copper layer. The lower copper layer of the signal substrate has the same potential as the upper copper layer of the ceramic substrate. The upper copper layer of the control terminal is electrically connected to the signal pins and the connecting elements. Regarding the substrate material, please refer to the explanations regarding the ceramic substrate.

[0013] The connecting elements are preferably designed as bond wires. Two bond wires each electrically connect the upper copper layer of the control terminal to one of the power semiconductors. The bond wires are made, for example, of aluminum or another highly electrically conductive material.

[0014] The power semiconductor is a current valve with an input, an output, and a control terminal. The input and output are connected to the upper copper layer and the leadframe, respectively. The power semiconductor can be electrically insulated by encapsulation, particularly injection molding, preferably transfer molding. Current scaling can be achieved by varying the number and size of the power semiconductors connected in parallel.

[0015] Preferably, the ceramic substrate is substantially rectangular, with a first load terminal assigned to each of the longer sides and the second load terminal assigned to each of the shorter sides of the ceramic substrate. In other words, the first load terminals are arranged on opposite sides of the semiconductor package and can extend in opposite directions. This allows the semiconductor package to be symmetrical. Furthermore, the semiconductor package can be used flexibly. The second load terminal is preferably arranged centrally on one of the shorter sides of the semiconductor package.

[0016] The upper copper layer of the ceramic substrate is at least electrically connected to other components of the semiconductor package. First sintered layers are preferably applied to the upper copper layer in order to at least electrically connect the upper copper layer of the ceramic substrate to the second load terminal and the power semiconductors. Due to the large number of components connected to the upper copper layer, a large number of separate first sintered layers are also arranged on the surface of the upper copper layer of the ceramic substrate. In addition to the electrical connection, a thermal connection of the upper copper layer of the ceramic substrate is preferably made to the second load terminal, the control terminal, and the power semiconductors.

[0017] The first sintered layers can be designed as receptacles, in particular for the power semiconductors, wherein power semiconductors arranged in the receptacles are electrically connected in parallel between the upper copper layer and the leadframe. A sintered layer is provided to establish or fix an electrical connection between two components of the semiconductor package. In addition, the sintered layer improves the thermal properties in the contact area. The sintered layer enables a reliable and permanent connection between two components. The sintered layer is created by a sintering process in which powder particles, a sintered paste, or a sintered film are melted using heat and pressure, thus producing a dense and homogeneous layer that enables, in particular, efficient heat transfer.The sintered layer can consist of various materials that are both electrically conductive and have good thermal properties. Preferably, a second sintered layer, a bond buffer layer, and a solder layer are arranged between the respective leadframe and the associated power semiconductor, starting from the respective power semiconductor. In other words, the bond buffer layer is arranged between the solder layer and the second sintered layer, with the solder layer being assigned to the leadframe and the second sintered layer to the respective power semiconductor. The second sintered layer creates a dense, homogeneous connection layer between the power semiconductor and the bond buffer. The bond buffer can be a copper layer. The solder layer creates a dense, homogeneous connection layer between the bond buffer layer and the leadframe. Alternatively, the solder layer can be a sintered layer.Reference is made to the above statements, which are applicable analogously.

[0018] The bond buffer is a layer that reduces mechanical stress on the power semiconductor. The bond buffer compensates for differences in the thermal expansion coefficients between the leadframe and the power semiconductor. Furthermore, the bond buffer effectively dissipates heat from the power semiconductor. This prevents temperature hotspots, reducing stress on the power semiconductor and extending its service life. Thus, the bond buffer layer further improves the performance of the semiconductor package.

[0019] A solder layer is "softer" than a sintered layer and can therefore compensate for forces that can arise from so-called "thermal mismatch." "Thermal mismatch" refers to the situation when two components or materials have different thermal expansion coefficients and therefore expand or contract differently when the temperature changes. This can lead to stresses and deformations, especially when the materials or components are connected to each other. The thermal discrepancy can cause cracks, delamination, or other damage. The solder layer is designed to compensate for this discrepancy. The solder layer can be formed depending on the design of the leadframe, in particular any cross-connectors or arm segments. The solder layer can be segmented and, in principle, have any surface geometry. Preferably, exactly two signal pins are connected to the control connection.In other words, exactly two signal pins are connected to the upper copper layer of the control terminal or the signal substrate. If only two signal pins are provided, these pins are intended for gate control of the semiconductor package. The power semiconductors are controlled via the two signal pins, the upper copper layer of the signal substrate, and the connecting elements. The signal pins are connected to the power semiconductors for signal transmission.

[0020] In a further development of the invention, the control terminal is electrically connected to further signal pins, which are electrically connected via additional connecting elements to a temperature sensor arranged on the upper copper layer of the ceramic substrate. When bond wires are used as connecting elements, two further bond wires are electrically connected between the upper copper layer of the signal substrate of the control terminal and the temperature sensor. The further signal pins are connected to control the temperature sensor. The further signal pins are connected to the temperature sensor in a signal-transmitting manner. The temperature sensor can be connected to the upper copper layer of the ceramic substrate via a further first sintered layer in order to detect the temperature of the ceramic substrate.To simplify the design and / or if the temperature of the power semiconductors or other elements of the semiconductor package can be measured in another way, the temperature sensor and the associated additional components can be omitted.

[0021] The semiconductor package further preferably comprises two or more first power semiconductors and an identical number of second power semiconductors. In other words, the semiconductor package has just as many first power semiconductors as second power semiconductors. One first load terminal is thus electrically connected to two or more first power semiconductors via the associated leadframe, while the other first load terminal is electrically connected to the two or more second power semiconductors via the associated leadframe. Current scaling can be achieved by adjusting the number of chips. Preferably, six power semiconductors are provided, of which three power semiconductors are assigned to one of the first load terminals and the remaining three power semiconductors are assigned to the other first load terminal. The size or area of ​​the power semiconductors can also be adjusted for current scaling.A surface area of ​​20, 25 or 32 mm is conceivable. 2 However, for reasons of current symmetry, it is advantageous if all power semiconductors have the same size or area, i.e. the same properties.

[0022] To further improve current symmetry, the at least two first power semiconductors are arranged in series and spaced from one another, wherein the at least two second power semiconductors are arranged in series and at identical distances from one another and parallel to the first power semiconductors. In the longitudinal direction of the semiconductor package, i.e. along the longer side of the rectangular ceramic substrate, the first and second power semiconductors have essentially constant distances from one another. Likewise, the first and second power semiconductors have a constant distance from one another in the transverse direction. With three first and three second power semiconductors each, these are thus arranged in a 2x3 arrangement on the upper ceramic layer of the ceramic substrate. The control connection can be elongated and aligned essentially parallel to the two rows of power semiconductors.The control terminal is arranged in particular between the two power semiconductor rows.

[0023] In the case of a plurality of first or second power semiconductors, the respective leadframe preferably has at least one cross-connector that connects the first load terminal to two first or two second power semiconductors, respectively. In other words, the leadframe of the one first load terminal has at least one first cross-connector that connects two first power semiconductors to each other, while the leadframe of the other first load terminal comprises at least one second cross-connector that connects two second power semiconductors to each other.

[0024] Furthermore, the respective cross-connector preferably comprises one or more arm segments, which at least partially come into contact with the solder layer. Accordingly, the first cross-connector of the leadframe of one of the first load connections has at least one first arm segment for electrically connecting the respective first load connection to one of the first power semiconductors and at least one second arm segment for electrically connecting the same first load connection to a further first power semiconductor. For each further first power semiconductor, the first cross-connector of the leadframe can comprise at least one further arm segment in order to realize an electrical connection to the further first power semiconductor. Two or more cross-connectors can also be provided in order to electrically connect the respective first load connection to one or more power semiconductors.Everything stated above and below for one of the first load connections applies equally and analogously to the other first load connection, and vice versa. The first load connections are mirror-symmetrical.

[0025] In order to keep the contact area between the leadframe and the power semiconductor as small as possible, it is advantageous if the respective arm segment is divided into several sections, with contact sections for contacting and connection sections for connecting two contact sections. In other words, the respective leadframe can be connected to the associated power semiconductor via several smaller areas. The aforementioned connection section is a type of bridge, which reduces the contact area with the chip and thus stresses within the system. Preferably, the respective arm segment has at least two contact sections that contact the solder layer, with the two contact sections being connected to one another via the connection section that does not contact the solder layer.One of the attachment sections is connected to the respective leadframe, while the other attachment section forms a distal end of the respective arm segment.

[0026] To further improve the current symmetry within the upper copper layer of the ceramic substrate, the semiconductor package further comprises two third load terminals, which have the same potential as the second load terminal and which are each electrically connected to the upper copper layer of the ceramic substrate. The third load terminals are load terminals for current balancing. For this purpose, the third load terminals are preferably arranged at an opposite end of the ceramic substrate with respect to the second load terminal and have a potential identical to the second load terminal. The third load terminals also form the "drain" side of the semiconductor package. On the side of the upper copper layer facing away from the ceramic layer, a respective first sintered layer can be arranged between the respective third load terminal and the upper copper layer of the ceramic substrate in order to improve contact.

[0027] Preferably, a third load terminal is assigned to each of the longer sides of the ceramic substrate. In other words, the third load terminals are arranged on opposite sides of the semiconductor package and extend in opposite directions, analogous to the first load terminals. The third load terminals are arranged at a transverse distance from the first load terminals, preferably far enough away that no interaction can occur during operation. Thus, a first load terminal and a third load terminal are arranged on each of the longer sides of the semiconductor package. The third load terminals can also have a contact surface that lies in the same plane as the contact surfaces of the first load terminals or the second load terminal on the top side of the semiconductor package.Depending on the design of the power module, the third load terminals can be arranged on the short side of the ceramic substrate opposite to the second load terminal.

[0028] To insulate the components of the semiconductor package, the semiconductor package is encapsulated using injection molding. In other words, the semiconductor package is encapsulated using a molding process. The molding process involves molding a plastic housing made of insulating material around one or more power semiconductors. Encapsulation protects the power semiconductors from external influences such as moisture and dust. The molding process involves injecting liquid plastic as insulating material into a mold in which the components of the semiconductor package are placed. After the plastic has hardened, the mold or tool is removed, protecting the semiconductor package. The semiconductor package is encapsulated, for example, using transfer or compression molding.In transfer molding, a defined amount of a molding material, typically a thermoset or thermoplastic, is poured into a mold cavity through a sprue. During transfer molding, the mold walls are typically heated to a temperature above the melting temperature of the molding material to ensure good flow properties within the cavity. A wide variety of thermoplastics and thermosets are suitable for transfer molding.

[0029] If the semiconductor package comprises third load terminals, which are also assigned to the longer sides of the ceramic substrate and arranged at a distance from the first load terminals, at least one recess is formed in the insulating material spatially between the first and third load terminals on the same side of the semiconductor package. The recess can be a bead, a shoulder, or the like, which is formed or shaped in the insulating material (also called a "mold") and is provided for generating the necessary air and creepage distances. The respective recess is therefore advantageous for a compact design of the semiconductor package, since it allows the first load terminal and the third load terminal of the respective side of the ceramic substrate to be arranged closer to one another without the load terminals negatively influencing one another.

[0030] In a further aspect of the invention, an electronic power module according to the invention comprises a heat sink on which several semiconductor packages according to one of the preceding claims are arranged. The lower copper layer of the ceramic layer of the respective semiconductor package can be connected to the heat sink, for example, using so-called nanowire technology, by sintering, soldering, or pressing using an organic insulator. The lower copper layer can be connected directly to the heat sink. Alternatively, an insulation layer can be arranged between the lower copper layer and the heat sink.

[0031] Preferably, six semiconductor packages are arranged on the heat sink, with two semiconductor packages each combined to form a half-bridge and each connected in series. In an alternative embodiment, twelve semiconductor packages are arranged on the heat sink, with four semiconductor packages each combined to form a half-bridge. The resulting half-bridges are preferably electrically connected in parallel. With six semiconductor packages, one semiconductor package is provided per switching position. With twelve semiconductor packages, two semiconductor packages are provided per switching position. Regardless of the number of semiconductor packages, all semiconductor packages can be arranged and cooled on a common heat sink, for example designed as a cooling plate or the like.

[0032] In a further aspect of the invention, an electric drive axle according to the invention, also called an E-axle, comprises an electric machine and an electronic power module proposed herein. The electric machine is a three-phase electric machine. The power module is provided in a motor controller that controls the electric machine. In addition to the electric machine, the electric drive axle can include an optional transmission to provide torque and speed for driving a drive wheel of the motor vehicle. In addition to the electric machine, a motor controller can also be included. The electric machine is supplied with electrical energy from an energy storage device.

[0033] In a further aspect of the invention, a motor vehicle according to the invention comprises an electric drive axle according to the invention or an electronic power module according to the invention. The motor vehicle can, in particular, comprise a motorcycle, a passenger car, a truck, or a bus.

[0034] The motor vehicle comprises at least two axles. Preferably, two axles are provided, with at least one of the axles being an electric drive axle and being drivable by at least one electric motor.

[0035] The above definitions and statements regarding technical effects, advantages, and advantageous embodiments of the semiconductor package according to the invention also apply mutatis mutandis to the power module according to the invention according to the second aspect of the invention, to the electric drive axle according to the invention according to the third aspect of the invention, and to the motor vehicle according to the invention according to the fourth aspect of the invention, and vice versa. It is understood that the features mentioned above and those to be explained below can be used not only in the respective combinations specified, but also in other combinations or on their own, without departing from the scope of the present invention.

[0036] To the extent that elements are designated by numbering, for example, "first component," "second component," and "third component," this numbering is intended purely for differentiation in the designation and does not represent a dependency of the elements on one another or a mandatory sequence of the elements. This means, in particular, that a device does not have to have a "first component" in order to have a "second component." The device may also comprise a "first component" and a "third component," but without necessarily having a "second component."

[0037] The invention will now be described in more detail with reference to the accompanying figures, in which:

[0038] Figure 1 is a highly schematic view of a motor vehicle with an electric drive axle;

[0039] Figure 2 shows an exemplary motor control of the drive axle, comprising an electronic power module with half bridges according to the invention;

[0040] Figure 3 is a circuit diagram illustrating the circuit of the electronic power module according to the invention shown in Figure 2;

[0041] Figure 4 is a schematic view of the electronic power module according to the invention shown in Figures 2 and 3 with several semiconductor packages according to the invention;

[0042] Figure 5 is a schematic perspective view of an exemplary semiconductor package according to Figure 4 according to a first embodiment;

[0043] Figure 6 is a schematic exploded view of the semiconductor package according to Figure 5; Figure 7 is a schematic perspective view of the semiconductor package according to Figures 5 and 6 without showing the insulation material;

[0044] Figure 8 is a schematic side view of the semiconductor package according to Figure 5 to Figure ? without showing the insulation material;

[0045] Figure 9 is a detailed sectional view of the semiconductor package according to Figure 8 to illustrate the electronic connection of a power semiconductor;

[0046] Figure 10 is a detailed perspective view of the semiconductor package according to Figures 5 to 9 to illustrate the electronic connection of a lead frame with power semiconductors;

[0047] Figure 11 is a schematic plan view of the semiconductor package according to the invention according to a second embodiment without showing the insulation material; and

[0048] Figure 12 shows a schematic plan view of the semiconductor package according to the invention according to a third embodiment without showing the insulation material; wherein identical or similar components are provided with the same reference numerals.

[0049] Figure 1 shows an electric drive axle 100 in a motor vehicle 105. The motor vehicle 105 may additionally include an internal combustion engine 110 connected to a drive wheel 120 of the motor vehicle 105 via a transmission 115. In this case, the motor vehicle 105 would be a hybrid vehicle.

[0050] The electric drive axle 110 comprises an electric machine 125, which can also act on the drive wheel 120, preferably by means of the transmission 115. Furthermore, a power converter 130 can be provided, which can be fed with electrical energy from an electrical energy storage device 135. The electrical energy storage device 135 is preferably electrochemically constructed, but a fuel cell or another power source can also be used, for example. The power converter 130 is preferably configured to provide phase-shifted alternating currents to the electric machine 125. The electric machine 125 is implemented, for example, as a permanent-magnet synchronous machine, but other embodiments are also possible. The voltages and frequencies of the alternating currents provided can be determined such that the electric machine 125 converts a predetermined torque or rotates at a predetermined speed.A field-oriented control system can be implemented to control the direction of rotation and speed. The nominal voltage of the electrical energy storage device 135 is typically several hundred to over 1000 V. The current through the electric drive motor 125 can be several hundred A.

[0051] Figure 2 shows a motor controller 200 with a power module 202, comprising three half-bridges 205, which can be controlled, for example, by means of a common control device 210. The motor controller 200 is configured to control the rotational behavior of the electric machine 125 and typically operates digitally using a microcomputer.

[0052] Each half-bridge 205 comprises two semiconductor packages 212 according to the invention, divided into an upper semiconductor package 215 and a lower semiconductor package 220. The semiconductor packages 212, 215, 220 are connected in series between DC voltage potentials of the energy storage device 135 as shown. A DC link capacitor 225 is preferably provided between the potentials. A center tap 230 between the semiconductor packages 212, 215, 220 is connected to an associated phase of the electric machine 125. The upper semiconductor package 215 lies between a high potential of the energy storage device 135 and the center tap 230, and the lower semiconductor package 220 lies between the center tap 230 and a low potential of the energy storage device 135.

[0053] The semiconductor packages 212, 215, 220 can be controlled independently of one another, each like an electrical switch, to close or open. The control device 210 is configured to alternately close and open the semiconductor packages 212, 215, 220, so that at no time are both semiconductor packages 215, 220 of a half-bridge 205 closed. A voltage that occurs at the center tap 230 of the respective half-bridge 205 depends on a ratio of the duty cycles of the upper semiconductor package 215 and the lower semiconductor package 220. During normal operation of the electric machine 125, predetermined currents can thus be controlled through the semiconductor packages 212, 215, 220.

[0054] Figure 3 shows a circuit diagram of the semiconductor package 212, 215, 220 of the power module 202. In this case, the respective semiconductor package 212, 215, 220 has two first load terminals 300, 305, which are combined here for simplification into a single terminal as the "source," a second load terminal 310, and two third load terminals 315, 320, which are combined here for simplification into a single terminal as the "drain." The semiconductor package 212, 215, 220 also has two signal pins 325, 330 as control terminals, which are provided for gate control. The "gate" is the electrode between the "drain," i.e., the second and third load terminals 310, 315, 320, and the "source," i.e., the first load terminals 300, 305, and serves to control the switching behavior of the half-bridge 205. It enables the activation and deactivation of the semiconductor package 212, 215, 220 in the half-bridge 205.In this case, six parallel-connected power semiconductors 335, 340, 345, 350, 355, 360 are arranged between the load terminals 300 - 320, which can be controlled via the signal pins 325, 330.

[0055] Figure 4 shows a top view of the electronic power module 202 according to Figure 2. The power module 202 comprises a heat sink 400, on which the six semiconductor packages 212, 215, 220 or the three half-bridges 205, each consisting of two semiconductor packages 215, 220 connected in series, are arranged. Each semiconductor package 212, 215, 220 is assigned as a discrete individual package to a switching position of the power module 202. Alternatively, the power module 202 can also be arranged with twelve semiconductor packages 212, 215, 220 or six half-bridges 205 together on the heat sink 400, with two semiconductor packages 212, 215, 220 each being assigned as discrete individual packages to a switching position of the power module 202.

[0056] The semiconductor packages 212, 215, 220 are configured identically regardless of their number, which is why only one exemplary semiconductor package 212 is shown and described below in Figures 5 ff. The other semiconductor packages 212, 215, 220 are configured analogously.

[0057] Figure 5 shows the semiconductor package 212 in its manufactured state as a separately handleable unit. Shown here are the aforementioned load terminals 300-320, as well as the previously mentioned signal pins 325 and 330 for gate control, as well as two additional signal pins 500 and 505, which will be discussed in more detail below.

[0058] The semiconductor package 212 is encapsulated by injection molding, with an insulating material 510 forming a housing for the semiconductor package 212, so to speak, in order to protect the parts described below, where necessary, from interaction with one another and from external influences, in particular dirt and moisture. Figure 5 shows that, spatially between a first load terminal 300, 305 and a third load terminal 315, 320 of the same longer side of the semiconductor package 212, which is T-shaped in cross section and rectangular in plan view, a recess 515 in the form of a bead is formed in the insulating material 510 in order to realize the required air and creepage distance. This allows the distance between the load terminals 300, 305, 315, 320 on the same side to be made smaller, whereby the semiconductor package 212 can be designed more compactly.In this sense, one of the third load terminals 315, together with one of the first load terminals 300, is assigned to one of the longer sides of the semiconductor package 212, while the other third load terminal 320, together with the other first load terminal 305, is assigned to the opposite side of the semiconductor package 212. The second load terminal 310 is assigned to the shorter side of the semiconductor package 212 that is further away from the third load terminals 315, 320 in order to realize current symmetry within the semiconductor package 212. The two third load terminals 315, 320 have the same potential as the second load terminal 310.

[0059] The load terminals 300-320 each have a surface that lies in a plane with a surface of the insulation material 510, thereby forming the flat upper surface of the semiconductor package 212 shown in Figure 5. Via the load terminals 300-320, the semiconductor packages 212, 215, 220 of a half-bridge 205 are connected to each other, to a busbar arrangement (not shown here), and externally.

[0060] According to Figures 6 and 7, the semiconductor package 212 comprises a ceramic substrate 600 which is essentially rectangular in plan view and, as can be seen more clearly in Figure 8, has a ceramic layer 800 between a lower copper layer 805 and an upper copper layer 810. Furthermore, the semiconductor package 212 comprises a control terminal 605 which is electrically connected to signal pins 325, 330 for controlling the semiconductor package 212, signal pins 500, 505 for signal-transmitting connection to a temperature sensor (not shown here), and to the power semiconductors 335-360 via connecting elements 610 designed as bond wires.

[0061] A first load terminal 300, 305 and a third load terminal 315, 320 are each assigned to one of the longer sides of the ceramic substrate 600. The second load terminal 310 is assigned to one of the shorter sides of the ceramic substrate 600. According to Figure 7, several first sintered layers 700 are applied to the upper copper layer 810 in order to directly electrically connect the upper copper layer 810 of the ceramic substrate 600 to the second load terminal 310, the third load terminals 315, 320, the control terminal 605, and the power semiconductors 335-360. The load terminals 300-320 can be punched out of a sheet metal as a lead frame and formed into the desired shape by forming.

[0062] In the present case, the power semiconductors 335, 340, 345 of the row of three arranged to the left of the control terminal 605 are to be understood as first power semiconductors, which are assigned to the left first load terminal 300. The power semiconductors 350, 355, 360 of the row of three arranged to the right of the control terminal 605 are to be understood as second power semiconductors, which are assigned to the right first load terminal 305. Thus, the semiconductor package 212 comprises three first power semiconductors 335, 340, 345 and an identical number of second power semiconductors 350, 355, 360. The three first power semiconductors 335, 340, 345 are arranged in series and spaced from one another, with the three second power semiconductors 350, 355, 360 being arranged in series and at identical distances from one another and parallel to the first power semiconductors. Thus, the power semiconductors 335 - 360 are arranged in a 2x3 arrangement on the ceramic substrate 600.The power semiconductors 335-360 are identically designed and have the same size and area. The proposed design of the semiconductor package 212 allows for current symmetry to be realized, so that all power semiconductors 335-360 are supplied with current essentially evenly, which in turn optimizes the performance of the semiconductor package 212.

[0063] Each first load terminal 300, 305 comprises a leadframe 615, 620 configured as a connecting arm to electrically connect the respective first load terminal 300, 305 at least indirectly to the upper copper layer 810. According to Figure 9, which shows an example of the layer structure between the leadframe 615 of the first load terminal 300 and one of the associated first power semiconductors 335, starting from the upper copper layer 810 of the ceramic substrate 600, i.e., from bottom to top, a first sintered layer 700, thereon the first power semiconductor 335, thereon a second sintered layer 900, thereon a bond buffer layer 905 configured as a copper layer, thereon a solder layer 910, and thereon the leadframe 615. Thus, the leadframe 615 is soldered onto the first power semiconductor 335. The connection between the leadframes 615, 620 and the other power semiconductors 340 - 360 is designed analogously.

[0064] The design of the leadframes 615, 620 is described below with reference to Figure 7 and Figure 10. Accordingly, the leadframe 615 of the left first load connection 300 has two cross-connectors 705, 710 for connecting the left first load connection 300 to the three first power semiconductors 335, 340, 345 to the left of the control connection 605. The leadframe 620 of the right first load connection 305, mirror-inverted to the leadframe 615 of the left first load connection 300, also has two cross-connectors 705, 710 for connecting the right first load connection 305 to the three second power semiconductors 350, 355, 360 to the right of the control connection 605. Each cross-connector 705, 710 has three arm segments 715, 720, 725, which are partially bonded to an associated solder layer 910 of the respective power semiconductor 335-360, shown in Figure 9. The solder layers 910 are formed here as parallel strips.The solder layers 910 are adapted to the design of the arm segments 715, 720, 725. The solder layers 910 can be formed segmentally, i.e., with interruptions. In order to achieve or improve the desired current symmetry, according to Figure 7, using the example of the power semiconductor row arranged to the left of the control terminal 605, two arm segments 715, 720 of the first cross-connector 705 extend to the first (335) of the three first power semiconductors and another arm segment 725 to the second (340) of the three first power semiconductors, with two arm segments 715, 720 of the second cross-connector 710 extending to the third (345) of the three first power semiconductors and another arm segment 725 likewise extending to the second (340) of the three first power semiconductors. Thus, the same area of ​​the left first load terminal 300 is applied to each first power semiconductor 335, 340, 345 and the power semiconductors 335, 340, 345 can be supplied with current evenly.

[0065] In this context, Figure 10 also illustrates the design of the respective arm segment 715, 720, 725, here using the example of the second cross-connector 710 of the leadframe 615 of the left first load terminal 300. Specifically, each arm segment 715, 720, 725 is divided into several sections, namely two contact sections 1000, 1005 for contacting the leadframe 615 with the solder layer 910, and a connecting section 1010 that integrally connects the two contact sections 1000, 1005 to one another, is not in contact with the solder layer 910, and is designed as a bridge. This keeps the contact area between the leadframe 615 and the first power semiconductors 335, 340, 345 as small as possible, which reduces the load on the first power semiconductors 335, 340, 345.

[0066] To avoid unnecessary repetition, it is expressly pointed out that the first load connection 305 arranged to the right of the control connection 605, with the leadframe 620 formed thereon as well as the cross-connectors 705, 710 and arm segments 715, 720, 725 encompassed thereby, is essentially mirror-inverted to the previously described left first load connection 300. Therefore, what has been said about the left first load connection 300 applies analogously to the right first load connection 310.

[0067] Figure 8 shows that the control terminal 605 has a multi-layer structure. The control terminal 605 is to be understood as a gate carrier or signal substrate, which transmits signals, which are conducted into the semiconductor package 212 via the signal pins 325, 330, to the power semiconductors 335-360 via the connecting elements 610. The control terminal 605 has a ceramic layer 815, which is arranged between another lower copper layer 820 and another upper copper layer 825. The lower copper layer 820 is electrically connected to the upper copper layer 810 of the ceramic substrate 600 via a first sintered layer 700. The connecting elements 610 are directly electrically connected to the upper copper layer 825 of the control terminal 605, with two connecting elements 610 each contacting one of the power semiconductors 335-360.

[0068] The upper copper layer 825 of the control terminal 605 is segmented according to Figure 7. In other words, the upper copper layer 825 of the control terminal 605 consists of several segments. The design of the segments depends on the requirements of the control terminal 605. The control terminal 605 is, as already indicated, further electrically connected to two further signal pins 500, 505, which are electrically connected via connecting elements (not shown here) that can be designed as bond wires, analogous to the other connecting elements 610, to a temperature sensor arranged on the upper copper layer 810 of the ceramic substrate 600. The temperature sensor is also not shown here. In this regard, Figure 7 shows a further first sintered layer 700 in the upper right corner of the ceramic substrate 600 in the region of the second load terminal 310, on which the temperature sensor can be arranged.The connecting elements 610 for connecting the control terminal 605 to this first sintered layer 700 are indicated in Figure 12.

[0069] Figure 11 shows an alternative embodiment of the previously described semiconductor package according to Figures 5 to 10, with only the differences being discussed below. As can be seen in Figure 11, the temperature sensor, and accordingly the associated control pins 500, 505, the connecting elements, and the additional first sintered layer 700 can be omitted if the temperature of the semiconductor package 212 is determined or detected by other means. This allows the structure of the semiconductor package 212 to be simplified.

[0070] Figure 12 shows a further possible embodiment of the previously described semiconductor package according to Figures 5 to 10, although only the differences will be discussed below. In the present case, the semiconductor package 212 has only four power semiconductors 335, 345, two of which are assigned to one first load terminal 300 and the other two first load terminals 350, 360 to the other first load terminal 305. Depending on the requirements of the semiconductor package 212, individual power semiconductors can therefore be dispensed with according to Figure 12. For reasons of current symmetry, the number of first power semiconductors must always be selected to be identical to the number of second power semiconductors. The semiconductor package 212 can be adapted to the existing requirements using simple means. In this example, one of the first and second power semiconductors 340, 355, in this case the middle one, is dispensed with.This also simplifies the design of the leadframes 615, 620. Likewise, the number of first and second power semiconductors can be increased to the same extent, so that, for example, eight, ten, or more power semiconductors are arranged on the upper copper layer 810 of the ceramic substrate 600 and connected to the control terminal 605.

[0071] Reference symbol electric drive axle

[0072] Motor vehicle

[0073] Combustion engine transmission

[0074] Drive wheel electric machine

[0075] power converter

[0076] Energy storage

[0077] Engine control power module

[0078] Half bridge

[0079] Control device Semiconductor package Upper semiconductor package Lower semiconductor package

[0080] DC link capacitor center tap

[0081] First load connection

[0082] First load connection

[0083] Second load connection

[0084] Third load connection

[0085] Third load connection

[0086] Signal pin for gate control Signal pin for gate control First power semiconductor First power semiconductor First power semiconductor Second power semiconductor Second power semiconductor

[0087] heat sink

[0088] Signal pin for temperature sensor

[0089] Signal pin for temperature sensor

[0090] Insulation material

[0091] recess

[0092] Ceramic substrate

[0093] Control connection

[0094] connecting element

[0095] Leadframe

[0096] Leadframe

[0097] First sinter layer

[0098] First cross connector

[0099] Second cross connector

[0100] First arm segment

[0101] Second arm segment

[0102] Third arm segment

[0103] Ceramic layer of the ceramic substrate

[0104] Lower copper layer of the ceramic substrate

[0105] Upper copper layer of the ceramic substrate Ceramic layer of the control terminal

[0106] Lower copper layer of the control connection

[0107] Upper copper layer of the control connection

[0108] Second sintered layer

[0109] Bond buffer layer

[0110] Solder layer 1000 First contact section of the arm segment

[0111] 1005 Second section of the arm segment

[0112] 1010 Connecting section of the arm segment

Claims

Patent claims 1. A semiconductor package (212, 215, 220) for an electronic power module (202), comprising a ceramic substrate (600) having a ceramic layer (800) between a lower copper layer (805) and an upper copper layer (810), two first load terminals (300, 305) each having a leadframe (615, 620), wherein one of the first load terminals (300) is associated with at least one first power semiconductor (335) and the other first load terminal (305) is associated with at least one second power semiconductor (350), and wherein the respective power semiconductor (335, 350) is arranged between the upper copper layer (810) of the ceramic substrate (600) and the leadframe (615, 620) of the associated first load terminal (300, 305) and is electrically connected thereto, a second load terminal (310) which is connected to the upper copper layer (810) is electrically connected, a control terminal (605) which is connected to signal pins (325, 330) for controlling the semiconductor package (212, 215,220) and via connecting elements (610) with the power semiconductors (335, 350).

2. Semiconductor package (212, 215, 220) according to claim 1, wherein the ceramic substrate (600) is substantially rectangular, and wherein a first load terminal (300, 305) is assigned to one of the longer sides and the second load terminal (310) is assigned to one of the shorter sides of the ceramic substrate (600).

3. Semiconductor package (212, 215, 220) according to claim 1 or claim 2, wherein first sintered layers (700) are applied to the upper copper layer (810) of the ceramic substrate (600) in order to at least electrically connect the upper copper layer (810) to the second load terminal (310), to the control terminal (605) and to the power semiconductors (335, 350).

4. Semiconductor package (212, 215, 220) according to one of the preceding claims, wherein between the respective leadframe (615, 620) and the associated power semiconductor (335, 350) starting from the respective power semiconductor ter (335, 350) a second sintered layer (900), a bond buffer layer (905) and a solder layer (910) are arranged.

5. Semiconductor package (212, 215, 220) according to one of the preceding claims, wherein the control terminal (605) is electrically connected to further signal pins (500, 505) which are electrically connected via connecting elements to a temperature sensor arranged on the upper copper layer (810).

6. Semiconductor package (212, 215, 220) according to one of the preceding claims, comprising two or more first power semiconductors (335, 340, 345) and an identical number of second power semiconductors (350, 355, 360).

7. Semiconductor package (212, 215, 220) according to one of the preceding claims, wherein the at least two first power semiconductors (335, 340, 345) are arranged in series and spaced from one another, and wherein the at least two second power semiconductors (350, 355, 360) are arranged in series and at identical distances from one another and parallel to the first power semiconductors (335, 340, 345).

8. Semiconductor package (212, 215, 220) according to claim 6 or claim 7, wherein the respective leadframe (615, 620) comprises at least one cross-connector (705) which connects the first load terminal (300, 305) to two first or two second power semiconductors (335, 340, 345, 350, 355, 360).

9. Semiconductor package (212, 215, 220) according to claim 8 in conjunction with claim 4, wherein the respective cross-connector (705) comprises one or more arm segments (715) which at least partially come into contact with the solder layer (900).

10. The semiconductor package (212, 215, 220) according to any one of the preceding claims, further comprising two third load terminals (315, 320) having the same potential as the second load terminal (310) and each electrically connected to the upper copper layer (810) of the ceramic substrate (600).

11. Semiconductor package (212, 215, 220) according to claim 10 in conjunction with claim 2, wherein a third load terminal (315, 320) is assigned to each of the longer sides of the ceramic substrate (600).

12. The semiconductor package (212, 215, 220) according to any one of the preceding claims, wherein the semiconductor package (212, 215, 220) is encapsulated by injection molding.

13. Semiconductor package (212, 215, 220) according to claim 12 in conjunction with claim 11, wherein at least one recess (515) is formed in the insulation material (510) spatially between the first and third load terminals (300, 305, 315, 320) of the same side of the semiconductor package (212, 215, 220).

14. Electronic power module (202) for a motor control (200), comprising a heat sink (400) on which a plurality of semiconductor packages (212, 215, 220) according to one of the preceding claims are arranged.

15. Electronic power module (202) according to claim 14, wherein six semiconductor packages (212, 215, 220) are arranged on the heat sink (400), wherein two semiconductor packages (212, 215, 220) are combined to form a half-bridge (205) and are each connected in series.

16. Electronic power module (202) according to claim 14, wherein twelve semiconductor packages (212, 215, 220) are arranged on the heat sink (400), wherein four semiconductor packages (212, 215, 220) are combined to form a half-bridge (205).

17. Electric drive axle (100), comprising an electric machine (125) and an electronic power module (202) according to one of claims 14 to 16.

18. Motor vehicle (105) comprising an electric drive axle (100) according to claim 17.

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