Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor in which the insulation properties of the entire dielectric layer are increased and for which the reliability of the multilayer ceramic capacitor can be improved.This multilayer ceramic capacitor comprises: a laminate that includes a plurality of laminated dielectric layers and that has a first main surface and a second main surface which face each other in the lamination direction of the plurality of dielectric layers, a first lateral surface and a second lateral surface which face each other in the width direction orthogonal to the lamination direction, and a first end surface and a second end surface which face each other in the length direction orthogonal to the lamination direction and the width direction; a first external electrode that has a first internal electrode layer disposed above the plurality of dielectric layers and exposed to the first end surface, a second internal electrode layer disposed above the plurality of dielectric layers and exposed to the second end surface, a substrate electrode layer disposed above the first end surface, and a plating layer disposed above the substrate electrode layer; and a second external electrode that has a substrate electrode layer disposed above the second end surface, and a plating layer disposed above the substrate electrode layer. Dielectric particles are disposed in the dielectric layers. The dielectric particles include Mn and Zr, and in the dielectric particles, the atomic ratio (Mn / Zr) of Mn to Zr is 0.60 to 0.80.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors have been known for some time. Generally, multilayer ceramic capacitors include a ceramic sintered body made of a dielectric ceramic such as barium titanate (BaTiO). A plurality of internal electrodes are arranged inside the ceramic sintered body so as to overlap with each other via dielectric layers. External electrodes are formed on one end surface and the other end surface of the ceramic sintered body so as to be electrically connected to the internal electrodes (see, for example, Patent Document 1).

[0003] Japanese Patent Application Publication No. 8-306580

[0004] However, in a typical multilayer ceramic capacitor such as that disclosed in Patent Document 1, the amount of Mn dissolved in the dielectric particles in the dielectric layer is insufficient, and Mn tends to segregate at the grain boundaries of the dielectric particles. The Mn-segregated layer becomes a low-resistance layer, which reduces the insulation properties of the entire dielectric layer and reduces the reliability of the multilayer ceramic capacitor.

[0005] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor in which the insulation properties of the entire dielectric layer are increased, thereby improving the reliability of the multilayer ceramic capacitor.

[0006] A multilayer ceramic capacitor according to the present invention comprises a laminate including a plurality of laminated dielectric layers, the laminate having first and second main surfaces opposing each other in a lamination direction of the plurality of dielectric layers, first and second side surfaces opposing each other in a width direction perpendicular to the lamination direction, and first and second end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction; first internal electrode layers arranged on the plurality of dielectric layers and exposed at the first end surfaces; and second internal electrode layers arranged on the plurality of dielectric layers and exposed at the second end surfaces. The multilayer ceramic capacitor includes a first external electrode having a base electrode layer disposed on the first end face and a plating layer disposed on the base electrode layer, and a second external electrode having a base electrode layer disposed on the second end face and a plating layer disposed on the base electrode layer, wherein dielectric particles are disposed in the dielectric layer, the dielectric particles contain Mn and Zr, and the atomic ratio of Mn to Zr (Mn / Zr) in the dielectric particles is 0.60 or more and 0.80 or less.

[0007] According to the multilayer ceramic capacitor of the present invention, by configuring the dielectric particles so that the atomic ratio of Mn to Zr (Mn / Zr) is 0.60 or more and 0.80 or less, the amount of Mn dissolved inside the dielectric particles can be ensured and the amount of Mn segregated to the grain boundaries between the dielectric particles can be reduced, thereby increasing the insulation properties of the entire dielectric layer and improving the reliability of the multilayer ceramic capacitor.

[0008] According to the present invention, in the multilayer ceramic capacitor, the insulation properties of the entire dielectric layer are increased, and the reliability can be improved.

[0009] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0010] 1 is a perspective view showing an appearance of an example of a multilayer ceramic capacitor according to an embodiment of the present invention; 2 is a front view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; 3 is a plan view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 1; 5 is a schematic cross-sectional view taken along line V-V in FIG. 1; and 6 is a schematic cross-sectional view taken along line VI-VI in FIG. 4. (a) is a cross-sectional view showing a structure in which opposing electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into two, (b) is a cross-sectional view showing a structure in which opposing electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into three, and (c) is a cross-sectional view showing a structure in which opposing electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into four.

[0011] An example of a multilayer ceramic capacitor according to an embodiment of the present invention will now be described.

[0012] 1. Multilayer Ceramic Capacitor An example of a multilayer ceramic capacitor according to an embodiment of the present invention will be described. FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 3 is a plan view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4.

[0013] The multilayer ceramic capacitor 10 includes a laminate 12 and external electrodes 30. The laminate 12 is formed by alternately stacking a plurality of dielectric layers 14 and a plurality of internal electrode layers 16, and is composed of an internal layer portion 15a that exhibits capacitance, and a first external layer portion 15b1 and a second external layer portion 15b2 that are arranged to sandwich the internal layer portion 15a from the upper and lower main surfaces.

[0014] Hereinafter, the configuration of each of the laminate 12, the internal electrode layer 16, and the external electrode 30 will be described in that order.

[0015] (Laminate) The laminate 12 includes a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 16. The laminate 12 further includes a first main surface 12a and a second main surface 12b that face in a height direction x, which is the stacking direction of the plurality of dielectric layers 14; a first side surface 12c and a second side surface 12d that face in a width direction y that is perpendicular to the height direction x; and a first end surface 12e and a second end surface 12f that face in a length direction z that is perpendicular to the height direction x and the width direction y. The length direction z is also defined as the L direction, which is the direction connecting the first end surface 12e and the second end surface 12f. The width direction y is also defined as the W direction, which is the direction connecting the first side surface 12c and the second side surface 12d. The height direction x is also defined as the T direction, which is the direction connecting the first main surface 12a and the second main surface 12b.

[0016] The laminate 12 has a rectangular parallelepiped shape. The "rectangular parallelepiped shape" includes a rectangular parallelepiped with rounded corners and ridges. Note that a corner refers to a portion where three adjacent faces of the laminate 12 intersect, and a ridge refers to a portion where two adjacent faces of the laminate 12 intersect. In other words, a "rectangular parallelepiped" member refers to any member having a first main surface 12a and a second main surface 12b, a first side surface 12c and a second side surface 12d, and a first end surface 12e and a second end surface 12f.

[0017] The first and second main surfaces 12a and 12b, the first and second side surfaces 12c and 12d, and the first and second end surfaces 12e and 12f may have irregularities or the like formed on some or all of them.

[0018] Inside the laminate 12, a plurality of substantially rectangular first internal electrode layers 16a and second internal electrode layers 16b (described later) are alternately arranged at equal intervals along the thickness direction T. The first internal electrode layers 16a and second internal electrode layers 16b are substantially parallel to the first main surface 12a and the second main surface 12b, respectively. The first internal electrode layers 16a and second internal electrode layers 16b face each other in the thickness direction T with the dielectric layer 14 interposed therebetween.

[0019] As shown in Figures 4 and 5, the laminate 12 has, in the height direction x connecting the first main surface 12a and the second main surface 12b, an inner layer portion 15a in which a plurality of internal electrode layers 16 face each other, a first outer layer portion 15b1 formed from a plurality of dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 located closest to the first main surface 12a, and a second outer layer portion 15b2 formed from a plurality of dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 located closest to the second main surface 12b.

[0020] The first outer layer portion 15b1 is located on the first main surface 12a side of the laminate 12 and is an aggregate of multiple dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a.

[0021] The second outer layer portion 15b2 is located on the second main surface 12b side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b.

[0022] The region sandwiched between the first outer layer portion 15b1 and the second outer layer portion 15b2 is the inner layer portion 15a.

[0023] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 10 to 2000, including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of the dielectric layers 14 is preferably, for example, about 0.5 μm to 10 μm.

[0024] The ceramic material constituting the dielectric layer 14 may be, for example, a dielectric material. For example, a dielectric ceramic containing barium titanate (BaTiO3) as a main component may be used. Depending on the desired properties of the laminate, a material containing a minor component, such as a manganese compound, an iron compound, a chromium compound, a cobalt compound, or a nickel compound, in a smaller amount than the main component may be used.

[0025] Furthermore, dielectric particles are disposed in the dielectric layer 14, and the dielectric particles contain at least Mn and Zr, and it is preferable that the atomic ratio of Mn to Zr (Mn / Zr) in the dielectric particles is 0.60 or more and 0.80 or less. Generally, if Mn segregation occurs at the grain boundaries of the dielectric particles, the Mn-segregated layer has a lower resistance than the ceramic, and the reliability (HALT (Highly Accelerated Life Test)) of the multilayer ceramic capacitor 10 decreases. However, by adopting the above-mentioned configuration, the amount of Mn solid solution inside the dielectric particles can be guaranteed and the amount of Mn segregation to the grain boundaries between the dielectric particles can be reduced, thereby improving the reliability (HALT) of the multilayer ceramic capacitor 10.

[0026] If the atomic ratio (Mn / Zr) is 0.60 or less, the reliability (HALT) of the multilayer ceramic capacitor 10 decreases. If the atomic ratio (Mn / Zr) is 0.80 or more, a large amount of heat is applied when attempting to dissolve Mn in the grains, resulting in a decrease in the coverage of the internal electrode layers 16.

[0027] The dielectric particles in the dielectric layer 14 have a perovskite structure containing Ba, Sr, Zr, Ti, and Hf, and preferably contains at least one of Mn and Si. Selecting the above materials and composition has the advantage of ensuring good temperature characteristics.

[0028] The dielectric layer 14 preferably further contains at least La. With this configuration, La dissolves in the A site of the dielectric material, causing lattice distortion and increasing the amount of Mn dissolved in the B site of the dielectric material. As a result, the dissolution of Mn in the dielectric particles is further promoted, further improving the reliability (HALT) of the multilayer ceramic capacitor 10.

[0029] The La content is more preferably 0.3 mol or more and 1.0 mol or less. If the La content is less than 0.3 mol, the effect of improving the (HALT) of the multilayer ceramic capacitor 10 decreases. If the La content is more than 1.0 mol, the temperature characteristics deteriorate.

[0030] It is more preferable that the dielectric layer 14 has (number of moles of Ba+number of moles of Ca+number of moles of Sr+number of moles of La) / (number of moles of Zr+number of moles of Ti+number of moles of Hf) of 1.00 or more and 1.03 or less.

[0031] Here, the method for measuring the atomic ratio (Mn / Zr) will be explained. Mapping is performed by TEM analysis (TEM: Transmission Electron Microscope). The sample for TEM analysis is a thin specimen cut out using a Ga ion beam. Quantitative point analysis of the ceramic grains and grain boundaries is performed on the thinned sample using TEM-EDX (EDX: Energy Dispersive X-ray Spectroscopy). The atomic percentages of Mn and Zr calculated as an average of five points per grain boundary are then averaged over three grain boundaries to calculate the atomic ratio (Mn / Zr).

[0032] Furthermore, the method for measuring the La content will be explained. The La content is measured by pretreating a dielectric sample to form a solution, and then analyzing the amount of La contained in the sample using ICP-MS (inductively coupled plasma mass spectrometry). The La content is calculated relative to the total content using an average of n=2.

[0033] (Internal Electrode Layers) As shown in Figures 4 and 5, the internal electrode layers 16 include first internal electrode layers 16a and second internal electrode layers 16b. The first internal electrode layers 16a and the second internal electrode layers 16b are alternately stacked with the dielectric layers 14 interposed therebetween.

[0034] The first internal electrode layer 16a is disposed on the surface of the dielectric layer 14. The first internal electrode layer 16a has a first opposing electrode portion 18a facing the second internal electrode layer 16b, and a first lead electrode portion 20a located on one end side of the first internal electrode layer 16a and extending from the first opposing electrode portion 18a to the first end face 12e of the laminate 12. The end of the first lead electrode portion 20a is extended and exposed at the first end face 12e. Specifically, the end of the first lead electrode portion 20a is slightly recessed from the first end face 12e. The first lead electrode portion 20a is not exposed at the first principal surface 12a, the second principal surface 12b, or the first side face 12c, the second side face 12d.

[0035] The shape of the first opposing electrode portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view, although the corners in plan view may be rounded or may be formed obliquely (tapered) in plan view.

[0036] The shape of the first lead electrode portion 20a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first lead electrode portion 20a may be tapered in plan view, with a slope increasing in either direction.

[0037] The second internal electrode layer 16b is disposed on a surface of a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is disposed. The second internal electrode layer 16b has a second opposing electrode portion 18b facing the first internal electrode layer 16a, and a second extraction electrode portion 20b located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to the second end face 12f of the laminate 12. The end of the second extraction electrode portion 20b is extended and exposed at the second end face 12f. Specifically, the end of the second extraction electrode portion 20b is slightly recessed from the second end face 12f. The second extraction electrode portion 20b is not exposed at the first principal surface 12a, the second principal surface 12b, the first side face 12c, and the second side face 12d.

[0038] The shape of the second opposing electrode portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view, although the corners in plan view may be rounded or may be formed obliquely (tapered) in plan view.

[0039] The shape of the second extraction electrode portion 20b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second extraction electrode portion 20b may be tapered in plan view, with a slope increasing in either direction.

[0040] The laminate 12 includes side portions (hereinafter referred to as "W gaps") 22a of the laminate 12 formed between one ends of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the width direction y and the first side surface 12c, and between the other ends of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the width direction y and the second side surface 12d. Furthermore, the laminate 12 includes end portions (hereinafter referred to as "L gaps") 22b of the laminate 12 formed between an end of the first internal electrode layer 16a opposite to the first extraction electrode portion 20a and the second end surface 12f, and between an end of the second internal electrode layer 16b opposite to the second extraction electrode portion 20b and the first end surface 12e.

[0041] The number of stacked internal electrode layers 16 is not particularly limited, but is preferably 10 to 2000. The thickness of the internal electrode layers 16 is preferably about 0.2 μm to 2.0 μm.

[0042] The internal electrode layers 16 can be made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. The metal constituting the internal electrode layers 16 forms a compound with the metal constituting the conductive filler contained in the conductive resin layer of the external electrode 30, which will be described later.

[0043] The thickness of each of the first internal electrode layer 16a and the second internal electrode layer 16b is preferably, for example, about 0.2 μm or more and 2.0 μm or less.

[0044] As shown in FIG. 7 , the laminate 12 may have, in addition to the first internal electrode layer 16 a and the second internal electrode layer 16 b, a floating internal electrode layer 16 c that is not extended to either the first end face 12 e or the second end face 12 f. The floating internal electrode layer 16 c may divide the opposing electrode portion 26 c into multiple portions. For example, the structure may be a two-part structure as shown in FIG. 7 ( a ), a three-part structure as shown in FIG. 7 ( b ), or a four-part structure as shown in FIG. 7 ( c ), or of course, a structure with more than four parts. By dividing the opposing electrode portion 26 c into multiple portions, multiple capacitor components are formed between the opposing first internal electrode layer 16 a, the second internal electrode layer 16 b, and the floating internal electrode layer 16 c, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component is reduced, thereby increasing the withstand voltage of the multilayer ceramic capacitor 10.

[0045] Furthermore, like the first internal electrode layer 16a and the second internal electrode layer 16b, the floating internal electrode layer 16c can be made of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0046] As shown in FIGS. 1 to 3, external electrodes 30 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0047] The external electrode 30 preferably includes a base electrode layer 32 containing a metal component and glass, and a plating layer 34 disposed on the surface of the base electrode layer 32 .

[0048] The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0049] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed on at least the surface of the first end face 12e. The first external electrode 30a also extends from the first end face 12e of the laminate 12 and is disposed on part of the first main face 12a, part of the second main face 12b, and part of the first side face 12c, part of the second side face 12d. In this case, the first external electrode 30a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.

[0050] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed on at least the surface of the second end face 12f. The second external electrode 30b also extends from the second end face 12f of the laminate 12 and is disposed on part of the first main surface 12a, part of the second main surface 12b, and part of the first side surface 12c, and part of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

[0051] Within the laminate 12, capacitance is formed by the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b opposing each other via the dielectric layer 14. Therefore, capacitance can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, and the characteristics of a capacitor are exhibited.

[0052] The base electrode layer 32 includes a first base electrode layer 32a and a second base electrode layer 32b.

[0053] The first base electrode layer 32a is connected to the first internal electrode layer 16a and is disposed on the surface of the first end face 12e. The first base electrode layer 32a also extends from the first end face 12e and is disposed on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.

[0054] The second base electrode layer 32b is connected to the second internal electrode layer 16b and is disposed on the surface of the second end face 12f. The second base electrode layer 32b also extends from the second end face 12f and is disposed on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

[0055] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0056] Hereinafter, each of the configurations when the base electrode layer 32 is the baked layer, the conductive resin layer, and the thin film layer will be described.

[0057] (In the case of a baking layer) The baking layer contains a metal component and glass. The metal component of the baking layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The baking layer is formed by applying a conductive paste containing glass and a metal to the laminate and baking it. The baking layer is formed by simultaneously baking a laminated chip having internal electrode layers 16 and dielectric layers 14 and the conductive paste applied to the laminated chip, but may also be baked after baking the laminated chip having internal electrode layers 16 and dielectric layers 14. The baking layer may be a multi-layered layer.

[0058] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f at the center in the height direction x of the first base electrode layer 32a located on the first end face 12e is preferably, for example, approximately 10 μm or more and 150 μm or less.

[0059] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f at the center in the height direction x of the second base electrode layer 32b located on the second end face 12f is preferably, for example, approximately 10 μm or more and 150 μm or less.

[0060] The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z connecting the first end face 12e and the second end face 12f of the first base electrode layer 32a located on part of the first main surface 12a and the second main surface 12b is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0061] Furthermore, the thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z connecting the first end face 12e and the second end face 12f of the second base electrode layer 32b located on part of the first main surface 12a and the second main surface 12b is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0062] The thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end face 12e and the second end face 12f of the first base electrode layer 32a located on part of the first side surface 12c and the second side surface 12d is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0063] Furthermore, it is preferable that the thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end face 12e and the second end face 12f of the second base electrode layer 32b located on part of the first side surface 12c and the second side surface 12d is, for example, approximately 10 μm or more and 100 μm or less.

[0064] (Conductive Resin Layer) The conductive resin layer has a first conductive resin layer and a second conductive resin layer.

[0065] The first conductive resin layer is preferably arranged as a first base electrode layer 32a so as to further cover other layers such as a baked layer, and the second conductive resin layer is preferably arranged as a second base electrode layer 32b so as to further cover other layers such as a baked layer.

[0066] Specifically, the first and second conductive resin layers, as the first and second base electrode layers 32a and 32b, are preferably disposed on other layers, such as baked layers, located on the first and second end faces 12e and 12f, and extend to the first and second main faces 12a and 12b and the first and second side faces 12c and 12d, respectively. However, the first and second conductive resin layers may be disposed only on the other layers, such as baked layers, located on the first and second end faces 12e and 12f.

[0067] The thickness of the first conductive resin layer and the second conductive resin layer is preferably, for example, about 10 μm or more and 200 μm or less.

[0068] The first conductive resin layer and the second conductive resin layer contain a thermosetting resin and a metal component.

[0069] Because the first conductive resin layer and the second conductive resin layer contain a thermosetting resin, they are more flexible than the base electrode layer 32 made of, for example, a plating film or a fired product of a conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0070] Specific examples of the thermosetting resin include various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0071] The first conductive resin layer and the second conductive resin layer preferably contain a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based compounds can be used as the curing agent for the epoxy resin.

[0072] The metal contained in the first conductive resin layer and the second conductive resin layer may be Ag, Cu, or an alloy thereof. Alternatively, a metal powder having an Ag-coated surface may be used. When using a metal powder having an Ag-coated surface, it is preferable to use Cu or Ni as the metal powder.

[0073] Alternatively, Cu that has been treated to prevent oxidation can also be used. The reason for using Ag-coated metal is that it allows the base metal to be inexpensive while maintaining the above-mentioned properties of Ag.

[0074] The metal contained in the first conductive resin layer and the second conductive resin layer is preferably contained in an amount of 35 vol % or more and 75 vol % or less with respect to the volume of the entire conductive resin.

[0075] The shape of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited, and the conductive filler may be spherical, flat, or the like.

[0076] The average particle size of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, about 0.3 μm or more and 10 μm or less.

[0077] The metals contained in the first conductive resin layer and the second conductive resin layer are mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, contact between the conductive fillers forms an electrical path inside the conductive resin layer.

[0078] The metal contained in the first conductive resin layer and the second conductive resin layer may be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0079] The first conductive resin layer and the second conductive resin layer may each include a resin layer containing conductive particles and a thermosetting resin.

[0080] The conductive resin layer may be formed directly on the laminate without forming a baked layer.

[0081] (In the case of a thin film layer) When the base electrode layer 32 is formed as a thin film layer, the thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 10 μm or less in thickness on which metal particles are deposited.

[0082] Next, the first plating layer 34a and the second plating layer 34b, which are the plating layers 34 disposed on the base electrode layer 32, will be described with reference to FIGS.

[0083] The first plating layer 34a and the second plating layer 34b contain, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag--Pd alloy, Au, and the like.

[0084] The first plating layer 34a is disposed so as to completely cover the first base electrode layer 32a, and the second plating layer 34b is disposed so as to completely cover the second base electrode layer 32b.

[0085] The first plating layer 34a and the second plating layer 34b may be formed of multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of a lower plating layer (Ni plating layer) formed on the base electrode layer 32 by Ni plating and an upper plating layer (Sn plating layer) formed on the lower plating layer by Sn plating. That is, in this case, the first plating layer 34a has a first lower plating layer and a first upper plating layer located on the surface of the first lower plating layer. Furthermore, the second plating layer 34b has a second lower plating layer and a second upper plating layer located on the surface of the second lower plating layer.

[0086] The lower plating layer made of Ni plating is used to prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer made of Sn plating is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, making it easier to mount.

[0087] The thickness of each of the lower plating layer and the upper plating layer is preferably 1.0 μm or more and 15.0 μm or less.

[0088] 1 , the length direction z of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as L dimension, the height direction x of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as T dimension, and the width direction y of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as W dimension. The dimensions of the multilayer ceramic capacitor 10 are preferably such that the length direction z L dimension is 0.2 mm to 10.0 mm, the width direction y W dimension is 0.1 mm to 10.0 mm, and the height direction x T dimension is 0.1 mm to 5.0 mm. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0089] Furthermore, in the multilayer ceramic capacitor 10, the dielectric particles preferably have a relative dielectric constant of 30 or more. This makes it possible to more significantly reduce the displacement of the dielectric layers 14 in the multilayer ceramic capacitor 10 when a voltage is applied.

[0090] According to the multilayer ceramic capacitor 10, by configuring the dielectric particles so that the atomic ratio of Mn to Zr (Mn / Zr) is 0.60 or more and 0.80 or less, the amount of Mn dissolved in the dielectric particles can be ensured and the amount of Mn segregated to the grain boundaries between the dielectric particles can be reduced, thereby increasing the insulation properties of the entire dielectric layer and improving the reliability of the multilayer ceramic capacitor.

[0091] 2. Method for Manufacturing a Multilayer Ceramic Capacitor Next, a method for manufacturing a multilayer ceramic capacitor will be described.

[0092] (1) Prepare a dielectric sheet and a conductive paste for the internal electrode layers. The dielectric sheet and the conductive paste for the internal electrode layers contain a binder (for example, a known organic binder) and a solvent (for example, a known organic binder).

[0093] (2) Next, a conductive paste for the internal electrode layers is printed in a predetermined pattern on the dielectric sheets by, for example, screen printing or gravure printing, to prepare a dielectric sheet on which a first internal electrode pattern corresponding to the first internal electrode layer is formed and a dielectric sheet on which a second internal electrode pattern corresponding to the second internal electrode layer is formed. Note that, with regard to the dielectric sheets, a dielectric sheet for an outer layer on which no internal electrode pattern is printed is also prepared.

[0094] (3) A predetermined number of dielectric sheets for outer layers on which no internal electrode pattern is formed are stacked to form a portion that will become a second outer layer portion, and a dielectric sheet on which a first internal electrode pattern is formed and a dielectric sheet on which a second internal electrode pattern is formed are stacked in this order on top of that to form a portion that will become an inner layer portion.

[0095] (4) Furthermore, a predetermined number of dielectric sheets on which no internal electrode pattern is printed are stacked on top of the internal electrode pattern corresponding to the internal electrode layer located on the outermost surface of the inner layer portion to form a portion that will become the first outer layer portion, thereby producing a laminated sheet.

[0096] (5) The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0097] (6) The laminated block is cut to a predetermined size to cut out laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like. These are the steps for preparing a laminate.

[0098] (7) The laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and the materials of the internal electrode layers 16, but is preferably 900° C. or higher and 1400° C. or lower.

[0099] (8) Subsequently, the base electrode layer is formed. The base electrode layer is a baked layer. A conductive paste containing a glass component and a metal component is prepared for each of the first base electrode layer and the second base electrode layer.

[0100] (9) A conductive paste is applied to the first end face and the second end face of the laminate 12 by, for example, dipping or screen printing, and then a baking process is performed to form the first and second base electrode layers. The baking temperature is preferably 700° C. or higher and 900° C. or lower.

[0101] (10) When the base electrode layer is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of the baked layer, or the conductive resin layer may be formed directly on the laminate without forming a baked layer.

[0102] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate, followed by heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form the conductive resin layer. The heat treatment is preferably performed in a N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0103] The conductive resin paste can be applied by, for example, a method of applying the conductive resin paste by extruding it through a slit or a roller transfer method.

[0104] (11) If necessary, plating is applied to the surface of the base electrode layer to form a plating layer. In this embodiment, two plating layers are formed on the surfaces of the first and second base electrode layers. Specifically, a Ni plating layer is formed on the first and second base electrode layers, and a Sn plating layer is formed on the Ni plating layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0105] Here, we will explain the manufacturing method characterized by the present invention, in which "in the dielectric particles, the atomic ratio of Mn to Zr (Mn / Zr) is 0.60 or more and 0.80 or less," and the manufacturing method in which "the dielectric layer further contains at least La, and the La content is 0.3 mol or more and 1.0 mol or less." La may be added when the dielectric raw material is prepared, or it may be added later when the dielectric sheet is prepared. When La enters the A site, Mn becomes more likely to enter the B site, and the atomic ratio of Mn to Zr (Mn / Zr) in the dielectric particles changes.

[0106] In this manner, the multilayer ceramic capacitor 10 according to the embodiment shown in FIG. 1 is manufactured.

[0107] 3. Experimental Example Next, in order to confirm the effect of the multilayer ceramic capacitor according to the present invention described above, multilayer ceramic capacitors were fabricated as experimental samples according to the above-described manufacturing method, with the atomic ratio of Mn to Zr (Mn / Zr) being varied. HALT and the coverage (%) of the internal electrode layers were measured, and an experiment was conducted to confirm the reliability of the multilayer ceramic capacitors.

[0108] (1) Specifications of the Multilayer Ceramic Capacitors Produced as Examples Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors were produced as samples of Examples 1 to 3. Dimensions of the multilayer ceramic capacitor (design values): L x W x T = 1.68 mm x 0.87 mm x 0.88 mm Ceramic material: SrBaZrO3 + La Capacitance: 100 nF Material of the internal electrode layer: Ni

[0109] (2) Specifications of the Multilayer Ceramic Capacitor Fabricated as Comparative Examples Multilayer ceramic capacitors serving as samples of Comparative Example 1 and Comparative Example 2 were fabricated using the manufacturing method according to the above embodiment. Comparative Example 1 was fabricated using manufacturing method (1) without adding La. Comparative Example 2 was fabricated using manufacturing method (1) with La added, and then using manufacturing method (7) by maintaining the capacitor at high temperature in a low-oxygen atmosphere for 2 hours. Dimensions of the multilayer ceramic capacitor (design values): L x W x T = 1.68 mm x 0.87 mm x 0.88 mm Ceramic material: SrBaZrO3 Capacitance: 100 nF Material of internal electrode layer: Ni Specifications other than those described above were the same as those of the samples of the examples.

[0110] (3) HALT Measurement Method In the HALT test, each sample was individually set in a dedicated jig, placed in a high-temperature chamber at 150°C, and a direct current of 100V was applied between a pair of external electrodes, and this state was maintained for 100 hours. After the test, samples with a LogIR value of 10 or more were evaluated as "Good", samples with a LogIR value of more than the 8th power but less than the 10th power were evaluated as "Good", and samples with a LogIR value of 8 or less were evaluated as "Poor".

[0111] (4) Method for measuring the coverage (%) of the internal electrode layer The method for measuring the coverage of the first internal electrode layer and the second internal electrode layer located in the center of the laminate in the T direction with respect to the dielectric layer is as follows. First, the internal electrode layer and the dielectric layer located in the center of the laminate in the T direction are peeled off by electrolytic peeling or the like. Next, the vicinity of the center of the exposed internal electrode (position 1 / 2 in the W direction and 1 / 2 in the L direction) is observed using a microscope at a magnification of about 100x. Then, by analyzing the obtained image, the proportion of the area occupied by the internal electrode layer in the exposed part was determined. A coverage of the internal electrode layer of 80.0% or more was judged as "Good", and one less than 80% was judged as "Poor".

[0112] (5) Overall Judgment If both the HALT judgment and the internal electrode layer coverage rate (%) judgment were "Good", the overall judgment was "Good", and if either one was "Good" or "Poor", the overall judgment was "Poor".

[0113] (6) Results Table 1 shows the results of HALT (LogIR value), HALT judgment, coverage rate (%) of the internal electrode layer, coverage rate judgment of the internal electrode layer, and overall judgment for each sample of the multilayer ceramic capacitors according to Examples 1 to 3 and Comparative Examples 1 and 2.

[0114]

[0115] According to Table 1, the samples of Examples 1 to 3 each had a HALT LogIR value of 10 or more, and were therefore given a HALT rating of "good."

[0116] In addition, in each of the samples of Examples 1 to 3, the coverage (%) of the internal electrode layers was 80% or more, and therefore the coverage of the internal electrode layers was judged as "good."

[0117] On the other hand, in the sample according to Comparative Example 1, the HALT LogIR value was 8 or less, so the HALT judgment was judged as "x". In addition, since the coverage rate (%) of the internal electrode layer was 80% or more, the coverage rate judgment of the internal electrode layer was judged as "o".

[0118] In the sample according to Comparative Example 1, the HALT LogIR value was between 8 and 10, so the HALT judgment was judged as "△". Furthermore, the coverage rate (%) of the internal electrode layer was less than 80%, so the coverage rate judgment of the internal electrode layer was judged as "X".

[0119] Therefore, in the overall evaluation, each of the samples of Examples 1 to 3 was evaluated as "good", and each of the samples of Comparative Examples 1 and 2 was evaluated as "poor".

[0120] From the above results, it has been suggested that in this invention, by configuring the dielectric particles so that the atomic ratio of Mn to Zr (Mn / Zr) is 0.60 or more and 0.80 or less, the amount of Mn dissolved inside the dielectric particles can be ensured, the amount of Mn segregated to the grain boundaries between the dielectric particles can be reduced, the insulation properties of the entire dielectric layer can be increased, and the reliability of the multilayer ceramic capacitor can be improved.

[0121] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this.

[0122] In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0123] REFERENCE SIGNS LIST 10 Multilayer ceramic capacitor 12 Laminate 12a First main surface 12b Second main surface 12c First side surface 12d Second side surface 12e First end surface 12f Second end surface 14 Dielectric layer 15a Inner layer portion 15b1 First outer layer portion 15b2 Second outer layer portion 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 16c Floating internal electrode layer 18a First opposing electrode portion 18b Second opposing electrode portion 20a First lead electrode portion 20b Second lead electrode portion 22a Side portion 22b End portion 26c Counter electrode portion 30 External electrode 30a First external electrode 30b Second external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 34 plating layer 34a first plating layer 34b second plating layer x height direction (stacking direction) y width direction z length direction

Claims

1. A laminate including a plurality of stacked dielectric layers, having a first main surface and a second main surface facing each other in the stacking direction of the plurality of dielectric layers, a first side surface and a second side surface facing each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface facing each other in a length direction orthogonal to the stacking direction and the width direction; a first internal electrode layer disposed on the plurality of dielectric layers and exposed on the first end surface; a second internal electrode layer disposed on the plurality of dielectric layers and exposed on the second end surface; a first external electrode having a base electrode layer disposed on the first end surface and a plating layer disposed on the base electrode layer; and a second external electrode having a base electrode layer disposed on the second end surface and a plating layer disposed on the base electrode layer. In the multilayer ceramic capacitor, dielectric particles are disposed in the dielectric layer, the dielectric particles contain Mn and Zr, and an atomic ratio (Mn / Zr) of Mn to Zr in the dielectric particles is 0.60 or more and 0.80 or less.

2. The multilayer ceramic capacitor according to claim 1, wherein the dielectric particles in the dielectric layer further include Ba, Sr, Zr, Ti, Hf, optionally include Ca, have a perovskite structure, and further include at least one of Mn and Si.

Images