Multilayer ceramic electronic component

Abstract

The present invention provides a highly reliable multilayer ceramic electronic component in which it is possible to suppress the occurrence of a crack in a laminate of the multilayer ceramic electronic component.　This multilayer ceramic capacitor 1 includes an external electrode 40 which has, from the lower side, a first external electrode 40A that comprises a first base electrode layer 50A, a first organic layer 70A, and a first plating layer 60A, and a second external electrode 40B that comprises a second base electrode layer 50B, a second organic layer 70B, and a second plating layer 60B. In the length direction, the first dimension EL1 of the first base electrode layer is larger than the second dimension EL2 of the second base electrode layer, a part of the first base electrode layer 50A is exposed on the surface of the first organic layer 70A, a part of the second base electrode layer 50B is exposed on the surface of the second organic layer 70B, and the first atomic percentage MR1 of the main component metal of the first base electrode layer 50A on the surface of the first organic layer 70A is larger than the second atomic percentage MR2 of the main component metal of the second base electrode layer 50B on the surface of the second organic layer 70B.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] Multilayer ceramic capacitors have been known as multilayer ceramic electronic components. Generally, multilayer ceramic capacitors include a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes connected to the internal electrode layers and provided on both end surfaces of the laminate. For example, Patent Document 1 discloses a multilayer ceramic capacitor having the above-described structure, in which terminal electrodes serving as external electrodes are made of a metal component and an inorganic binder, and in which a plurality of voids are formed therein.

[0003] Japanese Patent Application Publication No. 5-3132

[0004] The multilayer ceramic capacitor of Patent Document 1 has terminal electrodes with voids. This reduces external stress and suppresses the occurrence of cracks inside the capacitor. This improves the reliability of the multilayer ceramic capacitor. However, in recent years, higher reliability has been required, and further measures are needed.

[0005] An object of the present invention is to provide a highly reliable multilayer ceramic electronic component that is capable of suppressing cracks from occurring in the laminates of the multilayer ceramic electronic component.

[0006] A multilayer ceramic electronic component according to the present invention comprises a laminate including a plurality of ceramic layers and a plurality of internal conductor layers stacked alternately, and having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height direction and the width direction; and external electrodes connected to the internal conductor layers, the external electrodes having a first external electrode arranged on the first end surface and a second external electrode arranged on the second end surface, The first external electrode has a first base electrode layer disposed on the first end face, a first organic layer disposed on the first base electrode layer, and a first plating layer disposed on the first organic layer. The second external electrode has a second base electrode layer disposed on the second end face, a second organic layer disposed on the second base electrode layer, and a second plating layer disposed on the second organic layer. The first base electrode layer is disposed to extend from the first end face to a portion of the first main surface and a portion of the second main surface. a first dimension is a lengthwise dimension of the first base electrode layer, which is disposed extending from the first end face of the laminate to the first main surface and a portion of the second main surface, to an end on the side of the second end face; and a second dimension is a lengthwise dimension of the second base electrode layer, which is disposed extending from the second end face of the laminate to the first main surface and a portion of the second main surface, to an end on the side of the first end face; the first dimension is larger than the second dimension. a surface of the first organic layer is formed as a surface where a part of the first base electrode layer is exposed, and a surface of the second organic layer is formed as a surface where a part of the second base electrode layer is exposed, and when an atomic percentage of a main component metal of the first base electrode layer on the surface of the first organic layer arranged on the first main surface side and the second main surface side is defined as a first atomic percentage, and an atomic percentage of a main component metal of the second base electrode layer on the surface of the second organic layer arranged on the first main surface side and the second main surface side is defined as a second atomic percentage, the first atomic percentage isgreater than the second atomic percentage.

[0007] According to the present invention, it is possible to provide a highly reliable multilayer ceramic electronic component that is capable of suppressing cracks from occurring in the laminate of the multilayer ceramic electronic component.

[0008] 1 is an external perspective view of the multilayer ceramic capacitor according to the first embodiment. FIG. 1 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 2 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 3 is a cross-sectional view taken along line IVA-IVA in FIG. 2. FIG. 4 is a cross-sectional view taken along line IVB-IVB in FIG. 2. FIG. 4 is an enlarged cross-sectional view of a portion indicated by R1 in FIG. 2. FIG. 4 is an enlarged cross-sectional view of a portion indicated by R2 in FIG. 2. FIG. 5 is a diagram illustrating a multilayer ceramic capacitor with a double structure. FIG. 6 is a diagram illustrating a multilayer ceramic capacitor with a triple structure. FIG. 7 is a diagram illustrating a multilayer ceramic capacitor with a quadruple structure. FIG. 6 is a cross-sectional view corresponding to FIG. 2 in the second embodiment. FIG. 7 is a cross-sectional view corresponding to FIG. 4A in the second embodiment. FIG. 7 is a cross-sectional view corresponding to FIG. 4B in the second embodiment.

[0009] First Embodiment A multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to a first embodiment of the present disclosure will now be described with reference to FIGS. 1 to 5B. FIG. 1 is an external perspective view of the multilayer ceramic capacitor 1 according to the first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4A is a cross-sectional view taken along line IVA-IVA in FIG. 2. FIG. 4B is a cross-sectional view taken along line IVB-IVB in FIG. 2. FIG. 5A is an enlarged cross-sectional view of a portion indicated by R1 in FIG. 2. FIG. 5B is an enlarged cross-sectional view of a portion indicated by R2 in FIG. 2.

[0010] 1, the multilayer ceramic capacitor 1 according to the first embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 10 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at opposite ends of the laminate 10 while being spaced apart from each other.

[0011] In Fig. 1, an arrow T indicates the height direction of the multilayer ceramic capacitor 1 and the laminate 10. This height direction T is also the thickness direction and lamination direction of the multilayer ceramic capacitor 1 and the laminate 10. In Fig. 1, an arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the height direction T. In Fig. 1, an arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the height direction T and the length direction L. A pair of external electrodes 40 is disposed at one end and the other end of the length direction L of the laminate 10, respectively.

[0012] 1 to 4B show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The height direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as an LT cross section. The cross section shown in FIG. 3 is also referred to as a WT cross section. The cross sections shown in FIGS. 4A and 4B are also referred to as LW cross sections.

[0013] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in a height direction T, a first end surface LS1 and a second end surface LS2 that face each other in a length direction L that is perpendicular to the height direction T, and a first side surface WS1 and a second side surface WS2 that face each other in a width direction W that is perpendicular to the height direction T and the length direction L.

[0014] As shown in FIG. 1 , the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, unevenness may be formed on part or all of the surfaces constituting the laminate 10.

[0015] The dimensions of the laminate 10 are not particularly limited, but if the dimension in the length direction L of the laminate 10 is defined as the L dimension, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the dimension in the height direction T of the laminate 10 is defined as the T dimension, then the T dimension is preferably 0.1 mm or more and 10 mm or less. If the dimension in the width direction W of the laminate 10 is defined as the W dimension, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0016] As shown in Figures 2 and 3, the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the height direction T.

[0017] The internal layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers alternately stacked in the height direction T, and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The internal layer portion 11 includes, in the height direction T, the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2. In the internal layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The internal layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0018] The plurality of dielectric layers 20 are made of a dielectric material, such as BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ The dielectric material may be a dielectric ceramic containing components such as BaTiO as the main component. The dielectric material may also be a material containing these main components to which subcomponents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds are added. The dielectric material may be a material containing BaTiO as the main component. ３ It is particularly preferred that the material contains:

[0019] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 15 μm or less. The number of laminated dielectric layers 20 is preferably 10 or more and 700 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers 20 in the inner layer portion 11 and the number of the dielectric layers 20 in each of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0020] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 as multiple first internal conductor layers and multiple second internal electrode layers 32 as multiple second internal conductor layers. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the height direction T with the dielectric layer 20 sandwiched therebetween. The first internal electrode layers 31 are extended to the first end face LS1. The second internal electrode layers 32 are extended to the second end face LS2. Note that, hereinafter, when it is not necessary to distinguish between the first internal electrode layers 31 and the second internal electrode layers 32, the first internal electrode layers 31 and the second internal electrode layers 32 may be collectively referred to as the internal electrode layers 30.

[0021] 4A , the first internal electrode layer 31 has a first opposing portion 31A and a first lead portion 31B. The first opposing portion 31A is a region facing the second internal electrode layer 32 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The first lead portion 31B is a portion that extends from the first opposing portion 31A to the first end face LS1 and is exposed at the first end face LS1.

[0022] 4B , the second internal electrode layer 32 has a second opposing portion 32A and a second lead portion 32B. The second opposing portion 32A is a region facing the first internal electrode layer 31 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The second lead portion 32B is a portion that extends from the second opposing portion 32A to the second end face LS2 and is exposed at the second end face LS2.

[0023] In this embodiment, the first opposing portion 31A and the second opposing portion 32A face each other with the dielectric layer 20 interposed therebetween, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0024] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first lead portion 31B and the second lead portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.

[0025] The dimension in the width direction W of the first opposing portion 31A and the dimension in the width direction W of the first lead portion 31B may be the same dimension, or one of the dimensions may be smaller. The dimension in the width direction W of the second opposing portion 32A and the dimension in the width direction W of the second lead portion 32B may be the same dimension, or one of the dimensions may be smaller.

[0026] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0027] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 10 or more and 700 or less.

[0028] 2 and 3 , the first main surface side outer layer portion 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may both be the same as the dielectric layers 20 used in the internal layer portion 11.

[0029] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. Figures 4A and 4B show the range of the counter electrode portion 11E in the width direction W and length direction L. The counter electrode portion 11E is also referred to as the effective portion of the capacitor.

[0030] The laminate 10 has a side surface outer layer portion. The side surface outer layer portion includes a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2. The first side surface outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side surface WS1. The second side surface outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side surface WS2. Figures 3, 4A, and 4B show the ranges in the width direction W of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2. The side surface outer layer portion is also referred to as a W gap or a side gap.

[0031] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion includes a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion located between the counter electrode portion 11E and the first end face LS1 and including the dielectric layer 20 and the first lead portion 31B. That is, the first end surface side outer layer portion LG1 is an assembly of the portions of the plurality of dielectric layers 20 on the first end face LS1 side and the plurality of first lead portions 31B. The second end surface side outer layer portion LG2 is a portion located between the counter electrode portion 11E and the second end face LS2 and including the dielectric layer 20 and the second lead portion 32B. That is, the second end surface side outer layer portion LG2 is an assembly of the portions of the plurality of dielectric layers 20 on the second end face LS2 side and the plurality of second lead portions 32B. 2, 4A, and 4B show the range of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the length direction L. The end surface side outer layer portions are also called L gaps or end gaps.

[0032] As shown in Figures 1 and 2, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0033] The first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B have shapes that are approximately plane-symmetric with respect to a WT cross section at the center in the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40.

[0034] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is in contact with the first lead portions 31B of each of the first internal electrode layers 31 exposed at the first end face LS1. This electrically connects the first external electrode 40A to the first internal electrode layers 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is in contact with the second lead portions 32B of each of the second internal electrode layers 32 exposed at the second end face LS2. This electrically connects the second external electrode 40B to the second internal electrode layers 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0036] As described above, in the laminate 10, capacitance is formed by the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 facing each other via the dielectric layer 20. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0037] 2, 4A, and 4B, the first external electrode 40A has a first base electrode layer 50A, a first organic layer 70A disposed on the first base electrode layer 50A, and a first plating layer 60A disposed on the first organic layer 70A. The second external electrode 40B has a second base electrode layer 50B, a second organic layer 70B disposed on the second base electrode layer 50B, and a second plating layer 60B disposed on the second organic layer 70B.

[0038] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first lead portions 31B of each of the first internal electrode layers 31 exposed at the first end face LS1. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0039] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with the second lead portions 32B of each of the second internal electrode layers 32 exposed at the second end face LS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0040] In this embodiment, the area of ​​the first main surface TS1 and the second main surface TS2 of the laminate 10 covered by the first base electrode layer 50A is larger than the area of ​​the first main surface TS1 and the second main surface TS2 of the laminate 10 covered by the second base electrode layer 50B.

[0041] 1 and 2, the first dimension EL1 of the first base electrode layer 50A is larger than the second dimension EL2 of the second base electrode layer 50B. The first dimension EL1 is the dimension in the length direction L from the first end surface LS1 of the laminate 10 to the end of the first base electrode layer 50A on the second end surface LS2 side, the first base electrode layer 50A extending to the first main surface TS1 and a portion of the second main surface TS2. The second dimension EL2 is the dimension in the length direction L from the second end surface LS2 of the laminate 10 to the end of the second base electrode layer 50B on the first end surface LS1 side, the second base electrode layer 50B extending to the first main surface TS1 and a portion of the second main surface TS2.

[0042] When the first dimension EL1 is larger than the second dimension, the effects of the present disclosure can be obtained even if the first dimension EL1 is less than 1.1 times the second dimension EL2. However, it is preferable that the first dimension EL1 be 1.1 times or more the second dimension EL2. This makes it possible to obtain the effects of the present disclosure more effectively. It is more preferable that the first dimension EL1 be 1.3 times or more. In this case, the effects of the present disclosure can be obtained even more effectively.

[0043] The first underlying electrode layer 50A and the second underlying electrode layer 50B include at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0044] The first base electrode layer 50A and the second base electrode layer 50B of this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as that of the dielectric layer 20, or a different type of ceramic material. The ceramic component may be, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３The main component metal of the first underlying electrode layer 50A and the main component metal of the second underlying electrode layer 50B are preferably Cu.

[0045] The baked layer is formed by, for example, applying and baking a conductive paste containing glass and metal to the laminate 10. The baked layer can be formed by co-firing a pre-fired laminated chip, which is the material for the laminate 10 having multiple internal electrodes and dielectric layers, with a conductive paste applied to the laminated chip. Alternatively, the baked layer can be formed by first firing the laminated chip to obtain the laminate 10, and then applying and baking a conductive paste to the laminate 10. In the above-described formation method, the baked layer is preferably formed by baking a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the ceramic material added. The baked layer may be multiple layers.

[0046] The thickness of the first base electrode layer 50A located on the first end surface LS1 in the length direction L is preferably, for example, approximately 2 μm or more and 220 μm or less at the center in the height direction T and width direction W of the first base electrode layer 50A.

[0047] The thickness corresponding to the length direction L of the second base electrode layer 50B located on the second end surface LS2 is preferably, for example, approximately 2 μm or more and 220 μm or less at the center in the height direction T and width direction W of the second base electrode layer 50B.

[0048] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness corresponding to the height direction T of the first base electrode layer 50A provided on this portion be, for example, approximately 4 μm or more and 15 μm or less at the center in the length direction L and width direction W of the first base electrode layer 50A provided on this portion.

[0049] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness corresponding to the width direction W of the first base electrode layer 50A provided on this portion be, for example, approximately 4 μm or more and 15 μm or less at the center in the length direction L and height direction T of the first base electrode layer 50A provided on this portion.

[0050] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness corresponding to the height direction T of the second base electrode layer 50B provided on this portion be, for example, approximately 4 μm or more and 15 μm or less at the center in the length direction L and width direction W of the second base electrode layer 50B provided on this portion.

[0051] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness corresponding to the width direction W of the second base electrode layer 50B provided on this portion is, for example, approximately 4 μm or more and 15 μm or less at the center in the length direction L and height direction T of the second base electrode layer 50B provided on this portion.

[0052] The first and second base electrode layers 50A and 50B are not limited to baked layers. For example, the first and second base electrode layers 50A and 50B may be thin film layers. The thin film layers are formed by a thin film formation method such as sputtering or vapor deposition. The thin film layers are layers of metal particles deposited to a thickness of 3 μm to 40 μm.

[0053] The first organic layer 70A is disposed so as to cover the first base electrode layer 50A. Details of the first organic layer 70A will be described later.

[0054] The second organic layer 70B is disposed so as to cover the second base electrode layer 50B. Details of the second organic layer 70B will be described later.

[0055] The first plating layer 60A is disposed so as to cover the first organic layer 70A.

[0056] The second plating layer 60B is disposed so as to cover the second organic layer 70B.

[0057] The first plating layer 60A and the second plating layer 60B may contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers. The first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0058] In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0059] In this embodiment, the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0060] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 2 μm or more and 15 μm or less.

[0061] The external electrode 40 of this embodiment may have, for example, a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be disposed so as to cover the baked layer. When the conductive resin layer is disposed so as to cover the baked layer, the conductive resin layer is disposed between the baked layer and the organic layer 70 (the first organic layer 70A and the second organic layer 70B). The conductive resin layer may completely cover the baked layer or may cover only a portion of the baked layer.

[0062] The conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to a physical shock or a shock due to a thermal cycle, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0063] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. The conductive particles preferably contain Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals and is therefore suitable as an electrode material. Furthermore, Ag is a noble metal, so it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as conductive particles.

[0064] The conductive particles may also be metal powder whose surface is coated with Ag. When using metal powder whose surface is coated with Ag, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy powder thereof. In order to maintain the properties of Ag while making the base metal inexpensive, it is preferable to use Ag-coated metal powder.

[0065] Furthermore, the conductive particles may be Cu or Ni that has been subjected to an anti-oxidation treatment. Furthermore, the conductive particles may be metal powder in which the surface of metal powder is coated with Sn, Ni, or Cu. When using metal powder in which the surface of Sn, Ni, or Cu is coated, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0066] The shape of the conductive particles is not particularly limited. The conductive particles may be spherical, flat, or other shapes, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0067] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the electrical conductivity of the conductive resin layer. Specifically, the conductive particles come into contact with each other to form electrical paths within the conductive resin layer.

[0068] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins, such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, the resin of the conductive resin layer preferably includes a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0069] The conductive resin layer may be formed of a plurality of layers. The thickness of the thickest part of the conductive resin layer is preferably 10 μm or more and 200 μm or less.

[0070] Next, the organic layer 70 according to this embodiment will be described with reference to Figures 2 to 5. The organic layer 70 according to this embodiment includes a first organic layer 70A and a second organic layer 70B.

[0071] The first organic layer 70A is disposed on the first base electrode layer 50A. A first plating layer 60A is disposed on the first organic layer 70A. The first organic layer 70A may also be disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2. In this embodiment, the first organic layer 70A is formed to extend to approximately the center of the first main surface TS1 and the second main surface TS2 in the length direction L, and to approximately the center of the first side surface WS1 and the second side surface WS2 in the length direction L.

[0072] The second organic layer 70B is disposed on the second base electrode layer 50B. A second plating layer 60B is disposed on the second organic layer 70B. The second organic layer 70B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second organic layer 70B is formed to extend to approximately the center of the first main surface TS1 and the second main surface TS2 in the length direction L, and to approximately the center of the first side surface WS1 and the second side surface WS2 in the length direction L.

[0073] For this reason, the first organic layer 70A and the second organic layer 70B are integrally formed at approximately the center of the first main surface TS1 and the second main surface TS2 in the length direction L and at approximately the center of the first side surface WS1 and the second side surface WS2 in the length direction L. In this manner, the first organic layer 70A and the second organic layer 70B of the present embodiment are integrally formed so as to cover the entire portion of the surface of the laminate 10 that is exposed from the external electrode 40.

[0074] The state of the base electrode layer 50 covered with the organic layer 70 will be described with reference to Figures 5A and 5B. Figure 5A is an enlarged cross-sectional view of a portion indicated by R1 in Figure 2. Figure 5B is an enlarged cross-sectional view of a portion indicated by R2 in Figure 2. As shown in Figure 5A, the first organic layer 70A is formed between the first base electrode layer 50A formed on the dielectric layer 20 and the first Ni plating layer 61A. As shown in Figure 5B, the second organic layer 70B is formed between the second base electrode layer 50B formed on the dielectric layer 20 and the second Ni plating layer 61B.

[0075] The surface of the first organic layer 70A is formed as a surface where a portion of the first base electrode layer 50A is exposed. That is, the first organic layer 70A has a plurality of voids as shown in FIG. 5A . The surface of the second organic layer 70B is formed as a surface where a portion of the second base electrode layer 50B is exposed. That is, the second organic layer 70B has a plurality of voids as shown in FIG. 5B .

[0076] Here, the atomic percentage of the main component metal of the first base electrode layer 50A on the surface of the first organic layer 70A arranged on the first main surface TS1 side and the second main surface TS2 side is defined as a first atomic percentage MR1. The atomic percentage of the main component metal of the second base electrode layer 50B on the surface of the second organic layer 70B arranged on the first main surface TS1 side and the second main surface TS2 side is defined as a second atomic percentage MR2. Here, the first atomic percentage MR1 is greater than the second atomic percentage MR2.

[0077] Preferably, the first atomic percentage MR1 is greater than 0.6 atom% and less than 4.0 atom%, and the second atomic percentage MR2 is smaller than the first atomic percentage MR1 and is greater than or equal to 0.6 atom% and less than 4.0 atom%. When the first atomic percentage MR1 and the second atomic percentage MR2 are less than 0.6 atom%, plating defects are likely to occur. Furthermore, when the first atomic percentage MR1 and the second atomic percentage MR2 are greater than 4.0 atom%, it may be difficult to achieve a sufficient peel-promoting effect. By setting the first atomic percentage MR1 and the second atomic percentage MR2 within the above ranges, deposition of the plating layer provided on the base electrode layer is inhibited, thereby reducing the bonding area between the base electrode layer and the plating layer. This reduces the adhesion between the base electrode layer and the plating layer, thereby promoting peeling between the base electrode layer and the plating layer.

[0078] The first atomic percentage MR1 is preferably greater than the second atomic percentage MR2 and is more preferably 1.0 atom % or greater. This allows the effects of the present disclosure to be more effectively achieved. The second atomic percentage MR2 is preferably smaller than the first atomic percentage MR1 and is more preferably 0.6 atom % or greater and 2.6 atom % or less. This allows the effects of the present disclosure to be more effectively achieved.

[0079] The second atomic percentage MR2 is preferably equal to or less than half of the first atomic percentage MR1, which allows the effects of the present disclosure to be more effectively achieved.

[0080] As described above, the main component metal of the first base electrode layer 50A and the main component metal of the second base electrode layer 50B are preferably Cu. However, the main component metal of the first base electrode layer 50A and the main component metal of the second base electrode layer 50B are not limited to Cu. For example, Ni, Ag, Pd, an Ag—Pd alloy, or Au may be used.

[0081] The first organic layer 70A and the second organic layer 70B contain an organosilicon compound, which allows the first organic layer 70A and the second organic layer 70B to be reliably formed on the surfaces of the laminate 10, the base electrode layer 50, etc., thereby improving reliability.

[0082] However, the compositions constituting the first organic layer 70A and the second organic layer 70B are not limited thereto. Examples of the first organic layer 70A and the second organic layer 70B include a fatty acid coating. The fatty acid coating is a layer in which fatty acids are dotted on the surface of the base electrode layer. When a fatty acid coating is used as the first organic layer 70A and the second organic layer 70B, the fatty acid is present at least on the surface of the base electrode layer. More specifically, the fatty acid is present at least on the surface of the first base electrode layer 50A and the surface of the second base electrode layer 50B. As a result, the carboxyl groups of the fatty acid are ionized and adsorbed to the base electrode layer by ionic bonding. This inhibits the deposition of the plating layer formed on the base electrode layer at the adsorbed portions, thereby reducing the bonding area between the base electrode layer and the plating layer. This reduces the adhesion between the base electrode layer and the plating layer, thereby promoting the peeling of the base electrode layer from the plating layer formed thereon. Therefore, when the multilayer ceramic capacitor is subjected to an impact such as a drop or a thermal cycle, the base electrode layer and the plating layer can be stably separated from each other, allowing stress to be released, thereby preventing cracks from occurring in the laminate of the multilayer ceramic capacitor.

[0083] The total atomic percentage (atom %) of Si, C, N, and O on the surface of the first organic layer 70A is preferably 90 atom % or more. The total atomic percentage (atom %) of Si, C, N, and O on the surface of the second organic layer 70B is preferably 90 atom % or more.

[0084] The thickness of the first organic layer 70A is preferably 5 nm or more and 500 nm or less. Furthermore, the thickness of the first organic layer 70A is more preferably 100 nm or more and 200 nm or less. The thickness of the second organic layer 70B is preferably 5 nm or more and 500 nm or less. Furthermore, the thickness of the second organic layer 70B is more preferably 100 nm or more and 200 nm or less.

[0085] The above is the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, the L dimension is preferably 0.2 mm or more and 10 mm or less. If the heightwise dimension of the multilayer ceramic capacitor 1 is defined as T, the T dimension is preferably 0.1 mm or more and 10 mm or less. If the widthwise dimension of the multilayer ceramic capacitor 1 is defined as W, the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0086] <Atomic Percentage of Organic Layer Surface Components> Next, a method for measuring the atomic percentage of the organic layer surface components in this embodiment will be described. First, only one external electrode of a multilayer ceramic capacitor is mounted to a mounting substrate using solder, leaving the other external electrode in a floating state. Next, the floating other external electrode is pressed vertically from the bottom to separate the base electrode layer and the plating layer on the one external electrode mounted on the mounting substrate, exposing the organic layer. XPS analysis is then performed on the multilayer ceramic capacitor 1 from which the plating layer has been separated. First, X-rays are irradiated onto the entire surface of the exposed organic layer. The thermoelectron acceleration voltage is 15 kV. Next, qualitative analysis of all elements is performed using a wide scan, followed by quantitative analysis of all elements using a narrow scan, allowing the abundance ratio (atom %) of all elements on the surface of the organic layer to be calculated. Note that in this embodiment, narrow scan spectra are calculated for elements detected from the wide scan spectrum, normalized so that the sum of the detected elements equals 100 atom %, and then XPS analysis is performed. The abundance ratio (atom %) is an atomic percentage that indicates the proportion of atoms excluding hydrogen and helium.

[0087] As a result, the atomic percentage of the main component metal of the first base electrode layer 50A on the surface of the first organic layer 70A arranged on the first main surface TS1 side and the second main surface TS2 side can be calculated as a first atomic percentage MR1. Furthermore, the atomic percentage of the main component metal of the second base electrode layer 50B on the surface of the second organic layer 70B arranged on the first main surface TS1 side and the second main surface TS2 side can be calculated as a second atomic percentage MR2. When the main component metal of the first base electrode layer 50A and the second base electrode layer 50B is Cu, the first atomic percentage MR1 and the second atomic percentage MR2 are calculated as Cu (atom %).

[0088] Here, the first atomic percentage MR1 of the present disclosure is calculated as the average value of the measured values ​​on the surface of the first organic layer 70A arranged on the first main surface TS1 side and the measured values ​​on the surface of the first organic layer 70A arranged on the second main surface TS2 side. The second atomic percentage MR2 of the present disclosure is calculated as the average value of the measured values ​​on the surface of the second organic layer 70B arranged on the first main surface TS1 side and the measured values ​​on the surface of the second organic layer 70B arranged on the second main surface TS2 side.

[0089] <First Dimension EL1, Second Dimension EL2> Next, a method for measuring the first dimension EL1 and the second dimension EL2 will be described. First, the LT cross section at the center of the width direction W of the laminate 10 is exposed by polishing. Next, the exposed LT cross section is used as the measurement object, and the first dimension EL1 and the second dimension EL2 are measured using a digital microscope. Here, the first dimension EL1 of the present disclosure is calculated as the average value of the measurement value on the first main surface TS1 side and the measurement value on the second main surface TS2 side. The second dimension EL2 of the present disclosure is calculated as the average value of the measurement value on the first main surface TS1 side and the measurement value on the second main surface TS2 side.

[0090] Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0091] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. Both the dielectric sheet for the dielectric layer 20 and the conductive paste for the internal electrode layer 30 contain a binder and a solvent. The binder and solvent may be known. The paste made of a conductive material is, for example, a metal powder to which an organic binder and an organic solvent have been added.

[0092] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet by, for example, screen printing or gravure printing using a printing plate patterned to have the shape of the internal electrode layer 30 of this embodiment. As a result, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared.

[0093] A predetermined number of dielectric sheets on which the pattern of the internal electrode layer 30 is not printed are stacked to form a portion that will become the first main surface side outer layer portion 12 on the first main surface TS1 side. Dielectric sheets on which the pattern of the first internal electrode layer 31 is printed and dielectric sheets on which the pattern of the second internal electrode layer 32 is printed are stacked alternately in sequence on top of that to form a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets on which the pattern of the internal electrode layer 30 is not printed are stacked on top of this portion that will become the second main surface side outer layer portion 13 on the second main surface TS2 side. In this way, a laminated sheet is obtained.

[0094] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0095] The laminated block is then cut into individual pieces of a predetermined size to obtain a plurality of laminated chips, which may then be polished by barrel polishing or the like to round off corners and ridges.

[0096] Next, the laminated chip is fired to obtain the laminate 10. The firing temperature at this time depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably, for example, 900° C. or higher and 1400° C. or lower.

[0097] A conductive paste that will become the base electrode layer 50 is applied to both end surfaces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. The baked layer can be formed by applying a conductive paste containing a glass component and a metal to the laminate 10 by a method such as dipping, and then performing a baking process. The temperature for the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0098] In this embodiment, dipping is performed so that the first base electrode layer 50A extends from the first end surface LS1 to portions of the first main surface TS1 and the second main surface TS2. Also, dipping is performed so that the second base electrode layer 50B extends from the second end surface LS2 to portions of the first main surface TS1 and the second main surface TS2. At this time, dipping is performed so that the distance over which the first base electrode layer 50A extends is longer than the distance over which the second base electrode layer 50B extends, and the first dimension EL1 is longer than the second dimension. At this time, dipping is preferably performed so that the first base electrode layer 50A extends to portions of the first side surface WS1 and the second side surface WS2. Furthermore, dipping is preferably performed so that the second base electrode layer 50B extends to a portion of the first side surface WS1 and the second side surface WS2. In this case, by dipping both ends of the laminate 10 in the conductive paste, the first main surface TS1 and the second main surface TS2, and the first side surface WS1 and the second side surface WS2 can be dipped simultaneously. This facilitates the dipping process.

[0099] The laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, it is preferable to form the baked layer by adding a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are baked simultaneously to form the laminate 10 with the baked layer formed.

[0100] Next, an organic layer loosely coated with an organic compound is formed on the base electrode layer. A method for forming an organic layer loosely coated with an organic compound on the base electrode layer can be to dilute the organic compound with an organic solvent and spray coat it. Specifically, for example, a solution is prepared by diluting a silane coupling agent with IPA (2-propanol). The laminate with the base electrode layer formed is placed in a barrel device, and the solution is spray coated onto the laminate with the base electrode layer formed. The laminate is then removed from the barrel device, spread on filter paper, and heat-treated in an oven at 100°C to 200°C for a predetermined time (30 to 60 minutes) to harden the organic layer.

[0101] Alternatively, the organic compound may be diluted with an organic solvent to prepare a solution, and then the solution may be applied to a laminate on which a base electrode layer has been formed, followed by thermal curing. Here, the solution may be applied by dipping or the like.

[0102] In this embodiment, the first organic layer 70A and the second organic layer 70B are formed so that the coverage of the second organic layer 70B arranged on the first principal surface TS1 side and the second principal surface TS2 side is higher than the coverage of the first organic layer 70A arranged on the first principal surface TS1 side and the second principal surface TS2 side. That is, the first organic layer 70A and the second organic layer 70B are formed so that the first atomic percentage MR1, which is the atomic percentage of the main component metal of the first base electrode layer 50A on the surface of the first organic layer 70A arranged on the first principal surface TS1 side and the second principal surface TS2 side, is higher than the second atomic percentage MR2, which is the atomic percentage of the main component metal of the second base electrode layer 50B on the surface of the second organic layer 70B arranged on the first principal surface TS1 side and the second principal surface TS2 side.

[0103] The target atomic percentage of the main component metal of the base electrode layer on the surface of the organic layer and the thickness of the organic layer can be controlled by controlling the solution concentration, coating method, coating time, and coating temperature.

[0104] In this embodiment, the same amount of organic layer is first formed on the first base electrode layer 50A and the second base electrode layer 50B by the above-described spray coating and heat treatment. As a result, the first atomic percentage MR1, which is the atomic percentage of the main component metal of the first base electrode layer 50A on the surface of the first organic layer 70A arranged on the first principal surface TS1 side and the second principal surface TS2 side, becomes equal to the second atomic percentage MR2, which is the atomic percentage of the main component metal of the second base electrode layer 50B on the surface of the second organic layer 70B arranged on the first principal surface TS1 side and the second principal surface TS2 side. The second base electrode layer 50B is then dipped in a silane coupling agent solution and heat-treated. This additional dipping and heat treatment results in a higher organic layer coverage of the second base electrode layer 50B than the first base electrode layer 50A. Therefore, the first external electrode 40A and the second external electrode 40B are formed in a state in which the first atomic percentage MR1 is greater than the second atomic percentage MR2.

[0105] Thereafter, a plating layer is formed on the surface of the organic layer 70. In this embodiment, a first plating layer 60A is formed on the surface of the first organic layer 70A. Furthermore, a second plating layer 60B is formed on the surface of the second organic layer 70B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0106] When a conductive resin layer is provided, the conductive resin layer may be disposed so as to cover the baked layer. When providing the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied onto the baked layer, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to thermally harden, forming a conductive resin layer. The atmosphere during this heat treatment is N ２In order to prevent the resin from scattering and the various metal components from being oxidized, the oxygen concentration is preferably 100 ppm or less.

[0107] Through the above manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0108] The configuration of the multilayer ceramic capacitor 1 is not limited to the configuration shown in Figures 1 to 4B. For example, the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a double structure, a triple structure, or a quadruple structure as shown in Figures 6 to 8.

[0109] The multilayer ceramic capacitor 1 shown in FIG. 6 is a double-structure multilayer ceramic capacitor 1, and includes, as the internal electrode layers 30, a first internal electrode layer 33, a second internal electrode layer 34, and a floating internal electrode layer 35 that is not extended to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in FIG. 7 is a triple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as the floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in FIG. 8 is a quadruple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as the floating internal electrode layers 35. By providing the floating internal electrode layers 35 as the internal electrode layers 30 in this way, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. This reduces the voltage applied to each capacitor component, thereby achieving a high withstand voltage for the multilayer ceramic capacitor 1. It goes without saying that the multilayer ceramic capacitor 1 of this embodiment may have a multi-row structure of four or more rows.

[0110] Second Embodiment In the multilayer ceramic capacitor 1 according to the above-described embodiment, the first organic layer 70A and the second organic layer 70B extend to approximately the center in the length direction L of the first main surface TS1 and the second main surface TS2 and to approximately the center in the length direction L of the first side surface WS1 and the second side surface WS2, and are integrally formed to cover the entire portion of the surface of the laminate 10 that is exposed from the external electrode 40. However, the configuration of the first organic layer 70A and the second organic layer 70B is not limited to this.

[0111] The multilayer ceramic capacitor 1 according to the second embodiment will be described below with reference to FIGS. 9 to 10B. FIG. 9 is a cross-sectional view corresponding to FIG. 2 in the second embodiment. FIG. 10A is a cross-sectional view corresponding to FIG. 4A in the second embodiment. FIG. 10B is a cross-sectional view corresponding to FIG. 4B in the second embodiment. Note that configurations similar to those in the first embodiment may be given the same names and detailed descriptions thereof may be omitted.

[0112] 1, the multilayer ceramic capacitor 1 according to the second embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 10 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at opposite ends of the laminate 10 while being spaced apart from each other.

[0113] As shown in Figures 1 and 9, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0114] 9, 10A, and 10B, the first external electrode 40A has a first base electrode layer 50A, a first organic layer 70bA disposed on the first base electrode layer 50A, and a first plating layer 60A disposed on the first organic layer 70bA. The second external electrode 40B has a second base electrode layer 50B, a second organic layer 70bB disposed on the second base electrode layer 50B, and a second plating layer 60B disposed on the second organic layer 70bB.

[0115] The organic layer 70b according to this embodiment includes a first organic layer 70bA and a second organic layer 70bB.

[0116] The first organic layer 70bA is disposed on the first base electrode layer 50A. A first plating layer 60A is disposed on the first organic layer 70bA. The first organic layer 70bA may also be disposed on a portion of the first principal surface TS1, a portion of the second principal surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first organic layer 70bA is formed to extend to a portion of the first principal surface TS1, a portion of the second principal surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0117] The second organic layer 70bB is disposed on the second base electrode layer 50B. A second plating layer 60B is disposed on the second organic layer 70bB. The second organic layer 70bB may also be disposed on a portion of the first principal surface TS1, a portion of the second principal surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In this embodiment, the second organic layer 70bB is formed to extend to a portion of the first principal surface TS1, a portion of the second principal surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0118] That is, in the multilayer ceramic capacitor 1 according to this embodiment, there is a portion between the first external electrode 40A and the second external electrode 40B where the organic layer 70b is not present. Therefore, the first organic layer 70bA and the second organic layer 70bB in this embodiment are not formed integrally, and part of the surface of the laminate 10 is exposed. Even in this case, an organic layer is formed at the end of the base electrode layer of the external electrode, which is the starting point of the crack, and therefore the effect of suppressing cracks can be obtained.

[0119] Also in this embodiment, by making the first dimension EL1 on the first end face LS1 side larger than the second dimension EL2 on the second end face LS2 side, the deflection load applied to the second external electrode 40B on the second end face LS2 side can be increased. Furthermore, by making the first atomic percentage MR1 on the first end face LS1 side larger than the second atomic percentage MR2 on the second end face LS2 side, the adhesion between the second base electrode layer 50B and the second plating layer 60B of the second external electrode 40B on the second end face LS2 side, where the deflection load is greater, can be reduced. Therefore, it is possible to preferentially promote peeling between the second base electrode layer 50B and the second plating layer 60B of the second external electrode 40B on the second end face LS2 side, thereby achieving the effect of suppressing cracks.

[0120] The multilayer ceramic capacitor 1 according to the first embodiment is a two-terminal type having two external electrodes, but is not limited to this and may be a multi-terminal type having a large number of external electrodes.

[0121] In the above-described embodiment, a multilayer ceramic capacitor in which the dielectric layers 20 made of a dielectric ceramic are used as ceramic layers has been described as an example of the multilayer ceramic electronic component. However, the multilayer ceramic electronic component of the present disclosure is not limited to this. For example, the ceramic electronic component of the present disclosure can also be applied to various multilayer ceramic electronic components, such as piezoelectric components using piezoelectric ceramic as the ceramic layers and thermistors using semiconductor ceramic as the ceramic layers. Examples of piezoelectric ceramics include PZT (lead zirconate titanate)-based ceramics, and examples of semiconductor ceramics include spinel-based ceramics.

[0122] The multilayer ceramic capacitor 1 according to the embodiment described above provides the following advantages.

[0123] The multilayer ceramic capacitor 1 according to the embodiment includes a laminate 10 including a plurality of dielectric layers 20 (ceramic layers 20) and a plurality of internal electrode layers 30 (internal conductor layers 30) stacked alternately, and having a first main surface TS1 and a second main surface TS2 facing in a height direction T, a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the height direction T and the width direction W, and an external electrode 40 connected to the internal electrode layer 30, wherein the external electrode 40 is a first The semiconductor device has a first external electrode 40A arranged on the first end face LS1 and a second external electrode 40B arranged on the second end face LS2, the first external electrode 40A having a first base electrode layer 50A arranged on the first end face LS1, a first organic layer 70A arranged on the first base electrode layer 50A, and a first plating layer 60A arranged on the first organic layer 70A, and the second external electrode 40B having a second base electrode layer 50B arranged on the second end face LS2, a second organic layer 70B arranged on the second base electrode layer 50B, and a second plating layer 60A arranged on the second organic layer 70B. The first base electrode layer 50A is disposed extending from the first end face LS1 to a portion of the first main surface TS1 and the second main surface TS2, and the second base electrode layer 50B is disposed extending from the second end face LS2 to a portion of the first main surface TS1 and the second main surface TS2. A first dimension EL1 is a dimension in a length direction L of the first base electrode layer 50A disposed extending from the first end face LS1 to a portion of the first main surface TS1 and the second main surface TS2, the dimension in a length direction L of the first base electrode layer 50A extending from the first end face LS1 to a portion of the first main surface TS1 and the second main surface TS2, on the second end face LS2 side. When the dimension in the length direction L to the terminal end on the first end face LS1 side of the second base electrode layer 50B arranged to extend to the first main surface TS1 and a part of the second main surface TS2 is defined as a second dimension EL2, the first dimension EL1 is larger than the second dimension EL2, the surface of the first organic layer 70A is formed as a surface where a part of the first base electrode layer 50A is exposed, and the surface of the second organic layer 70B is formed as a surface where a part of the second base electrode layer 50B is exposed, and on the surfaces of the first organic layer 70A arranged on the first main surface TS1 side and the second main surface TS2 side,When the atomic percentage of the main component metal of the first base electrode layer 50A is a first atomic percentage MR1 and the atomic percentage of the main component metal of the second base electrode layer 50B on the surface of the second organic layer 70B arranged on the first main surface TS1 side and the second main surface TS2 side is a second atomic percentage MR2, the first atomic percentage MR1 is larger than the second atomic percentage MR2.

[0124] By making the first dimension EL1 on the first end face LS1 side larger than the second dimension EL2 on the second end face LS2 side, the deflection load applied to the second external electrode 40B on the second end face LS2 side can be increased. Furthermore, by making the first atomic percentage MR1 on the first end face LS1 side larger than the second atomic percentage MR2 on the second end face LS2 side, the adhesion between the second base electrode layer 50B and the second plating layer 60B of the second external electrode 40B on the second end face LS2 side, where the deflection load is greater, can be reduced. This makes it possible to preferentially promote peeling between the second base electrode layer 50B and the second plating layer 60B of the second external electrode 40B on the second end face LS2 side, thereby providing a highly reliable multilayer ceramic electronic component that is capable of suppressing cracks from occurring in the laminate 10 of the multilayer ceramic electronic component.

[0125] In conventional multilayer ceramic capacitors, when an excessive bending load or the like is applied, excessive delamination occurs between the laminate and the external electrodes, which can result in the multilayer ceramic capacitor being detached from the mounting substrate. According to this embodiment, as described above, when a substrate bending stress or a thermal cycle shock is applied to the multilayer ceramic electronic component, delamination can be preferentially and stably caused between the base electrode layer and the plating layer of the other external electrode, the second external electrode, while the first external electrode, which is one of the two external electrodes, remains bonded to the mounting substrate. This makes it possible to reliably release stress without the multilayer ceramic capacitor being detached from the mounting substrate, and also suppresses cracks from occurring in the laminate.

[0126] In the multilayer ceramic capacitor 1 according to the embodiment, the first atomic percentage MR1 is greater than 0.6 atom % and less than 4.0 atom %, and the second atomic percentage MR2 is smaller than the first atomic percentage MR1 and is greater than or equal to 0.6 atom % and less than 4.0 atom %.

[0127] This makes it possible to provide a highly reliable multilayer ceramic electronic component while suppressing the occurrence of plating defects.

[0128] In the multilayer ceramic capacitor 1 according to the embodiment, the main component metal of the first underlying electrode layer 50A and the main component metal of the second underlying electrode layer 50B are Cu.

[0129] This makes it possible to suppress the diffusion of hydrogen into the internal dielectric layers during manufacturing, prevent deterioration of insulation resistance, and provide a highly reliable multilayer ceramic electronic component while keeping manufacturing costs down.

[0130] In the multilayer ceramic capacitor 1 according to the embodiment, the first organic layer 70A and the second organic layer 70B are made of an organosilicon compound.

[0131] This ensures that the organic layer is formed on the surface of the laminate and the underlying electrode layer of the external electrode, thereby improving reliability.

[0132] The present invention is not limited to the configurations of the above-described embodiments, and can be applied by making appropriate modifications within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0133] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor (multilayer ceramic electronic component) 10 Laminate 20 Dielectric layer (ceramic layer) 30 Internal electrode layer (internal conductor layer) 40 External electrode 40A First external electrode 40B Second external electrode 50A First base electrode layer 50B Second base electrode layer 60A First plating layer 60B Second plating layer 70A First organic layer 70B Second organic layer EL1 First dimension EL2 Second dimension L Length direction LS1 First end face LS2 Second end face MR1 First atomic percentage MR2 Second atomic percentage T Height direction TS1 First main surface TS2 Second main surface W Width direction WS1 First side surface WS2 Second side surface

Claims

1. A laminate including a plurality of ceramic layers and a plurality of internal conductor layers laminated alternately, having a first main surface and a second main surface facing each other in a height direction, a first side surface and a second side surface facing each other in a width direction orthogonal to the height direction, and a first end surface and a second end surface facing each other in a length direction orthogonal to the height direction and the width direction; and an external electrode connected to the internal conductor layer, the external electrode having a first external electrode disposed on the first end surface and a second external electrode disposed on the second end surface, the first external electrode having a first base electrode layer disposed on the first end surface, a first organic layer disposed on the first base electrode layer, and a first plating layer disposed on the first organic layer, the second external electrode having a second base electrode layer disposed on the second end surface, a second organic layer disposed on the second base electrode layer, and a second plating layer disposed on the second organic layer, the first base electrode layer extending from the first end surface to a part of the first main surface and the second main surface, the second base electrode layer extending from the second end surface to a part of the first main surface and the second main surface, when a lengthwise dimension from the first end surface of the laminate to a termination on the second end surface side in the first base electrode layer extending from the first end surface to a part of the first main surface and the second main surface is defined as a first dimension, and a lengthwise dimension from the second end surface of the laminate to a termination on the first end surface side in the second base electrode layer extending from the second end surface to a part of the first main surface and the second main surface is defined as a second dimension, the first dimension is larger than the second dimension, the surface of the first organic layer is formed as a surface where a part of the first base electrode layer is exposed, the surface of the second organic layer is formed as a surface where a part of the second base electrode layer is exposed, when an atomic percentage of a main component metal of the first base electrode layer on the surface of the first organic layer disposed on the first main surface side and the second main surface side is defined as a first atomic percentage, and an atomic percentage of a main component metal of the second base electrode layer on the surface of the second organic layer disposed on the first main surface side and the second main surface side is defined as a second atomic percentage,The stacked ceramic electronic component in which the first atomic percentage is greater than the second atomic percentage.

2. The stacked ceramic electronic component according to claim 1, wherein the first atomic percentage is more than 0.6 atom% and 4.0 atom% or less, the second atomic percentage is less than the first atomic percentage, and is 0.6 atom% or more and less than 4.0 atom%.

3. The stacked ceramic electronic component according to claim 1 or 2, wherein the main component metal of the first base electrode layer and the main component metal of the second base electrode layer are Cu.

4. The stacked ceramic electronic component according to any one of claims 1 to 3, wherein the first organic layer and the second organic layer are organosilicon compounds.

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