Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention provides: a semiconductor device in which it is possible to suppress warpage and distortion of a wafer due to expansion or the like of a polysilicon film at the time when embedding the polysilicon film in a trench; and a method for manufacturing a semiconductor device. This semiconductor device is provided with: a semiconductor substrate (10) that has a first conductivity type; a first semiconductor layer (2) that has a second conductivity type; a first semiconductor region (3) that has the first conductivity type; a trench (6); a gate insulating film (7); a gate electrode (8); an interlayer insulating film (9); a first electrode (11); and a second electrode (24). With respect to the trench (6), a TEOS film (30) is embedded inside the gate electrode (8).

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0002] Conventionally, a field effect transistor has been known in which an interlayer insulating film, rather than a gate electrode, is formed on a gate oxide film at the bottom of a trench, thereby reducing the capacitance between the gate electrode and the drain region by the absence of a gate electrode at the bottom of the trench (see, for example, Patent Document 1 below).

[0003] Japanese Patent Application Publication No. 9-181311

[0004] In conventional semiconductor devices, trenches are filled with a polysilicon film, but subsequent high-temperature processes can cause the polysilicon film to expand, resulting in large stress on the surface of the device and causing the wafer to warp or distort.

[0005] In order to solve the problems associated with the conventional techniques described above, the present disclosure aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress warping and distortion of a wafer due to, for example, the expansion of a polysilicon film when the polysilicon film is embedded in a trench.

[0006] In order to solve the above-mentioned problems and achieve the object of the present disclosure, a semiconductor device according to this disclosure has the following features: The semiconductor device includes a first semiconductor layer of a second conductivity type provided on the front surface side of a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type selectively provided in a surface layer of the first semiconductor layer opposite to the semiconductor substrate side, a trench penetrating the first semiconductor region and the first semiconductor layer and reaching the semiconductor substrate, a gate electrode provided inside the trench with a gate insulating film interposed therebetween, an interlayer insulating film provided on the gate electrode, a first electrode provided on the surfaces of the first semiconductor region and the first semiconductor layer, and a second electrode provided on the back surface of the semiconductor substrate. A TEOS film is embedded inside the trench, inside the gate electrode.

[0007] According to the above disclosure, a TEOS film is embedded inside the gate electrode in the trench. The TEOS film can offset the residual stress of the polysilicon film. This can suppress warping and distortion of the wafer due to stress such as thermal expansion of the polysilicon film embedded in the trench, thereby suppressing warping and slip defects throughout the wafer. In addition, high-order in-plane distortion of the wafer due to stress can also be suppressed. As a result, the characteristic variations of the semiconductor device can be reduced, and reliability can be improved.

[0008] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure have the advantage of being able to suppress warping and distortion of the wafer due to expansion of the polysilicon film when the polysilicon film is embedded in the trench.

[0009] FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment. FIG. 2 is a flowchart showing a procedure for forming a gate electrode in a method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view (part 1) schematically showing gate electrode formation in a method for manufacturing a semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view (part 2) schematically showing gate electrode formation in a method for manufacturing a semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view (part 3) schematically showing gate electrode formation in a method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view (part 4) schematically showing gate electrode formation in a method for manufacturing a semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view (part 5) schematically showing gate electrode formation in a method for manufacturing a semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view (part 6) schematically showing gate electrode formation in a method for manufacturing a semiconductor device according to the first embodiment. FIG. 9 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment. FIG. 10 is a flowchart showing a procedure for forming a gate electrode in a method for manufacturing a semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view (part 1) schematically showing gate electrode formation in a method for manufacturing a semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view (part 2) schematically showing gate electrode formation in a method for manufacturing a semiconductor device according to the second embodiment. FIG. 13 is a cross-sectional view (part 3) schematically showing gate electrode formation in the method for manufacturing a semiconductor device according to the second embodiment. FIG. 14 is a cross-sectional view (part 4) schematically showing gate electrode formation in the method for manufacturing a semiconductor device according to the second embodiment. FIG. 15 is a cross-sectional view (part 5) schematically showing gate electrode formation in the method for manufacturing a semiconductor device according to the second embodiment. FIG. 16 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. FIG. 17 is a flowchart showing the procedure for gate electrode formation in the method for manufacturing a semiconductor device according to the third embodiment. FIG. 18 is a cross-sectional view (part 1) schematically showing gate electrode formation in the method for manufacturing a semiconductor device according to the third embodiment. FIG. 19 is a cross-sectional view (part 2) schematically showing gate electrode formation in the method for manufacturing a semiconductor device according to the third embodiment.Fig. 20 is a flow chart showing the procedure for forming a gate electrode in a conventional semiconductor device manufacturing method, and Fig. 21 is a cross-sectional view showing the occurrence of slip defects in a conventional semiconductor device.

[0010] Summary of Embodiments of the Present Disclosure To solve the above-described problems and achieve the object of the present disclosure, a semiconductor device according to the present disclosure has the following features. The semiconductor device includes: a first semiconductor layer of a second conductivity type provided on a front surface side of a semiconductor substrate of a first conductivity type; a first semiconductor region of the first conductivity type selectively provided in a surface layer of the first semiconductor layer opposite to the semiconductor substrate side; a trench penetrating the first semiconductor region and the first semiconductor layer and reaching the semiconductor substrate; a gate electrode provided inside the trench with a gate insulating film interposed therebetween; an interlayer insulating film provided on the gate electrode; a first electrode provided on the surfaces of the first semiconductor region and the first semiconductor layer; and a second electrode provided on a back surface of the semiconductor substrate. A TEOS film is embedded inside the trench, the gate electrode being spaced apart from the gate electrode.

[0011] According to the above disclosure, a TEOS film is embedded inside the gate electrode in the trench. The TEOS film can offset the residual stress of the polysilicon film. This can suppress warping and distortion of the wafer due to stress such as thermal expansion of the polysilicon film embedded in the trench, thereby suppressing warping and slip defects throughout the wafer. In addition, high-order in-plane distortion of the wafer due to stress can also be suppressed. As a result, the characteristic variations of the semiconductor device can be reduced, and reliability can be improved.

[0012] Furthermore, in the semiconductor device according to the present disclosure, the TEOS film penetrates the gate insulating film at the bottom of the trench and contacts the semiconductor substrate.

[0013] According to the disclosure above, the gate electrodes are separated at the bottom of the trench, resulting in smaller Miller capacitance and faster switching.

[0014] Furthermore, in the semiconductor device disclosed above, the TEOS film is provided between the gate electrode and the interlayer insulating film.

[0015] Furthermore, in the semiconductor device according to the present disclosure, the trench is filled with an SOG film instead of the TEOS film.

[0016] According to the above disclosure, slits are formed when filling trenches with a polysilicon film. These slits allow for a reduction in stress compared to conventional methods. This method can be used in configurations where the stress caused by the polysilicon film is small, for example, where the trench spacing is wide, and can suppress warpage and slip defects across the entire wafer. It can also suppress high-order in-plane distortion of the wafer due to stress.

[0017] In addition, in the semiconductor device according to the present disclosure, the width of the TEOS film is 0.16 μm or more and 0.28 μm or less.

[0018] In order to solve the above-mentioned problems and achieve the object of the present disclosure, a method for manufacturing a semiconductor device according to the present disclosure has the following features. First, a first step is performed to form a first semiconductor layer of a second conductivity type on the front surface side of a semiconductor substrate of a first conductivity type. Next, a second step is performed to selectively form a first semiconductor region of the first conductivity type in a surface layer of the first semiconductor layer opposite the semiconductor substrate. Next, a third step is performed to form a trench that penetrates the first semiconductor region and the first semiconductor layer and reaches the semiconductor substrate. Next, a fourth step is performed to form an insulating film along the inner wall of the trench. Next, a fifth step is performed to fill the trench with a polysilicon film so as to form a slit inside the trench. Next, a sixth step is performed to etch back the polysilicon film, leaving a portion that will become a gate electrode inside the trench. Next, a seventh step is performed to remove the insulating film from the surface of the first semiconductor region and the first semiconductor layer, leaving a portion that will become a gate insulating film inside the trench. Next, an eighth step is performed to perform a high-temperature heat treatment on the semiconductor substrate. Next, a ninth step is performed to fill the slit with a TEOS film. Next, a tenth step is performed in which an interlayer insulating film is formed on the gate electrode, an eleventh step is performed in which a first electrode is formed on the surfaces of the first semiconductor region and the first semiconductor layer, and a twelfth step is performed in which a second electrode is formed on the back surface of the semiconductor substrate.

[0019] Furthermore, the method for manufacturing a semiconductor device according to the present disclosure is characterized in that, in the above disclosure, after the fifth step and before the sixth step, it includes a thirteenth step of filling the slit with positive resist and exposing the positive resist to leave the positive resist at the bottom of the slit, and after the sixth step and before the seventh step, it includes a fourteenth step of removing the positive resist at the bottom of the slit.

[0020] In order to solve the above-mentioned problems and achieve the object of the present disclosure, a method for manufacturing a semiconductor device according to the present disclosure has the following features. First, a first step is performed in which a first semiconductor layer of a second conductivity type is formed on the front surface side of a semiconductor substrate of a first conductivity type. Next, a second step is performed in which a first semiconductor region of the first conductivity type is selectively formed in a surface layer of the first semiconductor layer opposite the semiconductor substrate side. Next, a third step is performed in which a trench is formed that penetrates the first semiconductor region and the first semiconductor layer and reaches the semiconductor substrate. Next, a fourth step is performed in which an insulating film is formed along the inner wall of the trench. Next, a fifth step is performed in which a polysilicon film is embedded inside the trench to form a slit. Next, a sixth step is performed in which an SOG film is deposited so as to embed the slit. Next, a seventh step is performed in which the SOG film and the insulating film on the surface of the first semiconductor region and the first semiconductor layer are removed, leaving a portion that will become a gate insulating film inside the trench. Next, an eighth step is performed in which the semiconductor substrate is subjected to a high-temperature heat treatment. Next, a ninth step is performed in which an interlayer insulating film is formed on the gate electrode. Next, a tenth step is performed in which a first electrode is formed on the surface of the first semiconductor region and the first semiconductor layer, and an eleventh step is performed in which a second electrode is formed on the back surface of the semiconductor substrate.

[0021] <Findings that Form the Basis of the Present Disclosure> First, problems with conventional semiconductor devices will be described. Conventionally, semiconductor devices have been known in which a polysilicon (poly-silicon) diode for use as a temperature sensor or the like is provided via an insulating layer on the front surface of a semiconductor, such as a Si substrate (semiconductor chip), that is the same as a trench-structure IGBT (Insulated Gate Bipolar Transistor) or MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0022] Conventional IGBTs have a planar gate structure, but a vertical trench structure was developed to reduce the ON voltage for the purpose of lowering power consumption. This is because by placing the gate on the sidewall of the trench, the cell density can be significantly increased and the voltage drop in the channel can be reduced compared to the planar type. In addition, since the JFET portion of the channel does not exist in the trench structure, the voltage effect in that portion can also be reduced.

[0023] In conventional semiconductor device manufacturing processes, as the diameter of crystal wafers increases, the physical stress caused by high-temperature processes makes the wafer more susceptible to warping and distortion. For example, in IGBT devices, the trench structure occupies a large portion of the wafer surface in the active region.

[0024] FIG. 20 is a flowchart showing the steps for forming a gate electrode in a conventional semiconductor device manufacturing method. The gate electrode is formed as follows after forming a surface device structure. First, a trench is formed through the surface device structure by photolithography and etching (step S101). Next, a gate insulating film is formed along the inner wall of the trench by, for example, thermal oxidation (step S102). Next, a polysilicon (poly-Si) film is formed on the front surface of the semiconductor wafer so as to fill the trench (step S103). Next, this polysilicon film is etched back, for example, to leave a portion that will become the gate electrode inside the trench (step S104). Next, the gate insulating film remaining on the front surface of the semiconductor wafer is removed (step S105). This is followed by a high-temperature heat treatment (step S106). This results in the formation of the gate electrode.

[0025] FIG. 21 is a cross-sectional view showing the occurrence of slip defects in a conventional semiconductor device. When forming the gate electrode 108, a polysilicon film is embedded in the trench 106. Subsequent high-temperature processes cause the polysilicon film to expand, generating large stress T on the surface side. This stress T causes warping and distortion of the wafer, further increasing the likelihood of slip defects 110. In FIG. 21, the slip defects 110 are depicted on the guard links outside the active region, but they are not limited to this location. For example, slip defects 110 can also occur between the trenches 106. In FIG. 21, reference numerals 107, 111, and 112 denote the gate insulating film, the interface where the polysilicon film is bonded during polysilicon film implantation, and the silicon layer, respectively.

[0026] However, CZ crystals with high oxygen concentrations manifest as defects such as OSFs, which raise concerns about the impact on leakage characteristics. For this reason, power semiconductor chips such as IGBTs generally use FZ wafers, which have fewer crystal defects, because they pass large currents in the vertical (cross-sectional) direction.

[0027] However, because FZ crystals have a low oxygen concentration, stress on the crystal is likely to manifest as slip defects. Therefore, when uneven stress is applied to one side of a wafer, the wafer curves unevenly. When an attempt is made to flatten the wafer by chucking it with a vacuum chuck or the like in an exposure machine during the photolithography process, the uneven stress within the wafer surface changes the local magnification of the wafer, resulting in high-order in-plane distortion (IPD) of the wafer that cannot be resolved by position and rotation correction alone.

[0028] As described above, with conventional technology, the stress within the wafer causes slip defects, which are crystal defects, resulting in poor characteristics and in-plane distortion of the wafer that shifts the mark position, which serves as the origin for pattern overlay, resulting in poor overlay accuracy. Conventional approaches to address slip defects have required lower temperatures for heat treatment, while measures to improve alignment accuracy have required increasing the number of distortion measurement samples per wafer and high-level misalignment correction, resulting in reduced throughput. Furthermore, defects and misalignment have led to increased poor characteristics and reduced reliability.

[0029] Preferred embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to the present disclosure that solve the problems of conventional semiconductor devices described above will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions without these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. Furthermore, the terms "same" or "equivalent" should preferably be interpreted as including variations within 5% in consideration of variations in manufacturing.

[0030] First Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to a first embodiment that solves the above-described problems will be described below. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. The structure of the semiconductor device according to the first embodiment will be described using a trench-type RC-IGBT 150 as an example. The semiconductor device according to the first embodiment shown in FIG. 1 is an RC-IGBT 150 in which an IGBT with a trench structure and a diode connected in anti-parallel to the IGBT are integrated on the same semiconductor substrate (semiconductor chip). The RC-IGBT 150 includes an active region, which is a region through which current flows when the RC-IGBT is on, and an edge termination region that surrounds the active region; however, FIG. 1 illustrates only the active region.

[0031] The RC-IGBT 150 has an IGBT region (transistor portion) 21 that serves as the operating region of the IGBT and an FWD region (diode portion) 22 that serves as the operating region of the diode, which are arranged in parallel on the same semiconductor substrate as the active region.

[0032] In the semiconductor wafer (first conductivity type semiconductor substrate) 10 in the active region, n - An n-type accumulation layer 5 may be provided in the surface layer of the front surface (first main surface) of the n-type drift layer 1. The n-type accumulation layer 5 is a so-called charge storage layer (Carrier Storage Layer: CSL) that reduces the spreading resistance of carriers. A p-type base region (first semiconductor layer of a second conductivity type) 2 is provided on the n-type accumulation layer 5, extending from the IGBT region 21 to the FWD region 22. The p-type base region 2 functions as a p-type anode region in the FWD region 22. An n-type charge carrier (Pb) is formed through the p-type base region 2. - A trench 6 is provided in the IGBT region 21 and the FWD region 22, and in the IGBT region 21, n-type + The p-type base region 2 is provided with a first emitter region (first semiconductor region of a first conductivity type) 3. The trenches 6 are arranged at predetermined intervals in, for example, a striped planar layout, and separate the p-type base region 2 into a plurality of regions (mesa portions). A gate insulating film 7 is provided inside the trench 6 along the inner wall of the trench 6, and a gate electrode 8 is provided inside the gate insulating film 7.

[0033] In the first embodiment, a TEOS (tetraethoxy silane) film 30 is buried inside the gate electrode 8 in the trench 6. The TEOS film 30 can offset the residual stress of a polysilicon film 32 (see FIG. 5 ) for forming the gate electrode 8. Furthermore, the TEOS film 30 is preferably provided between the gate electrode 8 and an interlayer insulating film 9 (described later). The trench 6 has a width of 0.8 μm to 1.4 μm and a depth of 5 μm to 6 μm. The width of the TEOS film 30 is approximately 0.2 μm, which is about ⅕ of the width of the trench 6, for example, 0.16 μm to 0.28 μm.

[0034] In the first embodiment, the TEOS film 30 penetrates the gate insulating film 7 at the bottom of the trench 6 to form an n-type - The gate electrode 8 is in contact with the type drift region 1. This separates the gate electrode 8 at the bottom of the trench 6. In this case, the Miller capacitance is reduced, resulting in faster switching (see, for example, Reference 1 below).

[0035] (Reference 1) Ultra Low Miller Capacitance Trench-Gate IGBT with the Split Gate Structure Procedures of the 27th International Symposium on Power Semiconductor Devices & IC's (May 10-14, 2015)

[0036] In the IGBT region 21, inside the p-type base region 2, n-type + The n-type emitter region 3 is selectively provided. + The emitter region 3 faces the gate electrode 8 across a gate insulating film 7 provided on the inner wall of the trench 6. + In this case, n + type emitter region 3 and p + In the FWD region 22, the p-type base region 2 has n + type emitter region 3 and p +The n-type contact region 4 is not provided. The front surface electrode 11 is connected to the n-type contact region 4 via the contact hole 20. + The n-type emitter region 3 is in contact with the n-type emitter region 3 and is electrically insulated from the gate electrode 8 by an interlayer insulating film 9. + An opening may be selectively provided in the p-type emitter region 3, and the front surface electrode 11 and the p-type base region 2 may be electrically connected through the opening. + When the contact region 4 is provided, the front electrode 11 and the p + The front surface electrode 11 functions as an emitter electrode in the IGBT region 21, and as an anode electrode in the FWD region 22. A Ti film 17 and a TiN film 18 are provided between the front surface electrode 11 and the interlayer insulating film 9 as barrier metals for preventing diffusion of metal atoms from the front surface electrode 11 toward the gate electrode 8, for example.

[0037] Alternatively, a structure may be used in which a contact plug is embedded in a contact hole 20 formed in the interlayer insulating film 9. The contact plug is made of, for example, a metal film made of tungsten (W), which has high embedding properties. The front surface electrode 11 is made of an Al film or an Al alloy film such as Al-Si. When the cell pitch is wide, a structure may be used in which the inside of the contact hole 20 is filled with the front surface electrode 11 without forming a contact plug. Hereinafter, the contact plug in the contact hole 20 or the front surface electrode 11 will be referred to as a plug electrode 15.

[0038] n - An n-type field stop (FS) layer 12 is provided on the rear surface of the substrate inside the drift layer 1. The n-type FS layer 12 is connected to the p-type base region 2 and the n-type - The pn junction between the p-type drift layer 1 and the + This has the function of suppressing the extension of the depletion layer toward the collector region 13 .

[0039] Also, n - In the n-type drift layer 1, the FWD region 22 has a larger n-type conductivity than the n-type FS layer 12. -A lifetime control region 26 may be provided at a shallow position from the front surface of the type drift layer 1. The lifetime control region 26 is formed by introducing lattice defects (indicated by x marks) such as vacancies (V) that act as lifetime killers by irradiation with hydrogen (H) or helium (He). Forming the lifetime control region 26 can reduce losses in the device. The lifetime control region 26 may extend to the vicinity of the boundary between the IGBT region 21 and the FWD region 22. The lifetime control region 26 may also extend to the chip edge in the edge termination region.

[0040] n - The surface layer on the rear surface (second main surface) side of the n-type drift layer 1 is more n-type than the n-type FS layer 12. - At a shallow position from the rear surface of the drift layer 1, p + The collector region 13 is provided in the FWD region 22. + A cathode region 14 is provided. + The cathode region 14 is p + The back electrode 24 is adjacent to the p-type collector region 13. + collector region 13 and n + The back electrode 24 functions as a collector electrode in the IGBT region 21 and as a cathode electrode in the FWD region 22.

[0041] (Method for Manufacturing a Semiconductor Device According to the First Embodiment) Next, a method for manufacturing a semiconductor device according to the first embodiment will be described. - n-type semiconductor wafer 10 - Forming the n-type drift region 1. - n-type drift region 1 - A mold semiconductor wafer 10 may be prepared. The material of the semiconductor wafer 10 may be silicon (Si) or silicon carbide (SiC). The following description will be given taking as an example a case where the semiconductor wafer 10 is a silicon wafer.

[0042] Next, a set of steps of photolithography and ion implantation is repeatedly performed under different conditions to form a surface device structure including a MOS structure on the front surface side of the semiconductor wafer 10. For example, first, the p-type base region 2 of the IGBT, n + type emitter region 3 and p + The p-type contact region 4 is formed (first and second steps). The p-type base region 2 is formed over the entire active region from the IGBT region 21 to the FWD region 22. The p-type base region 2 also serves as a p-type anode region in the FWD region 22. + type emitter region 3 and p + The p-type contact region 4 is selectively formed inside the p-type base region 2 in the IGBT region 21 .

[0043] The semiconductor wafer 10 has a p-type base region 2 and an n-type field stop (FS) layer 12 (described later), + collector region 13 and n + The portion other than the cathode region 14 is n - In the IGBT region 21, - An n-type accumulation layer 5 may be formed between the n-type drift region 1 and the p-type base region 2. The n-type accumulation layer 5 accumulates n-type charge when the IGBT is turned on. - It acts as a barrier to minority carriers (holes) in the n-type drift region 1, - The type drift region 1 has a function of accumulating minority carriers.

[0044] Next, the front surface of the semiconductor wafer 10 is thermally oxidized to form a field oxide film that covers the front surface of the semiconductor wafer 10 in the edge termination region. The formation of the trench-structured gate electrode 8 of the first embodiment will be described below. Figure 2 is a flowchart showing the procedure for forming the gate electrode in the method for manufacturing a semiconductor device according to the first embodiment. Figures 3 to 8 are cross-sectional views that schematically show the formation of the gate electrode in the method for manufacturing a semiconductor device according to the first embodiment.

[0045] First, n-type semiconductor layers are formed in the IGBT region 21 by photolithography and etching. + The n-type emitter region 3, the p-type base region 2, and the n-type accumulation layer 5 are -Trenches 6 are formed so as to reach the type drift region 1 (step S11: third process). The state up to this point is shown in FIG. 3. When viewed from the front surface side of the semiconductor wafer 10, the trenches 6 are arranged in a stripe-like layout extending in a direction (depth direction in FIG. 1 ) perpendicular to the direction in which the IGBT region 21 and the FWD region 22 are aligned (horizontal direction in FIG. 1 ).

[0046] The trenches 6 are also formed in the FWD region 22 in the same layout as in the IGBT region 21. In the FWD region 22, the trenches 6 penetrate the p-type base region 2 (p-type anode region) to form n-type trenches. - The insulating film 31 reaches the mold drift region 1. Next, an insulating film 31 is formed along the inner wall of the trench 6 by, for example, thermal oxidation (step S12: fourth process). The state up to this point is shown in FIG.

[0047] Next, a polysilicon (poly-Si) film 32 is formed on the front surface of the semiconductor wafer 10 so as to fill the trenches 6 (step S13: fifth process). The state up to this point is shown in FIG. 5. Here, the filling condition for the polysilicon film 32 is such that the trenches 6 are not completely filled. As a result, the trenches 6 are not sufficiently filled with the polysilicon film 32, and a slit 35 is formed. The width of the slit 35 is approximately 0.2 μm, which is about 1 / 5 of the width of the trenches 6, for example, between 0.16 μm and 0.28 μm. This is because if the width of the slit 35 is too narrow, it may not be possible to fill the TEOS film 30.

[0048] Next, the polysilicon film 32 is etched back, for example, to leave a portion that will become the gate electrode 8 inside the trench 6 (step S14: sixth step). The state up to this point is shown in FIG. After this etching, channel ions may be implanted into the p-type base region 2.

[0049] If etch-back is performed while the slits 35 are still formed, the polysilicon film 32 at the bottom of the trench 6 is etched, and the polysilicon film 32 is separated at the bottom. In this case, the gate electrode 7 is also separated at the bottom, which has the effect of reducing the mirror capacitance and speeding up switching.

[0050] Next, the insulating film 31 remaining on the front surface of the semiconductor wafer 10 is removed (step S15: seventh step). The state up to this point is shown in FIG. 7. The insulating film 31 remaining inside the trench 6 becomes the gate insulating film 7. After this, a high-temperature heat treatment is performed (step S16: eighth step). Next, the slit 35 is filled with a TEOS film 30 (step S17: ninth step). The state up to this point is shown in FIG. 8. Through the steps up to this point, the gate electrode 8 of the first embodiment is formed.

[0051] It is known that the film stress of the polysilicon film 32 changes depending on the film formation temperature and the heat treatment after embedding. On the other hand, it is also known that the film stress of the TEOS film 30 can be adjusted by adjusting the embedding conditions such as the film formation temperature and growth flow rate (see, for example, Reference 2 below). Therefore, by adjusting the embedding conditions of the TEOS film 30 and depositing it so as to offset the residual stress of the polysilicon film 32 after the heat treatment, the residual stress of the polysilicon film 32 can be offset.

[0052] (Reference 2) Mihaela CARP; Violeta DEDIU; Florian PISTRITU; Edwin A. LASZLO; Ciprian ILIESCU, “effective control of TEOS Effective control of TEOS-PECVD thin film depositions”, 2020 International Semiconductor Conference (CAS)

[0053] As described above, in the first embodiment, when the trench 6 is filled with the polysilicon film 32, the polysilicon film 32 is filled so as to form the slit 35, and the TEOS film 30 is filled into the slit 35 to cancel out the residual stress of the polysilicon film 32. Therefore, according to the semiconductor device manufacturing method of the first embodiment, it is possible to suppress warpage and distortion of the wafer due to stress such as thermal expansion of the polysilicon film 32 caused by filling the trench 6, and to suppress warpage and slip defects throughout the wafer. It is also possible to suppress high-order in-plane distortion of the wafer due to stress. As a result, it is possible to reduce the characteristic variation of the semiconductor device and realize improved reliability.

[0054] Returning to the explanation of the manufacturing method of the semiconductor device, the p-type base region 2 and the n + type emitter region 3, p + The contact region 4, the trench 6, the gate insulating film 7, and the gate electrode 8 constitute a MOS gate having a trench structure. + type emitter region 3, p + An n-type contact region 4 and an n-type accumulation layer 5 may be formed. + The n-type emitter region 3 may be disposed in at least one mesa region between adjacent trenches 6 (mesa regions). + There may be a mesa region in which the n-type emitter region 3 is not disposed. + The emitter regions 3 may be selectively arranged at predetermined intervals in the direction in which the trenches 6 extend in a stripe shape.

[0055] Next, after forming the surface device structure, an interlayer insulating film 9 made of two layers, for example, a BPSG film and an HTO film, is formed on the front surface of the semiconductor wafer 10 so as to cover the gate electrode 8 (step 10). Next, the interlayer insulating film 9 is patterned to form a plurality of contact holes 20 penetrating the interlayer insulating film 9 in the depth direction. The depth direction is the direction from the front surface to the back surface of the semiconductor wafer 10. The contact holes 20 in the IGBT region 21 are provided with n-type contact holes. + type emitter region 3 and p + The p-type contact region 4 is exposed. The p-type base region 2 is exposed in the contact hole 20 of the FWD region 22.

[0056] Next, a Ti film is formed uniformly by sputtering inside the contact hole 20 and on the surface of the interlayer insulating film 9. Next, a TiN film 18 is formed by sputtering on the surface of the Ti film 17. As a result, a barrier metal 25 is stacked on the interlayer insulating film 9 and inside the contact hole 20.

[0057] Next, the surface of the TiN film 18 and the inside of the contact hole 20 are filled with the plug electrode 15 by, for example, sputtering. Next, the Ti film 17, the TiN film 18, and the plug electrode 15 in the contact hole 20 are removed by etching, and the plug electrode 15 is formed in the contact hole 20.

[0058] Next, an Al metal film that will become the front electrode 11 is formed by, for example, sputtering. The metal film may be made of, for example, aluminum containing 1% silicon (Al-Si). Next, the Al metal film is patterned. Next, the patterned Al metal film is annealed in a hydrogen atmosphere to form the front electrode 11.

[0059] The front surface electrode 11 is connected to the p-type base region 2 and the n-type + type emitter region 3 and p + The front surface electrode 11 is electrically connected to the p-type contact region 4 and functions as an emitter electrode. The front surface electrode 11 is electrically connected to the p-type base region 2 in the FWD region 22 and functions as an anode electrode. + The p-type emitter region 3 may be electrically connected to the p-type base region 2 in the mesa region where the p-type emitter region 3 is not disposed.

[0060] Next, the semiconductor wafer 10 is ground from the backside to a thickness corresponding to the thickness of the semiconductor device. Next, a set of photolithography and ion implantation processes is repeatedly performed under different conditions to form a backside device structure on the backside of the semiconductor wafer 10. For example, an n-type field stop (FS) layer 12, an n-type field stop (FS) layer 13, and an n-type field stop (FS) layer 14 are formed on the backside of the semiconductor wafer 10. + type cathode region 14 and p + A mold collector region 13 is formed.

[0061] n + The n-type cathode region 14 is formed over the entire back surface of the semiconductor wafer 10 in a surface layer on the back surface of the semiconductor wafer 10 after grinding. The n-type field stop layer 12 is formed on the n-type field stop layer 12 from the back surface of the semiconductor wafer 10 after grinding. +The n-type field stop layer 12 is formed at a position deeper than the n-type cathode region 14. The n-type field stop layer 12 is formed at least from the IGBT region 21 to the FWD region 22. The n-type field stop layer 12 is + The cathode region 14 may be in contact with the cathode region 14 .

[0062] Next, photolithography and ion implantation are performed to form n + The portion of the cathode region 14 corresponding to the IGBT region 21 is p + By changing it to the type p + A p-type collector region 13 is formed. + The collector region 13 is n-type in the direction in which the IGBT region 21 and the FWD region 22 are aligned. + The cathode region 14 is in contact with the + The n-type collector region 13 may be in contact with the n-type field stop layer 12 in the depth direction.

[0063] Next, by heat treatment (annealing), p + collector region 13 and n + The FS layer 12 is activated. Next, a passivation film is formed on the front surface of the semiconductor wafer 10 so as to cover the edge termination region. Next, the passivation film is patterned to expose the emitter electrode, anode electrode, and each electrode pad. Ni-P plating is grown on the emitter electrode and anode electrode, and Au plating is grown thereon to form surface electrodes (step 11).

[0064] Next, a photoresist film (not shown) having openings corresponding to the FWD regions 22 is formed on the front surface of the semiconductor wafer 10. Using this photoresist film as a mask (shielding film), helium is irradiated with high acceleration energy and a deep range to form n - A lifetime control region 26 may be formed by introducing (forming) helium defects that act as lifetime killers inside the mold drift region 1 .

[0065] Then, the photoresist film is removed by ashing. Next, a back surface electrode 24 is formed on the entire back surface of the semiconductor wafer 10 (twelfth step). The back surface electrode 24 is p +collector region 13 and n + The back electrode 24 functions as a collector electrode and also as a cathode electrode. The semiconductor wafer 10 is then cut (diced) into individual chips, thereby completing the RC-IGBT chips 150 (semiconductor chips).

[0066] As described above, according to the first embodiment, a TEOS film is buried inside the gate electrode in the trench. The TEOS film can offset the residual stress of the polysilicon film. This makes it possible to suppress warping and distortion of the wafer due to stress such as thermal expansion of the polysilicon film buried in the trench, and suppress warping and slip defects throughout the wafer. It is also possible to suppress high-order in-plane distortion of the wafer due to stress. As a result, it is possible to reduce the characteristic variations of the semiconductor device and realize improved reliability. Furthermore, the TEOS film penetrates the gate insulating film at the bottom of the trench and forms an n-type TEOS film. - The gate electrode is in contact with the gate drift region, which separates it at the bottom of the trench, reducing Miller capacitance and allowing for faster switching.

[0067] Second Embodiment Next, a second embodiment will be described. FIG. 9 is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. In the second embodiment, the structure of the trench 6 is different from that of the first embodiment. In the second embodiment, a TEOS film 30 is embedded inside the gate electrode 8 in the trench 6, as in the first embodiment. However, the gate insulating film 7 and the gate electrode 8 are provided at the bottom of the trench 6, and the TEOS film 30 does not penetrate the gate insulating film 7 at the bottom of the trench 6. In the second embodiment, as in the first embodiment, the TEOS film 30 can offset the residual stress of the polysilicon film 32. Furthermore, it is preferable that the TEOS film 30 be provided between the gate electrode 8 and the interlayer insulating film 9.

[0068] (Method of manufacturing a semiconductor device according to a second embodiment) Next, a method of manufacturing a semiconductor device according to a second embodiment will be described. Since the method of manufacturing a semiconductor device according to the first embodiment is the same as the method of manufacturing a semiconductor device according to the first embodiment except for the formation of the gate electrode 8, the formation of the gate electrode 8 will be described. Fig. 10 is a flowchart showing the procedure for forming a gate electrode in the method of manufacturing a semiconductor device according to the second embodiment. Figs. 11 to 15 are cross-sectional views schematically showing the formation of a gate electrode in the method of manufacturing a semiconductor device according to the second embodiment.

[0069] First, n-type semiconductor layers are formed in the IGBT region 21 by photolithography and etching. + The n-type emitter region 3, the p-type base region 2, and the n-type accumulation layer 5 are - A trench 6 is formed so as to reach the mold drift region 1 (step S21). The state up to this point is the same as in the first embodiment, so a description thereof will be omitted (see FIG. 3). Next, an insulating film 31 is formed along the inner wall of the trench 6 by, for example, thermal oxidation (step S22). The state up to this point is the same as in the first embodiment, so a description thereof will be omitted (see FIG. 4).

[0070] Next, a polysilicon (poly-Si) film 32 is formed on the front surface of the semiconductor wafer 10 so as to fill the trenches 6 (step S23). The state up to this point is the same as in the first embodiment, so a description thereof will be omitted (see FIG. 5). Here, the conditions for filling the polysilicon film 32 are such that the trenches 6 are not completely filled. As a result, the trenches 6 are not sufficiently filled with the polysilicon film 32, and slits 35 are formed.

[0071] Next, the slits 35 are filled with positive resist 33. The state up to this point is shown in FIG. 11. Next, the positive resist 33 is exposed to light. In this case, the positive resist 33 at the bottom of the slits 35 is not exposed to light, so a positive resist process is carried out in which the positive resist 33 remains at the bottom of the slits 35 (step S24: thirteenth process). The state up to this point is shown in FIG. 12.

[0072] Next, the polysilicon film 32 is etched back, for example, to leave a portion that will become the gate electrode 8 inside the trench 6 (step S25). Because the positive resist 33 remains at the bottom of the slit 35, the polysilicon film 32 in the slit 35 is not etched even when etched back. The state up to this point is shown in FIG. 13. After this etching, channel ion implantation may be performed on the p-type base region 2. In this case, ions are not implanted into the bottom of the trench 6 because the positive resist 33 at the bottom of the slit 35 serves as a mask for ion implantation.

[0073] Next, the positive resist 33 at the bottom of the slit 35 is removed (step S26: fourteenth step). Next, the insulating film 31 remaining on the front surface of the semiconductor wafer is removed (step S27). The state up to this point is shown in FIG. 14. The insulating film 31 remaining inside the trench 6 becomes the gate insulating film 7. After this, a high-temperature heat treatment is performed (step S28). Next, a TEOS film 30 is buried (step S29). The state up to this point is shown in FIG. 15. At this time, as in the first embodiment, the burying conditions for the TEOS film 30 are adjusted to cancel out the residual stress of the polysilicon film 32 after the heat treatment, thereby canceling out the residual stress of the polysilicon film 32. Through the steps up to this point, the gate electrode 8 of the second embodiment is formed.

[0074] As described above, according to the second embodiment, a TEOS film is embedded inside the gate electrode in the trench. The TEOS film can offset the residual stress of the polysilicon film. This can suppress warping and distortion of the wafer due to stress such as thermal expansion of the polysilicon film embedded in the trench, thereby suppressing warping and slip defects throughout the wafer. In addition, high-order in-plane distortion of the wafer due to stress can also be suppressed. As a result, it is possible to reduce the characteristic variations of the semiconductor device and achieve improved reliability.

[0075] Third Embodiment Next, a third embodiment will be described. FIG. 16 is a cross-sectional view showing the structure of a semiconductor device according to the third embodiment. In the third embodiment, the structure of the trench 6 is different from that of the first embodiment. In the third embodiment, unlike the first embodiment, an SOG (spin-on-glass) film 34 is embedded inside the gate electrode 8 in the trench 6. Preferably, the SOG film 34 is provided between the gate electrode 8 and the interlayer insulating film 9. The trench 6 has a width of 0.8 μm to 1.4 μm and a depth of 5 μm to 6 μm. The width of the SOG film 34 is approximately 0.2 μm, which is about ⅕ of the width of the trench 6, for example, 0.16 μm to 0.28 μm.

[0076] Unlike the TEOS film 30, the SOG film 34 cannot offset the residual stress of the polysilicon film 32. However, in the third embodiment, slits 35 are formed when the trenches 6 are filled with the polysilicon film 32 (see FIG. 18 ). The SOG film 34 shrinks by approximately 10% after heat treatment, depending on the material. Therefore, adjusting the width of the SOG film 34 can offset the expansion of the polysilicon film 32 and alleviate the stress. Furthermore, the slits 35 can reduce stress more than conventional methods. This method can be used in configurations where the stress caused by the polysilicon film 32 is small, such as configurations where the trenches 6 are widely spaced and have a low density, thereby suppressing warpage and slip defects throughout the wafer. Furthermore, it can also suppress high-order in-plane distortion of the wafer due to stress.

[0077] (Method of manufacturing a semiconductor device according to a third embodiment) Next, a method of manufacturing a semiconductor device according to a third embodiment will be described. Since the method of manufacturing a semiconductor device according to the first embodiment is the same as the method of manufacturing a semiconductor device according to the first embodiment except for the formation of the gate electrode 8, the formation of the gate electrode 8 will be described. Fig. 17 is a flowchart showing the procedure for forming a gate electrode in the method of manufacturing a semiconductor device according to the third embodiment. Figs. 18 and 19 are cross-sectional views schematically showing the formation of a gate electrode in the method of manufacturing a semiconductor device according to the third embodiment.

[0078] First, n-type semiconductor layers are formed in the IGBT region 21 by photolithography and etching. +The n-type emitter region 3, the p-type base region 2, and the n-type accumulation layer 5 are - A trench 6 is formed so as to reach the mold drift region 1 (step S31). The state up to this point is the same as in the first embodiment, so a description thereof will be omitted (see FIG. 3). Next, an insulating film 31 is formed along the inner wall of the trench 6 by, for example, thermal oxidation (step S32). The state up to this point is the same as in the first embodiment, so a description thereof will be omitted (see FIG. 4).

[0079] Next, a polysilicon (poly-Si) film 32 is formed on the front surface of the semiconductor wafer 10 so as to fill the trenches 6 (step S33). The process up to this point is the same as in the first embodiment, so a detailed description is omitted (see FIG. 5). The conditions for filling the polysilicon film 32 are such that the trenches 6 are not completely filled. Therefore, the trenches 6 are not sufficiently filled with the polysilicon film 32, forming slits 35. Next, an SOG film 34 is deposited so as to fill the slits 35 (step S34: sixth step). The process up to this point is illustrated in FIG. 18. Next, the SOG film 34 on the device surface is removed by etch-back (step S35: seventh step). This removes the polysilicon film 32 and insulating film 31 from the front surface of the semiconductor wafer 10, and the SOG film 34 fills the slits 35. After this, channel ions may be implanted into the p-type base region 2. The insulating film 31 remaining inside the trenches 6 becomes the gate insulating film 7. High-temperature heat treatment is then performed (step S36). Through the steps up to this point, the gate electrode 8 of the third embodiment is formed.

[0080] As described above, according to the third embodiment, an SOG film is buried inside the gate electrode in the trench. In the third embodiment, a slit is formed when the trench is filled with a polysilicon film. This slit can reduce stress more than conventional methods. This can be used in a configuration where the stress caused by the polysilicon film is small, for example, in a configuration where the trench spacing is wide, and warpage and slip defects can be suppressed throughout the wafer. In addition, high-order in-plane distortion of the wafer due to stress can also be suppressed.

[0081] In the above, the present disclosure has been described using an example in which a MOS gate structure is configured on the first main surface of a silicon substrate. However, this is not a limitation, and various changes are possible for the type of semiconductor (e.g., silicon carbide (SiC)), the surface orientation of the substrate main surface, and the like. Furthermore, while the embodiments of the present disclosure have been described using a trench IGBT as an example, this is not a limitation, and the present disclosure is applicable to semiconductor devices with various configurations, such as MOS semiconductor devices such as trench MOSFETs. Furthermore, in each embodiment of the present disclosure, the first conductivity type is n-type and the second conductivity type is p-type. However, the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type.

[0082] As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are useful for high-voltage semiconductor devices used in power conversion devices and power supply devices for various industrial machines and the like.

[0083] 1n - n-type drift region 2 p-type base region 3 + Type emitter region 4p + 1. Type contact region 5: n-type accumulation layer 6, 106: trench 7, 107: gate insulating film 8, 108: gate electrode 9: interlayer insulating film 10: semiconductor wafer 11: front electrode 12: n-type field stop layer 13: p + Mold collector region 14 n + REFERENCE SIGNS LIST 15 Plug electrode 17 Ti film 18 TiN film 20 Contact hole 21 IGBT region 22 FWD region 24 Back electrode 25 Barrier metal 26 Lifetime control region 30 TEOS film 31 Insulating film 32 Polysilicon film 33 Positive resist 34 SOG film 35 Slit 110 Slip defect 111 Interface 112 Silicon layer 150 RC-IGBT T stress

Claims

1. A semiconductor device comprising: a first semiconductor layer of a second conductivity type provided on the front surface side of a semiconductor substrate of a first conductivity type; a first semiconductor region of a first conductivity type selectively provided in a surface layer of the first semiconductor layer opposite to the semiconductor substrate side; a trench that penetrates the first semiconductor region and the first semiconductor layer and reaches the semiconductor substrate; a gate electrode provided inside the trench via a gate insulating film; an interlayer insulating film provided on the gate electrode; a first electrode provided on the surfaces of the first semiconductor region and the first semiconductor layer; and a second electrode provided on the back surface of the semiconductor substrate, wherein the trench has a TEOS film embedded inside the gate electrode.

2. The semiconductor device according to claim 1, wherein said TEOS film penetrates said gate insulating film at the bottom of said trench and contacts said semiconductor substrate.

3. The semiconductor device according to claim 1, wherein the TEOS film is provided between the gate electrode and the interlayer insulating film.

4. The semiconductor device according to claim 1, wherein the trench is filled with an SOG film instead of the TEOS film.

5. The semiconductor device according to any one of claims 1 to 3, wherein the width of the TEOS film is not less than 0.16 µm and not more than 0.28 µm.

6. A first step of forming a first semiconductor layer of a second conductivity type on the front surface side of a semiconductor substrate of a first conductivity type; a second step of selectively forming a first semiconductor region of a first conductivity type in a surface layer of the first semiconductor layer on the side opposite to the semiconductor substrate; a third step of forming a trench penetrating the first semiconductor region and the first semiconductor layer and reaching the semiconductor substrate; a fourth step of forming an insulating film along the inner wall of the trench; a fifth step of embedding a polysilicon film so as to form a slit inside the trench; a sixth step of etching back the polysilicon film to leave a portion that will become a gate electrode inside the trench; a seventh step of removing the insulating film on the surface of the first semiconductor region and the first semiconductor layer to leave a portion that will become a gate insulating film inside the trench; an eighth step of subjecting the semiconductor substrate to high temperature heat treatment; a ninth step of embedding a TEOS film in the slit; a tenth step of forming an interlayer insulating film on the gate electrode; and an eleventh step of forming a first electrode on the surface of the first semiconductor region and the first semiconductor layer. a twelfth step of forming a second electrode on a rear surface of the semiconductor substrate.

7. The method for manufacturing a semiconductor device according to claim 6, further comprising a thirteenth step, after the fifth step and before the sixth step, of filling the slits with positive resist and exposing the positive resist to leave the positive resist at the bottom of the slits, and a fourteenth step, after the sixth step and before the seventh step, of removing the positive resist at the bottom of the slits.

8. A method for manufacturing a semiconductor device comprising: a first step of forming a first semiconductor layer of a second conductivity type on a front surface side of a semiconductor substrate of a first conductivity type; a second step of selectively forming a first semiconductor region of a first conductivity type in a surface layer of the first semiconductor layer opposite to the semiconductor substrate side; a third step of forming a trench that penetrates the first semiconductor region and the first semiconductor layer and reaches the semiconductor substrate; a fourth step of forming an insulating film along an inner wall of the trench; a fifth step of filling the trench with a polysilicon film so as to form a slit; a sixth step of depositing an SOG film so as to fill the slit; a seventh step of removing the SOG film and the insulating film from the surfaces of the first semiconductor region and the first semiconductor layer and leaving a portion that will become a gate insulating film inside the trench; an eighth step of subjecting the semiconductor substrate to a high-temperature heat treatment; a ninth step of forming an interlayer insulating film on the gate electrode; a tenth step of forming a first electrode on the surfaces of the first semiconductor region and the first semiconductor layer; and an eleventh step of forming a second electrode on the back surface of the semiconductor substrate.

Images