Design assistance system, design assistance device, and design assistance method

Abstract

Provided is a design assistance system for a semiconductor integrated circuit, the system capable of shortening the product development period in low-volume diversified production. The design assistance system assists the design of circuits for a semiconductor device manufactured in cooperation with a plurality of functional circuit forming fabs and a post-wiring process fab. The plurality of functional circuit forming fabs handle, among pre-processes, a pre-wiring process for independently forming functional circuit blocks corresponding to individual functions, and said fabs stock the functional circuit blocks in a wafer bank. A functional circuit design tool supplying server 1000 selects a functional circuit block corresponding to an individual function for achieving the desired overall function, and assists design for disposing the functional circuit block on a semiconductor substrate. A post-wiring design tool supplying server 2000 assists pattern design and logic design of a post-wiring process in which the plurality of functional circuit blocks are selectively connected using a design rule different than that for the pre-wiring process.

Description

Design support system, design support device, and design support method

[0001] The present invention relates to a design support system, a design support device, and a design support method for supporting a design process for forming a semiconductor integrated circuit on a semiconductor substrate.

[0002] (Development trends of semiconductor integrated circuits)

[0003] In semiconductor integrated circuits formed on semiconductor substrates typified by silicon (Si) semiconductors, performance has been improved by increasing the number of active devices such as transistors formed on one chip, in other words, by increasing the degree of integration.

[0004] Since the development and practical application of large-scale semiconductor integrated circuits (LSIs), Moore's Law has been used as an empirical rule of thumb to predict the long-term trends in their manufacturing and production. Initially, Moore's Law stated that the number of transistors on an integrated circuit will double every two years. While Moore's Law has generally maintained its trend over the long term due to improvements in the transistor structure of semiconductor integrated circuits and advances in microfabrication technology, its limitations have been pointed out in recent years.

[0005] For example, taking a typical transistor structure, CMOS (Complementary Metal-Oxide-Semiconductor) transistor, one of the challenges in miniaturization is suppressing short channel effects when P-channel FET transistors and N-channel FET transistors are configured planarly on a silicon substrate. Therefore, developments have been made to change the FET (Field Effect Transistor) from a planar (flat) type FET to a FinFET, which improves performance by changing the shape of the silicon substrate from a flat type to a fin (fish fin) type, as well as a Gate-All-Around type nanosheet structure in which the gate surrounds the entire periphery of the channel.

[0006] As a result, the most advanced process currently being developed and put into practical use for logic ICs in semiconductor integrated circuits is an ultra-fine technology, sometimes called the "2 nm process."

[0007] However, the applications of semiconductor integrated circuits are not limited to chips for processing artificial intelligence calculations, which require such cutting-edge processes, but are actually widely distributed, including those that require semiconductor integrated circuits manufactured using processes based on earlier miniaturization technology.

[0008] Furthermore, the wiring width / wiring spacing pitch formed using cutting-edge EUV (Extreme Ultraviolet Lithography) lithography is approximately 20-30 nm, and the term "2 nm process" is a symbolic name used due to so-called "area scaling" rather than referring to the planar wiring processing dimensions as transistor structures become three-dimensional. In reality, integrated circuits with looser processing accuracy depending on the transistor structure, such as those called "22-28 nm process," are currently widely used for automotive control applications and as "logic processing LSIs" mounted on the back of image sensors.

[0009] Meanwhile, in the past, semiconductor integrated circuit manufacturing was vertically integrated, with a single company handling everything from design to circuit formation on semiconductor substrates (semiconductor wafers), cutting chips from the semiconductor wafers, bonding, and packaging. However, nowadays, semiconductor integrated circuits are generally manufactured through horizontal division of labor, with fabless companies in charge of design, foundry companies (hereinafter simply referred to as "fabs") in charge of wafer processing, and assembly companies in charge of assembly.

[0010] FIG. 31 is a conceptual diagram showing a conventional manufacturing process for a semiconductor device.

[0011] Referring to Figure 31, the front-end process is also called the wafer process, and is a process for manufacturing LSI chips on a silicon wafer. In contrast, the back-end process is an assembly process in which the LSI chips (also called "dies" in the back-end process) completed on the wafer are cut out individually and packaged. In the front-end process, the workpiece to be worked on is in the form of a silicon wafer, whereas in the back-end process, it may be a silicon wafer, a chip, or a packaged chip.

[0012] As shown in Figure 31, currently, front-end and back-end processes are often performed in separate fabs. In the front-end process, the front-end process mainly refers to the process up to transistor formation, while the back-end process refers to the wiring process thereafter. (ASIC and cell-based design)

[0013] In particular, as mentioned above, unlike general-purpose semiconductor integrated circuits, application-specific integrated circuits often do not necessarily need to be manufactured using cutting-edge processes. Here, application-specific integrated circuits are generally called ASICs (application specific integrated circuits), and refer to integrated circuits that combine multiple circuits with different functions for a specific application.

[0014] ASICs can be broadly divided into "full-custom ICs," in which logic circuits are built from scratch, and "semi-custom ICs," in which designs are made by combining basic circuits and functional blocks. Naturally, full-custom ICs require a longer development period and higher development costs.

[0015] On the other hand, semi-custom ICs that aim to mitigate these disadvantages include the "gate array" method, in which a semi-finished product filled with basic logic circuits is prepared and functions are implemented by specifying the wiring between the circuits, and the "standard cell" method, in which modularized circuits (cells) that implement a certain degree of functionality are combined.

[0016] A cell-based integrated circuit (IC) designed using the "standard cell" method is configured as an integrated circuit that mixes large-scale circuit blocks (megacells and macrocells) based on standard cells, for example.

[0017] Conventionally, cell-based semi-custom design methods have been widely adopted for ASIC design, and this design method aims to improve the efficiency of IC design by combining common design assets (Intellectual Property: IP) registered in libraries and using automatic placement and routing tools.

[0018] Patent Document 1 discloses a semiconductor integrated circuit designed to include a plurality of basic cells each having a predetermined function and interconnected by internal wiring, a wiring region formed on a semiconductor substrate and having external wiring connecting the basic cells, power supply wiring and ground wiring for supplying power to the semiconductor elements, a first decoupling capacitor formed on the semiconductor substrate and consisting only of pMOS transistors, and a second decoupling capacitor formed on two metal layers on the semiconductor substrate. The decoupling capacitor cell, consisting of the first decoupling capacitor and the second decoupling capacitor, is arranged in an unused region not occupied by the basic cells, and is connected to the power supply wiring and ground wiring, thereby enabling the design of a cell-based IC that can reduce power consumption and ground noise.

[0019] Meanwhile, in response to the increasing sophistication and multi-functionality of functions to be realized by semiconductor integrated circuits, technologies are also being used in which a chip (die) produced in one semiconductor manufacturing factory and another chip (die) produced in another semiconductor manufacturing factory are assembled into a single package in a post-process. For example, known technologies include "2.5D packaging technology," which uses an interposer to arrange, connect, and mount multiple semiconductor chips in parallel, and "3D packaging technology," which mounts multiple semiconductor chips, including memories and microcontrollers, by stacking them in three dimensions within a package.

[0020] In this way, when semiconductor chips produced in different semiconductor manufacturing factories are combined and implemented, the designer designs the semiconductor device using two or more PDKs (Process Design Kits) provided by the foundries that manufacture each chip.

[0021] PDK is a collection of information necessary for designing custom ICs or analog ICs for a certain semiconductor process. Foundries that handle semiconductor front-end processes (including transistor manufacturing processes such as diffusion) often provide it to designers at fabless semiconductor manufacturers or IDMs (Integrated Device Manufacturers), who are users, for each process (see Non-Patent Document 1).

[0022] Custom ICs and analog ICs may require design on a transistor-by-transistor basis, and the PDK contains the necessary information for this, such as the circuit diagram symbols for the transistors in the process, the transistor SPICE (Simulation Program with Integrated Circuit Emphasis) model, transistor mask-level data (parameterized cell data such as PCELL and QCELL data), mask layout design constraints (so-called DRC (design rule checking) rules), and parasitic parameter extraction rules.

[0023] This information is used in IC design software called EDA (electronic design automation) tools. PDKs often also include design guidelines and design examples (reference designs).

[0024] In contrast to PDKs for custom IC and analog IC design, the information provided by foundries to digital LSI designers is often simply called a "design kit." This is also prepared for each process. The basis of a design kit is various design data (models for EDA tools) for the basic design elements of that process (standard cells and macrocells). Like PDKs, it often also includes design guidelines and design examples (reference designs).

[0025] Patent Document 2 discloses a PDK creation method and a PDK creation program that enable simultaneous design of all layers of a stacked IC. Specifically, the PDK creation method of Patent Document 2 includes acquiring multiple design information libraries corresponding to multiple chips used in a semiconductor device, assigning a different identifier to each character string included in the design information library, and integrating the multiple design information libraries. By assigning a different identifier to each character string included in the design information library, the names of simulation models and the like can be made different for each design information library. Therefore, multiple design information libraries are integrated while avoiding duplication of simulation model names and the like. It is then disclosed that by using the design information library thus created, it becomes possible to simultaneously design all layers of a stacked IC.

[0026] JP 2013-201158 A JP 2017-156877 A

[0027] https: / / xtech.nikkei.com / dm / article / WORD / 20130115 / 260353 /

[0028] As explained above, compared to standard logic ICs, standard memory ICs, programmable logic devices that rewrite circuit designs, and FPGAs, ASICs can offer advantages such as smaller mounting area, lower power consumption, faster operating speeds, and lower unit costs.

[0029] However, even if a semi-custom IC is designed using standard cell technology or the like, it is still necessary to complete the wafer process, test the device, and improve the design. This means that from the perspective of users such as fabless manufacturers, there are still problems of high development costs and long development times.

[0030] Furthermore, foundry companies are focusing on mass-producing a small variety of semiconductor chips using cutting-edge or semi-cutting-edge processes, which have high profit margins, and so tend to give lower priority to the manufacture of semiconductor integrated circuits, which have looser design standards. Moreover, as the diameter of semiconductor substrates (wafers) increases, it becomes necessary to order the manufacture of a considerable number of chips from foundries for each prototype. Repeating the process of prototyping and improvement increases TAT ​​(turn-around time), which is the time required to fully complete a product, and increases development costs.

[0031] On the other hand, for example, semiconductor integrated circuits that are premised on processing analog signals from sensors, such as those used in IoT (Internet of Things), often require high-mix, low-volume production.

[0032] As a result, there is a need for a design method and a manufacturing method of semiconductor integrated circuits that are suitable for small-lot production of a wide variety of products, rather than the product development of one-of-a-kind semiconductor products according to the conventional manufacturing model.

[0033] The present invention has been made to solve the above-mentioned problems, and aims to provide a design support system, design support device, and design support method for semiconductor integrated circuits that can shorten product development time in high-mix, low-volume production.

[0034] (Item 1) According to one aspect of the present invention, there is provided a design support system that provides a tool for supporting circuit design of a semiconductor device manufactured in cooperation with a plurality of semiconductor manufacturing sites, the plurality of semiconductor manufacturing sites including a plurality of first semiconductor manufacturing sites that are responsible for a pre-wiring process in a first manufacturing process under a first design rule, and at least one second semiconductor manufacturing site that is responsible for a post-wiring process in a second manufacturing process under a second design rule that is different from the first design rule, the system including a first design support device that supports design of a circuit pattern to be formed in the pre-wiring process on each of a plurality of dies on a semiconductor substrate, each die including a plurality of circuit blocks, the plurality of circuit blocks including a plurality of functional circuit blocks for respectively realizing a plurality of individual functions that constitute the overall function of the semiconductor device on the semiconductor substrate, the plurality of functional circuit blocks being configured to implement the first design rule based on the first design rule. The semiconductor manufacturing system includes a plurality of stock circuit blocks for which design information for circuit patterns corresponding to manufacturing processes for each semiconductor manufacturing site is prepared in advance, and the first design support device includes a first design support means for selecting a predetermined number of stock circuit blocks from the plurality of stock circuit blocks to realize an overall function and supporting a design for arranging the stock circuit blocks on a semiconductor substrate, and further includes a second design support device for supporting the design of a post-wiring pattern in a post-wiring process for selectively connecting the plurality of circuit blocks formed in the pre-wiring process, and the second design support device includes a second design support means for selecting a second semiconductor manufacturing site in accordance with the manufacturing process for manufacturing the selected plurality of stock circuit blocks and for supporting logic design and pattern design for the post-wiring process using a second design rule corresponding to the first design rule of the selected stock circuit blocks.

[0035] (Item 2) Preferably, in the configuration of item 1, the plurality of circuit blocks further include a plurality of adjustment circuit blocks that are provided on the semiconductor substrate separately from the plurality of functional circuit blocks and that perform tuning for the performance realized by each of the functional circuit blocks.

[0036] (Item 3) Preferably, in the configuration of item 2, the plurality of functional circuit blocks includes at least one custom circuit block for which circuit pattern design information is designed by a user based on a first design rule of a selected first semiconductor manufacturing site, the first design support device includes a storage device that stores correspondences that associate the plurality of semiconductor manufacturing sites with a plurality of circuit design core groups each including the plurality of functional circuit blocks in accordance with the manufacturing processes of the plurality of semiconductor manufacturing sites, and the first design support means performs support for logic design and pattern design of the custom circuit block based on the first design rule that corresponds to the first semiconductor manufacturing site selected in accordance with the circuit design core group.

[0037] (Item 4) Preferably, in the configuration of Item 3, when the first design support means determines that a plurality of stock circuit blocks is insufficient to achieve the overall performance, the first design support means prompts the user to design a custom circuit block.

[0038] (Item 5) Preferably, in the configuration of any one of Items 1 to 4, the correspondence includes a first correspondence with functional circuit blocks corresponding to each of a plurality of individual functions that make up the overall function, and a second correspondence with performance specifications for the individual functions of the functional circuit blocks and a plurality of circuit design core groups for realizing the respective performance specifications, and each circuit design core group includes design information of stock circuit blocks for defining a predetermined individual circuit pattern that can realize the performance specification for at least one of the individual functions.

[0039] (Item 6) Preferably, in the configuration of Item 5, the first design support module includes a core group selection means for selecting a circuit design core group including a combination of functional circuit blocks that can realize the overall function, and a design means for identifying a first semiconductor manufacturing site among a plurality of semiconductor manufacturing sites that corresponds to the selected circuit design core group, and for executing logic design and pattern design based on a first design rule of the identified first semiconductor manufacturing site.

[0040] (Item 7) Preferably, in the configuration of any one of items 2 to 5, the first design support device includes a mask pattern generation means for generating pattern data of an optical mask for executing an exposure process of dies on a semiconductor substrate, each of which forms a semiconductor device, by a divided projection exposure method, in at least a part of a pattern transfer process at the first semiconductor manufacturing site, and the second design support device includes a drawing data generation means for generating drawing data for forming a wiring pattern that connects a circuit block to a semiconductor substrate, in the pattern transfer process at the second semiconductor manufacturing site.

[0041] (Item 8) Preferably, in the configuration of Item 7, the first design rule of the selected stock circuit block includes an overlap margin for the connection portion at the via hole for connecting the wiring formed in the pre-wiring process and the wiring formed in the post-wiring process based on the second design rule.

[0042] (Item 9) Preferably, in the configuration of item 7 or 8, the drawing data generated by the drawing data generating means includes data of different wiring patterns in a post-wiring process for dies among the plurality of dies that have common patterns of functional circuit blocks and adjustment circuit blocks.

[0043] (Item 10) Preferably, in the configuration of Item 9, the different wiring patterns are wiring patterns that connect a common functional circuit block to different adjustment circuit blocks in a first die and a second die included in a die having a common pattern.

[0044] (Item 11) Preferably, in the configuration of any one of items 1 to 10, the plurality of functional circuit blocks include a variable function block in which the characteristics of individual functions can be changed by a post-wiring pattern, and the variable function block has a basic circuit pattern for realizing the individual function and a characteristic adjustment circuit pattern for adjusting the characteristics by the basic circuit pattern, and the second design support means supports a design in which the basic circuit pattern and the characteristic adjustment circuit pattern are connected by a post-wiring pattern common to a predetermined number of dies on the semiconductor substrate.

[0045] (Item 12) Preferably, in the configuration of Item 11, the characteristic adjustment circuit pattern includes a plurality of first passive circuit patterns, each of which is designed to have a first impedance value, and the post-wiring pattern common to the die includes a first post-wiring pattern that connects a number of the plurality of first passive circuit patterns to each other, the number of which is specified at the time of design.

[0046] (Item 13) Preferably, in the configuration of Item 12, the plurality of circuit blocks further include a plurality of adjustment circuit blocks provided on the semiconductor substrate separately from the plurality of functional circuit blocks, for tuning the performance realized by each of the functional circuit blocks.

[0047] (Item 14) Preferably, in the configuration of Item 13, the plurality of adjustment circuit blocks include a plurality of second passive circuit patterns, each of which is designed to have a second impedance value smaller than the first impedance value, and the post-wiring pattern includes a first post-wiring pattern that is common to a predetermined number of dies and a second post-wiring pattern that differs among the predetermined number of dies and connects the second passive circuit pattern to the first passive circuit pattern.

[0048] (Item 15) Preferably, in the configuration of any one of items 11 to 14, the basic circuit pattern is an analog circuit.

[0049] (Item 16) According to another aspect of the present invention, there is provided a computer-based design support method in which a tool operates to support circuit design of a semiconductor device manufactured in cooperation with a plurality of semiconductor manufacturing sites, the plurality of semiconductor manufacturing sites including a plurality of first semiconductor manufacturing sites responsible for a pre-wiring process in a first manufacturing process under a first design rule, and at least one second semiconductor manufacturing site responsible for a post-wiring process in a second manufacturing process under a second design rule different from the first design rule, the computer including an arithmetic unit and a memory device, the memory device storing design information of a plurality of circuit blocks, the plurality of circuit blocks including a plurality of functional circuit blocks for realizing, on a semiconductor substrate, a plurality of individual functions that constitute the overall function of the semiconductor device, the plurality of functional circuit blocks being manufactured in cooperation with a plurality of first semiconductor manufacturing sites based on the first design rule. The system includes a plurality of stock circuit blocks for which design information for circuit patterns corresponding to processes is prepared in advance, and includes a step in which an arithmetic device selects a predetermined number of stock circuit blocks from the plurality of stock circuit blocks to realize an overall function and supports the design of circuit patterns in a pre-wiring process for forming the plurality of circuit blocks on a semiconductor substrate, and a step in which the system supports the design of post-wiring patterns in a post-wiring process for selectively connecting the plurality of circuit blocks formed in the pre-wiring process, and the step of supporting the design of post-wiring patterns includes a step of selecting a second semiconductor manufacturing site in accordance with the manufacturing process that manufactured the selected plurality of stock circuit blocks, and performing support for logic design and pattern design for the post-wiring process using a second design rule that corresponds to the first design rule of the selected stock circuit blocks.

[0050] (Item 17) According to yet another aspect of the present invention, there is provided a design support device for a functional circuit that supports the design of a pre-wiring process in a design support system that provides tools to support the circuit design of a semiconductor device manufactured in cooperation with a plurality of semiconductor manufacturing sites, the plurality of semiconductor manufacturing sites including a plurality of first semiconductor manufacturing sites that are responsible for a pre-wiring process in a first manufacturing process under a first design rule, and at least one second semiconductor manufacturing site that is responsible for a post-wiring process in a second manufacturing process under a second design rule that is different from the first design rule, the device comprising a storage device that stores design information for a plurality of circuit blocks required for the design support, the plurality of circuit blocks being a plurality of functional circuit blocks for realizing, on a semiconductor substrate, each of a plurality of individual functions that constitute the overall function of the semiconductor device. The system further includes a processor for executing design support processing based on information stored in the storage device, the processor selecting a predetermined number of stock circuit blocks from the plurality of stock circuit blocks for realizing an overall function, supporting the design of arranging the circuit patterns in the pre-wiring process on the semiconductor substrate, and storing the design information of the arrangement of the circuit patterns in the pre-wiring process in a predetermined shared memory area for sharing in a design process of a post-wiring process for selectively connecting the plurality of circuit blocks formed in the pre-wiring process.

[0051] (Item 18) Preferably, in the configuration of Item 17, the design support device for functional circuits includes a mask pattern generation means for generating pattern data of an optical mask for performing exposure of dies on a semiconductor substrate, each of which forms a semiconductor device, by a divided projection exposure method in at least a part of the pattern transfer process at the first semiconductor manufacturing site, and the pattern transfer process at the second semiconductor manufacturing site is a process of directly drawing a wiring pattern that connects a circuit block to the semiconductor substrate.

[0052] (Item 19) Preferably, in the configuration of Item 18, the first design rule of the selected stock circuit block includes an overlap margin for the connection portion at the via hole to connect the wiring formed in the pre-wiring process with the wiring formed in the post-wiring process based on the second design rule.

[0053] (Item 20) According to yet another aspect of the present invention, in a design support system that provides a tool to support circuit design of a semiconductor device manufactured in cooperation with a plurality of semiconductor manufacturing sites, the design support device supports design of a post-wiring process in response to design of a pre-wiring process, the plurality of semiconductor manufacturing sites including a plurality of first semiconductor manufacturing sites that are responsible for a pre-wiring process in a first manufacturing process under a first design rule, and at least one second semiconductor manufacturing site that is responsible for a post-wiring process in a second manufacturing process under a second design rule that is different from the first design rule, the design support device includes a storage device that stores stock information of a plurality of semiconductor substrates that have been completed up to the formation of a plurality of circuit blocks for each of a plurality of dies in the pre-wiring process and are stocked, and the plurality of circuit blocks each perform a plurality of individual functions that constitute the overall function of the semiconductor device, on the semiconductor substrate. The semiconductor device further includes a computing device for executing design support processing based on information stored in the storage device, and the computing device selects a semiconductor substrate for performing a post-wiring process based on the stock information, and supports the design process of a post-wiring pattern in a post-wiring process for selectively connecting the plurality of circuit blocks formed in the pre-wiring process.

[0054] (Item 21) Preferably, in the configuration of Item 20, the design support device includes direct writing pattern generation means for generating direct writing data for executing the transfer of wiring patterns of dies on which semiconductor devices are respectively formed on a semiconductor substrate by a direct writing method in a pattern transfer process at the second semiconductor manufacturing site.

[0055] (Item 22) Preferably, in the configuration of item 20 or 21, the plurality of functional circuit blocks include a variable function block whose characteristics of individual functions can be changed by a post-wiring pattern, and the variable function block has a basic circuit pattern for realizing the individual function and a characteristic adjustment circuit pattern for adjusting the characteristics according to the basic circuit pattern, and the design support means supports a design that connects the basic circuit pattern and the characteristic adjustment circuit pattern by a post-wiring pattern that is common to a predetermined number of dies on the semiconductor substrate.

[0056] (Item 23) Preferably, in the configuration of Item 22, the characteristic adjustment circuit pattern includes a plurality of first passive circuit patterns, each of which is designed to have a first impedance value, and the post-wiring pattern common to the die includes a first post-wiring pattern that connects a number of the plurality of first passive circuit patterns to each other as specified at the time of design.

[0057] (Item 24) Preferably, in the configuration of Item 23, the plurality of circuit blocks further include a plurality of adjustment circuit blocks provided on the semiconductor substrate separately from the plurality of functional circuit blocks, for tuning the performance realized by each of the functional circuit blocks.

[0058] (Item 25) Preferably, in the configuration of Item 24, the plurality of adjustment circuit blocks includes a plurality of second passive circuit patterns, each of which is designed to have a second impedance value smaller than the first impedance value, and the post-wiring pattern includes a first post-wiring pattern common to a predetermined number of dies and a second post-wiring pattern that differs among the predetermined number of dies and connects the second passive circuit pattern to the first passive circuit pattern.

[0059] According to the present invention, it is possible to provide a design support system, a design support device, and a design support method for semiconductor integrated circuits that can shorten the product development period in high-mix low-volume production.

[0060] FIG. 1 is a conceptual diagram showing an overview of a manufacturing flow of a semiconductor device according to a first embodiment. FIG. 2 is a diagram showing an example of a cross-sectional structure of a semiconductor device according to the manufacturing flow of the present embodiment. FIG. 3 is a conceptual diagram for explaining a manufacturing process of the semiconductor device shown in FIG. 2. FIG. 4 is a conceptual diagram for explaining a configuration of a design platform of the design support system according to the present embodiment. FIG. 5 is a conceptual diagram for explaining an extracted portion of a server device that provides the design platform. FIG. 6 is a conceptual diagram showing an overview of the configuration of a function-fab relation DB1500.2. FIG. 7 is a diagram for explaining details of the configuration of a function-fab relation DB1500.2. FIG. 8 is a diagram for explaining details of the configuration of a function-fab relation DB1500.2. FIG. 9 is a diagram for explaining details of the configuration of a function-fab relation DB1500.2. FIG. 10 is a diagram showing the configurations of a functional circuit design tool providing server 1000, a post-wiring design tool providing server 2000, and designer terminals 5000.1 to 5000.P. FIG. 11 is a functional block diagram showing the configuration of a functional circuit design tool providing server 1000. FIG. 12 is a functional block diagram showing the configuration of a post-wiring design tool providing server 2000. 1 is a block diagram illustrating the hardware configuration of the functional circuit design tool providing server 1000. FIG. 2 is a flowchart illustrating the operation of the functional circuit design tool providing server 1000. FIG. 3 is a flowchart illustrating the operation of the functional circuit design tool providing server 1000. FIG. 4 is a flowchart illustrating the operation of the post-wiring design tool providing server 2000. FIG. 5 is a diagram illustrating a plurality of dies formed on a semiconductor substrate after a pre-wiring process. FIG. 6 is a diagram illustrating a plurality of dies formed on a semiconductor substrate after a post-wiring process. FIG. 7 is a diagram illustrating design rules for the top layer wiring in a wiring group in the pre-wiring process, and design rules for the contact portion between the top layer wiring M1 and the wiring M2 formed in the post-wiring process. FIG. 8 is a conceptual diagram illustrating various modified examples of the pattern of the contact portion between the top layer wiring and the wiring formed in the post-wiring process. FIG. 9 is a conceptual diagram illustrating a comparison of the flexibilities of design methods for digital circuits and analog circuits. FIG. 10 is a diagram illustrating the relationship between the "function," "characteristics," and "characteristic values" realized by a functional circuit, using an operational amplifier as an example. FIG. 11 is a diagram illustrating three types of design conditions for an "amplifier."25 is a circuit diagram showing a circuit configuration when the circuit with the three conditions shown in FIG. 24 is designed using a full custom method. FIG. 26 is a circuit diagram showing a circuit configuration when the circuit with the three conditions shown in FIG. 24 is designed using the design method of embodiment 2. FIG. 27 is a conceptual diagram showing a functional block and an adjustment circuit block for adjusting the performance of the functional block. FIG. 28 is a conceptual diagram showing a prototyping process when using the design method of embodiment 2 in comparison with a conventional prototyping process. FIG. 29 is a conceptual diagram explaining aspects of appropriation and reuse of design data within or between foundries. FIG. 29 is a conceptual diagram showing the effect of the design method of the embodiment. FIG. 30 is a conceptual diagram showing a conventional manufacturing process of a semiconductor device. cc.

[0061] The following describes the configurations of a design support system, a design support device, and a design support method for a semiconductor integrated circuit according to embodiments of the present invention. Note that in the following embodiments, components and processing steps denoted by the same reference numerals are the same or equivalent, and their description will not be repeated unless necessary.

[0062] In the following description, the software for supporting the design of semiconductor integrated circuits executed on the computer of the design support device of the present invention will be described as a computer program that is installed on a stand-alone computer device and executes support for circuit design.

[0063] However, the processing of the design support system may be distributed among multiple computer devices, and the computer processing may be executed by a single or multiple arithmetic units. Furthermore, the processing of the design support system is not limited to a program installed on such a general-purpose computer device, and may generally be realized as a dedicated arithmetic processing device that combines an arithmetic unit and a storage device. (Definition of Terms)

[0064] The definitions of terms used in this specification are as follows:

[0065] 1) "Semiconductor wafer": A typical example is a wafer cut from a single crystal silicon (Si) ingot and shaped to a specified thickness and diameter. However, the type of semiconductor is not limited to silicon and may be other semiconductors. Furthermore, the wafer may be made of an insulator wafer as the base material, with a semiconductor layer grown on the surface of this insulator wafer by a specified crystal growth method.

[0066] 2) "Through hole": A general term for the part in a semiconductor device that provides electrical continuity between wiring layers such as gate wiring and metal wiring. Examples include contact holes that connect the silicon substrate to upper wiring, cell contacts that connect capacitor electrodes to the substrate or wiring, and via holes that connect metal wiring.

[0067] 3) "Front-end process": This is the process of forming multiple integrated circuit chips (dies) on a semiconductor wafer, which are made up of multiple active elements (e.g., transistors) and which perform the overall function of the target device.

[0068] 4) "First semiconductor manufacturing site" and "second semiconductor manufacturing site": The "first semiconductor manufacturing site" is a site where the "front-end process" and "pre-wiring process" described below are performed in the wafer process for manufacturing the target semiconductor device. The "second semiconductor manufacturing site" is a site where the "post-wiring process" described below is performed in the wafer process for manufacturing the target semiconductor device. The "first semiconductor manufacturing site" and the "second semiconductor manufacturing site" may be separate plants, such as a "first semiconductor factory" and a "second semiconductor factory," respectively. Alternatively, at least one of multiple "first semiconductor manufacturing sites" and the "second semiconductor manufacturing site" may be located in different areas (e.g., different buildings) within the same plant. However, as described below, "semi-finished wafers" manufactured at the "first semiconductor manufacturing site" are temporarily stocked as inventory in a "wafer bank," and then, based on the selection of a circuit designer in the post-wiring process, selected wafers are sent to the manufacturing process at the "second semiconductor manufacturing site." Furthermore, the "first semiconductor manufacturing site" and the "second semiconductor manufacturing site" may be configured to employ different design rules and use different wiring formation process technologies.

[0069] 5) "Pre-wiring process": This pre-wiring process includes, within the first semiconductor manufacturing site, a process of forming active elements (e.g., transistors) on a semiconductor wafer (front-end process) and a process of electrically connecting multiple transistors using a wiring layer via contact holes opened in an insulating layer formed on the transistors (the first half of the back-end process). It includes at least a wiring process via cell contacts and may also include a metal wiring process via via holes. In the pre-wiring process, multiple semiconductor circuits of multiple types are formed on a semiconductor substrate, each corresponding to a separate function as an electrical circuit and including a functional circuit and an adjustment circuit.

[0070] 6) "Front-end process": A process in which active elements (e.g., transistors) are formed on a semiconductor wafer in a pre-processing step, and includes up to the metal filling step if metal filling (e.g., formation of W plugs) is performed in the contact holes of the transistor.

[0071] 7) "Back-end process": This refers to a process in the pre-processing stage in which multilayer wiring is formed after the front-end process. In silicon semiconductor processes, aluminum wiring (including alloys primarily made of Al) is often used for the lower layer wiring of multilayer wiring, while copper wiring is often used for the upper layer wiring. Furthermore, the so-called "dual damascene process" is often used for copper wiring. Note that all of the wiring layers in the back-end process may be aluminum wiring. Alternatively, all of the wiring layers in the back-end process may be copper wiring formed by the dual damascene process. However, the process for forming multilayer wiring is not limited to these examples.

[0072] 8) "Functional circuit": A plurality of circuits that realize, on a semiconductor substrate, each of the plurality of individual functions that constitute the overall function of the semiconductor device to be manufactured. The functional circuit may also include a "variable function circuit" whose individual functions and characteristics can be changed by subsequent wiring patterns. The variable function circuit includes a basic circuit and a characteristic adjustment circuit. Different circuit functions and characteristics can be realized by selectively connecting the basic circuit and the characteristic adjustment circuit by subsequent wiring patterns. The basic circuit includes, but is not limited to, active circuits such as operational amplifiers and diodes. The characteristic adjustment circuit is a passive circuit that includes resistors, capacitors, inductors, etc. An "active circuit" is a circuit that includes active elements that provide active functions such as amplifying, rectifying, and converting supplied electrical energy. A "passive circuit" is a circuit that includes at least one passive element that performs passive operations such as consuming, storing, and releasing supplied electrical energy.

[0073] 9) "Adjustment circuit": A plurality of circuits provided on a semiconductor substrate separately from the plurality of functional circuit blocks, for tuning the performance realized by each of the functional circuit blocks. The adjustment circuit may include active elements such as transistors (e.g., individual MOSFETs) in addition to passive circuits, as long as its purpose is to tune (fine-tune) the performance of the functional circuits. The adjustment circuit may also be realized as a collection of passive elements and transistors.

[0074] 10) "Post-wiring process": This refers to the process of forming wiring that connects functional circuits and adjustment circuits formed on a semiconductor chip at a second semiconductor manufacturing site different from the first semiconductor manufacturing site after the process of manufacturing transistors on a semiconductor wafer (front-end process) and the pre-wiring process are completed within a first semiconductor manufacturing site as the latter half of the back-end process among the pre-wiring processes. Although not particularly limited, the post-wiring process can be configured to include a process of forming an interlayer insulating film by direct imaging technology using a photosensitive organic insulating film and a process of forming copper wiring using dual damascene technology, which are performed as many times as necessary.

[0075] 11) "Back-end process": This includes the process in a back-end foundry where semiconductor chips (dies) are cut from wafers on which semiconductor circuits have been formed in the front-end process (front-end process + front-end wiring process + back-end wiring process), followed by bonding and assembly into packages and pre-shipment inspection. It may also include the process of forming plating wiring on the bonding pads formed in the front-end process as a base for bump formation to create a flip-chip configuration or a stacked structure. In other words, in the back-end process, a stacked structure chip connected to wafers may be formed by wafer-based flip-chip connection. The process of forming this plating wiring may also be included in the front-end process.

[0076] 12) "Design rule": In this specification, this refers to the minimum design width of wiring in a wafer process.

[0077] 13) "Semi-finished wafer": A semiconductor substrate (wafer) that is temporarily removed from the first semiconductor manufacturing site after the pre-wiring process is completed and stored in a designated storage area. Therefore, within the chip formed on the semiconductor substrate, multiple functional circuits and at least one adjustment circuit are formed through the front-end process and pre-wiring process. Preferably, a protective film, as described below, is formed over the substantially entire surface, and multiple through holes may be formed in this protective film for wiring connections in the post-wiring process.

[0078] 14) "Stock": This refers to semi-finished wafers that have completed the pre-wiring process being taken out of the first semiconductor manufacturing site and temporarily stored in a designated storage area. In the case where the "first semiconductor manufacturing site" and the "second semiconductor manufacturing site" are the "first semiconductor factory" and the "second semiconductor factory" operated by different businesses, this refers to semi-finished wafers being shipped from the first semiconductor factory and stored as inventory in a storage area (such as a storage warehouse). This storage area is called a "wafer bank."

[0079] Although the definitions of the above terms are based on typical technology at the time of filing this application, if the technical content and process flow of the semiconductor manufacturing process are improved or refined as technology advances, this does not prevent the definitions from being modified and interpreted within the scope of the spirit of the present invention as explained in the following specification.

[0080] In the first embodiment described below, a silicon semiconductor is used as an example of the semiconductor substrate, and a planar FET transistor is used as an example of the active element formed on the semiconductor substrate.

[0081] In addition, the pre-wiring process will be described assuming that aluminum wiring is used as the lower layer wiring, and the post-wiring process will be described assuming that copper wiring is formed using a direct imaging technique using a photosensitive organic insulating film as the interlayer insulating film and dual damascene technology. However, as mentioned above, the multilayer wiring process is not limited to this process flow. Also, as an example, the "first semiconductor manufacturing site" and the "second semiconductor manufacturing site" will be described assuming that they are separate factories, namely, a "first semiconductor factory" and a "second semiconductor factory." [Embodiment 1] (Outline of the manufacturing flow of embodiment 1)

[0082] FIG. 1 is a conceptual diagram showing an outline of a manufacturing flow of a semiconductor device according to the first embodiment.

[0083] Referring to FIG. 1, wafers are received and the first half of the front-end process (front-end process and pre-wiring formation process) is carried out by a plurality of semiconductor manufacturing factories corresponding to a plurality of functional circuit formation fabs 01 to N (N≧2, natural number).

[0084] As will be described later, the functional circuit fabrication fabs 01-N each use different semiconductor process technologies to form semiconductor chips on silicon wafers. Therefore, even if they are based on the same design, the functional circuits do not necessarily have the same characteristics or perform the same. Furthermore, the functional circuit fabrication fabs 01-N can manufacture different functional circuits with different performance characteristics, and the types of functional circuits they can manufacture also differ. Accordingly, the types and characteristics of the adjustment circuits formed by the functional circuit fabrication fabs 01-N also differ.

[0085] When the pre-wiring formation process is completed in the functional circuit formation fabs 01 to N, "functional circuits" and "adjustment circuits" according to the manufacturing process of each functional circuit formation fab 01 to N are formed on the semiconductor wafer.

[0086] Here, although the semiconductor wafers shipped from the functional circuit forming fabs 01-N have formed thereon the functional circuits that realize individual functions and the adjustment circuits that tune them, they do not have formed thereon the wiring that connects the functional circuits to each other, the functional circuits to the adjustment circuits, or the adjustment circuits to each other. For this reason, the "semiconductor device" that will ultimately be manufactured has not yet been formed on the semiconductor wafer, and only the individual components have been formed. Therefore, the semiconductor wafers shipped from the functional circuit forming fabs 01-N are called "semi-finished wafers."

[0087] Semi-finished wafers shipped from these multiple functional circuit forming fabs 01 to N are temporarily stored as inventory in a place called a wafer bank. Semi-finished wafers stored in a wafer bank are called "stock semiconductor wafers."

[0088] From the perspective of a designer of the "semiconductor device" that will ultimately be manufactured, there are cases where the semiconductor device that he or she has designed and is about to outsource manufacturing can be manufactured by connecting with wiring the functional circuits and adjustment circuits already formed on wafers stored in a wafer bank. In this case, it is possible to manufacture a prototype without the time required for the pre-wiring process.

[0089] Furthermore, in any of the multiple post-wiring process foundries 01 to M (M≧1, natural number), by connecting post-wiring onto stock semiconductor wafers stored in a wafer bank, it is possible to complete the prototyping of a "semiconductor device."

[0090] Furthermore, as will be explained later, the post-wiring formation process can be configured to use a direct imaging technique using a photosensitive organic insulating film as the interlayer insulating film and a dual damascene technique to form copper wiring.

[0091] In this case, the pre-wiring formation process can be a pattern transfer process using, for example, a stepper using a reticle or a segmented projection exposure method using reduced projection by a scanner. As a result, the combination of functional circuits and adjustment circuits created up to the pre-wiring process can include multiple patterns (e.g., two types of combined patterns) within the same reticle. However, when viewed as an entire semiconductor wafer, the same pattern of the combination of functional circuits and adjustment circuits is repeated the number of times equal to the number of exposure steps using the reticle. Here, "step" refers to the process of exposing the reticle in segmented projection exposure. In a stepper, a square area of ​​the reticle is exposed with a single light irradiation (one shot) in one step, whereas in a scanner, the reticle and wafer are synchronized and exposed by irradiating light while moving laterally across a long, narrow slit-shaped irradiation area.

[0092] Although not particularly limited, for example, assume that multiple functional circuits and multiple adjustment circuits are formed on the same die, and multiple chips (dies) are included within a single reticle. In this case, for example, the combination of functional circuits is common among the multiple chips (dies). However, the connection method between the adjustment circuits can be changed between the dies to match the characteristics and performance of the functional circuits. As a result, it is possible to manufacture a semiconductor device with desired performance by changing, within a single wafer, the "selection and connection method of adjustment circuits to be combined with functional circuits from among multiple adjustment circuits." However, in this case, the range of possible changes in the selection and connection of these adjustment circuits is limited at least to the number of chips (dies) within a single reticle. In other words, the range of change in this case is generally limited to the number of chips within a single reticle.

[0093] On the other hand, in this embodiment, although not particularly limited, the lithography process (pattern transfer process) for post-wiring is a process using a direct writing process. Furthermore, when a direct writing process is adopted, it is ultimately possible to form different post-wiring patterns based on the designer's design for each semiconductor chip manufactured on a single semiconductor wafer. In this case, there is no longer a restriction that the wiring pattern must be common between exposure steps for chips (dies) present in a reticle, as in the pre-wiring process.

[0094] In other words, for a chip (die) located at a specific position within one exposure step, if all steps up to the post-wiring process are exposed using a stepper or scanner that uses a reticle as a mask, the post-wiring will have the same pattern between different steps. In this case, the chip (die) at the specific position within the reticle has a common functional circuit pattern and adjustment circuit pattern between different steps.

[0095] On the other hand, if the post-wiring process is performed by direct writing, it is possible to provide different post-wiring connection patterns between chips (dies) on a semiconductor substrate.

[0096] As a result, the direct imaging process makes it possible to prototype a greater variety of "combinations of functional circuits" and the corresponding "selection and connection method of adjustment circuits to be combined with the functional circuits from among multiple adjustment circuits" within a single wafer than with the segmented projection exposure method.

[0097] As a result, performing the post-wiring process by direct writing is more desirable in terms of optimizing the method of connecting the post-wiring (post-wiring pattern) for one prototype lot than using the division projection exposure method.

[0098] In addition, when multi-layer wiring is performed in the pre-wiring process, the top-layer wiring in the pre-wiring process is the wiring that will be connected to the wiring in the subsequent wiring process. For example, direct writing technology can be used for lithography to form an etching mask for this top-layer wiring (e.g., Al wiring). In this case, the minimum lithography requirements for the top-layer wiring in the pre-wiring process are less strict than those for the lower-layer wiring. On the other hand, using direct writing technology in the pre-wiring process also has the advantage of increasing the degree of freedom in pattern variation during the initial prototype and in pattern revision after the initial prototype. In addition, the wiring layer that uses direct writing technology in the pre-wiring process is not limited to the top-layer wiring. Multiple wiring layers above the pre-wiring process may also be formed using direct writing technology.

[0099] Therefore, if a semiconductor device is manufactured using the manufacturing flow shown in FIG. 1, it is possible to provide a circuit design method that can address issues identified in the initial manufacturing of a semiconductor integrated circuit in a short period of time and at low cost.

[0100] That is, depending on the issues identified in the initial manufacturing, they may be able to be addressed by changing the wiring pattern in the post-wiring process. In such cases, in the second or subsequent manufacturing runs, the results of the initial prototype in which the pattern in the post-wiring process was significantly changed can be utilized to reduce the extent of the changes, making it possible to manufacture semiconductor chips with a good yield and equipped with the desired semiconductor integrated circuits.

[0101] Here, for example, the following are assumed to be issues that may become apparent during initial manufacturing: i) Degradation of performance due to items that are not adequately described in the specifications alone (parasitic elements, parasitic capacitance, noise, etc.) ii) Items that cannot be fully verified by simulation alone (circuit oscillation, input offset voltage, etc.) iii) Items that become apparent due to insufficient simulation caused by insufficient parasitic element settings or thermal design (thermal runaway, etc.) iv) Items that become apparent after the semiconductor integrated circuit has been manufactured (ESD (Electro-Static-Discharge) tolerance, EMI (Electro-Magnetic Interference) tolerance, etc.) v) Degradation of performance due to a mismatch with the process performance (component performance) of the manufacturing line

[0102] In the manufacturing flow shown in FIG. 1, the functional circuit and the adjustment circuit are arranged independently so that after the above-mentioned problems are identified, they can be solved by revising the design, and the connection between the functional circuit and the adjustment circuit can be changed as needed in a post-wiring process.

[0103] Moreover, since such changes are made only in the post-wiring process, there is a high possibility that the problem can be solved before the design change for solving the problem leads to a complete revision of the design.

[0104] As a result, it is possible to reduce the development period and development costs. (Example of a cross-sectional structure according to the manufacturing flow of this embodiment and details of the manufacturing flow)

[0105] FIG. 2 is a diagram showing an example of a cross-sectional structure of a semiconductor device according to the manufacturing flow of this embodiment.

[0106] 3A to 3C are conceptual diagrams for explaining the manufacturing process of the semiconductor device shown in FIG.

[0107] 2 and 3, in the design process, functional circuits corresponding to individual functions for achieving the overall function of the semiconductor device to be manufactured and adjustment circuits corresponding to these functional circuits are designed according to the procedure described below, thereby creating a photolithography mask for the processes (front-end process + pre-wiring process) to be carried out in the functional circuit formation fab. As described above, such a photolithography mask can be a reticle used in an optical stepper or scanner.

[0108] As shown in FIG. 2, the adjustment circuit ACKT is provided on the semiconductor substrate SUB separately from the functional circuit FCKT, and is a circuit for tuning the performance realized by the functional circuit ACKT.

[0109] After a mask is created and a semiconductor substrate SUB (bare wafer) is received at a functional circuit fabrication facility, the silicon wafer surface is thermally oxidized after undergoing prescribed cleaning and drying processes. A silicon nitride film is then formed on top of the oxide film using a low-pressure CVD (Chemical Vapor Deposition) method or similar. A shallow trench is then etched using step-by-step projection lithography to form a buried oxide film. The buried oxide film is formed using a CVD method or similar. The buried oxide film is then planarized using a CMP (Chemical Mechanical Polishing) process, and the oxide and nitride films are then removed to form an isolation region ISO. This is called shallow trench isolation (STI) technology. Depending on the processing dimensions, other methods for forming element isolation regions, such as LOCOS (Local Oxidation of Silicon) technology, may also be used.

[0110] Next, after forming a sacrificial oxide film, a well region for forming a MOSFET is formed by ion implantation and activation annealing. In the case of CMOS, a p-type P well and an n-type N well are formed to form a twin well, but in Figure 2, a single well is assumed.

[0111] Next, a gate oxide film GOF and a polysilicon film and a silicide film that will become a gate electrode material TG are laminated, and a resist pattern of the gate electrode is formed by photolithography using a division projection exposure method, and the gate electrode is formed by etching. After the resist is removed, a drain region DL and a source region SL are formed by ion implantation and annealing using, for example, a self-alignment technique.

[0112] Subsequently, an etching stopper layer and an interlayer insulating film, which are so-called PMD (Pre Metal Dielectrics) films, are formed by, for example, plasma CVD technology, and planarization is also performed here by CMP technology.

[0113] A resist pattern is then formed by photolithography using a step-and-step projection exposure method, and contact holes to the source region SL and the drain region DL are etched. After the resist is removed, a glue layer (TiN / Ti, etc.) is formed in the contact holes by sputtering, and a blanket W film is formed by low-pressure CVD. The excess W film and glue layer on the PMD film are removed by a CMP process, forming a W plug CH in the contact hole. Although not shown in the figure, a W plug is also formed in the contact hole to the gate electrode at the same time.

[0114] Thereafter, for example, an aluminum wiring layer is formed as a first-layer metal wiring by a sputtering method or the like, and a resist pattern is formed by photolithography using a division projection exposure method. A pattern of the first-layer metal wiring M1 is formed by dry etching. After the resist is removed, an insulating film layer is formed using a silicon oxide film, and then planarized again by CMP technology. Thereafter, a silicon nitride film PLV1 is formed as a passivation film in the pre-wiring process.

[0115] Although not particularly limited, the silicon nitride film PLV1 functions as a protective film or passivation film for the circuit on the semi-finished semiconductor substrate after the pre-wiring process is completed.

[0116] The formation of the protective film prevents moisture from the outside air and impurities such as sodium from entering the circuits on the semi-finished semiconductor substrate.

[0117] Thereafter, via holes V1 are formed in the uppermost wiring layer (in this example, the first-layer metal wiring M1) in the previous wiring step to connect the metal wiring M2 in the subsequent wiring step. The via holes V1 can be formed by dry etching using a resist pattern obtained by photolithography using a division projection exposure method.

[0118] After the via hole V1 is formed, the resist is removed.

[0119] At this point, the front-end process and pre-wiring process are completed. After that, the electrical characteristics of the formed functional circuits and adjustment circuits are tested, and the information on the test results is stored in a predetermined common storage area (for example, the storage device 2300 described below) and shipped to a wafer bank as stock semiconductor wafers. Because the silicon nitride film PLV1 is formed on the surface, even if the wafers are stocked in this way, the impact on reliability can be suppressed.

[0120] Therefore, semi-finished semiconductor substrates shipped to the wafer bank do not achieve their full functionality at the time of shipping, and are therefore called "semi-finished wafers" as described above.

[0121] Although not particularly limited, the formation of the via hole V1 may be performed at the beginning of the post-wiring process. For example, in the pre-wiring process, only the via hole V1 portion in the TEG (Test Element Group) portion may be opened to test the circuit, and the via hole V1 in the connection portion with the wiring in the post-wiring process may be opened by etching in the post-wiring process. Such etching is performed, for example, by dry etching, by forming an etching resist mask by exposure using a photomask or exposure using a direct writing technique.

[0122] A design process (not shown) for post-wiring is performed based on the test results, and stock semiconductor wafers suitable for forming the semiconductor integrated circuit as the product envisioned by the designer are searched for and selected from within the wafer bank and shipped to the post-wiring process fab.

[0123] As will be described later, the configuration may be such that a designer selects a fab capable of forming a desired semiconductor integrated circuit from among a plurality of fabs.

[0124] When the stock semiconductor wafers on which the via holes V1 have been formed in the pre-wiring process are received by the post-wiring process fab, the interlayer insulating film in the post-wiring process is formed from a photosensitive organic insulating film. Although not particularly limited, the photosensitive organic insulating film may be made of photosensitive polyimide or the like.

[0125] In the post-wiring process, direct writing is performed on the photosensitive polyimide using, for example, a laser direct writing device. Laser direct writing allows for easy direct writing under atmospheric pressure, making it suitable as a wiring formation process in the post-wiring process. After direct writing, unnecessary portions of the photosensitive polyimide are removed by a development process to form a pattern of wiring M2 corresponding to the via hole V1, and the resulting pattern is cured.

[0126] However, the direct writing technique may use a technique other than laser light, or may use a photosensitive resin other than photosensitive polyimide.

[0127] Subsequently, the wiring M2 is formed by a dual damascene process.

[0128] Similarly, a photosensitive organic insulating film is again applied to the wafer, and a pattern of the via hole V2 and a corresponding pattern of the wiring M3 are formed by direct writing, followed by curing. The wiring M3 is formed by a dual damascene process.

[0129] Subsequently, a final passivation film PLV2 is formed. The passivation film PLV2 may be, for example, a silicon nitride film formed by plasma CVD.

[0130] In the photolithography and etching processes, openings are formed in the passivation film PLV2 in predetermined regions of the wiring M3, and in the wiring film formation process, bonding pads BP are formed.

[0131] The lithography method for etching such through holes may be photolithography using a photoresist and a mask, or direct writing technology. When using such photolithography methods, it is assumed that the frame on which the chip is mounted is standardized in the subsequent process (assembly process). In other words, it is assumed that the pad positions on the chip side for wire bonding are standardized. However, there is a possibility that pads that are not wire bonded may occur due to bonding options, etc. The direct writing method can flexibly accommodate such cases, allowing for a configuration in which only the necessary through holes are opened.

[0132] The semiconductor manufacturing process described above can be realized by combining commonly used process technologies, so detailed explanations of the process conditions for each step will be omitted. Those skilled in the art will be able to set the process conditions and execute each step. (Configuration of the Design Platform)

[0133] FIG. 4 is a conceptual diagram for explaining the configuration of a design platform of the design support system according to this embodiment.

[0134] FIG. 5 is a conceptual diagram illustrating the server device that provides the design platform from the configuration shown in FIG.

[0135] 4 and 5 may be an on-premise server or a cloud server. However, from the viewpoint of sharing and using data among multiple designers, a cloud server is preferable. Here, the designers may belong to the same company or different companies.

[0136] Furthermore, the designer who designs the functional circuit and the designer who designs the semiconductor device as the final product (design of the post-wiring process) may be designers from the same company or different companies. In Figure 4, a case is generally shown in which the designers are from different companies.

[0137] If the designer who designs the functional circuit and the designer who designs the semiconductor device as the final product are from different companies, the company who designs the functional circuit can develop a business of providing design information for the functional circuit to the company that manufactures and sells the semiconductor device as the final product. Alternatively, the company to which the designer who designs the semiconductor device as the final product belongs can develop a business of selling semi-finished wafers stocked in a wafer bank WBANK to the company that manufactures and sells the semiconductor device as the final product.

[0138] By configuring the design platform as shown in FIG. 4, it is possible to realize such a variety of business forms.

[0139] 4 and 5, the design platform is a design support system that provides tools to support the circuit design of semiconductor devices manufactured in cooperation with functional circuit formation fabs WFFAB.1 to WFFAB.N and post-wiring process fabs WLFAB.1 to WLFAB.M.

[0140] The functional circuit fabrication fabs WFFAB.1 to WFFAB.N are responsible for a first manufacturing process under a first design rule and are responsible for a pre-wiring process. The post-wiring process fabs WLFAB.1 to WLFAB.M are responsible for a second manufacturing process under a second design rule different from the first design rule and are responsible for a post-wiring process.

[0141] The functional circuit fabrication fabs WFFAB01 to WFFABN provide design reference data (PDK) to the design platform, and the storage device 1500 stores the data as pre-wiring process design reference data 1500.1.

[0142] The functional circuit design tool providing server 1000 supports the design of circuit patterns in a pre-wiring process for forming a plurality of circuit blocks on a semiconductor substrate. Here, the plurality of circuit blocks includes a plurality of functional circuit blocks for implementing, on the semiconductor substrate, a plurality of individual functions that constitute the overall function of the semiconductor device to be manufactured. Furthermore, the plurality of functional circuit blocks includes a plurality of stock circuit blocks for which design information for circuit patterns corresponding to the manufacturing process for each of the functional circuit fabrication fabs WFFAB.1 to WFFAB.N is prepared in advance based on the first design rule. The design information for the stock circuit blocks is stored in the storage device 1600 as a functional circuit design library 1600.1, and performance information (specification information) for the stock circuit blocks is stored as standard circuit performance information 1600.2.

[0143] The functional circuit design tool providing server 1000 selects a predetermined number of stock circuit blocks from a plurality of stock circuit blocks for realizing the overall function of a semiconductor device and supports the design of placing the selected circuit blocks on a semiconductor substrate for the designer terminals 5000.1 to 5000.P (P: natural number). Here, "design support" refers to support for logic design and pattern design, and can be realized, for example, by linking with an existing EDA tool.

[0144] The plurality of circuit blocks are provided on the semiconductor substrate separately from the plurality of functional circuit blocks, and each includes a plurality of adjustment circuit blocks for tuning the performance realized by the functional circuit block. Design information of the adjustment circuits is stored in an adjustment circuit design library 1600.3, and performance information of the adjustment circuits is stored as standard circuit performance information 1600.2.

[0145] After the pre-wiring process is completed, design information and specification information of the formed functional circuits, and design information and specification information of the adjustment circuits for the semi-finished wafers stored in the wafer bank WBANK are stored as an intra-wafer-bank stock information database (hereinafter referred to as an "intra-wafer-bank stock information DB") 2300.1 in the storage device 2300. Although not particularly limited, the storage of information in this intra-wafer-bank stock information DB 2300.1 and the updating of information as described below can be performed by the functional-circuit design tool providing server 1000.

[0146] If functional circuit design tool providing server 1000 determines that wafers on which functional circuits and adjustment circuits capable of achieving the overall function are formed are stocked in wafer bank WBANK, it provides designer terminals 5000.1 to 5000.P with a function of confirming through simulation that the desired overall function will be achieved by connecting the functional circuits and adjustment circuits on these wafers with post-wiring. If functional circuit design tool providing server 1000 determines as a result of the simulation that the overall function will be achieved, it selects these stocked semi-finished wafers as wafers to be sent to the post-wiring process. Information indicating this selection is stored in wafer bank stock information DB 2300.1.

[0147] Furthermore, once a specific company has selected to send a wafer stocked in wafer bank WBANK to the post-wiring process in this manner, access to the information on this wafer in wafer bank stock information DB2300.1 is managed so that it is limited to this specific company only.

[0148] On the other hand, if the functional circuit design tool providing server 1000 determines that it is difficult to achieve the overall functionality with the stocked semi-finished wafers, it supports the design of manufacturing new functional circuits and adjustment circuits that correspond to the missing functions in addition to the selected predetermined number of stock circuit blocks and corresponding adjustment circuit blocks.

[0149] As described above, it is assumed that designer terminals 5000.1 to 5000.P are installed in a company (functional circuit design company) different from the company (fabless manufacturer) that designs the post-wiring process. However, designer terminals 5000.1 to 5000.P may also be installed in the same company that designs the post-wiring process.

[0150] Furthermore, storage device 1500 stores a function-fab relation database (hereinafter referred to as the "function-fab relation DB") 1500.2 used to select and identify functional circuit formation fabs WFFAB.1 to WFFAB.N responsible for manufacturing semiconductor substrates on which semiconductor devices achieving the overall function are formed, as will be described later. Function-fab relation DB 1500.2 stores correspondence between "individual functions" for achieving the overall function based on PDK information and "design information in functional circuit design library 1600.1 and adjustment circuit design library 1600.3." "Function circuit design library 1600.1 and adjustment circuit design library 1600.3" are provided in advance corresponding to the processes of functional circuit formation fabs WFFAB.1 to WFFAB.N.

[0151] Functional circuit design library 1600.1 and adjustment circuit design library 1600.3 are collectively referred to as "IP core design information." The IP core design information includes the types of functional circuits that can be manufactured in each of the corresponding functional circuit fabrication fabs WFFAB.1 to WFFAB.N, their design information, and specifications for the functional circuits, as well as the types of adjustment circuits that can be manufactured, their design information, and specifications for the adjustment circuits. This information can be provided as a PDK.

[0152] The plurality of functional circuit blocks also includes at least one custom circuit block for which design information for a circuit pattern is designed by one of designer terminals 5000.1 to 5000.P based on a first design rule of a fab selected from among functional circuit formation fabs WFFAB.1 to WFFAB.N.

[0153] When functional circuit design tool providing server 1000 determines that multiple stock circuit blocks are insufficient to achieve overall performance, it displays a message to designer terminals 5000.1 through 5000.P performing design corresponding to the pre-wiring process, prompting them to design a custom circuit block. Then, functional circuit design tool providing server 1000 supports the logic design and pattern design of the custom circuit block and the corresponding adjustment circuit block based on the IP core design information and a first design rule corresponding to the fab selected as the fab responsible for manufacturing the semi-finished wafer that achieves the overall function. Here, when selecting the fab responsible for manufacturing the semi-finished wafer that achieves the overall function based on the IP core design information, the fab capable of producing the largest number of functional circuits corresponding to the individual functions required to achieve the overall function may be selected. When the custom circuit block design is completed, functional circuit design tool providing server 1000 provides mask data for creating a reticle to the selected fab from functional circuit formation fabs WFFAB.1 through WFFAB.N.

[0154] The company in charge of the design of the pre-wiring process may choose to add the design information of the newly designed custom circuit block and the corresponding adjustment circuit block to the "IP core design information." In this case, the newly designed custom circuit block is added as one of the stock circuit blocks.

[0155] The post-wiring design tool providing server 2000 supports the designer terminals 5100.1 to 5000.Q (Q: natural number) in designing circuit patterns in the post-wiring process for selectively connecting multiple circuit blocks formed in the pre-wiring process. Note that among the multiple circuit blocks formed in the pre-wiring process, there may be some that are not connected to any other circuit blocks in the post-wiring pattern and are therefore unused.

[0156] The post-wiring design tool provision server 2000 selects one of the post-wiring process fabs WLFAB.1 to WLFAB.M depending on the manufacturing process that produced the selected multiple stock circuit blocks. While the selection method is not particularly limited, for example, as described below, the selection may be performed based on the overlay margin for exposure in the post-wiring process, depending on the pattern and dimension information of the contact portion between the top-layer wiring in the pre-wiring process and the wiring formed in the post-wiring process. The post-wiring design tool provision server 2000 then executes logic design and pattern design support for the post-wiring process using a second design rule that corresponds to the first design rule of the selected stock circuit block. Here again, "design support" refers to support for logic design and pattern design, and can be realized, for example, by linking with an existing EDA tool.

[0157] Corresponding to the post-wiring process, the storage device 2500 stores wiring structure design reference data 2500.1 provided as PDK from the post-wiring process fabs WLFAB.1 to WLFAB.M, and adjustment circuit parameter data 2500.2 indicating performance parameters of adjustment circuits formed in the pre-wiring process. The performance parameters of the adjustment circuits can be configured to include not only design parameters but also information on the results of circuit tests performed in the pre-wiring process.

[0158] The post-wiring design tool providing server 2000 refers to the wafer bank stock information DB 2300 and performs logic design and pattern design for post-wiring for wafers flowing to the post-wiring process based on the wiring structure design reference data 2500.1 and adjustment circuit parameter data 2500.2 (including test data for functional circuits in the pre-wiring process).

[0159] The post-wiring design tool providing server 2000 provides the drawing data for direct drawing to a selected fab from among the post-wiring process fabs WLFAB.1 to WLFAB.M.

[0160] Once the post-wiring process is complete, post-processing is carried out in one of the assembly process fabs ASFAB.1 to ASFAB.L that is responsible for the assembly process, and finally, the semiconductor device that will become the product is shipped.

[0161] From design terminals 5000.1 to 5000.Q, depending on the designer or the designer's company, information regarding issues discovered during prototyping and methods for resolving those issues through redesign or reprototyping can be stored as needed in problem information and solution information database (hereinafter referred to as "problem information and solution information DB") 2200.1 of storage device 2200. Once information is stored in problem information and solution information DB 2200.1, this information can be referenced from designer terminals 5000.1 to 5000.P, allowing it to be used as reference when selecting functional circuits provided by functional circuit design tool provision server 1000 and when designing circuit patterns in the pre-wiring process. In this way, by referencing information on past defects, it is possible to further shorten the construction period for prototyping.

[0162] The information stored in the problem information and solution information DB 2200.1 may be configured so that it can be referenced only from designer terminals 5000.i of companies that are permitted to reference the information through a separate contract or the like with the company in charge of designing the post-wiring process.

[0163] Alternatively, the information stored in the problem information and solution information DB 2200.1 may be made available to a wider range of companies. In any case, the extent to which companies can access the information depends on the agreement between the operator and users of the design platform.

[0164] Furthermore, functional circuit design tool providing server 1000 can train its artificial intelligence to use information stored in problem information and solution information DB 2200.1 as learning data, problem information as input, and solution methods as output. In this case, functional circuit design tool providing server 1000 can be configured to automatically respond to designer terminals 5000.1-5000.P by proposing solutions to the problems. Alternatively, the content of the AI ​​learning is not limited to this configuration. For example, if information is accumulated indicating that a problem has occurred due to a combination of specific functional circuits or a combination of a specific functional circuit and a specific adjustment circuit, a warning of the possibility of a malfunction can be given to the designer on designer terminal 5000.1-5000.P while the designer is performing the design process. (Conceptual diagram of function / fab related data)

[0165] FIG. 6 is a conceptual diagram showing an outline of the configuration of the function / fab relationship DB 1500.2.

[0166] 7 to 10 are diagrams for explaining the details of the configuration of the function / fab relationship DB 1500.2.

[0167] Referring to FIG. 6, function-fab relationship DB 1500.2 stores the following correspondence relationships.

[0168] That is, the function / fab relationship DB1500.2 includes a first correspondence relationship TBL1 that shows the relationship between the functional circuit blocks corresponding to each of the multiple individual functions that make up the overall function for realizing an application or product, and the adjustment circuits that can tune the performance of the functional circuit blocks in accordance with the functional circuit blocks, and a second correspondence relationship TBL2 that shows the performance specifications for the individual functions of the functional circuit blocks and the performance specifications of the adjustment circuit blocks, and multiple IP core design information groups for realizing each of these performance specifications.

[0169] FIG. 7 shows the details of the first correspondence table TBL1.

[0170] For example, when a motor control semiconductor integrated circuit is targeted as the semiconductor layer device that will be the final product, it is assumed that (function AA, function BB, . . . ) are required as individual functions.

[0171] These individual functions (function AA, function BB, ...) correspond to functional circuits (analog-digital conversion circuit ADC, digital-analog conversion circuit DAC, ...), and performance specifications are set for each functional circuit.

[0172] Similarly, adjustment functions (transistor capacitance adjustment, constant current source current value adjustment, phase margin adjustment, etc.) and corresponding functional circuits are set corresponding to individual functions (function AA, function BB, etc.), and the performance specifications of these are also set.

[0173] In FIG. 7, the existence of a correspondence between the adjustment circuit and the functional circuit corresponding to each required individual function and each adjustment function is indicated by a circle.

[0174] Note that the functional circuits corresponding to the individual functions are not limited to those mentioned above, and include, for example, the following circuits: OSC (oscillator circuit) RTC (real-time clock circuit) PLL (phase-locked loop circuit) VCO (voltage-controlled oscillator) OP-AMP (operational amplifier circuit) COMP (comparator) REF (reference voltage generation circuit, reference current generation circuit) POR (power-on reset circuit) REG (regulator circuit) CP (charge pump circuit) I / O (input / output circuit) MEM (small-scale memory circuit)

[0175] However, the functional circuits are not limited to these.

[0176] In addition, the corresponding adjustment circuits include the following circuits: Passive circuits such as parasitic element adjustment circuits Input offset voltage adjustment circuits Noise adjustment circuits Thermal runaway adjustment circuits ESD tolerance adjustment circuits EMI tolerance adjustment circuits Resistance / capacitance adjustment array circuits

[0177] The adjustment circuit is not limited to these.

[0178] 8 shows the relationship between the functional circuits and their specifications for achieving individual functions and the adjustment circuits and their specifications, and the IP core design information (IP core group 1, IP core group 2, ..., custom core) that can be achieved in advance. Here too, the existence of a correspondence is indicated by a circle.

[0179] The IP core group i (i: natural number) includes design information of a stock circuit block, and the custom core includes design information of a custom circuit block.

[0180] Each of the IP core design information groups includes "stock circuit block design information" for defining a preset individual circuit pattern that can realize the performance specifications for at least one of the individual functions.

[0181] 6, function-fab relationship DB1500.2 includes a correspondence table 3 between IP core design information (IP core group 1, IP core group 2, ..., custom core) as circuit design information and the IP cores that can be manufactured in the respective functional circuit fabrication fabs WFFAB.1 to WFFAB.N. FIG. 9 shows such correspondence table 3.

[0182] Furthermore, the function-fab relationship DB 1500.2 includes a correspondence table TBL4 between manufacturable IP core design information, corresponding foundries, and manufacturing processes (manufacturing processes under the first design rule). FIG. 10 shows such correspondence table TBL4.

[0183] Based on the function-fab relation DB 1500.2, the functional circuit design tool provision server 1000 selects a group of IP core design information including a combination of functional circuit blocks that can realize the overall function. The functional circuit design tool provision server 1000 then identifies a fab corresponding to the selected group of IP core design information from among the functional circuit fabrication fabs WFFAB.1 to WFFAB.N, and executes logic design and pattern design based on a first design rule corresponding to the identified fab. (Configuration and Operation of Servers Constituting the Design Platform)

[0184] The configuration and operation of the servers that make up the design platform will be explained below with reference to the drawings.

[0185] 11 is a diagram showing the configuration of the functional circuit design tool providing server 1000, the post-wiring design tool providing server 2000, and the designer terminals 5000.1 to 5000.P.

[0186] Here, it is assumed that designer terminals 5000.1 to 5000.P correspond to designer terminals 5000.1 to 5000.Q, respectively, and designer terminals 5000.1 to 5000.Q are not shown in the figure. Hereinafter, when designer terminals 5000.1 to 5000.P are collectively referred to as designer terminal 5000.

[0187] As an example, the functional circuit design tool providing server 1000 and the post-wiring design tool providing server 2000 of the design platform are servers on the cloud, and are communicably connected to designer terminals 5000.1 to 5000.P via a network 2. (Configuration and Operation of the Functional Circuit Design Tool Providing Server 1000)

[0188] FIG. 12 is a functional block diagram showing the configuration of the functional circuit design tool providing server 1000.

[0189] 15 and 16 are flowcharts for explaining the operation of the functional circuit design tool providing server 1000. FIG.

[0190] Referring to FIG. 12, the functional circuit design tool providing server 1000 includes a communication interface 1002 for communicating with the outside, a processing unit 1100, and a memory 1200 that operates as a working storage area for the processing unit 1100.

[0191] The manufactured semiconductor acquisition module 1110, individual function setting module 1120, adjustment circuit setting module 1130, IP core selection module 1140, foundry selection module 1150, logic circuit design module 1160, circuit pattern design module 1170, and mask pattern generation module 1180 described in Figures 15 and 16 correspond to the functions of a CPU (Central Processing Unit) corresponding to the arithmetic processing unit 1100 executing corresponding modules in a program stored in memory when a computer operates as the functional circuit design tool provision server 1000.

[0192] 12, 15, and 16, when a designer uses the designer terminal 5000 to set the overall function of the semiconductor circuit to be designed and the specifications of the individual functions to realize it (S100), the manufactured semiconductor acquisition module 1110 and the individual function setting module 1120 of the functional circuit design tool provision server 1000 acquire information on this overall function and individual functions, and the IP core selection module 1140 searches for IP core design information that can achieve the overall function based on the specifications of the functional circuits that realize each individual function (S104).

[0193] If the IP core selection module 1140 determines that the entire function can be realized with the stocked functional circuit IP core library (Y in S106), it selects an IP core group that can realize the required functional circuit and adjustment circuit (step 108). On the other hand, if the IP core selection module 1140 determines that the entire function cannot be realized (N in S106), it proceeds to step 150 in FIG.

[0194] Returning to step 108, the foundry selection module 1150 then selects a foundry that has a process capable of realizing the selected IP core group (step S110).

[0195] In response to the selection of a foundry, the designer uses the designer terminal 5000 to set the specifications of an adjustment circuit for changing the characteristics of the functional circuit (S112).

[0196] The foundry selection module 1150 reads stock design information of the adjustment circuit corresponding to the functional circuit of the set specifications from the database in the storage device 1600 (step S114), and determines whether there are any wafers in the wafer bank on which circuits have already been formed by referring to the wafer bank stock information DB2300.1 (S116).

[0197] If the foundry selection module 1150 determines that a formed wafer exists (Y in S116), the logic circuit design module 1160 and the circuit pattern design module 1170 acquire information on the circuit layout on the wafer in the wafer bank (S118), proceed to step S164 of the processing in Figure 16, and update the wafer bank stock information DB2300.1 so that the wafer to be sent to the post-wiring process is specified in the wafer bank stock information DB2300.1.

[0198] On the other hand, if the foundry selection module 1150 determines that there are no formed wafers (N in S116), the logic circuit design module 1160 and the circuit pattern design module 1170 design and determine the placement of the IP cores (functional circuits and adjustment circuits) in the IP core group within the reticle (S120).

[0199] Referring to FIG. 16, if the IP core selection module 1140 determines in step S106 that the overall function cannot be realized (N in S106), this fact is notified to the designer terminal 5000, and the designer sets the circuit specifications for the missing individual functions via the designer terminal 5000 (S150).

[0200] The logic circuit design module 1160 supports the logic design of the functional circuits of the missing individual functions and the logic design of the corresponding adjustment circuits (S152).

[0201] Next, the circuit pattern design module 1170 designs patterns for the logically designed functional circuit and adjustment circuit, stores them in the storage device 1600 as custom design information, and also updates the function / foundry relation DB (S154).

[0202] Furthermore, the logical circuit design module 1160 and the circuit pattern design module 1170 support logical design and, if necessary, pattern design for achieving the overall function based on stock design information of the stored functional circuits and adjustment circuits and the generated custom design information, and simulate the possibility of achieving the overall function (S156).

[0203] When the designer instructs the design of a circuit layout based on the structural design standards of the corresponding foundry process using the designer terminal 5000 (S158), the circuit pattern design module 1170 determines the patterns and layout of the front-end process and pre-wiring process of the functional circuit and adjustment circuit that can realize the target function (S160), and the mask pattern generation module 1180 generates and outputs mask data based on the layout information in the reticle of the functional circuit and adjustment circuit (S162).

[0204] The logic circuit design module 1160 and the circuit pattern design module 1170 update the wafer bank stock information DB in response to the completion of the pre-wiring process and the storage in the wafer bank (S164). (Configuration and Operation of the Post-wiring Design Tool Providing Server 2000)

[0205] FIG. 13 is a functional block diagram showing the configuration of the post-wiring design tool providing server 2000.

[0206] FIG. 17 is a flowchart for explaining the operation of the post-wiring design tool providing server 2000.

[0207] Referring to FIG. 13, the post-wiring design tool providing server 2000 includes a communication interface 2002 for communicating with the outside, a processing unit 2100, and a memory 2200 that operates as a working storage area for the processing unit 2100.

[0208] The manufactured semiconductor acquisition module 2110, individual function setting module 2120, adjustment circuit setting module 2130, IP core selection module 2140, foundry selection module 2150, logic circuit design module 2160, circuit pattern design module 2170, and drawing data generation module 2180 described in FIG. 17 correspond to the functions of a CPU corresponding to the processing unit 2100 executing corresponding modules in a program stored in memory when a computer operates as the post-wiring design tool providing server 2000.

[0209] 13 and 17, when the overall functions of the semiconductor device to be manufactured are set in the designer terminal 5000, the target foundry is identified from the individual functions and adjustment functions by the manufactured semiconductor acquisition module 2110, the individual function setting module 2120, the adjustment circuit setting module 2130, the IP core selection module 2140, and the foundry selection module 2150, as in Fig. 12, and test result data of wafers that have completed the pre-wiring process is acquired (S200), and wafers to be sent to the post-wiring process are searched for and selected from the wafers in the wafer bank (S202). Note that if the company that designed the pre-wiring process also designs the post-wiring process, the wafers to be sent to the post-wiring process may be identified from the wafers in the wafer bank based on information obtained from the design of the pre-wiring process.

[0210] When the designer terminal 5000 references the wafer bank stock information DB and indicates that there are wafers in the wafer bank on which circuits have already been formed (Y in S204), the post-wiring design tool providing server 2000 selects an adjustment circuit based on the performance margin of the functional circuit and presents it to the designer terminal 5000 (S206). Then, when the designer terminal 5000 specifies a connection between the functional circuit and the adjustment circuit (S208), the logic circuit design module 2160 executes logic circuit design (including simulation) for the post-wiring process. Based on the results of the logic circuit design, the logic circuit design module 2160 presents to the designer terminal 5000 candidate functional circuits and adjustment circuits capable of realizing the target function (S210). The designer terminal 5000 selects candidate functional circuits and adjustment circuits capable of realizing the target function (S212), and instructs the design of a wiring layout based on the structural design criteria for the corresponding post-wiring process (S214). The circuit pattern design module 2170 generates a wiring layout in response to the instruction, and the drawing data generation module 2180 generates and outputs drawing data (S216).

[0211] FIG. 14 is a block diagram for explaining the hardware configuration of the functional circuit design tool providing server 1000 shown in FIG.

[0212] In the following description, the functional circuit design tool providing server 1000 is assumed to operate on a server running on the cloud. However, the functional circuit design tool providing server 1000 may also operate on an on-premise server, for example.

[0213] Although the configuration of the functional circuit design tool providing server 1000 will be described below as an example, the hardware configurations of the post-wiring design tool providing server 2000 and the designer terminal 5000 are basically the same.

[0214] 14, server 1000 may be configured such that a computing device (CPU: Central Processing Unit) within its own housing executes the computational processing, or such that part of the program processing is executed on another server. In the following description, it is assumed that the computing device within its own housing executes the computational processing.

[0215] Referring to FIG. 14, the server 1000 comprises a computer device 1010, a network communication unit 1012 for communicating with a network, and a recording medium (e.g., a memory card) 1210 for recording data from the outside and providing it to the computer device 1010.

[0216] For example, a USB memory, a memory card, or an external storage device can be used as the recording medium 1210. Also, for example, a wired LAN or wireless LAN communication function can be used as the network communication unit 1012. The network communication unit 1012 and the input / output interface 1090 constitute the communication interface 1002.

[0217] As shown in FIG. 14 , the computer main body constituting this computer device 1010 includes, in addition to a disk drive 1030 and a memory drive 1020, a CPU 1100 connected to a bus 1050, a memory 1200 including a ROM (Read Only Memory) 1200.1 and a RAM (Random Access Memory) 1200.2, a nonvolatile rewritable storage device 1300, and an input / output interface 1090 for communicating over a network and exchanging data with external devices. The nonvolatile storage device 1300 may be, for example, a hard disk drive (HDD) or a solid state drive (SSD). The following description will be given assuming an SSD. An optical disk can be inserted into the disk drive 1030. A memory card 1210 can be inserted into the memory drive 1020.

[0218] When the programs of the computer device 1010 operate, the data and programs that store the information that is the basis for the operation of the computer are stored in the SSD 1300 in the following description.

[0219] 14, the medium capable of recording information such as a program to be installed in the computer main body may be, for example, a DVD-ROM (Digital Versatile Disc), a memory card, a USB memory, etc. To accommodate such cases, the computer main body is provided with a drive device (memory drive 1020, disk drive 1030) capable of reading these media.

[0220] The main components of the computer device 1010 are computer hardware and software executed by the CPU 1100. Generally, such software is stored in a storage medium and distributed or distributed via a network, and is obtained via the disk drive 1030 or the network communication unit 1012 and temporarily stored in the SSD 1300. The software is then read from the SSD 1300 into RAM 1200.2 in memory and executed by the CPU 1100. Note that when connected to a network, the software may be directly loaded into the RAM and executed without being stored in the SSD 1300.

[0221] When distributing a program for functioning as computer system 1010, the program does not necessarily need to include an operating system (OS) that causes computer system 1010 to execute functions such as an information processing device. The program only needs to include instructions that call appropriate functions (modules) in a controlled manner and achieve the desired results. How computer system 1010 operates is well known, and a detailed description thereof will be omitted.

[0222] Furthermore, the CPU 1100 may be a single-core processor or a multi-core processor. That is, it may be a single-core processor or a multi-core processor. The server 1000 may also be configured with multiple servers to perform distributed processing. (Configuration of the die after the pre-wiring process and the die after the post-wiring process)

[0223] FIG. 18 is a diagram for explaining a plurality of dies formed on a semiconductor substrate after the pre-wiring process.

[0224] In FIG. 18, a plurality of function circuits and a plurality of adjustment circuits are formed on one die.

[0225] In FIG. 18, the functional circuits and adjustment circuits are represented by multiple layers because, as explained in FIG. 2, multiple wiring and insulating film layers are formed sequentially when manufacturing these circuits.

[0226] FIG. 19 is a diagram for explaining a plurality of dies formed on a semiconductor substrate after a post-wiring process.

[0227] In FIG. 19, two dies are shown as examples of different die configurations.

[0228] As described above, the functional circuit design tool provision server 1000 generates optical mask patterns for performing exposure processing of dies on a semiconductor substrate, on which semiconductor devices are respectively formed, using a step-by-step projection exposure method in a pattern transfer process at a first semiconductor manufacturing site (e.g., a functional circuit formation fab). Here, as described above, at least one upper wiring layer in the pre-wiring process may be formed using a direct writing technique. Therefore, in other words, the optical mask patterns are generated for at least a portion of the pattern transfer process at the first semiconductor manufacturing site. Writing data for implementing the direct writing method may be generated for the remaining steps of the pattern transfer process at the first semiconductor manufacturing site. Meanwhile, the post-wiring design tool provision server 2000 generates writing data for forming wiring patterns that connect circuit blocks to a semiconductor substrate in a pattern transfer process at a second semiconductor manufacturing site (e.g., a post-wiring process fab).

[0229] By using direct writing, as shown in FIG. 19, different wiring patterns are formed in a post wiring process for dies among a plurality of dies that have common patterns for the functional circuit block and the adjustment circuit block.

[0230] More specifically, this different wiring pattern is a wiring pattern that connects a common functional circuit block and a different adjustment circuit block in a first die and a second die included in a die in which the patterns of the functional circuit block and the adjustment circuit block are common.

[0231] FIG. 20 is a diagram showing design rules for the uppermost layer wiring in the wiring group in the pre-wiring process, and design rules for the contact portion between the uppermost layer wiring M1 and the wiring M2 formed in the post-wiring process.

[0232] As shown in FIG. 20A, the design rules for the top layer wiring are that the wiring interval is S (nm) and the wiring width is L (nm).

[0233] On the other hand, as shown in FIG. 20(b), in the design rules for the contact portion between the top layer wiring in the pre-wiring process and the wiring formed in the post-wiring process, the first design rule of the stock circuit block includes an overlap margin for the connection portion at the via hole for connecting the wiring formed in the pre-wiring process and the wiring formed in the post-wiring process based on the second design rule.

[0234] More specifically, although not particularly limited, for example, in the configuration shown in FIG. 20, it is desirable for the relationship to be as follows: i) or ii).

[0235] Here, DR ＢＥ , D.R. ＦＥ are the minimum design dimensions of the wiring width in the pre-wiring process and the post-wiring process, respectively. The pre-wiring process has a smaller minimum design dimension as a design standard than the post-wiring process, and the alignment accuracy between masks (between processes) is also higher.

[0236] Therefore, although not particularly limited, for example, it is desirable that the planar structure of the top layer wiring formed in the pre-wiring process has a rectangular portion for forming a via hole contact, and that one side of this rectangular portion is set to 2.5 times or more the minimum width of the design criteria of the top layer wiring. Here, "2.5 times" means a typical value in the formula exemplified in ii) when DR ＢＥ = 2.0 μm, DR ＦＥ = 0.8 μm, but is not limited to this.

[0237] FIG. 21 is a conceptual diagram showing various modified examples of the pattern of the contact portion between the uppermost wiring in the pre-wiring process and the wiring formed in the post-wiring process.

[0238] As shown in FIG. 21, there are various possibilities for the shape of the contact formation region formed in the uppermost wiring layer in the pre-wiring step for connection with the first layer wiring layer in the post-wiring step.

[0239] Therefore, according to the design support system and design support method of the first embodiment, it is possible to shorten the product development period in the case of high-mix low-volume production.

[0240] Furthermore, by allowing designers from multiple companies to use the design support system as a design platform and share the information necessary for design, it becomes easier to further shorten the time required for design and prototyping.

[0241] Furthermore, such a design platform also enables transactions in which a company supplying semi-finished wafers sells the semi-finished wafers to a fabless company in charge of the post-wiring process. As a result, the design platform does not necessarily need to manage the semi-finished wafers as inventory, and the entry of a variety of semi-finished wafer suppliers further shortens the lead time and reduces costs for prototyping and mass production of a given semiconductor device. [Embodiment 2]

[0242] In the first embodiment described above, a configuration has been described in which the "performance" achieved by the functional circuit blocks is tuned using an "adjustment circuit" for the "functional circuits" formed in the pre-wiring process by using a post-wiring pattern in the post-wiring process.

[0243] In the second embodiment, a configuration will be described in which not only the "performance" can be adjusted but also the "function" and "characteristics" of a functional circuit can be changed by using a post wiring pattern.

[0244] For example, as an example, in the case of a so-called "op-amp (operational amplifier)" circuit, there are analog circuits whose functions and characteristics can be changed by changing the characteristic values ​​(e.g., resistance values ​​and capacitance values) of externally connected passive circuits (e.g., resistors and capacitors) and the manner of connection to the input / output nodes, such as "amplifier amplifier," "attenuator amplifier," "buffer amplifier," "comparator," "differentiator circuit," "integrator circuit," and "detector / absolute value circuit." More specifically, assuming the existence of a basic circuit called an "operational amplifier," it is possible to realize functions and characteristics such as "amplification," "filtering," "signal conversion (e.g., converting current changes to voltage changes)," "signal processing (e.g., signal synthesis, differentiation, and integration)," and "oscillation" depending on the characteristic values ​​of the passive circuits connected to the input / output nodes and the manner of connection.

[0245] In contrast, the "performance" that was the subject of adjustment in the first embodiment was the degree of functionality realized with the same characteristics and functions, and the "adjustment circuit" was used to tune such performance to bring it closer to the design value. For example, in the case of "amplification," this means fine-tuning the "amplification rate."

[0246] In contrast to this, in the second embodiment, a configuration will be described in which the "function realized by the functional circuit" and the "characteristics of the functional circuit" themselves can be changed by the post-wiring pattern in the post-wiring process. By adopting such a configuration, the degree of freedom in design is increased when changing specifications by the post-wiring pattern in the post-wiring process by using "semi-finished wafers" formed in the pre-wiring process and temporarily stored as inventory in a "wafer bank."

[0247] FIG. 22 is a conceptual diagram showing a comparison of the flexibility of design methods for digital circuits and analog circuits.

[0248] The horizontal axis of FIG. 22 represents flexibility, and here "flexibility" refers to the degree to which the circuit function can be switched by changing the wiring pattern in the second design and prototype stage or later, depending on the prototype results after the first design and prototype stage.

[0249] In a fully custom IC, where both the digital and analog circuits are designed using a cell-based method, if any design changes occur after the first design phase based on the results of prototyping, it is basically necessary to start the design over from scratch.

[0250] On the other hand, there are design methods such as the "gate array method," "embedded array method," and "analog master slice method" that allow the switching of circuit functions by rewiring using a photomask.

[0251] The gate array method for digital circuits is a semi-custom LSI that is manufactured by wiring according to the design onto a substrate that has logic cells (e.g., two-input NAND gates) pre-fabricated. Circuit functions can be switched or changed by rewiring using a photomask, without making any changes to the logic cells.

[0252] On the other hand, the analog master slice method is a method in which wafers with elements such as transistors, resistors, and capacitors formed on them are prepared in advance, and the photomask used to form the wiring layer is changed to realize functions that suit the user's needs, thereby realizing a user's own analog semi-custom IC / LSI.

[0253] For digital circuits or circuits that combine digital and analog circuits, the "embedded array method" is sometimes used. The "embedded array method" is a design and manufacturing method that combines the features of gate arrays and cell-based ICs. Once the cell-based IP to be used by the user has been decided, silicon wafers are sent to the manufacturing line in advance. Meanwhile, a gate array is manufactured for the circuit portion of the user's logic. Once the user's logic design is complete, placement and wiring of the user's logic portion is carried out using a wiring layer-only process.

[0254] Furthermore, the most flexible method is the "FPGA (Field Programmable Gate Array) method" or the "design method of the first or second embodiment" which performs rewiring without using a photomask.

[0255] "FPGA" is a design method for digital circuits that integrates logic circuits, allowing designers to program the logic circuit configuration in the field. The internal circuit configuration, or the processing content of the device, can be rewritten by programming.

[0256] In contrast to this, the "design method of the first or second embodiment" can be applied to digital circuits, analog circuits, and mixed circuits of digital and analog circuits.

[0257] As a result, according to the "design method of embodiment 1" as explained above or the "design method of embodiment 2" described below, it is possible to develop semiconductor integrated circuit chips with high flexibility and reduced development costs, for example, in analog / digital-analog hybrid ICs.

[0258] FIG. 23 is a diagram showing the relationship between the "functions," "characteristics," and "characteristic values" realized by a functional circuit, taking an operational amplifier as an example.

[0259] As mentioned above, examples of functions (major categories) realized by an operational amplifier in a basic circuit include an "amplifier," an "attenuator amplifier," a "buffer amplifier," and a "comparator."

[0260] Further, as a function (subcategory) of the "amplifying amplifier" and the "attenuating amplifier", classification as to whether the power down mode is on or off is also exemplified.

[0261] Generally, operational amplifiers are designed to operate within a certain range of power supply voltages, and operational amplifiers equipped with a power-down function can be set to a mode that keeps the power supply current below a predetermined value. This power-down function achieves low power consumption, for example, when the amplifier is battery-powered.

[0262] The characteristic of an amplifier is voltage gain, and the base pattern (circuit pattern manufactured up to the pre-wiring process) is designed so that the characteristic value can be changed to values ​​such as 10 dB, 20 dB, etc. The characteristic of an attenuating amplifier is also voltage gain, and the characteristic value is designed so that it can be changed to values ​​such as -20 dB.

[0263] Using the same operational amplifier circuit configuration as a basic circuit, these functions can be variably set by connecting passive circuits (resistance values) of predetermined values ​​to the input / output nodes of this circuit in a predetermined connection manner.

[0264] However, in the case of an analog circuit that is intended to be rewired using a conventional photomask as explained in FIG. 22, it is necessary to design a circuit pattern including a wiring pattern individually for each function.

[0265] In contrast, in the design method of the second embodiment, the configuration of the operational amplifier circuit is formed as a basic circuit pattern in the pre-wiring process, and the connection with the passive circuit is changed in the post-wiring process. In this way, it is possible to form a single common circuit pattern (base pattern) on the semiconductor substrate in the pre-wiring process for all functions.

[0266] FIG. 24 is a diagram showing three types of design conditions for the "amplifier."

[0267] As shown in FIG. 24, the functions (major classification) are the same as those of an amplifier, but the functions (minor classification) include the presence or absence of power down, and the characteristic value is the voltage gain, which is changed between 10 dB and 20 dB, and a design condition is set as variations A, B, and C.

[0268] FIG. 25 is a circuit diagram showing a circuit configuration when the circuit for the three conditions shown in FIG. 24 is designed by a full custom method.

[0269] Variation A is an amplifier as an analog circuit, has no power-down function, and has a voltage gain of 10 dB.

[0270] Accordingly, as shown in FIG. 25, in the “non-inverting amplifier circuit” corresponding to variation A, if the resistance R1 between the inverting input and ground is set to 10 kΩ, the resistance R2 of the feedback from the output to the inverting input becomes 20 kΩ.

[0271] This can be calculated backwards from the fact that, when the input voltage of the non-inverting amplifier circuit is Vi and the output voltage is Vo, the gain G (dB) is expressed by the following formula:

[0272] Similarly, in the "non-inverting amplifier circuit" corresponding to variation B, if the resistance R1 between the inverting input and ground is set to 10 kΩ, the resistance R2 of the feedback from the output to the inverting input will be 90 kΩ.

[0273] Furthermore, the "non-inverting amplifier circuit" corresponding to variation C has a configuration in which a power-down function is added to the "non-inverting amplifier circuit" corresponding to variation B.

[0274] FIG. 26 is a circuit diagram showing the circuit configuration when the circuit for the three conditions shown in FIG. 24 is designed by the design method of the second embodiment.

[0275] First, in the pre-wiring step, the basic circuit 6000 and the characteristic adjustment circuit 6100 are formed.

[0276] In this example, the basic circuit 6000 is an analog circuit, an operational amplifier circuit having a power-down function.

[0277] That is, in FIG. 26, for example, as a plurality of functional circuit blocks formed in the pre-wiring process, an "operational amplifier circuit with a power-down function" is formed as a basic circuit pattern of a variable functional block whose individual functions and characteristics can be changed by a post-wiring pattern.

[0278] The characteristic adjustment circuit 6100 is a circuit pattern for adjusting the function and characteristics of the basic circuit pattern.

[0279] The characteristic adjustment circuit 6000 includes a plurality of first passive circuit patterns 6110.i (e.g., resistor patterns, i: natural number). Each of these first passive circuit patterns is designed to have a first impedance value (e.g., 10 kΩ). However, the impedance values ​​of the first passive circuit patterns in the characteristic adjustment circuit 6100 do not necessarily have to be the same, and they may be designed to have different values.

[0280] Variation A is an amplifier with no power down function and a voltage gain of 10 dB.

[0281] 26 , in the “non-inverting amplifier circuit” corresponding to variation A, in the characteristic adjustment circuit 6100, a post-wiring pattern is designed so that the inverting input node is connected to the ground node via one first passive circuit pattern so that the resistance value R1 between the inverting input node and the ground node is 10 kΩ. Furthermore, a post-wiring pattern is designed so that the output node is connected to the inverting input node via two first passive circuit patterns so that the resistance value R2 of the feedback from the output node to the inverting input node is 20 kΩ. Furthermore, the node PD of the power-down function is connected to the “Low” level so that the power-down function is turned off.

[0282] In FIG. 26, the post wiring pattern is shown by dotted lines.

[0283] In the "non-inverting amplifier circuit" corresponding to variation B, in the characteristic adjustment circuit 6100, a post-wiring pattern is designed so that the inverting input node is connected to the ground node via one first passive circuit pattern so that the resistance value R1 between the inverting input node and the ground node is 10 kΩ. Furthermore, a post-wiring pattern is designed so that the output node is connected to the inverting input node via nine first passive circuit patterns so that the resistance value R2 of the feedback from the output node to the inverting input node is 90 kΩ. Furthermore, the power-down function node PD is connected to the "Low" level so that the power-down function is turned off.

[0284] Furthermore, in the "non-inverting amplifier circuit" corresponding to variation C, the node PD of the power-down function is connected to the "High" level so as to turn on the power-down function in the "non-inverting amplifier circuit" corresponding to variation B.

[0285] That is, for example, assume that N dies (N: natural number) are formed on a semiconductor substrate in the pre-wiring process. In the design method of the second embodiment, as described below, the basic circuit pattern 6000 and the characteristic adjustment circuit pattern 6100 are connected to at least m dies (m≦N, m: natural number) on the semiconductor substrate by a post-wiring pattern common to these dies. That is, at least m dies on the semiconductor substrate are designed so that the functions and characteristics realized by the basic circuits of the variable function blocks are common. Another die among the N dies may be designed so that the functions and characteristics realized by the basic circuits are different from those of the m dies. Alternatively, the post-wiring pattern may be designed so that the functions and characteristics realized by the basic circuits are common to all N dies.

[0286] For example, suppose a circuit of variation B is prototyped for m dies on a semiconductor substrate. In this case, the post-wiring pattern common to the m dies includes a first post-wiring pattern that enables a plurality of first passive circuit patterns, the number of which is specified at the time of design (nine in FIG. 26 ), to be connected to each other so that the functions and characteristics realized by the basic circuits of the variable function blocks are common.

[0287] FIG. 27 is a conceptual diagram showing a functional block and an adjustment circuit block for adjusting the performance of the functional block.

[0288] As shown in FIG. 27 , the plurality of circuit blocks formed on a die on a semiconductor substrate each include a plurality of adjustment circuit blocks 6200, 6300 for tuning the performance achieved by the functional circuit block. The plurality of adjustment circuit blocks 6200, 6300 are formed separately from the plurality of functional circuit blocks within the die on the semiconductor substrate on which these functional circuit blocks are formed. Note that the number of adjustment circuit blocks is not limited to this example and may be greater. Furthermore, the number of passive circuit patterns formed within the adjustment circuit block and the impedance values ​​of each passive circuit pattern are not limited to the example described below.

[0289] FIG. 27 shows an example of a variable function block as the functional circuit block, as described in FIG. 26 . The variable function block has an "operational amplifier circuit with a power-down function" formed as a basic circuit pattern. Corresponding to variation C, in the characteristic adjustment circuit 6100, a post-wiring pattern is designed so that the inverting input node is connected to the ground node via one first passive circuit pattern, so that the resistance value R1 between the inverting input node and the ground node is 10 kΩ. Furthermore, nine first passive circuit patterns are selected corresponding to the resistance value R2 of the feedback from the output node to the inverting input node, and are designed to be connected by a post-wiring pattern via the adjustment circuit block. Furthermore, the node PD of the power-down function is connected to the "High" level to turn on the power-down function.

[0290] The adjustment circuit block 6200 includes a plurality of second passive circuit patterns (e.g., resistor patterns), each of which is designed to have a second impedance value (e.g., 1 kΩ) smaller than the first impedance value (e.g., 10 kΩ).

[0291] The adjustment circuit block 6300 includes a plurality of third passive circuit patterns (e.g., resistor patterns), each of which is designed to have a third impedance value (e.g., 100Ω) smaller than the first impedance value (e.g., 10 kΩ).

[0292] The rear wiring pattern includes a first rear wiring pattern that is common to the m dies as described above and is provided for the nine first passive circuit patterns, and second rear wiring patterns 6400.1 and 6400.2 that connect the second passive circuit pattern and the third passive circuit pattern to the first passive circuit pattern.

[0293] 27, the wiring pattern for the first prototype is designed to connect four first passive circuit patterns, three second passive circuit patterns, two third passive circuit patterns, and five first passive circuit patterns in series. As a result, the resistance value R2 of the feedback from the output node to the inverting input node is as follows: R2 = 4 x 10 (kΩ) + 3 x 1 (kΩ) + 2 x 0.1 (kΩ) + 5 x 10 (kΩ) = 93.2 (kΩ).

[0294] In the first prototype, the first passive circuit pattern selected in the characteristic adjustment circuit 6100 may be common to the m dies, and the second passive circuit pattern selected in the adjustment circuit block 6200 and the third passive circuit pattern selected in the adjustment circuit block 6300 may also be common. Alternatively, the second passive circuit pattern selected in the adjustment circuit block 6200 and the third passive circuit pattern selected in the adjustment circuit block 6300 may differ between the dies depending on the purpose of the prototype.

[0295] After the first prototype is manufactured, the circuit characteristics are electrically evaluated. Based on the evaluation, it may be found that the performance achieved by the functional block (for example, the voltage gain of an amplifier) ​​needs to be changed.

[0296] In this case, in the second prototype, in order to change the performance achieved by the functional block (for example, the voltage amplification factor of an amplifier), the first post-wiring pattern provided for the first passive circuit pattern selected in the characteristic adjustment circuit 6100 is the same as in the first prototype, and the post-wiring patterns connecting the second passive circuit pattern selected in the adjustment circuit block 6200 and the third passive circuit pattern selected in the adjustment circuit block 6300 are changed to second post-wiring patterns 6400.3 and 6400.4.

[0297] 27, in the second prototype, the post wiring pattern is designed to connect four first passive circuit patterns, one second passive circuit pattern, eight third passive circuit patterns, and five first passive circuit patterns in series. As a result, the resistance value R2 of the feedback from the output node to the inverting input node is as follows: R2 = 4 x 10 (kΩ) + 1 x 1 (kΩ) + 8 x 0.1 (kΩ) + 5 x 10 (kΩ) = 91.8 (kΩ).

[0298] In this way, by changing the design of the post-wiring pattern to be formed on the stocked semiconductor substrate after the pre-wiring process is completed, it is possible to adjust the performance of the function achieved by the functional block for each prototype. In this case, for example, depending on the value to be adjusted, at least one of the second passive circuit pattern of the adjustment circuit block 6200 and the third passive circuit pattern of the adjustment circuit block 6300 may be configured so that there is no pattern to be connected in the post-wiring pattern.

[0299] Furthermore, by changing the design of the post-wiring pattern to be formed on the stock semiconductor substrate after the pre-wiring process is completed, it is also possible to change the "functions and characteristics" achieved by the functional block.

[0300] FIG. 28 is a conceptual diagram showing a prototyping process when the design method of the second embodiment is used in comparison with a conventional prototyping process.

[0301] Here, the conventional method is exemplified as a full-custom IC in which a wiring pattern is formed using a photomask.

[0302] In the conventional method, the circuit patterns formed on the dies on the semiconductor substrate during prototyping are the same. As a result, if the desired characteristic values ​​are not obtained in prototyping (1), a modified circuit pattern must be formed again for all dies on the semiconductor substrate in prototyping (2) and the characteristic values ​​must be confirmed. If the desired characteristic values ​​are not obtained in prototyping (2), prototyping (3) is performed.

[0303] In particular, there are limitations to simulation for analog circuits, and the characteristic values ​​of the simulation results and the actual chip often differ, so it is necessary to make prototypes multiple times.

[0304] In other words, it is necessary to verify by trial and error until the optimum characteristic value is found.

[0305] In contrast, in the design method of the second embodiment, no changes are made to the circuit patterns ("base patterns") that are manufactured and stored in the pre-wiring process. Based on this premise, for example, assuming that n x m dies are formed in a semiconductor substrate, it is possible to design and prototype the post-wiring pattern in the post-wiring process by changing it for each row of m dies.

[0306] In this case, although not limited to this, a semiconductor substrate on which a base pattern has been formed and stored can be selected from a wafer bank, and the manufacturing process can be executed by changing the second passive circuit pattern selected in the adjustment circuit block 6200 and the third passive circuit pattern selected in the adjustment circuit block 6300 in n ways for each row of n×m dies, for example. In this case, it is also possible to perform verification equivalent to that performed on a single prototype for n prototypes. This type of verification is called "multi-variation simultaneous verification."

[0307] The first passive circuit pattern selected in the characteristic adjustment circuit 6100 can be common to all dies, or can have different configurations for different rows of dies.

[0308] That is, in the design method of the embodiment, by performing the post-wiring process using direct-draw rewiring, it is possible to simultaneously prototype multiple variations and verify the device characteristics. Therefore, compared to the conventional method, it is possible to significantly shorten the construction period for the redesign process for adjustments.

[0309] Unlike digital processing, which handles signals of "0" or "1," the analog circuits mentioned above are difficult to design because they must handle minute signal changes. Enabling this kind of "multiple variation simultaneous verification" is highly effective in shortening the development time for analog circuits or mixed circuits that combine analog and digital circuits.

[0310] FIG. 29 is a conceptual diagram illustrating the manner in which design data is diverted and reused within a foundry or between foundries.

[0311] In the past, when a "functional circuit" used in the manufacture of product X at a single foundry (Fab A) was to be redesigned from scratch when manufacturing product Y, which has different required characteristics, even within the same foundry.

[0312] However, when the design method of the second embodiment is used, it is possible to reuse most of the design data of the "functional circuit" used in the manufacture of product X in fab A, as is, in the design for the manufacture of product Y in fab A. Not only that, it is also possible to reuse most of the design data of the "functional circuit" used in the manufacture of product X in fab A, as is, in the design for the manufacture of product Z in fab B.

[0313] In this sense, it is possible to shorten the construction period required for design.

[0314] FIG. 30 is a conceptual diagram showing the effect of the design method according to the embodiment.

[0315] As explained in FIG. 28, in the design method of the embodiment, by reusing design IP as shown in FIG. 29, not only can the design lead time (LT) be shortened, but also by enabling "simultaneous verification of multiple variations," it is possible to reduce development costs and significantly shorten the lead time required for development.

[0316] The embodiments disclosed herein are merely examples of configurations for specifically implementing the present invention, and do not limit the technical scope of the present invention. The technical scope of the present invention is defined by the claims, not by the description of the embodiments, and is intended to include modifications within the literal scope of the claims and within the scope of equivalent meanings.

[0317] 1000 Functional circuit design tool providing server, 1002 Communication interface, 1100 Processing unit, 1200 Memory, 1110 Manufactured semiconductor acquisition module, 1120 Individual function setting module, 1130 Adjustment circuit setting module, 1140 IP core selection module, 1150 Foundry selection module, 1160 Logic circuit design module, 1170 Circuit pattern design module, 1180 Mask pattern generation module, 1500, 1600 Storage device, 2000 Post-wiring design tool providing server, 2002 Communication interface, 2100 Processing unit, 2200 Memory, 2110 Manufactured semiconductor acquisition module, 2120 Individual function setting module, 2130 Adjustment circuit setting module, 2140 IP core selection module, 2150 Foundry selection module, 2160 Logic circuit design module, 2170 Circuit pattern design module, 2180 Drawing data generation module, 2200, 2300, 2500 storage devices, 5000.1 to 5000.P, 5000.1 to 5000.Q designer terminal, 6000 basic circuit, 6100 characteristic adjustment circuit, WFFAB.1 to WFFAB.N functional circuit formation foundries, WLFAB.1 to WLFAB.M post-wiring process foundries, WBANK wafer bank, ASFAB.1 to ASFAB.L assembly process foundries.

Claims

1. A design support system providing a tool for supporting circuit design of a semiconductor device manufactured in cooperation with a plurality of semiconductor manufacturing sites, the plurality of semiconductor manufacturing sites including a plurality of first semiconductor manufacturing sites performing a pre-wiring process in a first manufacturing process under a first design rule, and at least one second semiconductor manufacturing site performing a post-wiring process in a second manufacturing process under a second design rule different from the first design rule, the system comprising: a first design support device supporting design of a circuit pattern to be formed in the pre-wiring process on each of a plurality of dies on a semiconductor substrate, each of the dies including a plurality of circuit blocks, the plurality of circuit blocks including a plurality of functional circuit blocks for realizing, on the semiconductor substrate, a plurality of individual functions constituting an overall function of the semiconductor device, the plurality of functional circuit blocks including a plurality of stock circuit blocks for which design information for a circuit pattern corresponding to the manufacturing process for each of the first semiconductor manufacturing sites is prepared in advance based on the first design rule, the first design support device including a first design support means for supporting design for selecting a predetermined number of stock circuit blocks for realizing the overall function from the plurality of stock circuit blocks, and arranging the stock circuit blocks on the semiconductor substrate, The design support system further comprises a second design support device that supports design of a post-wiring pattern in a post-wiring process for selectively connecting a plurality of circuit blocks formed in the pre-wiring process, the second design support device including second design support means that selects the second semiconductor manufacturing site in accordance with a manufacturing process in which the selected plurality of stock circuit blocks are manufactured, and executes support for logic design and pattern design for the post-wiring process with the second design rule corresponding to a first design rule of the selected stock circuit block.

2. The design support system of claim 1, wherein said plurality of circuit blocks further includes a plurality of adjustment circuit blocks provided on said semiconductor substrate separately from said plurality of functional circuit blocks, for tuning the performance realized by each of said functional circuit blocks.

3. The design support system of claim 2, wherein the plurality of functional circuit blocks include at least one custom circuit block for which circuit pattern design information is designed by a user based on the first design rule of the selected first semiconductor manufacturing site, the first design support device includes a storage device that stores correspondences between the plurality of semiconductor manufacturing sites and a plurality of circuit design core groups including the plurality of functional circuit blocks in accordance with manufacturing processes of the plurality of semiconductor manufacturing sites, and the first design support means executes support for logical design and pattern design of the custom circuit block based on the first design rule corresponding to the first semiconductor manufacturing site selected in accordance with the circuit design core group.

4. A design support system as claimed in claim 3, wherein said first design support means, when it determines that said plurality of stock circuit blocks are insufficient to achieve said overall performance, prompts said user to design said custom circuit block.

5. A design support system as described in claim 3, wherein the correspondence relationship includes a first correspondence relationship with the functional circuit blocks each corresponding to a plurality of the individual functions constituting the overall function, and a second correspondence relationship between performance specifications for the individual functions of the functional circuit blocks and the plurality of circuit design core groups for realizing each of the performance specifications, and each of the circuit design core groups includes design information of the stock circuit blocks for defining a predetermined individual circuit pattern capable of realizing the performance specification for at least one of the individual functions.

6. A design support system as described in claim 5, wherein said first design support module includes: a core group selection means for selecting said circuit design core group including a combination of said functional circuit blocks capable of realizing said overall function; and a design means for identifying a first semiconductor manufacturing site among said plurality of semiconductor manufacturing sites that corresponds to said selected circuit design core group, and for executing logic design and pattern design based on said first design rule of the identified first semiconductor manufacturing site.

7. A design support system as described in claim 2, wherein the first design support device includes a mask pattern generation means for generating pattern data of an optical mask for performing an exposure process of dies on which the semiconductor devices are respectively formed on the semiconductor substrate by a divided projection exposure method during at least a portion of a pattern transfer process at the first semiconductor manufacturing site, and the second design support device includes a drawing data generation means for generating drawing data for forming a wiring pattern that connects the circuit blocks to the semiconductor substrate during a pattern transfer process at the second semiconductor manufacturing site.

8. A design support system as claimed in claim 7, wherein the first design rule of the selected stock circuit block includes an overlap margin of a connection portion at a via hole for connecting wiring formed in the pre-wiring process and wiring formed in the post-wiring process based on the second design rule.

9. A design support system as claimed in claim 7, wherein the drawing data generated by said drawing data generating means includes data of different wiring patterns in said post-wiring process for dies among said plurality of dies in which the patterns of said functional circuit block and said adjustment circuit block are common.

10. A design support system as claimed in claim 9, wherein the different wiring patterns are wiring patterns that connect the common functional circuit block and the different adjustment circuit blocks in a first die and a second die included in a die having the common pattern.

11. A design support system as described in claim 1, wherein the plurality of functional circuit blocks include a variable function block capable of changing characteristics of the individual functions by the post-wiring pattern, the variable function block having a basic circuit pattern for realizing the individual function and a characteristic adjustment circuit pattern for adjusting the characteristics by the basic circuit pattern, and the second design support means supports a design for connecting the basic circuit pattern and the characteristic adjustment circuit pattern with the post-wiring pattern common to a predetermined number of the dies on the semiconductor substrate.

12. A design support system as claimed in claim 11, wherein the characteristic adjustment circuit pattern includes a plurality of first passive circuit patterns, each of the first passive circuit patterns being designed to have a first impedance value, and the post-wiring pattern common to the die includes a first post-wiring pattern that connects to each other a number of the plurality of first passive circuit patterns specified at the time of design.

13. A design support system as claimed in claim 12, wherein said plurality of circuit blocks further includes a plurality of adjustment circuit blocks provided on said semiconductor substrate separately from said plurality of functional circuit blocks, for tuning the performance realized by each of said functional circuit blocks.

14. A design support system as described in claim 13, wherein the plurality of adjustment circuit blocks include a plurality of second passive circuit patterns, each of the second passive circuit patterns being designed to have a second impedance value smaller than the first impedance value, and the post-wiring pattern includes the first post-wiring pattern common to the predetermined number of the dies and a second post-wiring pattern that differs among the predetermined number of the dies and connects the second passive circuit pattern to the first passive circuit pattern.

15. The design support system according to any one of claims 11 to 14, wherein the basic circuit pattern is an analog circuit.

16. A computer-based design support method in which a tool for supporting circuit design of a semiconductor device manufactured in cooperation with a plurality of semiconductor manufacturing sites operates, the plurality of semiconductor manufacturing sites including a plurality of first semiconductor manufacturing sites responsible for a pre-wiring process in a first manufacturing process under a first design rule, and at least one second semiconductor manufacturing site responsible for a post-wiring process in a second manufacturing process under a second design rule different from the first design rule, the computer including an arithmetic unit and a memory device, the memory device storing design information for a plurality of circuit blocks, the plurality of circuit blocks including a plurality of functional circuit blocks for realizing, on the semiconductor substrate, a plurality of individual functions constituting an overall function of the semiconductor device, the plurality of functional circuit blocks including a plurality of stock circuit blocks for which design information for a circuit pattern corresponding to the manufacturing process for each of the first semiconductor manufacturing sites based on the first design rule is prepared in advance, the arithmetic unit selecting a predetermined number of stock circuit blocks for realizing the overall function from the plurality of stock circuit blocks to support the design of a circuit pattern in the pre-wiring process for forming the plurality of circuit blocks on the semiconductor substrate, and supporting the design of a post-wiring pattern in a post-wiring process for selectively connecting the plurality of circuit blocks formed in the pre-wiring process, The design support method includes a step of supporting the design of the post-wiring pattern by selecting the second semiconductor manufacturing site according to the manufacturing process that manufactured the selected plurality of stock circuit blocks, and performing support for logic design and pattern design for the post-wiring process with the second design rule that corresponds to the first design rule of the selected stock circuit blocks.

17. A design support device for supporting design of a pre-wiring process in a design support system that provides tools to support circuit design of a semiconductor device manufactured in cooperation with a plurality of semiconductor manufacturing sites, the plurality of semiconductor manufacturing sites including a plurality of first semiconductor manufacturing sites that are responsible for the pre-wiring process in a first manufacturing process under a first design rule, and at least one second semiconductor manufacturing site that is responsible for a post-wiring process in a second manufacturing process under a second design rule different from the first design rule, the device comprising a storage device that stores design information of a plurality of circuit blocks required for the design support, the plurality of circuit blocks including a plurality of functional circuit blocks for realizing, on the semiconductor substrate, each of a plurality of individual functions that constitute an overall function of the semiconductor device, the plurality of functional circuit blocks including a plurality of stock circuit blocks in which design information of a circuit pattern corresponding to the manufacturing process for each of the first semiconductor manufacturing sites based on the first design rule is prepared in advance, and the device further comprises a calculation device for executing design support processing based on the information stored in the storage device, the calculation device selecting a predetermined number of stock circuit blocks for realizing the overall function from the plurality of stock circuit blocks, and supporting a design for arranging the circuit pattern in the pre-wiring process on the semiconductor substrate, A design support device for storing, in a specified shared memory area, design information of an arrangement of circuit patterns in the pre-wiring process in a design process of a post-wiring process for selectively connecting a plurality of circuit blocks formed in the pre-wiring process in order to share the design information.

18. The design support system according to claim 17, wherein the design support device includes a mask pattern generating means for generating pattern data of an optical mask for performing exposure of dies on the semiconductor substrate, on which the semiconductor devices are respectively formed, by a divided projection exposure method during at least a part of a pattern transfer process at the first semiconductor manufacturing site, and the pattern transfer process at the second semiconductor manufacturing site is a process of directly drawing a wiring pattern that connects the circuit blocks to the semiconductor substrate.

19. A design support system as claimed in claim 18, wherein the first design rule of the selected stock circuit block includes an overlap margin for a connection portion at a via hole for connecting wiring formed in the pre-wiring process and wiring formed in the post-wiring process based on the second design rule.

20. A design support system for providing tools to support circuit design of a semiconductor device manufactured in cooperation with a plurality of semiconductor manufacturing sites, the design support device supporting design of a post-wiring process in response to design of a pre-wiring process, the plurality of semiconductor manufacturing sites including a plurality of first semiconductor manufacturing sites performing the pre-wiring process in a first manufacturing process under a first design rule, and at least one second semiconductor manufacturing site performing the post-wiring process in a second manufacturing process under a second design rule different from the first design rule, the device is provided with a storage device for storing stock information of a plurality of semiconductor substrates that have been completed up to the formation of a plurality of circuit blocks for each of a plurality of dies in the pre-wiring process and are stocked, the plurality of circuit blocks including a plurality of functional circuit blocks for realizing on the semiconductor substrate a plurality of individual functions that constitute the overall function of the semiconductor device, the plurality of functional circuit blocks including a plurality of stock circuit blocks for which design information of a circuit pattern corresponding to the manufacturing process for each of the first semiconductor manufacturing sites based on the first design rule is prepared in advance, the plurality of stock semiconductor substrates are formed by selecting a predetermined number of stock circuit blocks for realizing the overall function from the plurality of stock circuit blocks, and forming a circuit pattern in the pre-wiring process on the semiconductor substrate, The design support device further comprises an arithmetic unit for executing a design support process based on information stored in the storage device, wherein the arithmetic unit selects the semiconductor substrate for which the post-wiring process is to be performed based on the stock information, and supports a design process of a post-wiring pattern for a post-wiring process for selectively connecting a plurality of circuit blocks formed in the pre-wiring process.

21. The design support device according to claim 20, further comprising a direct writing pattern generating means for generating direct writing data for performing a direct writing method for transferring wiring patterns of dies on which the semiconductor devices are respectively formed on the semiconductor substrate in a pattern transfer process at the second semiconductor manufacturing site.

22. A design support device as described in claim 20, wherein the plurality of functional circuit blocks include a variable function block capable of changing characteristics of the individual functions by the post-wiring pattern, the variable function block having a basic circuit pattern for realizing the individual function and a characteristic adjustment circuit pattern for adjusting the characteristics by the basic circuit pattern, and the design support means supports a design for connecting the basic circuit pattern and the characteristic adjustment circuit pattern by the post-wiring pattern common to a predetermined number of the dies on the semiconductor substrate.

23. The design support device according to claim 22, wherein the characteristic adjustment circuit pattern includes a plurality of first passive circuit patterns, each of the first passive circuit patterns being designed to have a first impedance value, and the post-wiring pattern common to the die includes a first post-wiring pattern that connects to each other a number of the plurality of first passive circuit patterns designated at the time of design.

24. The design support device according to claim 23, wherein said plurality of circuit blocks further includes a plurality of adjustment circuit blocks provided on said semiconductor substrate separately from said plurality of functional circuit blocks, for tuning the performance realized by each of said functional circuit blocks.

25. The design support device of claim 24, wherein the plurality of adjustment circuit blocks include a plurality of second passive circuit patterns, each of the second passive circuit patterns being designed to have a second impedance value smaller than the first impedance value, and the post-wiring pattern includes the first post-wiring pattern common to the predetermined number of the dies and a second post-wiring pattern that differs among the predetermined number of the dies and connects the second passive circuit pattern to the first passive circuit pattern.

Images