Multilayer ceramic capacitor and mounting structure

Abstract

This multilayer ceramic capacitor comprises a laminate and external electrodes. The laminate is obtained by alternately layering an internal electrode and a dielectric layer, and has a first surface and a second surface which are opposite from each other in the layering direction. The external electrodes include a first external electrode and a second external electrode. The first external electrode and the second external electrode each have a main surface electrode part that is positioned at least on the first surface. The main surface electrode part or a region of the laminate that contacts the main surface electrode part has a first portion and a second portion which is has a greater thickness than the first portion and which, as viewed in the layering direction, is positioned closer to the center of the laminate than the first portion.

Description

Multilayer ceramic capacitor and mounting structure

[0001] The present disclosure relates to a multilayer ceramic capacitor and a mounting structure.

[0002] A multilayer ceramic capacitor described in Patent Document 1 is known.

[0003] Japanese Patent Application Laid-Open No. 2002-015940

[0004] The multilayer ceramic capacitor of the present disclosure includes a substantially rectangular parallelepiped laminate formed by alternately stacking a plurality of internal electrodes and a plurality of dielectric layers, the laminate having first and second surfaces opposing each other in a stacking direction, a first side surface and a second side surface opposing each other in a length direction perpendicular to the stacking direction, and a third side surface and a fourth side surface opposing each other in a width direction perpendicular to the stacking direction and the length direction; and a plurality of external electrodes, wherein the plurality of internal electrodes include a plurality of first internal electrodes and a plurality of second internal electrodes, the plurality of first internal electrodes being exposed on the first side surface, and the plurality of second internal electrodes being exposed on the second side surface, the plurality of external electrodes including a first external electrode and a second external electrode, the first external electrode being located from the first side surface to at least the first surface and connected to the plurality of first internal electrodes, and the second external electrode being located from the second side surface to at least the first surface and connected to the plurality of second internal electrodes, The first external electrode and the second external electrode each have a principal surface electrode portion located on at least the first surface, and the principal surface electrode portion or an area of ​​the laminate that contacts the principal surface electrode portion has a first portion and a second portion that is thicker in the stacking direction than the first portion and is located closer to the center of the laminate than the first portion when viewed in the stacking direction.

[0005] The multilayer ceramic capacitor of the present disclosure includes a substantially rectangular parallelepiped laminate formed by alternately stacking a plurality of internal electrodes and a plurality of dielectric layers, the laminate having first and second surfaces opposing each other in a stacking direction, a first side surface and a second side surface opposing each other in a length direction perpendicular to the stacking direction, and a third side surface and a fourth side surface opposing each other in a width direction perpendicular to the stacking direction and the length direction; and a plurality of external electrodes, wherein the plurality of internal electrodes include a plurality of first internal electrodes and a plurality of second internal electrodes, the plurality of first internal electrodes being exposed at corners extending from the first side surface to the third side surface and at corners extending from the second side surface to the fourth side surface, and the plurality of second internal electrodes being exposed at corners extending from the first side surface to the fourth side surface and at corners extending from the second side surface to the third side surface, and the plurality of external electrodes including a first external electrode, a second external electrode, a third external electrode, and a fourth external electrode, the first external electrode is located from the corner extending from the first side surface to the third side surface across at least the first surface and is connected to the plurality of first internal electrodes; the second external electrode is located from the corner extending from the second side surface to the fourth side surface across at least the first surface and is connected to the plurality of first internal electrodes; the third external electrode is located from the corner extending from the first side surface to the fourth side surface across at least the first surface and is connected to the plurality of second internal electrodes; the fourth external electrode is located from the corner extending from the second side surface to the fourth side surface across at least the first surface and is connected to the plurality of second internal electrodes; the first external electrode, the second external electrode, the third external electrode and the fourth external electrode each have a main surface electrode portion located at least on the first surface, The main surface electrode portion or the area of ​​the laminate that contacts the main surface electrode portion has a first portion and a second portion that is thicker in the stacking direction than the first portion and is located closer to the center of the laminate than the first portion when viewed in the stacking direction.

[0006] A mounting structure according to the present disclosure includes the multilayer ceramic capacitor described above and a substrate having a mounting surface, wherein the multilayer ceramic capacitor is mounted on the substrate such that the first surface of the laminate faces the mounting surface.

[0007] Objects, features, and advantages of the present disclosure will become more apparent from the detailed description and drawings below.

[0023] Fig. 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present disclosure. Fig. 2 is a plan view showing the multilayer ceramic capacitor of Fig. 1. Fig. 3 is a cross-sectional view taken along the cross-sectional line III-III of Fig. 2. Fig. 3 is a perspective view showing a mounting structure according to an embodiment of the present disclosure. Fig. 4 is a cross-sectional view showing a state in which the multilayer ceramic capacitor of Fig. 1 is mounted on a substrate using a mounting device. Fig. 5 is a cross-sectional view showing a state in which the multilayer ceramic capacitor of Fig. 1 is mounted on a substrate using a mounting device. Fig. 6 is a cross-sectional view showing a state in which the multilayer ceramic capacitor of Fig. 1 is mounted on a substrate using a mounting device. Fig. 7 is a cross-sectional view showing an enlarged view of a portion of the multilayer ceramic capacitor of Fig. 1. Fig. 8 is a cross-sectional view showing an enlarged view of a portion of the multilayer ceramic capacitor of Fig. 1. Fig. 9 is a cross-sectional view showing an enlarged view of a portion of the multilayer ceramic capacitor of Fig. 1. Fig. 10 is a cross-sectional view showing an enlarged view of a portion of the multilayer ceramic capacitor of Fig. 1. Fig. 11 is a cross-sectional view showing an enlarged view of a portion of the multilayer ceramic capacitor of Fig. 1. Fig. 12 is a perspective view showing a multilayer ceramic capacitor according to another embodiment of the present disclosure. Fig. 13 is a cross-sectional view taken along the cross-sectional line XIV-XIV of Fig. 14. Fig. 14 is a perspective view showing a laminate of the multilayer ceramic capacitor of Fig. 12. Fig. 15 is a perspective view showing a mounting structure according to another embodiment of the present disclosure. Fig. 16 is a perspective view illustrating a process for producing a mother laminate. 23 is a perspective view showing a mother laminate; FIG. 24 is a perspective view showing a mother laminate on which a main surface electrode portion precursor is formed; FIG. 25 is a perspective view showing a laminate precursor obtained by cutting the mother laminate of FIG. 19; FIG. 26 is a perspective view showing a laminate obtained by firing and polishing the laminate precursor of FIG. 20; FIG. 27 is a perspective view illustrating a manufacturing process of a mother laminate; FIG. 28 is a perspective view showing a mother laminate; FIG. 29 is a perspective view showing a laminate precursor obtained by cutting the mother laminate of FIG. 23; FIG. 29 is a perspective view showing a laminate obtained by firing and polishing the laminate precursor of FIG. 24.

[0008] In recent years, as electronic devices have become smaller and more functional, electronic components such as multilayer ceramic capacitors mounted on electronic devices have also been made smaller and thinner. However, when a multilayer ceramic capacitor is made thinner, the strength of the laminate that constitutes the multilayer ceramic capacitor becomes insufficient, and the durability of the laminate is likely to decrease.

[0009] Patent Document 1 discloses a multilayer ceramic capacitor in which a free reinforcing layer is formed inside the laminate, thereby increasing the durability of the laminate.

[0010] As multilayer ceramic capacitors become thinner, the free reinforcing layers of conventional multilayer ceramic capacitors are unable to ensure sufficient strength for the laminate, resulting in cracks in the laminate and a decline in the electrical properties and reliability of the laminate ceramic capacitor. Furthermore, multilayer ceramic capacitors are typically mounted on substrates for use. However, if the laminate of a conventional multilayer ceramic capacitor is warped, the laminate abuts the substrate when the multilayer ceramic capacitor is pressed against the substrate, causing stress to concentrate in specific areas of the laminate, resulting in cracks. Alternatively, even if the laminate of a conventional multilayer ceramic capacitor is not warped, warping can occur in the substrate when the multilayer ceramic capacitor is pressed against the substrate, causing stress to concentrate in specific areas of the laminate, resulting in cracks.

[0011] Hereinafter, embodiments of the multilayer ceramic capacitor and mounting structure of the present disclosure will be described with reference to the drawings. The drawings used in the following description are schematic, and the dimensional ratios and the like in the drawings do not necessarily correspond to the actual ones. In this specification, a Cartesian coordinate system XYZ is defined in some of the drawings for convenience. The X-axis direction is also referred to as the first direction or length direction. The Y-axis direction is also referred to as the second direction or width direction. The Z-axis direction is also referred to as the third direction, height direction, or stacking direction. In this specification, a plan view means a view in the Z-axis direction.

[0012] FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present disclosure, FIG. 2 is a plan view showing the multilayer ceramic capacitor of FIG. 1, and FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 2. FIG. 4 is a perspective view showing a mounting structure according to an embodiment of the present disclosure. FIGS. 5 to 7 are cross-sectional views showing how the multilayer ceramic capacitor of FIG. 1 is mounted on a substrate using a mounting device. FIGS. 8 to 11 are cross-sectional views showing an enlarged portion of the multilayer ceramic capacitor of FIG. 1. FIG. 12 is a perspective view showing a multilayer ceramic capacitor according to another embodiment of the present disclosure, FIG. 13 is a plan view showing the multilayer ceramic capacitor of FIG. 12, FIG. 14 is a cross-sectional view taken along the line XIV-XIV in FIG. 13, and FIG. 15 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 12. FIG. 16 is a perspective view showing a mounting structure according to another embodiment of the present disclosure. Note that the substrates shown in FIGS. 4 and 16 have wiring conductors, electronic components, etc. located on the substrate, but the wiring conductors, electronic components, etc. are omitted from FIGS. 4 and 16. 5 to 7 are diagrams for explaining the strength of the multilayer ceramic capacitor, and therefore omit wiring conductors, electronic components, solder paste, conductive resin paste, etc., located on the substrate. In addition, in Fig. 15, for ease of illustration, the portions of the internal electrodes and dummy electrodes exposed on the surface of the laminate are shown hatched.

[0013] A multilayer ceramic capacitor according to an embodiment of the present disclosure will be described. The multilayer ceramic capacitor 1 of this embodiment may be a thin multilayer ceramic capacitor. The thin multilayer ceramic capacitor may be, for example, a multilayer ceramic capacitor in which the ratio of the dimension in the length direction (X-axis direction) to the dimension in the height direction (Z-axis direction) is greater than 4. Hereinafter, the multilayer ceramic capacitor 1 may be simply referred to as capacitor 1.

[0014] As shown in FIG. 1, the multilayer ceramic capacitor 1 of this embodiment includes a laminate 2 and a plurality of external electrodes 3 .

[0015] The laminate 2 is formed by alternately stacking a plurality of internal electrodes 6 and a plurality of dielectric layers 7 in the stacking direction (Z-axis direction). As shown in Fig. 3, the laminate 2 may include a capacitance forming portion 4 and a pair of cover portions 5. The capacitance forming portion 4 is formed by alternately stacking a plurality of internal electrodes 6 and a plurality of dielectric layers 7 in the Z-axis direction, and forms a capacitance. The cover portions 5 are located on both ends of the capacitance forming portion 4 in the stacking direction.

[0016] The laminate 2 has a substantially rectangular parallelepiped shape. The laminate 2 has a first surface 8a and a second surface 8b that face each other in the stacking direction. Hereinafter, the first surface 8a and the second surface 8b may be collectively referred to as the main surfaces 8a and 8b. The laminate 2 also has a first side surface 9a and a second side surface 9b that face each other in the length direction (X-axis direction) perpendicular to the stacking direction (Z-axis direction), and a third side surface 9c and a fourth side surface 9d that face each other in the width direction (Y-axis direction) perpendicular to the stacking direction (Z-axis direction) and the length direction (X-axis direction). Hereinafter, the first side surface 9a, the second side surface 9b, the third side surface 9c, and the fourth side surface 9d may be collectively referred to as the side surfaces 9a to 9d.

[0017] As shown in FIG. 3 , the multiple internal electrodes 6 include multiple first internal electrodes 6 a and multiple second internal electrodes 6 b. The first internal electrodes 6 a and the second internal electrodes 6 b have mutually different polarities. In other words, when the first internal electrode 6 a has a first polarity, the second internal electrode 6 b has a second polarity different from the first polarity. The first internal electrodes 6 a and the second internal electrodes 6 b are alternately arranged in the stacking direction, with the dielectric layer 7 sandwiched between them. The multiple first internal electrodes 6 a are exposed on a first side surface 9 a of the laminate 2. The multiple second internal electrodes 6 b are exposed on a second side surface 9 b of the laminate 2.

[0018] The internal electrodes 6 are made of a conductive material. The internal electrodes 6 may be made of a metal material whose main component is, for example, a metal such as Ni (nickel), Cu (copper), Sn (tin), Pt (platinum), Pd (palladium), Ag (silver), or Au (gold), or an alloy thereof. The main component refers to the component that is contained in the highest proportion in the material or member of interest.

[0019] The dielectric layer 7 is made of a dielectric material, for example, BaTiO ３ (barium titanate), CaTiO ３ (Calcium titanate), SrTiO ３ (strontium titanate), BaZrO ３ The ceramic material constituting the dielectric layer 7 may contain, as a secondary component, a manganese (Mn) compound, a magnesium (Mg) compound, a silicon (Si) compound, a rare earth compound, or the like, in a content lower than that of the primary component.

[0020] As shown in FIGS. 1 to 3 , the multiple external electrodes 3 include a first external electrode 3a and a second external electrode 3b. The first external electrode 3a is located from the first side surface 9a to at least the first surface 8a. The first external electrode 3a may be located from the first side surface 9a to the first surface 8a and the second surface 8b, or may be located from the first side surface 9a to the first surface 8a, the second surface 8b, the third side surface 9c, and the fourth side surface 9d. The first external electrode 3a is connected to the end of the first internal electrode 6a exposed at the first side surface 9a. The second external electrode 3b is located from the second side surface 9b to at least the first surface 8a. The second external electrode 3b may be located from the second side surface 9b to the first surface 8a and the second surface 8b, or may be located from the second side surface 9b to the first surface 8a, the second surface 8b, the third side surface 9c, and the fourth side surface 9d. The second external electrode 3b is connected to the end of the second internal electrode 6b exposed on the second side surface 9b.

[0021] The external electrodes 3 are made of a conductive material. The external electrodes 3 may be made of a metal material whose main component is, for example, a metal such as Ni, Cu, Sn, Pt, Pd, Ag, or Au, or an alloy thereof. The external electrodes 3 may be formed by a thin-film formation technique such as plating, sputtering, or vapor deposition, or by a thick-film formation technique such as inkjet printing, dipping, screen printing, or gravure printing. The plating method may be, for example, electroless plating or electrolytic plating. The external electrodes 3 may be made to contain a conductive resin. The conductive resin may be, for example, an epoxy resin or phenolic resin containing a metal powder such as Ag.

[0022] The external electrode 3 may be configured by stacking multiple conductive layers. The multiple conductive layers may include conductive layers formed by thin-film formation technology and conductive layers formed by thick-film formation technology. As will be described in detail later, the base layer of the external electrode 3 (i.e., a layer other than the outermost layer) may be configured to include at least one dielectric layer and at least one conductive layer. In this case, adjusting at least one of the thickness and the number of the dielectric layers makes it easy to partially change the thickness of the external electrode 3. The dielectric layer may be configured, for example, of a ceramic material or a conductive resin. The ceramic material may be the same ceramic material as the ceramic material constituting the dielectric layer 7.

[0023] As shown in FIGS. 1 to 3 , the first external electrode 3a and the second external electrode 3b include at least a principal surface electrode portion 30 located on the first surface 8a. When the first external electrode 3a and the second external electrode 3b are located on the first surface 8a and the second surface 8b, the first external electrode 3a and the second external electrode 3b may include a principal surface electrode portion 30 located on the first surface 8a and the second surface 8b. The principal surface electrode portion 30 includes a first portion (also referred to as a thin portion) 31 and a second portion (also referred to as a thick portion) 32. The second portion 32 is thicker in the stacking direction (Z-axis direction) than the first portion 31. Furthermore, as shown in FIG. 2 , the second portion 32 is located closer to a center C of the laminate 2 in the principal surface electrode portion 30 than the first portion 31 in a plan view. The center C may be the center (centroid) of the first surface 8a or the second surface 8b in a plan view.

[0024] As shown in Fig. 2, the second portion 32 may extend across the entire laminate 2 (the entire first surface 8a) in the width direction (Y-axis direction) in a plan view. As shown in Figs. 2 and 3, the second portion 32 may have a point 32H, where the height H from the first portion 31 is highest, located closer to the center C than the center line M of the principal-surface electrode portion 30. The center line M may be a line that bisects the length of the principal-surface electrode portion 30 in the length direction (X-axis direction). The second portion 32 may be located at the end of the principal-surface electrode portion 30 closer to the center C.

[0025] As described above, the laminate 2 may include a pair of cover portions 5. The cover portions 5 are made of a dielectric material, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , BaZrO ３ The cover portion 5 may be made of a ceramic material mainly composed of a material such as a tantalum or the like. The cover portion 5 may be made of a plurality of dielectric layers stacked in the stacking direction (Z-axis direction). The dielectric layer that constitutes the cover portion 5 may be the dielectric layer 7 that constitutes the capacitance forming portion 4.

[0026] The cover portion 5 may include dummy electrodes 5a that do not contribute to the formation of capacitance. As shown in FIG. 3 , the dummy electrodes 5a may be located at both ends of the cover portion 5 in the longitudinal direction (X-axis direction). The dummy electrodes 5a on the first side surface 9a side may be exposed to the first side surface 9a, and the dummy electrodes 5a on the second side surface 9b side may be exposed to the second side surface 9b. The dummy electrodes 5a on the first side surface 9a side and the dummy electrodes 5a on the second side surface 9b side are not electrically connected. The dummy electrodes 5a may be exposed on at least one of the first surface 8a and the second surface 8b, as long as they are covered by the external electrode 3. The dummy electrodes 5a may be exposed on the third side surface 9c and the fourth side surface 9d, as long as they are covered by the external electrode 3. By including the dummy electrodes 5a in the cover portion 5, the adhesion between the laminate 2 and the external electrode 3 can be improved, thereby improving the reliability of the capacitor 1.

[0027] As shown in FIG. 4 , the capacitor 1 may be mounted on a substrate (also referred to as a circuit board) 10. An electronic component obtained by mounting the capacitor 1 on the substrate 10 is referred to as a mounting structure 20. The substrate 10 has a mounting surface 10a on which a first mounting electrode 11 and a second mounting electrode 12 are disposed. The capacitor 1 is mounted on the substrate 10 via a conductive bonding material CA so that the principal surface electrode portions 30 of the first external electrode 3a and the second external electrode 3b are electrically connected to the first mounting electrode 11 and the second mounting electrode 12, respectively. The conductive bonding material CA may be, for example, solder, a conductive adhesive, or the like. When the principal surface electrode portions 30 are located only on the first surface 8a of the laminate 2, the capacitor 1 is mounted on the substrate 10 so that the first surface 8a of the laminate 2 faces the mounting surface 10a. When the main surface electrode portion 30 is located on both the first surface 8a and the second surface 8b, the capacitor 1 is mounted on the substrate 10 so that either the first surface 8a or the second surface 8b faces the mounting surface 10a.

[0028] As shown in Figures 5 and 6, the capacitor 1 is mounted on the substrate 10 by pressing the capacitor 1, which has been picked up by the suction nozzle 15 of the mounting device, against the substrate 10, which has a conductive bonding material CA applied to its first mounting electrode 11 and second mounting electrode 12. Note that the first mounting electrode 11, the second mounting electrode 12, and the conductive bonding material CA are omitted from Figures 5 and 6. If the main surface electrode portion 30 does not have the second portion 32 (i.e., if the thickness of the main surface electrode portion 30 is approximately constant), and the laminate 2 is warped, the laminate 2 may come into contact with the substrate 10 when the capacitor 1 is pressed against the substrate 10. As a result, stress may be concentrated in a specific region of the laminate 2 (e.g., a region near the center C), which may cause a crack to occur in the specific region.

[0029] In the capacitor 1, because the main surface electrode portion 30 has the second portion 32, even if the laminate 2 is warped, when the capacitor 1 is pressed against the substrate 10, the second portion 32 comes into contact with the substrate 10, making it difficult for the laminate 2 to come into contact with the substrate 10. As a result, the occurrence of cracks in the laminate 2 can be reduced.

[0030] When the second portion 32 is located at the end of the main-surface electrode portion 30 on the side of the center C, it is possible to reduce the concentration of stress in a specific region of the laminate 2 (for example, a region near the center C) when the capacitor 1 is pressed against the substrate 10, regardless of the direction of warping of the laminate 2. As a result, it is possible to effectively reduce the occurrence of cracks in the specific region of the laminate 2.

[0031] The principal surface electrode portion 30 (second portion 32) may be located on both the first surface 8a and the second surface 8b. In this case, when mounting the capacitor 1 on the substrate 10, either the first surface 8a or the second surface 8b may face the mounting surface 10a, which simplifies the effort required to confirm the surface of the laminate 2 on which the principal surface electrode portion 30 (second portion 32) is located. As a result, the manufacturing cost of the mounting structure 20 in which the capacitor 1 is mounted on the substrate 10 can be reduced.

[0032] When the total thickness of the laminate 2 in the lamination direction (Z-axis direction) is Ttot, the thickness of the center C is Tc, and the height of the second portion 32 relative to the first portion 31 (hereinafter simply referred to as the height of the second portion 32) is H, the capacitor 1 may satisfy the following formula (1): Ttot - Tc < H (1)

[0033] The total thickness Ttot in formula (1) may be the length between the upper and lower ends of the laminate 2 in the stacking direction (Z-axis direction), as shown in Figures 5 and 6. The left side of formula (1) represents the warpage of the laminate 2. Because the height H of the second portion 32 is greater than the warpage of the laminate 2, even if the laminate 2 is warped, when the capacitor 1 is pressed against the substrate 10, the laminate 2 does not abut against the substrate 10, and the second portion 32 can abut against the substrate 10. As a result, stress concentration in a specific region of the laminate 2 (e.g., a region near the center C) can be reduced, and the occurrence of cracks in the laminate 2 can be reduced. This, in turn, reduces degradation of the electrical characteristics and reliability of the capacitor 1 and the mounting structure 20.

[0034] The height H of the second portion 32 may be, for example, less than 10 μm. In a small multilayer ceramic capacitor 1, for example, a capacitor 1 having dimensions of 2 mm or less in the length direction (X-axis direction) and width direction (Y-axis direction), the warpage of the laminate 2 is substantially less than 10 μm, and may even be less than 5 μm. Therefore, the second portion 32 can satisfy both formula (1) and H<10 μm. By setting the height H of the second portion 32 to less than 10 μm, the increase in manufacturing costs associated with forming the second portion 32 during manufacturing of the capacitor 1 can be suppressed. As a result, the manufacturing costs of the capacitor 1 can be reduced.

[0035] As shown in FIG. 7 , even if the laminate 2 does not warp, the substrate 10 may warp when the capacitor 1 is pressed against it. If the main-surface electrode portion 30 does not have the second portion 32, both ends of the capacitor 1 in the length direction (X-axis direction) abut against the substrate 10, which may result in stress concentrating in a specific region of the laminate 2 (e.g., a region near the center C), causing cracks to form in the specific region. Even if the substrate 10 warps when the capacitor 1 is pressed against it, the second portion 32 abuts against the substrate 10, making it less likely that both ends of the capacitor 1 in the length direction will abut against the substrate 10. As a result, the occurrence of cracks in the laminate 2 can be reduced.

[0036] As shown in FIG. 7 , when a point on the mounting surface 10a that overlaps with the center C in a planar view is designated as 10b, and points 10c and 10d that overlap with both ends of the laminate 2 in the longitudinal direction (X-axis direction) in a planar view are designated as 10c and 10d, respectively, the warpage of the substrate 10 may be a length L1 between points 10b and 10c in the stacking direction (Z-axis direction) or a length L2 between points 10b and 10d in the stacking direction. The warpage of the substrate 10 may be the longer of lengths L1 and L2. The warpage of the substrate 10 can be predicted in advance by taking into account the dimensions of the capacitor 1, the force pressing the capacitor 1 against the mounting surface 10a, and other factors. By making the height H of the second portion 32 greater than the warpage of the substrate 10, even if the substrate 10 warps, both ends of the capacitor 1 in the longitudinal direction are less likely to abut against the substrate 10, thereby reducing the likelihood of cracks occurring in the laminate 2.

[0037] Next, the configuration and method of forming the first portion 31 and the second portion 32 of the principal surface electrode portion 30 will be described.

[0038] The principal surface electrode portion 30 may be composed of at least one conductor layer. As shown in FIG. 8 , the principal surface electrode portion 30 may be composed of multiple conductor layers 30a, 30b, and 30c. The second portion 32 may be composed of conductor layers 30a, 30b, and 30c. The conductor layers 30a, 30b, and 30c that constitute the second portion 32 may be stacked in this order on the principal surfaces 8a and 8b. The first portion 31 may be composed of conductor layers 30a and 30c. The conductor layers 30a and 30c that constitute the first portion 31 may be stacked in this order on the principal surfaces 8a and 8b.

[0039] The conductor layer 30a may be formed by the above-mentioned thick film formation technique. The conductor layer 30a may be a dummy electrode 5a constituting part of the principal surfaces 8a, 8b. The conductor layer 30b covers part of the conductor layer 30a. The conductor layer 30b may be formed by the above-mentioned thick film formation technique. The conductor layer 30b may be formed by an inkjet method or a screen printing method. The conductor layer 30c covers the conductor layers 30a and 30b. The conductor layer 30c may be formed by the above-mentioned thin film formation technique. The conductor layer 30c may be formed by an electroless plating method or an electrolytic plating method. The conductor layer 30c may extend from on the conductor layers 30a, 30b to the side surfaces 9a to 9d of the laminate 2. The conductor layer 30c may be connected to the ends of the internal electrodes 6 exposed on the side surfaces 9a to 9d. By configuring the principal-surface electrode portion 30 with multiple conductor layers 30a, 30b, and 30c and by differentiating the number of conductor layers 30a, 30b, and 30c that constitute the second portion 32 from the number of conductor layers 30a, 30c that constitute the first portion 31, it is possible to easily form the principal-surface electrode portion 30 having the first portion 31 and the second portion 32. The laminate 2 may or may not have a dummy electrode 5a. However, if the laminate 2 has a dummy electrode 5a, the dummy electrode 5a is exposed on the first side surface 9a and the second side surface 9b where the external electrodes 3 are located. This allows a plating layer (conductor layer 30c) that constitutes part of the external electrodes 3 to be directly formed on the fired laminate 2 during the manufacturing process of the multilayer ceramic capacitor 1, eliminating the need for a process of applying a conductive paste as a base for the plating layer. Furthermore, this also improves adhesion between the laminate 2 and the conductor layer 30c. As a result, the deterioration of the electrical characteristics and reliability of the capacitor 1 can be reduced.

[0040] The principal surface electrode portion 30 may be composed of at least one dielectric layer and at least one conductor layer. As shown in FIG. 9 , the principal surface electrode portion 30 may be composed of a dielectric layer 30d and multiple conductor layers 30e and 30f. The second portion 32 may be composed of a dielectric layer 30d and conductor layers 30e and 30f. The dielectric layer 30d, the conductor layer 30e, and the conductor layer 30f constituting the second portion 32 may be stacked in this order on the principal surfaces 8a and 8b. The first portion 31 may be composed of conductor layers 30e and 30f. The conductor layers 30e and 30f constituting the first portion 31 may be stacked in this order on the principal surfaces 8a and 8b.

[0041] The dielectric layer 30d may be formed by firing a ceramic green sheet. The ceramic green sheet for the dielectric layer 30d may be formed by arranging a ceramic green sheet on at least one of the upper and lower surfaces of a base laminate when preparing the base laminate for constituting the laminate 2 (see FIG. 22). As shown in FIG. 9, when the second portion 32 is located at the end of the main-surface electrode portion 30 on the center C side, the dielectric layer 30d may extend further toward the center C. The conductor layer 30e contacts parts of the main surfaces 8a and 8b and covers part of the dielectric layer 30d. The conductor layer 30e may be formed by a thick-film formation technique. The conductor layer 30f covers the conductor layer 30e. The conductor layer 30f may cover part of the dielectric layer 30d. The conductor layer 30f may be formed by a thin-film formation technique. The conductor layer 30f may be formed by an electroless plating method or an electrolytic plating method. The conductor layer 30f may extend from on the conductor layer 30e to the side surfaces 9a to 9d of the laminate 2. The conductor layer 30f may be connected to the ends of the internal electrodes 6 exposed on the side surfaces 9a to 9d. By configuring the second portion 32 with the dielectric layer 30d and the conductor layers 30e and 30f and configuring the first portion 31 with the conductor layers 30e and 30f, it becomes possible to easily form a principal surface electrode portion 30 having a first portion (thin portion) 31 and a second portion (thick portion) 32. Furthermore, by adjusting the thickness of the dielectric layer 30d, the height H of the second portion 32 can be adjusted. The laminate 2 may or may not have a dummy electrode 5a. However, if the laminate 2 has the dummy electrode 5a, the dummy electrode 5a is exposed on the first and second side surfaces 9a and 9b where the external electrodes 3 are located. This allows a plating layer (conductor layer 30f) that forms part of the external electrodes 3 to be directly formed on the fired laminate 2 during the manufacturing process of the multilayer ceramic capacitor 1, eliminating the need for a process for applying a conductive paste as a base for the plating layer. This also improves adhesion between the laminate 2 and the conductor layer 30f. As a result, deterioration in the electrical characteristics and reliability of the capacitor 1 can be reduced.

[0042] In the capacitor 1 shown in FIG. 9 , the principal-surface electrode portion 30 is made of a conductor layer 30f, the laminate 2 further includes a dielectric layer 30d and a conductor layer 30e, and the region of the laminate 2 in contact with the principal-surface electrode portion 30 (conductor layer 30f) can be said to have a configuration including a first portion 31′ and a second portion 32′ that is thicker in the stacking direction than the first portion 31′ and is located closer to the center C of the laminate 2 than the first portion 31′ when viewed in the stacking direction. Note that the first portion 31′ is not located with the dielectric layer 30d, and the second portion 32′ is located with the dielectric layer 30d. In this case, when the capacitor 1 is mounted on the substrate 10, the second portion 32′ covering the second portion 32′ of the principal-surface electrode portion 30 (located directly above the second portion 32′) abuts against the substrate 10, making it difficult for the laminate 2 and both ends of the capacitor 1 in the longitudinal direction to abut against the substrate 10. As a result, it is possible to reduce the occurrence of cracks in the laminate 2. The first portion 31' and the second portion 32' may be located on one of the first surface 8a and the second surface 8b, or may be located on both of them.

[0043] 10 , the second portion 32 may be formed by alternately stacking a plurality of dielectric layers 30d and a plurality of conductor layers 30e on the main surfaces 8a and 8b, and forming a conductor layer 30f that covers the stack of the plurality of dielectric layers 30d and the plurality of conductor layers 30e. In this case, it becomes easy to adjust the height H of the second portion 32. Alternatively, the first portion 31 may be formed by stacking a plurality of conductor layers 30e and forming a conductor layer 30f that covers the stack of the plurality of conductor layers 30e.

[0044] 10 , the capacitor 1 has a principal surface electrode portion 30 made of a conductor layer 30f, a laminate 2 further including two dielectric layers 30d and two conductor layers 30e, and the region of the laminate 2 in contact with the principal surface electrode portion 30 (conductor layer 30f) can also be said to have a configuration including a first portion 31′ and a second portion 32′ that is thicker in the stacking direction than the first portion 31′ and is located closer to the center of the laminate 2 in the stacking direction than the first portion 31′. The first portion 31′ is a portion that does not overlap with the dielectric layer 30d in the stacking direction, and the second portion 32′ is a portion that overlaps with the dielectric layer 30d in the stacking direction. In this case, when the capacitor 1 is mounted on the substrate 10, the second portion 32 covering the second portion 32' of the main surface electrode portion 30 (located directly above the second portion 32') abuts against the substrate 10, making it difficult for the laminate 2 and both ends of the capacitor 1 in the longitudinal direction to abut against the substrate 10. As a result, it is possible to reduce the occurrence of cracks in the laminate 2. The first portion 31' and the second portion 32' may be located on either the first surface 8a or the second surface 8b, or may be located on both surfaces.

[0045] 11 , the principal surface electrode portion 30 may be composed of a dielectric layer 30g and a plurality of conductor layers 30h, 30i, and 30j. The second portion 32 may be composed of a dielectric layer 30g and a plurality of conductor layers 30h, 30i, and 30j. The conductor layer 30h, the dielectric layer 30g, the conductor layer 30i, and the conductor layer 30j constituting the second portion 32 may be stacked in this order on the principal surfaces 8a and 8b. The first portion 31 may be composed of conductor layers 30h, 30i, and 30j. The conductor layer 30h, the conductor layer 30i, and the conductor layer 30j constituting the first portion 31 may be stacked in this order on the principal surfaces 8a and 8b.

[0046] The conductor layer 30h may be formed by the above-mentioned thick film formation technique. The conductor layer 30h may be a dummy electrode 5a constituting part of the principal surfaces 8a, 8b. The dielectric layer 30g covers part of the conductor layer 30h. The dielectric layer 30g may be formed by firing a ceramic green sheet. The ceramic green sheet that becomes the dielectric layer 30g may be formed by applying ceramic slurry to the principal surfaces 8a, 8b and the conductor layer 30h and drying it. The conductor layer 30i covers part of the conductor layer 30h and part of the dielectric layer 30g. The conductor layer 30h may be formed by the above-mentioned thick film formation technique. The conductor layer 30j covers the conductor layer 30i. The conductor layer 30j may cover part of the dielectric layer 30g. The conductor layer 30j may be formed by the above-mentioned thin film formation technique. The conductor layer 30j may be formed by electroless plating or electrolytic plating. The conductor layer 30j may extend from the conductor layer 30i across the side surfaces 9a to 9d of the laminate 2. The conductor layer 30j may be connected to the ends of the internal electrodes 6 exposed on the side surfaces 9a to 9d. By forming the second portion 32 from the dielectric layer 30g and the conductor layers 30h, 30i, and 30j and forming the first portion 31 from the conductor layers 30h, 30i, and 30j, it becomes possible to easily form the principal surface electrode portion 30 having the first portion (thin portion) 31 and the second portion (thick portion) 32. Furthermore, the height H of the second portion 32 can be adjusted by adjusting the thickness of the dielectric layer 30g. The laminate 2 may or may not have a dummy electrode 5a. However, if the laminate 2 has a dummy electrode, the dummy electrode 5a is exposed on the first and second side faces 9a and 9b where the external electrodes 3 are located. This allows a plating layer (conductor layer 30j) that forms part of the external electrodes 3 to be formed directly on the fired laminate 2 during the manufacturing process of the multilayer ceramic capacitor 1, eliminating the need for a process for applying a conductive paste as a base for the plating layer. This also improves adhesion between the laminate 2 and the conductor layer 30f. As a result, deterioration in the electrical characteristics and reliability of the capacitor 1 can be reduced.

[0047] 11 , the capacitor 1 has a principal surface electrode portion 30 made of a conductor layer 30j, a laminate 2 further including a dielectric layer 30g and conductor layers 30h and 30i, and the region of the laminate 2 in contact with the principal surface electrode portion 30 (conductor layer 30j) can also be said to have a configuration including a first portion 31′ and a second portion 32′ that is thicker in the stacking direction than the first portion 31′ and is located closer to the center C of the laminate 2 than the first portion 31′ in the stacking direction. The first portion 31′ is a portion that does not overlap with the dielectric layer 30g in the stacking direction, and the second portion 32′ is a portion that overlaps with the dielectric layer 30g in the stacking direction. In this case, when the capacitor 1 is mounted on the substrate 10, the second portion 32 covering the second portion 32' of the main surface electrode portion 30 (located directly above the second portion 32') abuts against the substrate 10, making it difficult for the laminate 2 and both ends of the capacitor 1 in the longitudinal direction to abut against the substrate 10. As a result, it is possible to reduce the occurrence of cracks in the laminate 2. The first portion 31' and the second portion 32' may be located on either the first surface 8a or the second surface 8b, or may be located on both surfaces.

[0048] When the laminate 2 has the first portion 31′ and the second portion 32′, the capacitor 1 may satisfy the above formula (1), where Ttot is the total thickness of the laminate 2 excluding the first portion 31′ and the second portion 32′, Tc is the thickness of the center portion C of the laminate 2, and H is the height of the second portion 32′ relative to the first portion 31′. In this case, even if the laminate 2 is warped, when the capacitor 1 is pressed against the substrate 10, the laminate 2 does not abut against the substrate 10, and the second portion 32 of the principal surface electrode portion 30 can abut against the substrate 10. As a result, stress concentration in a specific region of the laminate 2 (e.g., the region near the center portion C) can be reduced, and the occurrence of cracks in the laminate 2 can be reduced. This in turn reduces degradation of the electrical characteristics and reliability of the capacitor 1 and the mounting structure 20.

[0049] The height H of the second portion 32' relative to the first portion 31' may be, for example, less than 10 μm. In a small multilayer ceramic capacitor 1, for example, a capacitor 1 having dimensions of 2 mm or less in the length and width directions, the warpage of the laminate 2 is substantially less than 10 μm, and may even be less than 5 μm. Therefore, the second portion 32' satisfies both formula (1) and H<10 μm. By setting the height H of the second portion 32' to less than 10 μm, the increase in manufacturing costs associated with forming the second portion 32' can be suppressed during the manufacture of the capacitor 1. As a result, the manufacturing costs of the capacitor 1 can be reduced.

[0050] Next, a multilayer ceramic capacitor according to a second embodiment of the present disclosure will be described. A multilayer ceramic capacitor 1A according to this embodiment differs from the multilayer ceramic capacitor 1 described above in the structures of the internal electrodes 6 and the external electrodes 3, but is otherwise similar to the multilayer ceramic capacitor 1 (e.g., the outer shape of the laminate 2, the materials of each component, etc.). Therefore, detailed description of the similar configuration will be omitted.

[0051] As shown in FIG. 12, the multilayer ceramic capacitor 1A includes a laminate 2 and a plurality of external electrodes 3.

[0052] 14, the multiple internal electrodes 6 include multiple first internal electrodes 6a and multiple second internal electrodes 6b. The first internal electrodes 6a and the second internal electrodes 6b have opposite polarities. The first internal electrodes 6a and the second internal electrodes 6b are alternately arranged in the stacking direction with the dielectric layer 7 interposed therebetween.

[0053] As shown in Fig. 15, the multiple first internal electrodes 6a are exposed at corners 2a extending from the first side surface 9a to the third side surface 9c and at corners 2b extending from the second side surface 9b to the fourth side surface 9d. As shown in Fig. 15, the multiple second internal electrodes 6b are exposed at corners 2c extending from the first side surface 9a to the fourth side surface 9d and at corners 2d extending from the second side surface 9b to the third side surface 9c.

[0054] As shown in FIGS. 12 and 13, the plurality of external electrodes 3 include a first external electrode 3a, a second external electrode 3b, a third external electrode 3c, and a fourth external electrode 3d.

[0055] The first external electrode 3a is located from the corner 2a extending from the first side surface 9a to the third side surface 9c across at least the first surface 8a. The first external electrode 3a may be located from the corner 2a extending from the first side surface 9a to the third side surface 9c across the first surface 8a and the second surface 8b. The first external electrode 3a is connected to the end of the first internal electrode 6a exposed at the corner 2a. The second external electrode 3b is located from the corner 2b extending from the second side surface 9b to the fourth side surface 9d across at least the first surface 8a. The second external electrode 3b may be located from the corner 2b extending from the second side surface 9b to the fourth side surface 9d across the first surface 8a and the second surface 8b. The second external electrode 3b is connected to the end of the first internal electrode 6a exposed at the corner 2b.

[0056] The third external electrode 3c is located from a corner 2c extending from the first side surface 9a to the fourth side surface 9d across at least the first surface 8a. The third external electrode 3c may be located from a corner 2c extending from the first side surface 9a to the fourth side surface 9d across the first surface 8a and the second surface 8b. The third external electrode 3c is connected to an end of the second internal electrode 6b exposed at the corner 2c. The fourth external electrode 3d is located from a corner 2d extending from the second side surface 9b to the third side surface 9c across at least the first surface 8a. The fourth external electrode 3d may be located from a corner 2d extending from the second side surface 9b to the third side surface 9c across the first surface 8a and the second surface 8b. The fourth external electrode 3d is connected to an end of the second internal electrode 6b exposed at the corner 2d.

[0057] As shown in Figures 12 to 14, the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d each include a principal surface electrode portion 30 located on at least the first surface 8a. When the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d are located on the first surface 8a and the second surface 8b, the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d may each include a principal surface electrode portion 30 located on the first surface 8a and the second surface 8b. The principal surface electrode portion 30 includes a first portion (also referred to as a thin portion) 31 and a second portion (also referred to as a thick portion) 32. The second portion 32 is thicker in the stacking direction (Z-axis direction) than the first portion 31. 13 , in plan view, the second portion 32 is located closer to the center C of the laminate 2 in the principal-surface electrode portion 30 than the first portion 31. The center C may be the center (centroid) of the first surface 8 a or the second surface 8 b in plan view.

[0058] As shown in Figures 13 and 14 , the second portion 32 only needs to have a point 32H, where the height H is highest from the first portion 31, located closer to the center C than the center line M of the principal-surface electrode portion 30 in the direction of the diagonal of the first surface 8a or the second surface 8b (hereinafter also referred to as the diagonal direction). The center line M may be a line that bisects the length of the principal-surface electrode portion 30 in the diagonal direction. The second portion 32 may be located at the end of the principal-surface electrode portion 30 closer to the center C. Figure 13 shows an example in which the shape of the second portion 32 in plan view is a sector (quadrants), but this is not limiting. The shape of the second portion 32 in plan view may be, for example, a rectangle, a right-angled triangle, or the like.

[0059] As shown in Fig. 16 , capacitor 1A may be mounted on a substrate (also referred to as a circuit board) 10. An electronic component obtained by mounting capacitor 1A on substrate 10 is referred to as mounting structure 20A. Substrate 10 has a mounting surface 10a on which first mounting electrode 11, second mounting electrode 12, third mounting electrode 13, and fourth mounting electrode 14 are arranged. Capacitor 1A is mounted on substrate 10 via conductive bonding material CA so that main surface electrode portions 30 of first external electrode 3a, second external electrode 3b, third external electrode 3c, and fourth external electrode 3d are electrically connected to first mounting electrode 11, second mounting electrode 12, third mounting electrode 13, and fourth mounting electrode 14, respectively. When the principal surface electrode portion 30 is located on only one of the first surface 8a and the second surface 8b of the laminate 2, the capacitor 1A is mounted on the substrate 10 so that the surface of the laminate 2 on which the principal surface electrode portion 30 is located faces the mounting surface 10a. When the principal surface electrode portion 30 is located on both the first surface 8a and the second surface 8b, the capacitor 1A is mounted on the substrate 10 so that either the first surface 8a or the second surface 8b faces the mounting surface 10a.

[0060] Capacitor 1A is mounted on substrate 10 by pressing capacitor 1A, which is picked up by suction nozzle 15 of a mounting device, against substrate 10, which has conductive bonding material CA applied to first mounting electrode 11, second mounting electrode 12, third mounting electrode 13, and fourth mounting electrode 14 (see FIGS. 5 to 7 ). Because main surface electrode portion 30 of capacitor 1A has second portion 32, even if laminate 2 is warped, when capacitor 1A is pressed against substrate 10, second portion 32 abuts against substrate 10, making it difficult for the ends of laminate 2 (ends in the length direction and ends in the width direction) to abut against substrate 10. As a result, the occurrence of cracks in laminate 2 can be reduced.

[0061] When the second portion 32 is located at the end of the main-surface electrode portion 30 on the side of the center C, it is possible to reduce stress concentration in a specific region of the laminate 2 (for example, a region near the center C) when the capacitor 1A is pressed against the substrate 10, regardless of the direction of warping of the laminate 2. As a result, it is possible to effectively reduce the occurrence of cracks in the specific region of the laminate 2.

[0062] The principal surface electrode portion 30 (second portion 32) may be located on both the first surface 8a and the second surface 8b. In this case, when mounting the capacitor 1A on the substrate 10, either the first surface 8a or the second surface 8b may face the mounting surface 10a, which simplifies the effort required to confirm the surface of the laminate 2 on which the principal surface electrode portion 30 (second portion 32) is located. As a result, the manufacturing cost of the mounting structure 20 in which the capacitor 1A is mounted on the substrate 10 can be reduced.

[0063] The capacitor 1A may satisfy the above formula (1). The total thickness Ttot, the thickness Tc of the center C, and the height H of the second portion 32 are the same as those described above. Because the height H of the second portion 32 is greater than the warpage of the laminate 2 (the left side of formula (1)), even if the laminate 2 warps, when the capacitor 1A is pressed against the substrate 10, the laminate 2 does not abut against the substrate 10, and the second portion 32 can abut against the substrate 10. As a result, stress concentration in a specific region of the laminate 2 (e.g., a region near the center C) can be reduced, and the occurrence of cracks in the laminate 2 can be reduced. This, in turn, reduces degradation of the electrical characteristics and reliability of the capacitor 1A and the mounting structure 20A.

[0064] The height H of the second portion 32 may be, for example, less than 10 μm. In a small multilayer ceramic capacitor 1A, for example, a capacitor 1A having dimensions of 2 mm or less in the length direction (X-axis direction) and width direction (Y-axis direction), the warpage of the laminate 2 is substantially less than 10 μm, and may even be less than 5 μm. Therefore, the second portion 32 can satisfy both formula (1) and H<10 μm. By setting the height H of the second portion 32 to less than 10 μm, the increase in manufacturing costs associated with forming the second portion 32 can be suppressed during the manufacturing of the capacitor 1A. As a result, the manufacturing cost of the capacitor 1A can be reduced.

[0065] As with capacitor 1, even if capacitor 1A is pressed against substrate 10 and warps, second portion 32 abuts against substrate 10, making it difficult for both ends of capacitor 1A in the longitudinal direction to abut against substrate 10. As a result, it is possible to reduce the occurrence of cracks in laminate 2. Furthermore, by making height H of second portion 32 larger than the warpage of substrate 10, it is possible to reduce the occurrence of cracks in laminate 2, making it difficult for both ends of capacitor 1A in the longitudinal direction to abut against substrate 10, even if warpage occurs in substrate 10.

[0066] Next, a manufacturing method of the multilayer ceramic capacitors 1, 1A will be described. The manufacturing method of the multilayer ceramic capacitor 1A will be described below. The multilayer ceramic capacitor 1 can be manufactured by the same manufacturing method as the multilayer ceramic capacitor 1A. Note that each component of the multilayer ceramic capacitor 1A has the same structure before and after cutting the base laminate, and also has the same structure before and after firing, so the above-mentioned terms and reference symbols may be used in the following description.

[0067] Fig. 17 is a perspective view illustrating the process for producing a mother laminate, Fig. 18 is a perspective view illustrating the mother laminate, Fig. 19 is a perspective view illustrating the mother laminate on which principal surface electrode portion precursors have been formed, Fig. 20 is a perspective view illustrating a laminate precursor obtained by cutting the mother laminate of Fig. 19, and Fig. 21 is a perspective view illustrating a laminate obtained by firing and polishing the laminate precursor of Fig. 20. Fig. 22 is a perspective view illustrating the process for producing a mother laminate, Fig. 23 is a perspective view illustrating the mother laminate, Fig. 24 is a perspective view illustrating a laminate precursor obtained by cutting the mother laminate of Fig. 23, and Fig. 25 is a perspective view illustrating a laminate obtained by firing and polishing the laminate precursor of Fig. 24. In Figs. 17 to 25, for ease of illustration, internal electrode patterns, dummy electrode patterns, precursors of conductor layers, etc. are shown with hatching.

[0068] An example of a manufacturing method for the multilayer ceramic capacitor 1A (hereinafter also referred to as a first manufacturing method) will be described. The first manufacturing method is a method for manufacturing the capacitor 1A having the main surface electrode portion 30 shown in Fig. 8. The first manufacturing method includes the steps of preparing a base laminate, preparing an unfired laminate, firing the unfired laminate, polishing the laminate, and forming external electrodes.

[0069] First, BaTiO ３ A raw material powder containing the above-mentioned as a main component is prepared, and an organic vehicle is mixed with the prepared raw material powder to prepare a ceramic slurry. The organic vehicle used to prepare the ceramic slurry may be, for example, a resin such as a butyral resin dissolved in a solvent mixture of ethyl alcohol and toluene.

[0070] Next, the prepared ceramic slurry is used to form a ceramic green sheet 16, which will become the dielectric layer 7, on a carrier film by a sheet forming method such as a die coater method, a doctor blade method, or a gravure coater method. The thinner the ceramic green sheet 16, the greater the capacitance of the multilayer ceramic capacitor can be.

[0071] Next, an organic vehicle is mixed with a powder containing a metal such as Ni, Cu, Sn, Pt, Pd, Ag, or Au, or an alloy thereof, as a main component, to prepare a conductive paste. The organic vehicle used to prepare the conductive paste may be, for example, a resin such as ethyl cellulose dissolved in a solvent mixture of a dihydroterpineol-based solvent and butyl cellosolve. A dispersant such as oleic acid or polyethylene glycol may be added to the conductive paste.

[0072] Next, an internal electrode pattern that will become the internal electrodes 6 is printed on the main surface of the ceramic green sheet 16 using the prepared conductive paste, to produce an internal electrode sheet 17. Furthermore, a dummy electrode pattern that will become the dummy electrodes 5a is printed on the main surface of the ceramic green sheet 16 using the prepared conductive paste, to produce a dummy electrode sheet 18. The internal electrode pattern and the dummy electrode pattern can be printed by a printing method such as screen printing or gravure printing.

[0073] Next, as shown in FIG. 17 , a predetermined number of dummy electrode sheets 18 are stacked, and then a predetermined number of internal electrode sheets 17 and a predetermined number of dummy electrode sheets 18 are stacked thereon to produce a temporary laminate. The predetermined number of internal electrode sheets 17 may be stacked while being offset by a predetermined distance. The predetermined distance may be, for example, half the period of the internal electrode pattern. In producing the temporary laminate, as shown in FIG. 17 , at least one ceramic green sheet 16 may be placed between the predetermined number of stacked dummy electrode sheets 18 and the predetermined number of stacked internal electrode sheets 17. Although not shown in FIG. 17 , the temporary laminate may be produced on a support sheet. The support sheet may be, for example, an adhesive release sheet such as a weak adhesive sheet or a foam release sheet.

[0074] Next, the temporary laminate is pressed in the stacking direction to obtain a base laminate 19 as shown in Fig. 18. The temporary laminate can be pressed using, for example, an isostatic press. The dummy electrode patterns exposed on the upper and lower surfaces of the base laminate 19 are precursors of the conductive layers 30a of the second portion 32 (see Fig. 8).

[0075] Next, as shown in Fig. 19, a precursor of the conductor layer 30b (see Fig. 8) of the second portion 32 is formed on the dummy electrode patterns exposed on the upper and lower surfaces of the base laminate 19. The precursor of the conductor layer 30b may be formed by an inkjet method or a screen printing method. The dummy electrode patterns exposed on the upper and lower surfaces of the base laminate 19 and the precursor of the conductor layer 30b are also referred to as main surface electrode portion precursors.

[0076] Next, the base laminate 19 is cut along the grid-shaped planned cutting lines CL (see FIG. 19 ) to produce a plurality of unsintered laminates 2 (hereinafter simply referred to as unsintered laminates 2 or laminate precursors) in which the main surface electrode portion precursors are located on the first surface 8 a and the second surface 8 b, as shown in FIG. 20 . The base laminate 19 may be cut while placed on a support sheet. The base laminate 19 may be cut using, for example, a press cutter, a dicing saw, or the like.

[0077] Next, the green laminate 2 is fired. The firing temperature may be set appropriately, and may be, for example, about 1100 to 1250°C. The green laminate 2 may be subjected to a degreasing treatment. The degreasing treatment may be performed in an air atmosphere, an inert gas atmosphere, or a reducing atmosphere. The degreasing treatment may be performed under atmospheric pressure or under reduced pressure. The fired laminate 2 may also be subjected to a re-oxidation treatment in an oxidizing atmosphere.

[0078] Next, the fired laminate 2 is placed in a rotary pot containing an abrasive and barrel-polished. This removes burrs from the surface of the laminate 2, rounds the corners, and fully exposes the internal electrodes 6 and dummy electrodes 5a at the corners 2a, 2b, 2c, and 2d. FIG. 21 shows the laminate 2 after polishing. By fully exposing the internal electrodes 6 at the corners 2a, 2b, 2c, and 2d, the internal electrodes 6 and the external electrodes 3 can be bonded well. Furthermore, by fully exposing the dummy electrodes 5a at the corners 2a, 2b, 2c, and 2d, the bonding strength between the laminate 2 and the external electrodes 3 can be increased. As a result, the electrical characteristics and reliability of the capacitor 1A can be improved.

[0079] Next, a conductor layer 30c is formed on the polished laminate 2 by plating, such as electroless plating or electrolytic plating, so as to cover the conductor layers 30a, 30b, thereby forming the external electrodes 3 (first external electrode 3a, second external electrode 3b, third external electrode 3c, and fourth external electrode 3d). This allows the manufacture of a multilayer ceramic capacitor 1A having the main surface electrode portion 30 shown in FIG.

[0080] Next, another example of a manufacturing method for the multilayer ceramic capacitor 1A (hereinafter also referred to as a second manufacturing method) will be described. The second manufacturing method is a method for manufacturing a capacitor 1A having the main surface electrode portion 30 shown in FIG. 9. The second manufacturing method includes the steps of preparing a base laminate, preparing an unfired laminate, firing the unfired laminate, polishing the laminate, and forming external electrodes. Note that detailed descriptions of steps similar to those in the first manufacturing method will be omitted.

[0081] First, in the same manner as in the first manufacturing method, the ceramic green sheets 16, the internal electrode sheets 17, and the dummy electrode sheets 18 are prepared.

[0082] Next, as shown in FIG. 22 , a conductor layer pattern 24 and a dielectric layer pattern 23 are stacked, and then a predetermined number of dummy electrode sheets 18, a predetermined number of internal electrode sheets 17, and a predetermined number of dummy electrode sheets 18 are stacked thereon, followed by stacking the dielectric layer pattern 23 and the conductor layer pattern 24 to produce a temporary laminate. The dielectric layer pattern 23 is a precursor of the dielectric layer 30d of the principal surface electrode portion 30 shown in FIG. 9 . The conductor layer pattern 24 is a precursor of the conductor layer 30e of the principal surface electrode portion 30 shown in FIG. 9 . The predetermined number of internal electrode sheets 17 may be stacked while being offset by a predetermined distance. The predetermined distance may be, for example, half the period of the internal electrode pattern. In producing the temporary laminate, as shown in FIG. 22 , at least one ceramic green sheet 16 may be placed between the predetermined number of stacked dummy electrode sheets 18 and the predetermined number of stacked internal electrode sheets 17. Although not shown in FIG. 22 , the temporary laminate may be produced on a support sheet. The support sheet may be, for example, a weak adhesive sheet or an adhesive release sheet such as a foam release sheet.

[0083] As shown in FIG. 22 , the dielectric layer pattern 23 is a lattice pattern and includes first band portions 23 a extending in a predetermined direction and second band portions 23 b extending in a direction intersecting the predetermined direction. A center (also referred to as a lattice point) 23 c in a plan view of the intersection (also referred to as an intersection) between the first band portions 23 a and the second band portions 23 b may constitute the center C (see FIG. 13 ) of the laminate 2. The conductor layer pattern 24 fills the openings in the dielectric layer pattern 23 and overlaps the intersection (also referred to as an overlapping portion) of the dielectric layer pattern 23. In the temporary laminate, the overlapping portion (also referred to as an overlapping portion) between the dielectric layer pattern 23 and the conductor layer pattern 24 may constitute a part of the second portion 32 of the principal surface electrode portion 30. The overlapping portion is a precursor of the dielectric layer 30 d and the conductor layer 30 e of the principal surface electrode portion 30 shown in FIGS. 9 and 10 , and is also referred to as a principal surface electrode portion precursor. 22 shows an example in which the planar shape of the overlapping portion is a right-angled triangle, but is not limited to this. The planar shape of the overlapping portion may be, for example, a sector (quadrant), a circle, a rectangle, or the like. By changing the planar shape of the overlapping portion, the planar shape of the second portion 32 can be adjusted. Furthermore, by changing the thickness of the dielectric layer pattern 23, the height H (see FIG. 14 ) of the second portion 32 can be adjusted.

[0084] Next, the temporary laminate is pressed in the lamination direction to obtain a mother laminate 19 as shown in Fig. 23. The temporary laminate can be pressed using, for example, a hydrostatic press.

[0085] Next, the base laminate 19 is cut along the grid-shaped cutting lines CL (see Figure 23) to produce a plurality of unsintered laminates 2 (hereinafter simply referred to as unsintered laminates 2 or laminate precursors) in which the main surface electrode portion precursors are located on the first surface 8a and the second surface 8b, as shown in Figure 24.

[0086] Next, the green laminate 2 is fired. The firing temperature may be set appropriately, and may be, for example, about 1100 to 1250°C. The green laminate 2 may be subjected to a degreasing treatment. The degreasing treatment may be performed in an air atmosphere, an inert gas atmosphere, or a reducing atmosphere. The degreasing treatment may be performed under atmospheric pressure or under reduced pressure. The fired laminate 2 may be subjected to a re-oxidation treatment in an oxidizing atmosphere.

[0087] Next, the fired laminate 2 is placed in a rotary pot containing an abrasive, and the laminate 2 is barrel-polished to remove burrs from the surface of the laminate 2, round the corners, and fully expose the internal electrodes 6 and dummy electrodes 5a at the corners 2a, 2b, 2c, and 2d. Figure 25 shows the laminate 2 after polishing. The polished laminate 2 has the dielectric layer 30d and the conductor layer 30e of the main-surface electrode portion 30 shown in Figure 9.

[0088] Next, a conductor layer 30f is formed on the polished laminate 2 by plating, such as electroless plating or electrolytic plating, so as to cover part of the dielectric layer 30d and the conductor layer 30e, thereby forming the external electrodes 3 (first external electrode 3a, second external electrode 3b, third external electrode 3c, and fourth external electrode 3d). This allows the manufacture of a capacitor 1A having the main surface electrode portion 30 shown in FIG.

[0089] When preparing the temporary laminate (see FIG. 22), a plurality of dielectric layer patterns 23 and a plurality of conductor layer patterns 24 are alternately stacked on the top and bottom of the temporary laminate, thereby making it possible to manufacture the multilayer ceramic capacitor 1A having the main surface electrode portion 30 shown in FIG. 10. Furthermore, when preparing the temporary laminate (see FIG. 22), by reversing the stacking order of the dielectric layer patterns 23 and the conductor layer patterns 24, it is possible to manufacture the multilayer ceramic capacitor 1A having the main surface electrode portion 30 shown in FIG. 11.

[0090] According to the multilayer ceramic capacitor and mounting structure of the present disclosure, even when the multilayer ceramic capacitor is thinned, the occurrence of cracks in the laminate when the multilayer ceramic capacitor is mounted on a substrate can be reduced, thereby reducing deterioration in the electrical characteristics and reliability of the multilayer ceramic capacitor and mounting structure.

[0091] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above-described embodiments, and various modifications, improvements, etc. are possible within the scope that does not deviate from the gist of the present disclosure.

[0092] The present disclosure can be implemented in the following configurations (A) to (G).

[0093] (A) A substantially rectangular parallelepiped laminate formed by alternately stacking a plurality of internal electrodes and a plurality of dielectric layers, the laminate having a first surface and a second surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a length direction perpendicular to the stacking direction, and a third side surface and a fourth side surface opposing each other in a width direction perpendicular to the stacking direction and the length direction; and a plurality of external electrodes, wherein the plurality of internal electrodes have a plurality of first internal electrodes and a plurality of second internal electrodes, the plurality of first internal electrodes being exposed on the first side surface, and the plurality of second internal electrodes being exposed on the second side surface, the plurality of external electrodes having a first external electrode and a second external electrode, the first external electrode being located from the first side surface across at least the first surface and connected to the plurality of first internal electrodes, the second external electrode being located from the second side surface across at least the first surface and connected to the plurality of second internal electrodes, and the first external electrode and the second external electrode each having a main surface electrode portion located at least on the first surface, a multilayer ceramic capacitor, wherein the main surface electrode portion or a region of the laminate that is in contact with the main surface electrode has a first portion and a second portion that is thicker in the stacking direction than the first portion and is located closer to a center of the laminate than the first portion when viewed in the stacking direction.

[0094] (B) A substantially rectangular parallelepiped laminate formed by alternately stacking a plurality of internal electrodes and a plurality of dielectric layers, the laminate having first and second surfaces opposing each other in the stacking direction, first and second side surfaces opposing each other in a length direction perpendicular to the stacking direction, and third and fourth side surfaces opposing each other in a width direction perpendicular to the stacking direction and the length direction; and a plurality of external electrodes, wherein the plurality of internal electrodes have a plurality of first internal electrodes and a plurality of second internal electrodes, and the plurality of first internal electrodes are exposed at corners extending from the first side surface to the third side surface and at corners extending from the second side surface to the fourth side surface, and the plurality of second internal electrodes are exposed at corners extending from the first side surface to the fourth side surface and at corners extending from the second side surface to the third side surface, and the plurality of external electrodes have a first external electrode, a second external electrode, a third external electrode, and a fourth external electrode, and the first external electrode is located from the corner extending from the first side surface to the third side surface to at least the first surface and is connected to the plurality of first internal electrodes, the second external electrode is located from the corner extending from the second side surface to the fourth side surface across at least the first surface, and is connected to the plurality of first internal electrodes; the third external electrode is located from the corner extending from the first side surface to the fourth side surface across at least the first surface, and is connected to the plurality of second internal electrodes; the fourth external electrode is located from the corner extending from the second side surface to the fourth side surface across at least the first surface, and is connected to the plurality of second internal electrodes; the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode each have a principal surface electrode portion located at least on the first surface, and a region of the principal surface electrode portion or the laminate in contact with the principal surface electrode portion has a first portion and a second portion that is thicker in the stacking direction than the first portion and is located closer to the center of the laminate than the first portion when viewed in the stacking direction.

[0095] (C) The multilayer ceramic capacitor according to (A) or (B) above, wherein the following formula (1) is satisfied, where Ttot is the total thickness of the laminate or the total thickness of the laminate excluding the first and second portions in the lamination direction, Tc is the thickness of the central portion of the laminate, and H is the height of the first portion relative to the second portion: Ttot - Tc < H (1)

[0096] (D) The multilayer ceramic capacitor according to (C) above, wherein H is less than 10 μm.

[0097] (E) The multilayer ceramic capacitor according to any one of (A) to (D) above, wherein the second portion is formed by stacking at least one dielectric layer and at least one conductor layer in the stacking direction.

[0098] (F) The multilayer ceramic capacitor according to (E) above, wherein the at least one dielectric layer and the at least one conductor layer are alternately stacked in this order on the first surface.

[0099] (G) The multilayer ceramic capacitor according to any one of (A) to (F), wherein the second portion is located closer to the center of the laminate than a center line that bisects the length of the main surface electrode portion in a direction in which a diagonal line of the first surface extends.

[0100] (H) A mounting structure including the multilayer ceramic capacitor according to any one of (A) to (G) above, and a substrate having a mounting surface, wherein the multilayer ceramic capacitor is mounted on the substrate so that the first surface of the laminate faces the mounting surface.

[0101] 1,1A Multilayer Ceramic Capacitor 2 Laminated Body 2a, 2b, 2c, 2d Corner 3 External Electrode 3a First External Electrode 3b Second External Electrode 3c Third External Electrode 3d Fourth External Electrode 30 Principal Surface Electrode Section 30a, 30b, 30c, 30e, 30f, 30h, 30i, 30j Conductor Layer 30d, 30g Dielectric layer 31, 31' First part 32, 32' Second part 4 Capacitance forming part 5 Cover part 5a Dummy electrode 6 Internal electrode 6a First internal electrode 6b Second internal electrode 7 Dielectric layer 8a First surface 8b Second surface 9a First side 9b Second side 9c Third side 9d Fourth side 10 Substrate 10a Mounting surface 10b, 10c, 10d Point 11 First mounting electrode 12 Second mounting electrode 13 Third mounting electrode 14 Fourth mounting electrode 15 Suction nozzle 16 Ceramic green sheet 17 Internal electrode sheet 18 Dummy electrode sheet 19 Base laminate 20, 20A Mounting structure 23 Dielectric layer pattern 23a First strip portion 23b Second strip portion 23c Center 24 Conductive layer pattern C Center portion

Claims

1. A laminate formed by alternately stacking a plurality of internal electrodes and a plurality of dielectric layers, the laminate having a first surface and a second surface opposing each other in a stacking direction, a first side surface and a second side surface opposing each other in a length direction perpendicular to the stacking direction, and a third side surface and a fourth side surface opposing each other in a width direction perpendicular to the stacking direction and the length direction; and a plurality of external electrodes, the plurality of internal electrodes having a plurality of first internal electrodes and a plurality of second internal electrodes, the plurality of first internal electrodes being exposed on the first side surface, and the plurality of second internal electrodes being exposed on the second side surface, the plurality of external electrodes having a first external electrode and a second external electrode, the first external electrode being located from the first side surface across at least the first surface and connected to the plurality of first internal electrodes, the second external electrode being located from the second side surface across at least the first surface and connected to the plurality of second internal electrodes, the first external electrode and the second external electrode each having a main surface electrode portion located at least on the first surface, the main surface electrode portion or a region of the laminate in contact with the main surface electrode portion has a first portion and a second portion that is thicker in the stacking direction than the first portion and is located closer to a center of the laminate than the first portion when viewed in the stacking direction.

2. A laminate having a substantially rectangular parallelepiped shape in which a plurality of internal electrodes and a plurality of dielectric layers are alternately laminated, the laminate having a first surface and a second surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a length direction perpendicular to the lamination direction, and a third side surface and a fourth side surface opposing each other in a width direction perpendicular to the lamination direction and the length direction; and a plurality of external electrodes, the plurality of internal electrodes having a plurality of first internal electrodes and a plurality of second internal electrodes, the plurality of first internal electrodes being exposed at corners extending from the first side surface to the third side surface and at corners extending from the second side surface to the fourth side surface, the plurality of second internal electrodes being exposed at corners extending from the first side surface to the fourth side surface and at corners extending from the second side surface to the third side surface, the plurality of external electrodes having a first external electrode, a second external electrode, a third external electrode, and a fourth external electrode, the first external electrode being located from the corner extending from the first side surface to the third side surface to at least the first surface and being connected to the plurality of first internal electrodes, a first external electrode disposed on the first surface of the first laminate and connected to the first portion of the first internal electrode; a second external electrode disposed on the first surface of the first laminate and connected to the first portion of the first internal electrode; a third external electrode disposed on the first surface of the first laminate and connected to the first portion of the first internal electrode; a fourth external electrode disposed on the first surface of the first laminate and connected to the first portion of the first internal electrode; 3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the following formula (1) is satisfied, where Ttot is the total thickness of the laminate or the total thickness of the laminate excluding the first and second portions in the lamination direction, Tc is the thickness of the central portion of the laminate, and H is the height of the second portion relative to the first portion: Ttot-Tc<H (1) 4. The multilayer ceramic capacitor according to claim 3, wherein H is less than 10 μm.

5. A multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the second portion is formed by stacking at least one dielectric layer and at least one conductive layer in the stacking direction.

6. The multilayer ceramic capacitor according to claim 5, wherein said at least one dielectric layer and said at least one conductive layer are alternately laminated in this order on said first surface.

7. A multilayer ceramic capacitor as claimed in any one of claims 1 to 6, wherein the second portion is located closer to the center of the laminate than a center line that bisects the length of the principal surface electrode portion in the direction in which the diagonal of the first surface extends.

8. A mounting structure comprising: the multilayer ceramic capacitor according to any one of claims 1 to 7; and a substrate having a mounting surface, wherein the multilayer ceramic capacitor is mounted on the substrate such that the first surface of the laminate faces the mounting surface.

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