Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device includes a semiconductor substrate, an interlayer insulating film provided with a contact hole above the semiconductor substrate, and a first upper electrode provided above the interlayer insulating film. The semiconductor device has: a first region having a first contact part electrically connected to the first upper electrode via the contact hole; and a second region having a second contact part electrically connected to the first upper electrode via the contact hole. The second contact part has higher resistance than the first contact part.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Patent Document 1 describes a semiconductor device in which a "silicide layer" is provided in a "contact hole." [Prior Art Documents] [Patent Documents] Patent Document 1: JP 2003-318396 A Patent Document 2: JP 2007-335554 A Patent Document 3: JP 2002-334850 A General disclosure

[0003] (Problem to be Solved) It is preferable to improve the reliability on the front surface side of a semiconductor device.

[0004] (Means for solving the problem) A first aspect of the present invention provides a semiconductor device comprising: a semiconductor substrate; an interlayer insulating film having a contact hole formed therein above the semiconductor substrate; and a first upper electrode formed above the interlayer insulating film, the semiconductor device having a first region having a first contact portion electrically connected to the first upper electrode through the contact hole; and a second region having a second contact portion electrically connected to the first upper electrode through the contact hole, the second contact portion having a higher resistance than the first contact portion.

[0005] The first contact portion may have a first alloy layer containing a first metal provided on the bottom surface of the contact hole, and a first barrier metal layer containing the first metal provided inside the contact hole.

[0006] The first barrier metal layer may include a metal film containing the first metal.

[0007] The barrier metal layer may have a lower barrier metal portion and an upper barrier metal portion stacked on the lower barrier metal portion, and the lower barrier metal portion may be denser than the upper barrier metal portion.

[0008] The upper barrier metal portion may be provided in contact with an upper surface of the first alloy layer.

[0009] The second contact portion may have the first alloy layer containing the first metal provided on the bottom surface of the contact hole, an oxide layer provided on the upper surface of the first alloy layer, and a second barrier metal layer provided inside the contact hole.

[0010] The second barrier metal layer may include a nitride of the first metal.

[0011] The first barrier metal layer may include a metal film containing the first metal.

[0012] The first barrier metal layer may have a lower barrier metal portion provided on the side wall of the contact hole and an upper barrier metal portion stacked on the lower barrier metal portion, and the lower barrier metal portion may be denser than the upper barrier metal portion.

[0013] The lower barrier metal portion may be a nitride of the first metal.

[0014] The semiconductor device may include a transistor portion and a diode portion, the transistor portion and the diode portion having an emitter electrode and a collector electrode between which a load current flows, and the first upper electrode may be the emitter electrode.

[0015] The first region may be provided in the transistor portion and spaced apart from the diode portion, and the second region may be provided in the transistor portion and adjacent to the diode portion.

[0016] The first region may be provided adjacent to the diode portion, and the second region may be provided spaced apart from the diode portion.

[0017] In a top view of the semiconductor substrate, an area ratio of the second region in the transistor portion may be higher than an area ratio of the first region in the transistor portion.

[0018] The diode portion may have the second region.

[0019] The thickness of the first oxide layer provided on the bottom surface of the contact hole of the second contact portion in the second region in the diode portion may be greater than the thickness of the second oxide layer provided on the bottom surface of the contact hole of the second contact portion in the second region in the transistor portion.

[0020] The second contact portion of the second region in the transistor portion may have a third contact portion and a fourth contact portion provided closer to the diode portion than the third contact portion, and the thickness of a fourth oxide layer provided on the bottom surface of the contact hole of the fourth contact portion may be greater than the thickness of a third oxide layer provided on the bottom surface of the contact hole of the third contact portion.

[0021] The oxide layer may contain an oxide of the first metal or an element that constitutes the semiconductor substrate.

[0022] The first barrier metal layer may include a nitride of the first metal.

[0023] The first alloy layer may include a silicide of the first metal.

[0024] The first metal may be titanium.

[0025] The semiconductor substrate may have a lifetime control region provided on a front surface side of the semiconductor substrate.

[0026] The semiconductor substrate may have a lifetime control region provided on the front surface side of the semiconductor substrate, and the lifetime control region may extend from the diode portion to the boundary between the first region in the transistor portion and the second region in the transistor portion.

[0027] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of forming an interlayer insulating film above a semiconductor substrate, forming a contact hole in the interlayer insulating film, forming a first upper electrode above the interlayer insulating film, forming a first contact portion in a first region, and forming a second contact portion in a second region, wherein the first contact portion is electrically connected to the first upper electrode through the contact hole, the second contact portion is electrically connected to the first upper electrode through the contact hole, and the second contact portion has a higher resistance than the first contact portion.

[0028] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0029] 1B shows an example of a top view of the semiconductor device 100. FIG. 1B shows an example of a top view of the semiconductor device 100. FIG. 1B shows an example of an a-a' cross section in FIG. 1B. FIG. 1B shows an enlarged cross section of the semiconductor device 100. FIG. 1B shows an enlarged cross section of the semiconductor device 100. FIG. 1B shows an enlarged cross section of the semiconductor device 100. FIG. 1B shows an enlarged cross section of the semiconductor device 100. FIG. 1B shows another example of the a-a' cross section in FIG. 1B. FIG. 1B shows another example of the a-a' cross section in FIG. 1B. FIG. 1B shows another example of the a-a' cross section in FIG. 1B. FIG. 1B shows an enlarged cross section of the semiconductor device 100. FIG. 1B shows an enlarged cross section of the semiconductor device 100. 1 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 2 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 3 is a flowchart showing an example of a manufacturing process of the semiconductor device 100. FIG. 4 is a flowchart showing an example of a manufacturing process of the semiconductor device 100. FIG. 5 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 6 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 7 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 8 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 9 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 10 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 11 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 12 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 13 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 14 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 15 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 16 is an enlarged cross-sectional view of the semiconductor device 100. FIG. 17 is an enlarged cross-sectional view of the semiconductor device 100. 21 is a diagram showing an example of a bb' cross section of Fig. 19. Fig. 22 is a diagram showing an example of a cc' cross section of Fig. 19. Fig. 23 is a diagram showing another example of a top view of the gate pad 112. Fig. 24 is a diagram showing an example of an ff' cross section of Fig. 21.21. A diagram showing an example of a gg' cross section of FIG. 21. A diagram showing an example of an hh' cross section of FIG. 21. Another example of a top view of the semiconductor device 100. A diagram showing an example of a dd' cross section of FIG. 23. A diagram showing an example of an ee' cross section of FIG. 23. A diagram showing another example of a dd' cross section of FIG. 23. A diagram showing another example of an ee' cross section of FIG. 23. Another example of a top view of the semiconductor device 100. Another example of a top view of the semiconductor device 100. Another example of a top view of the semiconductor device 100. Another example of a top view of the semiconductor device 100. Another example of a top view of the semiconductor device 100.

[0030] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0031] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0032] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0033] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0034] In this specification, when P+ type or N+ type is used, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is used, it means that the doping concentration is lower than that of P type or N type.

[0035] 1A shows an example of a top view of a semiconductor device 100. In this example, only some components of the semiconductor device 100 are shown, and some components are omitted.

[0036] The semiconductor substrate 10 has edges 102 in a top view. The semiconductor substrate 10 of this example has two pairs of edges 102 that face each other in a top view. In this example, the X-axis and the Y-axis are parallel to either of the edges 102.

[0037] An active portion 120 is provided on the semiconductor substrate 10. The active portion 120 is a region through which a main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode 52 is provided above the active portion 120, but is not shown in the figure.

[0038] The active section 120 is provided with a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of Fig. 1A, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the front surface 21 of the semiconductor substrate 10.

[0039] In this example, the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0040] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad and a cathode pad. Each pad is disposed near an edge 102. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode 52 in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0041] A gate potential is applied to the gate pad 112. The gate pad 112 is an example of a first upper electrode. The gate pad 112 is electrically connected to the gate conductive portion 44 of the gate trench portion 40 of the active portion 120. The semiconductor device 100 includes a gate wiring that connects the gate pad 112 and the gate trench portion 40. In FIG. 1A , the gate wiring is indicated by diagonal hatching.

[0042] The gate wiring in this example includes a peripheral gate wiring 130 and an inter-active portion gate wiring 131. The gate wiring may be configured using either the gate metal layer 50 or the connection portion 25, or an appropriate combination of both. The peripheral gate wiring 130 and the inter-active portion gate wiring 131 may have the same configuration or different configurations. The peripheral gate wiring 130 is disposed between the active portion 120 and the edge 102 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 120 in a top view. The area surrounded by the peripheral gate wiring 130 in a top view may also be the active portion 120. The peripheral gate wiring 130 is connected to the gate pad 112. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be configured using the gate metal layer 50 and the connection portion 25.

[0043] The inter-active portion gate wiring 131 is provided between the multiple active portions 120. In Fig. 1A, two active portions 120 are arranged side by side in the Y-axis direction. By providing the inter-active portion gate wiring 131 between the multiple active portions 120 inside the semiconductor substrate 10, it is possible to reduce variations in wiring length from the gate pad 112 for each region of the semiconductor substrate 10.

[0044] The inter-active portion gate wiring 131 is connected to the gate trench portion of the active portion 120. The inter-active portion gate wiring 131 is disposed above the semiconductor substrate 10. In this example, the inter-active portion gate wiring 131 is composed of a gate metal layer 50 and a connection portion 25. The gate metal layer 50 may be a metal layer containing aluminum or the like.

[0045] The inter-active portion gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the inter-active portion gate wiring 131 is provided extending in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 at approximately the center in the Y-axis direction, so as to cross the active portion 120. When the active portion 120 is divided by the inter-active portion gate wiring 131, the transistor portions 70 and the diode portions 80 may be arranged alternately in the X-axis direction in each divided region.

[0046] The edge termination structure 140 is provided on the front surface 21 of the semiconductor substrate 10. In a top view, the edge termination structure 140 is provided between the active section 120 and the edge 102. In this example, the edge termination structure 140 is disposed between the peripheral gate wiring 130 and the edge 102. The edge termination structure 140 relieves electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure 140 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active section 120.

[0047] 1B shows an example of a top view of the semiconductor device 100. The semiconductor device 100 of this example includes a transistor section 70 and a diode section 80. This figure is an enlarged view of the top surface of region A in FIG. 1A.

[0048] The transistor section 70 is a region obtained by projecting a collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT. In this example, the transistor section 70 is an IGBT. However, the transistor section 70 may be another transistor such as a MOSFET.

[0049] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the rear surface 23 side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 will be described later. A P+ type collector region 22 may be provided in an area of ​​the rear surface 23 of the semiconductor substrate 10 other than the cathode region 82. In this specification, an extension region 85 obtained by extending the diode section 80 in the Y-axis direction to a gate wiring described later may also be included in the diode section 80. The collector region 22 may be provided on the rear surface 23 of the extension region 85.

[0050] In this figure, the region around the active portion of the semiconductor device 100 is shown, and other regions are omitted. For example, an edge termination structure may be provided in the region on the negative side of the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a structure combining these. Note that, for convenience, this example describes the edge on the negative side of the Y-axis direction, but the same applies to other edges of the semiconductor device 100.

[0051] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a diamond substrate, or any other substrate. The semiconductor substrate 10 in this example is a silicon substrate. Note that, in this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 has a front surface 21 and a back surface 23, as described below.

[0052] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are an example of a first upper electrode. The gate trench portion 40 is an example of a MOS gate structure included in the semiconductor device 100. Note that although the semiconductor device 100 of this example is a transistor having a MOS gate structure, it may also be a diode having a MOS gate structure.

[0053] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. The gate metal layer 50 is provided above the connection portion 25 and the well region 17.

[0054] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal layer made of titanium or a titanium compound below the region made of aluminum or the like. The barrier metal layer will be described later. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0055] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 sandwiched therebetween. The interlayer insulating film 38 is omitted in FIG. 1B. A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38.

[0056] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70 via the connection portion 25. A plug layer made of tungsten or the like may be formed inside the contact hole 55. The plug layer will be described later.

[0057] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. A plug layer made of tungsten or the like may be formed inside the contact hole 56.

[0058] The connection portion 25 is connected to a front surface side metal layer such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. In this example, the connection portion 25 is provided extending in the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 may also be provided between the emitter electrode 52 and the dummy conductive portion. In this example, the connection portion 25 is not provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0059] The gate trench portion 40 is an example of a plurality of trench portions extending in a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 of this example may have two extension portions 41 extending along an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 that connects the two extension portions 41.

[0060] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be electrically connected to the gate conductive portion via the connection portion 25.

[0061] The dummy trench portion 30 is an example of a plurality of trench portions extending in a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Like the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). The dummy trench portion 30 in this example has an I-shape on the front surface 21 of the semiconductor substrate 10, but like the gate trench portion 40, it may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31.

[0062] The transistor section 70 of this example has a structure in which two gate trench sections 40 and two dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio. For example, the transistor section 70 has one dummy trench section 30 between two extension sections 41.

[0063] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 may be greater than the ratio of the dummy trench portions 30, or the ratio of the dummy trench portions 30 may be greater than the ratio of the gate trench portions 40. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 2:3 or 2:4. Furthermore, the transistor portion 70 may have all trench portions as gate trench portions 40 and may not have dummy trench portions 30.

[0064] The well region 17 is a second conductivity type region provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18, which will be described later. The well region 17 is an example of a well region provided on the peripheral side of the active portion 120. The active portion 120 will be described later. The well region 17 is, for example, of P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0065] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.

[0066] The mesa portion 71 is a mesa portion provided adjacent to a trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion extending from the front surface 21 of the semiconductor substrate 10 to the deepest bottom of each trench portion. The extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between the two extension portions may be considered as a mesa portion.

[0067] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction.

[0068] The base region 14 is a region of a second conductivity type provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, a P-type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends of the mesa portion 71 in the Y-axis direction. Note that FIG. 1B shows only one end of the base region 14 in the Y-axis direction.

[0069] The emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0070] The emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0071] The contact region 15 is provided above the base region 14 and is a second conductivity type region having a higher doping concentration than the base region 14. In this example, the contact region 15 is P+ type, for example. The contact region 15 in this example is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. The contact region 15 in this example is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0072] The semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other. The transistor section 70 of this example includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80. However, the semiconductor device 100 does not necessarily have to include the boundary section 90.

[0073] The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The boundary portion 90 in this example does not have an emitter region 12. In one example, the trench portion in the boundary portion 90 is a dummy trench portion 30. The boundary portion 90 in this example is arranged so that both ends in the X-axis direction are dummy trench portions 30.

[0074] The contact holes 54 are provided above the base region 14 in the diode section 80. The contact holes 54 are provided above the contact regions 15 in the boundary section 90. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction.

[0075] The mesa portion 91 is provided in the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0076] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has a well region 17 on the negative side in the Y-axis direction.

[0077] The emitter region 12 is provided in the mesa portion 71, but may not be provided in the mesa portion 81 or the mesa portion 91. The contact region 15 is provided in the mesa portion 71 and the mesa portion 91, but may not be provided in the mesa portion 81.

[0078] 1C shows an example of the aa' cross section in FIG. 1B. The aa' cross section is an XZ cross section passing through the contact region 15 in the transistor section 70. In the aa' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The collector electrode 24 is an example of a back-side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0079] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0080] The buffer region 20 is a region of a first conductivity type provided closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18. In this example, the buffer region 20 is, for example, N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type. Note that the buffer region 20 may be omitted.

[0081] The collector region 22 is provided below the buffer region 20 in the transistor section 70. The collector region 22 has the second conductivity type. In this example, the collector region 22 is, for example, a P+ type.

[0082] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal. The material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52.

[0083] The base region 14 is a region of the second conductivity type provided above the drift region 18. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0084] The contact region 15 is provided above the base region 14 in the mesa portion 91. The contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In another cross section, the emitter region 12 is provided above the base region 14. The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0085] The accumulation region 16 is a region of a first conductivity type that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. The accumulation region 16 in this example is, for example, an N+ type. However, the accumulation region 16 does not necessarily have to be provided.

[0086] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The dose of ion implantation into the accumulation region 16 is 1.0E+12 cm －２ Above, 1.0E+13cm －２ The ion implantation dose of the accumulation region 16 may be 3.0E+12 cm －２ Above, 6.0E + 12cm －２ By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0087] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these regions to reach the drift region 18. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include trenches formed in the order of forming the trenches and then forming the doped regions between the trenches.

[0088] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0089] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side across the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0090] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered on the front surface 21 with an interlayer insulating film 38.

[0091] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided so as to penetrate the interlayer insulating film 38. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited to this.

[0092] The interlayer insulating film 38 may be a silicon oxide film. The interlayer insulating film 38 may be a borophosphosilicate glass (BPSG) film, a borosilicate glass (BSG) film, or a phosphosilicate glass (PSG) film. The interlayer insulating film 38 may include a high temperature silicon oxide (HTO) film.

[0093] The semiconductor device 100 of this example includes a back surface side lifetime control region 151 and a front surface side lifetime control region 152. However, the semiconductor device 100 does not necessarily need to include either the back surface side lifetime control region 151 or the front surface side lifetime control region 152.

[0094] The back side lifetime control region 151 may be provided in the transistor portion 70. However, the back side lifetime control region 151 may be omitted. The back side lifetime control region 151 is a region in which a lifetime killer is intentionally formed by, for example, injecting impurities into the semiconductor substrate 10. In one example, the back side lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10. The back side lifetime control region 151 may also be formed by injecting protons. By providing the back side lifetime control region 151, it is possible to reduce the turn-off time and suppress the tail current, thereby reducing losses during switching.

[0095] The front surface side lifetime control region 152 is provided closer to the front surface 21 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the front surface side lifetime control region 152 is provided in the drift region 18. The front surface side lifetime control region 152 is provided in both the transistor section 70 and the diode section 80. The front surface side lifetime control region 152 is provided in the diode section 80 and the boundary section 90, and may not be provided in part of the transistor section 70. The front surface side lifetime control region 152 can suppress hole injection from the diode section 80 and the transistor section 70, thereby reducing reverse recovery loss.

[0096] The front surface side lifetime control region 152 may be formed by any method among the methods for forming the back surface side lifetime control region 151. The elements, doses, etc. for forming the back surface side lifetime control region 151 and the front surface side lifetime control region 152 may be the same or different.

[0097] The front surface side lifetime control region 152 is provided extending from the diode section 80 to the transistor section 70. The front surface side lifetime control region 152 may be formed by irradiation from the front surface 21 of the semiconductor substrate 10. The front surface side lifetime control region 152 may be formed by irradiation from the back surface 23 side of the semiconductor substrate 10. In this example, the front surface side lifetime control region 152 is provided below the gate trench section 40. When a particle beam or the like for forming the front surface side lifetime control region 152 passes through the MOS gate structure of the semiconductor device 100, defects may occur at the interface between the gate oxide film and the semiconductor substrate.

[0098] The lifetime killer is a carrier recombination center. The lifetime killer may be a lattice defect. For example, the lifetime killer may be a vacancy, a divacancy, a complex defect of these with an element constituting the semiconductor substrate 10, or a dislocation. The lifetime killer may also be a rare gas element such as helium or neon, or a metal element such as platinum. Electron beams or protons may be used to form the lattice defects.

[0099] The lifetime killer concentration is the concentration of carrier recombination centers. The lifetime killer concentration may be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and divacancies, the concentration of complex defects formed between these vacancies and elements constituting the semiconductor substrate 10, or the concentration of dislocations. The lifetime killer concentration may also be the chemical concentration of a rare gas element such as helium or neon, or the chemical concentration of a metal element such as platinum.

[0100] The back surface side lifetime control region 151 is provided closer to the back surface 23 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The back surface side lifetime control region 151 in this example is provided in the buffer region 20. The back surface side lifetime control region 151 in this example is provided over the entire surface of the semiconductor substrate 10 in the XY plane, and can be formed without using a mask. The back surface side lifetime control region 151 may be provided in a part of the semiconductor substrate 10 in the XY plane. The dose of impurities for forming the back surface side lifetime control region 151 is 0.5E+10 cm －２ Above, 1.0E+14cm －２ Even if it is less than 5.0E+10cm －２ Above, 1.0E+13cm －２ It may be the following:

[0101] The back surface-side lifetime control region 151 may be formed by implantation from the back surface 23 side. This makes it easier to avoid any influence on the front surface 21 side of the semiconductor device 100. For example, the back surface-side lifetime control region 151 is formed by irradiating helium or protons from the back surface 23 side. Here, whether the back surface-side lifetime control region 151 is formed by implantation from the front surface 21 side or the back surface 23 side can be determined by acquiring the state of the front surface 21 side by the SR method or by measuring leakage current.

[0102] The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is provided below the boundary section 90 in this example.

[0103] The semiconductor device 100 may be a power semiconductor device for controlling power, etc. The semiconductor device 100 of this example may have a vertical semiconductor structure including a backside metal layer on the backside 23 side of the semiconductor substrate 10. However, the semiconductor device 100 may also have a lateral semiconductor structure that does not include a metal layer on the backside 23 side.

[0104] In this example, an RC-IGBT with a trench gate structure is described as an example of the semiconductor device 100. However, the semiconductor device 100 may be a semiconductor device with a planar gate structure, or may be another semiconductor device such as a diode. The semiconductor device 100 may include an N-channel MOSFET or a P-channel MOSFET.

[0105] 2A is an enlarged view of a cross section of the semiconductor device 100. FIG. 2B is an enlarged view of a cross section of the semiconductor device 100. The cross section of FIG. 2A is an XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10, and the cross section of FIG. 2B is an XZ cross section passing through the contact region 15 on the front surface 21. In this example, an enlarged view of a cross section in the vicinity of a first contact portion 54A is shown. The first contact portion 54A is electrically connected to the emitter electrode 52 via a contact hole 54. The first contact portion 54A includes the contact hole 54, a first barrier metal layer 60, a first alloy layer 63, and a plug layer 64.

[0106] In this specification, the structure of the first contact portion 54A and the second contact portion 54B (described later) may be described using the contact hole 54, but a similar structure may also be applied to other contact holes such as the contact hole 55 and the contact hole 56. For convenience, in this specification, the inner wall of the contact hole 54, which is above the front surface 21 of the semiconductor substrate 10, will be described as a sidewall 54w, and the inner wall of the contact hole 54 which is below the front surface 21 of the semiconductor substrate 10 will be described as a bottom surface 54b.

[0107] The first barrier metal layer 60 is provided above the first alloy layer 63 in the contact hole 54. The first barrier metal layer 60 may be provided in contact with the upper surface of the interlayer insulating film 38. The first barrier metal layer 60 contains a nitride of a predetermined conductive first metal. In this example, the first barrier metal layer 60 is provided on the upper surface of the oxide layer 66 and the sidewall of the interlayer insulating film 38 in the contact hole 54, and has a metal film 69, a lower barrier metal portion 61, and an upper barrier metal portion 62. However, the first barrier metal layer 60 does not necessarily have to have the metal film 69 or the lower barrier metal portion 61.

[0108] The metal film 69 is provided on the sidewall 54w of the contact hole 54. The metal film 69 includes a first metal having a predetermined conductivity. The first metal may be at least one of titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), magnesium (Mg), vanadium (V), lanthanum (La), palladium (Pd), or zirconium (Zr). The first metal may be a metal having a hydrogen storage effect. For example, the first metal is titanium (Ti). The metal film 69 is a Ti film formed by sputtering. The metal film 69 may also be formed above the interlayer insulating film 38.

[0109] The first alloy layer 63 is provided on the bottom surface 54b of the contact hole 54. In this example, the first alloy layer 63 is provided on the upper surface of the semiconductor substrate 10. The first alloy layer 63 is formed by annealing a metal film 69 containing a first metal. The first alloy layer 63 may be an alloy composed of the first metal and a constituent element of a layer at the bottom surface of the contact hole 54. As an example, if the semiconductor substrate 10 is a silicon substrate, the first alloy layer 63 may be a silicide layer. As another example, if the semiconductor substrate 10 is a silicon carbide substrate, a gallium nitride substrate, a diamond substrate, or the like, the first alloy layer 63 may be an alloy layer containing these substrate materials and the first metal. In this example, the first alloy layer 63 is a titanium silicide layer formed by annealing a metal film 69 formed as an initial metal film on the bottom surface 54b of the contact hole 54. In addition, the doped regions, including the emitter region 12 and the contact region 15, may be formed so that they have a high concentration of N-type or P-type impurities at the points where they contact the first alloy layer 63 (not shown), thereby reducing contact resistance.

[0110] The lower barrier metal portion 61 is provided on the metal film 69 in the contact hole 54. The lower barrier metal portion 61 contains a nitride of a predetermined conductive first metal. For example, the lower barrier metal portion 61 is TiN. The lower barrier metal portion 61 is formed by annealing a metal film 69 containing the first metal. In this example, the lower barrier metal portion 61 is TiN formed by annealing, in a nitrogen atmosphere, a metal film 69 formed on the sidewall of the contact hole 54 as an initial metal film. Note that the entire metal film 69 may be converted into the lower barrier metal portion 61 during annealing. Alternatively, the lower barrier metal portion 61 may not be formed even by annealing.

[0111] The lower barrier metal portion 61 and the first alloy layer 63 may be formed by the same annealing process. For example, using a metal film 69 formed on the inner wall of the contact hole 54, the lower barrier metal portion 61 made of TiN is formed on the side wall 54w of the contact hole 54, and the first alloy layer 63 made of titanium silicide is formed on the bottom surface 54b of the contact hole 54. After the annealing, the metal film 69 may remain on the upper surface of the first alloy layer 63, or the lower barrier metal portion 61 may be formed on the upper surface of the first alloy layer 63 (or the metal film 69 remaining on the upper surface of the first alloy layer 63).

[0112] The upper barrier metal portion 62 is laminated on the lower barrier metal portion 61 in the contact hole 54. The upper barrier metal portion 62 includes a conductive material. For example, the upper barrier metal portion 62 is TiN. The upper barrier metal portion 62 is laminated on the first alloy layer 63 provided on the bottom surface 54b of the contact hole 54. In other words, the upper barrier metal portion 62 is provided in contact with the upper surface of the first alloy layer 63. The upper barrier metal portion 62 may be formed by sputtering a conductive material. In this example, the upper barrier metal portion 62 is TiN formed by sputtering. Alternatively, if the lower barrier metal portion 61 is not formed even by annealing, the upper barrier metal portion 62 may be laminated on the metal film 69.

[0113] The plug layer 64 is provided above the first barrier metal layer 60 in the contact hole 54. The plug layer 64 may be provided in contact with the upper barrier metal portion 62 in the contact hole 54. The plug layer 64 is a conductive material that fills the inside of the contact hole 54. The plug layer 64 may be made of a material different from that of the emitter electrode 52. For example, the material of the plug layer 64 is tungsten. The plug layer 64 may also be provided outside the contact hole 54, above the interlayer insulating film 38, in contact with the upper barrier metal portion 62. The plug layer 64 may be omitted, and the emitter electrode 52 may fill the inside of the contact hole 54.

[0114] The interlayer insulating film 38 has a contact hole 54 and is provided above the semiconductor substrate 10. The interlayer insulating film 38 has one insulating layer provided above the front surface 21, but may also have a plurality of stacked insulating layers. The interlayer insulating film 38 may be a silicon oxide film such as BPSG.

[0115] The lower barrier metal portion 61 is denser than the upper barrier metal portion 62. The lower barrier metal portion 61 and the upper barrier metal portion 62 may be formed by different film formation methods. The lower barrier metal portion 61 may be a TiN film formed by annealing Ti formed on the sidewall of the interlayer insulating film 38. The upper barrier metal portion 62 may be a TiN film formed by sputtering TiN. As a result, the lower barrier metal portion 61 may be a TiN film that is denser than the upper barrier metal portion 62. The lower barrier metal portion 61 and the upper barrier metal portion 62 may contain the same material.

[0116] The upper barrier metal portion 62 formed by sputtering does not require the formation of an initial metal film, and therefore, the influence of the hydrogen absorption effect caused by remaining Ti, etc. can be avoided. However, since the upper barrier metal portion 62 is not a dense film like the lower barrier metal portion 61, the plug layer 64 may invade the upper barrier metal portion 62 during its formation. However, since the lower barrier metal portion 61 is densely formed, the interlayer insulating film 38 can be protected from damage during the formation of the plug layer 64.

[0117] The lower barrier metal portion 61 may have a smaller thickness than the upper barrier metal portion 62. The lower barrier metal portion 61 may have a smaller thickness than the first alloy layer 63.

[0118] The lower barrier metal portion 61 may cover the sidewall 54w of the contact hole 54. The lower end of the lower barrier metal portion 61 may be in contact with the first alloy layer 63. That is, the bottom surface 54b and the sidewall 54w of the contact hole 54 may be covered with the first alloy layer 63 and the metal film 69, respectively.

[0119] The opening width of the contact hole 54 is the width of the contact hole 54 in the trench arrangement direction on the upper surface of the interlayer insulating film 38. The opening width of the contact hole 54 may be 100 nm or more and 1000 nm or less.

[0120] FIG. 2C is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of FIG. 2C is an XZ cross-section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. This example shows an enlarged cross-section of a first contact portion 54A according to a modified example. The first contact portion 54A of this example differs from the first contact portion 54A shown in FIGS. 2A and 2B in that a first barrier metal layer 60 is provided outside the contact hole 54 and above the interlayer insulating film 38. Other structures may be any of those described herein. The XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10 is the same as the XZ cross-section of FIG. 2C except that the emitter region 12 is provided instead of the contact region 15 of FIG. 2C , and is therefore not shown.

[0121] The first barrier metal layer 60 may be provided outside the contact hole 54 in contact with the upper surface of the interlayer insulating film 38. By forming the first barrier metal layer 60 also on the interlayer insulating film 38, reliability during mounting, such as wire bonding and resin sealing, can be improved. Furthermore, the first barrier metal layer 60 may not have the lower barrier metal portion 61 and the metal film 69 either inside or outside the contact hole 54. As an example, the first barrier metal layer 60 may only have the upper barrier metal portion 62 provided inside and outside the contact hole 54.

[0122] FIG. 2D is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of FIG. 2D is an XZ cross-section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. This example shows an enlarged cross-section of a first contact portion 54A according to a further modification. The first contact portion 54A of this example differs from the first contact portion 54A shown in FIG. 2C in that the plug layer 64 is provided outside the contact hole 54 and above the interlayer insulating film 38. Other structures may be any of those described herein. The XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10 is the same as the XZ cross-section of FIG. 2D except that the emitter region 12 is provided instead of the contact region 15 of FIG. 2D , and is therefore not shown.

[0123] The plug layer 64 may be provided outside the contact hole 54 in contact with the upper surface of the first barrier metal layer 60. By forming the plug layer 64 also on the interlayer insulating film 38, reliability during mounting such as wire bonding and resin sealing can be improved.

[0124] 2E is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of FIG. 2E is an XZ cross-section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, a structure in which the contact region 15 is located at the center of the mesa portion and the emitter region 12 is provided in contact with the trench portion will be described. The first contact portion 54A of this example differs from the first contact portion 54A of FIGS. 2A and 2B in that a first barrier metal layer 60 is provided above the interlayer insulating film 38 outside the contact hole 54 and that an emitter electrode 52 is provided in the contact hole 54 instead of the plug layer 64. The emitter electrode 52 is connected to the front surface 21 of the semiconductor substrate 10 via the contact hole 54.

[0125] Even when the plug layer 64 is not provided, the first barrier metal layer 60 is also formed on the interlayer insulating film 38, thereby improving reliability during packaging, such as resin encapsulation. Although the emitter regions 12 are located on both sides of the contact region 15 in FIG. 2E , they may be located on only one side. Even in the structure in which the contact regions 15 and the emitter regions 12 are alternately arranged along the trench portion as described with reference to FIGS. 2A to 2D , the first barrier metal layer 60 may be provided above the interlayer insulating film 38 outside the contact hole 54, and an emitter electrode 52 may be provided in the contact hole 54 instead of the plug layer 64, as in this example. Furthermore, the structure of the first barrier metal layer 60, emitter electrode 52, and plug layer 64 described with reference to FIGS. 2A to 2D may also be applied to the structure in which the contact regions 15 and the emitter regions 12 appear simultaneously in the cross section of the trench portion as shown in this example.

[0126] FIG. 3A is an enlarged cross-sectional view of the semiconductor device 100. FIG. 3B is an enlarged cross-sectional view of the semiconductor device 100. The cross-section in FIG. 3A is an XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10, and the cross-section in FIG. 3B is an XZ cross-section passing through the contact region 15 on the front surface 21. In this example, an enlarged cross-sectional view of the vicinity of the second contact portion 54B is shown. The second contact portion 54B is electrically connected to the emitter electrode 52 via the contact hole 54. The second contact portion 54B includes the contact hole 54, a second barrier metal layer 68, a first alloy layer 63, a plug layer 64, and an oxide layer 66. Here, differences from the first contact portion 54A shown in FIGS. 2A and 2B will be mainly described, and descriptions of common elements will be omitted as appropriate.

[0127] The first alloy layer 63 is provided on the bottom surface 54b of the contact hole 54. In this example, the first alloy layer 63 is provided on the upper surface of the semiconductor substrate 10. The first alloy layer 63 is formed by annealing a metal film 69 containing a first metal. In this example, the first alloy layer 63 is a titanium silicide layer formed by annealing the metal film 69 that is deposited on the bottom surface 54b of the contact hole 54 as an initial metal film.

[0128] The oxide layer 66 is provided on the upper surface of the first alloy layer 63 in the contact hole 54. The oxide layer 66 may be in contact with the upper surface of the first alloy layer 63 or may be in contact with the lower surface of the second barrier metal layer 68. The oxide layer 66 may be provided in contact with the first alloy layer 63 and the second barrier metal layer 68. That is, the oxide layer 66 may be provided as a laminate between the first alloy layer 63 and the second barrier metal layer 68.

[0129] The oxide layer 66 may contain an element that constitutes the first alloy layer 63. The oxide layer 66 may contain an oxide of silicon or an element that constitutes the semiconductor substrate 10. For example, the oxide layer 66 is a silicon oxide film. The composition of the oxide layer 66 is SiO, SiO ２ or Si ２ O ３The oxide layer 66 may include an oxide of a first metal having a predetermined conductivity. For example, the oxide layer 66 may include titanium, or may include a titanium oxide film. The composition of the oxide layer 66 may be TiO, TiO ２ or Ti ２ O ３ The oxide layer 66 may be at least one of the following. The oxide layer 66 may be a dense film that functions as a metal diffusion barrier layer. For example, the oxide layer 66 can prevent diffusion of the plug layer 64 during the formation of the plug layer 64 and protect the first alloy layer 63 from damage during the formation of the plug layer 64.

[0130] The oxide layer 66 may have a thickness smaller than that of the first alloy layer 63. The oxide layer 66 may have a thickness smaller than that of the upper barrier metal portion 62. The oxide layer 66 may have a thickness of 0.5 nm or more and 4.0 nm or less. For example, the oxide layer 66 has a thickness of 2.5 nm. The oxide layer 66 may have a thickness at the thickest position in the contact hole 54.

[0131] The oxide layer 66 may be formed by chemical exposure such as etching. The oxide layer 66 may be formed by etching the upper surface of the first alloy layer 63. The etching of the upper surface of the first alloy layer 63 may be wet etching or dry etching. The oxide layer 66 may be formed by dry etching of the upper surface of the first alloy layer 63.

[0132] The oxide layer 66 may be formed by etching to remove the metal film 69 or the lower barrier metal portion 61. In other words, the formation of the oxide layer 66 and the removal of the metal film 69 or the lower barrier metal portion 61 may be performed in the same process. By providing the oxide layer 66, the resistance of the second contact portion 54B becomes higher than the resistance of the first contact portion 54A, so that hole injection can be suppressed when the diode portion 80 is conductive, and reverse recovery loss can be reduced.

[0133] The second barrier metal layer 68 is provided above the oxide layer 66 in the contact hole 54. The second barrier metal layer 68 may be provided outside the contact hole 54 in contact with the upper surface of the interlayer insulating film 38. The second barrier metal layer 68 contains a nitride of a predetermined conductive first metal. In this example, the second barrier metal layer 68 is provided on the upper surface of the oxide layer 66 and on the sidewall of the interlayer insulating film 38 in the contact hole 54, and has an upper barrier metal portion 62.

[0134] The upper barrier metal portion 62 is laminated on the oxide layer 66 in the contact hole 54. The upper barrier metal portion 62 includes a conductive material. For example, the upper barrier metal portion 62 is TiN. The upper barrier metal portion 62 is laminated on the oxide layer 66 provided on the upper surface of the first alloy layer 63. The upper barrier metal portion 62 may be formed by sputtering a conductive material. In this example, the upper barrier metal portion 62 is TiN formed by sputtering. The upper barrier metal portion 62 may be provided in contact with the oxide layer 66. The upper barrier metal portion 62 formed by sputtering does not require the formation of an initial metal film, and therefore, the influence of the hydrogen absorption effect caused by remaining Ti or the like can be avoided.

[0135] The plug layer 64 is provided above the first barrier metal layer 60 or the second barrier metal layer 68 in the contact hole 54. The plug layer 64 may be provided in contact with the upper barrier metal portion 62 in the contact hole 54. The plug layer 64 is a conductive material that fills the inside of the contact hole 54. The plug layer 64 may be made of a different material from the emitter electrode 52. For example, the material of the plug layer 64 is tungsten. The plug layer 64 may also be provided outside the contact hole 54 above the interlayer insulating film 38 in contact with the upper barrier metal portion 62. The plug layer 64 may be omitted, and the emitter electrode 52 may fill the inside of the contact hole 54.

[0136] The interlayer insulating film 38 has a contact hole 54 and is provided above the semiconductor substrate 10. The interlayer insulating film 38 has one insulating layer provided above the front surface 21, but may also have a plurality of stacked insulating layers. The interlayer insulating film 38 may be a silicon oxide film such as BPSG.

[0137] The lower barrier metal portion 61 is denser than the upper barrier metal portion 62. The lower barrier metal portion 61 and the upper barrier metal portion 62 may be formed by different film formation methods. The lower barrier metal portion 61 may be a TiN film formed by annealing a Ti metal film 69 formed on the sidewall of the interlayer insulating film 38. The upper barrier metal portion 62 may be a TiN film formed by sputtering TiN. As a result, the lower barrier metal portion 61 may be a TiN film that is denser than the upper barrier metal portion 62. The lower barrier metal portion 61 and the upper barrier metal portion 62 may contain the same material.

[0138] The upper barrier metal portion 62 is not a dense film like the lower barrier metal portion 61, and therefore, during the formation of the plug layer 64, the plug layer 64 may invade the upper barrier metal portion 62. However, since the lower barrier metal portion 61 is densely formed, the interlayer insulating film 38 can be protected from damage during the formation of the plug layer 64.

[0139] The film thickness of the lower barrier metal portion 61 may be thinner than the film thickness of the upper barrier metal portion 62. The film thickness of the lower barrier metal portion 61 may be thinner than the film thickness of the first alloy layer 63. The lower barrier metal portion 61 may be thinned by etching after a dense film is formed. Etching after a dense film is formed may be performed using a chemical solution. The chemical solution used for etching may be, for example, hydrofluoric acid (hydrofluoric acid), ammonia hydrogen peroxide, or sulfuric acid. The ammonia hydrogen peroxide is ammonia (NH ４ OH), hydrogen peroxide (H ２ O ２ ) and water (H ２O). Etching after the dense film is formed may be dry etching, reverse sputtering, or the like. The film thickness of the lower barrier metal portion 61 may be 1 nm or more and 10 nm or less. The film thickness of the lower barrier metal portion 61 may be the film thickness at the thickest position in the contact hole 54. The film thickness of the lower barrier metal portion 61 may be formed within a predetermined range over the entire sidewall of the interlayer insulating film 38. The film thickness of the upper barrier metal portion 62 may be 1 nm or more and 100 nm or less. The film thickness of the first alloy layer 63 may be 1 nm or more and 200 nm or less.

[0140] The lower barrier metal portion 61 may cover the sidewall 54w of the contact hole 54. The lower end of the lower barrier metal portion 61 may be in contact with the oxide layer 66. That is, the bottom surface 54b and the sidewall 54w of the contact hole 54 may be covered with the first alloy layer 63 and the lower barrier metal portion 61, respectively.

[0141] The opening width of the contact hole 54 is the width of the contact hole 54 in the trench arrangement direction on the upper surface of the interlayer insulating film 38. The opening width of the contact hole 54 may be 100 nm or more and 1000 nm or less.

[0142] When electron beams, particle beams, etc. for forming the lifetime control region pass through the MOS gate structure, defects may occur near the interface between the oxide film of the MOS gate structure and the semiconductor layer. If a metal such as Ti, which has a hydrogen storage effect, is present near the MOS gate structure, it may store hydrogen diffusing into the gate portion, inhibiting hydrogen termination of dangling bonds in the MOS gate structure and causing fluctuations in the threshold voltage.

[0143] An unreacted initial metal film having a hydrogen absorption effect may remain on the upper surface of the first alloy layer 63 or on the sidewall 54w of the contact hole 54. In the semiconductor device 100 of this example, the upper surface of the first alloy layer 63 is etched and oxidized to reduce the amount of the remaining initial metal film having a hydrogen absorption effect, thereby forming an oxide layer 66. Furthermore, in the semiconductor device 100 of this example, the metal film 69 and the lower barrier metal portion 61 are removed or thinned to reduce the amount of remaining metal in the initial metal film having a hydrogen absorption effect. This suppresses the influence of the hydrogen absorption effect and promotes hydrogen termination of dangling bonds in the MOS gate structure. This suppresses fluctuations in the threshold voltage.

[0144] By providing the oxide layer 66, the semiconductor device 100 can ensure barrier properties during film formation of the plug layer 64. The semiconductor device 100 of this example can suppress fluctuations in threshold voltage while increasing the reliability of the front surface 21. Furthermore, the semiconductor device 100 can form a lifetime control region while suppressing fluctuations in threshold voltage, thereby reducing reverse recovery loss.

[0145] The electron beam and particle beam used to form the lifetime control region have a greater effect on the MOS gate structure when irradiated from the front surface 21 side of the semiconductor substrate 10, but can also affect the MOS gate structure when irradiated from the back surface 23 side of the semiconductor substrate 10. Therefore, the semiconductor device 100 can recover damage to the MOS gate structure and suppress fluctuations in threshold voltage even when irradiated from the back surface 23 side. When irradiating the semiconductor substrate 10 with a particle beam or the like from the back surface 23 side, the acceleration voltage increases and the device becomes larger. However, in the semiconductor device 100 of this example, the effect of irradiating the particle beam or the like from the front surface 21 can be suppressed, so the lifetime control region can be formed using a smaller device.

[0146] FIG. 3C is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of FIG. 3C is an XZ cross-section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. This example shows an enlarged cross-section of a modified second contact portion 54B and its vicinity. The second contact portion 54B of this example differs from the second contact portion 54B shown in FIGS. 3A and 3B in that a second barrier metal layer 68 is provided outside the contact hole 54 and above the interlayer insulating film 38. Other structures may be any of those described herein. The XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10 is the same as the XZ cross-section of FIG. 3C except that the emitter region 12 is provided instead of the contact region 15 of FIG. 3C , and is therefore not shown.

[0147] The second barrier metal layer 68 may be provided outside the contact hole 54 and in contact with the upper surface of the interlayer insulating film 38. Forming the second barrier metal layer 68 also on the interlayer insulating film 38 can improve reliability during packaging, such as wire bonding and resin encapsulation. FIG. 3D is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of FIG. 3D is an XZ cross-section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. This example shows an enlarged cross-sectional view of a vicinity of a second contact portion 54B according to a further modification. The second contact portion 54B of this example differs from the second contact portion 54B shown in FIG. 3C in that the plug layer 64 is provided above the interlayer insulating film 38 outside the contact hole 54. Other structures may be any of those described herein. The XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10 is the same as the XZ cross section of FIG. 3D except that the emitter region 12 is provided instead of the contact region 15 of FIG. 3D, and therefore is not shown.

[0148] The plug layer 64 may be provided outside the contact hole 54 in contact with the upper surface of the first barrier metal layer 60. By forming the plug layer 64 also on the interlayer insulating film 38, reliability during mounting such as wire bonding and resin sealing can be improved.

[0149] FIG. 3E is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of FIG. 3E is an XZ cross-section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, a structure in which the contact region 15 is located at the center of the mesa portion and the emitter region 12 is provided in contact with the trench portion will be described. The second contact portion 54B of this example differs from the second contact portion 54B of FIGS. 3A and 3B in that a second barrier metal layer 68 is provided above the interlayer insulating film 38 outside the contact hole 54 and that an emitter electrode 52 is provided in the contact hole 54 instead of the plug layer 64. The emitter electrode 52 is connected to the front surface 21 of the semiconductor substrate 10 via the contact hole 54. The other structures may be any of the configurations described herein.

[0150] Even when the plug layer 64 is not provided, the first barrier metal layer 60 is also formed on the interlayer insulating film 38, thereby improving reliability during packaging such as resin sealing.

[0151] FIG. 4A is an enlarged cross-sectional view of the semiconductor device 100. FIG. 4B is an enlarged cross-sectional view of the semiconductor device 100. The cross-section in FIG. 4A is an XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10, and the cross-section in FIG. 4B is an XZ cross-section passing through the contact region 15 on the front surface 21. This example shows an enlarged cross-section of a vicinity of a second contact portion 54B according to a modified example. The second contact portion 54B of this example differs from the second contact portion 54B shown in FIGS. 3A and 3B in the configuration of the second barrier metal layer 68. Here, differences from the second contact portion 54B shown in FIGS. 3A and 3B will be mainly described, and descriptions of common elements will be omitted as appropriate.

[0152] In this example, the second barrier metal layer 68 includes a metal film 69 and a lower barrier metal portion 61 below the upper barrier metal portion 62. That is, during the etching process for forming the oxide layer 66 on the first alloy layer 63, the metal film 69 and the lower barrier metal portion 61 may not be completely removed but may remain as thin films. The lower barrier metal portion 61 is provided on the metal film 69. The lower barrier metal portion 61 contains a nitride of a predetermined conductive first metal. For example, the lower barrier metal portion 61 is made of TiN. The lower barrier metal portion 61 is formed by annealing the metal film 69 containing the first metal. The lower barrier metal portion 61 is made of TiN formed by annealing the metal film 69, which is formed on the sidewall of the contact hole 54 as an initial metal film, in a nitrogen atmosphere. Alternatively, the metal film 69 may be completely removed by etching, and the lower barrier metal portion 61 may be provided on the sidewall 54w of the contact hole 54. Alternatively, the lower barrier metal portion 61 may be completely removed by etching, and the upper barrier metal portion 62 may be provided on the metal film 69 .

[0153] The lower barrier metal portion 61 and the first alloy layer 63 may be formed by the same annealing process. For example, using the metal film 69 formed on the inner wall of the contact hole 54, the lower barrier metal portion 61 of TiN is formed on the sidewall 54w of the contact hole 54, and the first alloy layer 63 of titanium silicide is formed on the bottom surface 54b of the contact hole 54. At this time, the lower barrier metal portion 61 and the metal film 69 remaining on the sidewall 54w or the bottom surface 54b of the contact hole 54 may be thinned by etching, and the lower barrier metal portion 61 and the metal film 69 remaining on the first alloy layer 63 provided on the bottom surface 54b of the contact hole 54 may be removed and thinned by etching and used to form the oxide layer 66.

[0154] 5A shows an example of a cross section taken along the line aa' in FIG. 1B. Fig. 5A shows an example of the arrangement of the first contact portion 54A and the second contact portion 54B. The transistor portion 70 has a first region 70-1 having the first contact portion 54A and a second region 70-2 having the second contact portion 54B.

[0155] The first region 70-1 is provided at a distance from the diode section 80, and the second region 70-2 is provided adjacent to the diode section 80. That is, in the transistor section 70 of this example, the region including the center in the trench arrangement direction is the first region 70-1, and the region provided between the first region 70-1 and the diode section 80 is the second region 70-2.

[0156] As described above, the second contact portion 54B has a higher resistance than the first contact portion 54A, and therefore, in the second region 70-2 adjacent to the diode portion 80, hole injection is suppressed when the diode portion 80 is conductive, thereby making it possible to suppress reverse recovery loss. On the other hand, in the first region 70-1, the oxide layer 66 is not provided on the bottom surface 54b of the contact hole 54, and therefore good contact resistance can be maintained.

[0157] The front surface side lifetime control region 152 is provided so as to extend to the boundary between the first region 70-1 and the second region 70-2. In other words, the front surface side lifetime control region 152 may be provided so as to extend from the diode section 80 to the second region 70-2. When the front surface side lifetime control region 152 is provided in the second region 70-2, the threshold voltage may be particularly reduced, but this reduction in threshold voltage can be suppressed by removing or thinning the metal film 69 that stores hydrogen and the lower barrier metal section 61 on the side surface 54w of the contact hole in the second contact section 54B.

[0158] The diode section 80 may be provided with a second contact section 54B. That is, the diode section 80 may be a second region 80-2. By providing the diode section 80 with the second contact section 54B, which has a higher resistance than the first contact section 54A, hole injection when the diode section 80 is conductive is suppressed, and reverse recovery loss can be suppressed.

[0159] The thickness of the oxide layer 66 provided on the second contact portion 54B of the diode portion 80 may be greater than the thickness of the oxide layer 66 provided on the second contact portion 54B of the second region 70-2, which further increases the resistance of the second contact portion 54B of the diode portion 80, further suppresses hole injection when the diode portion 80 is conductive, and further suppresses reverse recovery loss.

[0160] 5A, one second region 70-2 is provided between the first region 70-1 and the diode section 80, but multiple second regions 70-2 may be provided. In another example, the front surface side lifetime control region 152 may also be provided in at least a portion of the second region 70-2, but may not be provided in at least a portion of the first region 70-1, or may not be provided in at least a portion of the diode section 80. The front surface side lifetime control region 152 may or may not be provided over the entire surface of the semiconductor device 100. In yet another example, the thickness of the oxide layer 66 of the second contact portion 54B of the diode section 80 may be smaller than the thickness of the oxide layer 66 of the second contact portion 54B of the first region 70-1. The diode section 80 may be provided with a first contact portion 54A. That is, the diode section 80 may be provided with a first region 80-1 instead of or in addition to the second region 80-2.

[0161] 5B shows another example of the aa' cross section in FIG. 1B. Fig. 5B shows another example of the arrangement of the first contact portion 54A and the second contact portion 54B. The transistor portion 70 has a first region 70-1 having the first contact portion 54A and a second region 70-2 having the second contact portion 54B.

[0162] The first region 70-1 is provided adjacent to the diode section 80, and the second region 70-2 is provided spaced apart from the diode section 80. That is, in the transistor section 70 of this example, the region including the center in the trench arrangement direction is the second region 70-2, and the region provided between the second region 70-2 and the diode section 80 is the first region 70-1.

[0163] In the first region 70-1 adjacent to the diode section 80, the oxide layer 66 is not provided on the bottom surface 54b of the contact hole 54, so that good contact resistance can be maintained. This improves hole extraction and suppresses latch-up.

[0164] The front surface side lifetime control region 152 is provided so as to extend to the boundary between the first region 70-1 and the second region 70-2. In other words, the front surface side lifetime control region 152 may be provided so as to extend from the diode section 80 to the first region 70-1. When the front surface side lifetime control region 152 is provided in the first region 70-1, the threshold value may be particularly reduced, but this reduction in threshold value can be suppressed by removing or thinning the metal film 69 that stores hydrogen and the lower barrier metal section 61 on the side surface 54w of the contact hole in the second contact section 54B.

[0165] When viewed from above on the semiconductor substrate 10, the area ratio of the region where the front surface-side lifetime control region 152 is provided to the transistor portion 70 may be smaller than 0.5. That is, the area ratio of the second region 70-2 in the transistor portion 70 may be higher than the area ratio of the first region 70-1 in the transistor portion 70. When the metal film 69 having a hydrogen storage effect and the lower barrier metal portion 61 are removed or made thinner in the second region 70-2, which occupies a high area ratio in the transistor portion 70, fluctuations in the threshold voltage can be particularly suppressed.

[0166] The diode section 80 may be provided with a second contact section 54B. That is, the diode section 80 may be a second region 80-2. By providing the diode section 80 with the second contact section 54B, which has a higher resistance than the first contact section 54A, hole injection when the diode section 80 is conductive is suppressed, and reverse recovery loss can be suppressed.

[0167] The thickness of the oxide layer 66 provided on the second contact portion 54B of the diode portion 80 may be greater than the thickness of the oxide layer 66 provided on the second contact portion 54B of the second region 70-2, which further increases the resistance of the second contact portion 54B of the diode portion 80, further suppresses hole injection when the diode portion 80 is conductive, and further suppresses reverse recovery loss.

[0168] 5B shows a single first region 70-1 provided between the second region 70-2 and the diode section 80, but multiple first regions 70-1 may be provided. In another example, the front surface side lifetime control region 152 may also be provided in at least a portion of the first region 70-1, but may not be provided in at least a portion of the second region 70-2, or may not be provided in at least a portion of the diode section 80. The front surface side lifetime control region 152 may or may not be provided over the entire surface of the semiconductor device 100. In yet another example, the thickness of the oxide layer 66 of the second contact portion 54B of the diode section 80 may be smaller than the thickness of the oxide layer 66 of the second contact portion 54B of the second region 70-2. The diode section 80 may be provided with a first contact portion 54A. That is, the diode section 80 may be provided with a first region 80-1 instead of or in addition to the second region 80-2.

[0169] 5C is an enlarged view of a cross section of the semiconductor device 100. FIG. 5C shows an example of the second region 70-2. The configuration of the second region 70-2 shown in FIG. 5C may be applied to either the example of FIG. 5A or FIG. 5B. Note that while FIG. 5C shows the second contact portion 54B of FIG. 3A or FIG. 3B as the second contact portion 54B, any other second contact portion 54B described in this specification may also be used.

[0170] The second contact portion 54B has a third contact portion 54C and a fourth contact portion 54D that is provided closer to the diode portion 80 than the third contact portion 54C. The thickness of the oxide layer 66 of the fourth contact portion 54D is greater than the thickness of the oxide layer 66 of the third contact portion 54C. In other words, the multiple second contact portions 54B provided in the second region 70-2 may have thicker oxide layers 66 as they approach the diode portion 80. The thickness of the oxide layer 66 can be changed depending on the etching time.

[0171] As a result, the resistance of the second contact portion 54B becomes higher in the region closer to the diode portion 80, which further suppresses hole injection when the diode portion 80 is conductive, thereby further suppressing reverse recovery loss.

[0172] 5D is an enlarged view of a cross section of the semiconductor device 100. Fig. 5D shows an example in which the transistor section 70 is a first region 70-1 in which the first contact portion 54A is provided, and the diode section 80 is a second region 80-2 in which the second contact portion 54B is provided. Other structures may be any of the structures shown in this specification.

[0173] In this example, the provision of the first contact portion 54A in the first region 70-1 maintains good contact resistance, improves hole extraction, and suppresses latch-up. The provision of the second contact portion 54B in the second region 80-2 suppresses hole injection when the diode portion 80 is conductive, thereby suppressing reverse recovery loss. When the metal film 69 having a hydrogen storage effect and the lower barrier metal portion 61 are removed or thinned, fluctuations in the threshold voltage of the transistor portion 70 can be particularly suppressed.

[0174] 5E is an enlarged view of a cross section of the semiconductor device 100. Fig. 5E shows an example in which the transistor section 70 is a second region 70-2 in which the second contact section 54B is provided, and the diode section 80 is a first region 80-1 in which the first contact section 54A is provided. Other structures may be any of the structures shown in this specification.

[0175] In this example, by providing the second contact portion 54B in the second region 70-2, hole injection from the contact region 15 of the transistor portion 70, which has a higher concentration than the base region 14 of the diode portion 80, is suppressed when the diode portion 80 is conductive, thereby suppressing reverse recovery loss. When the metal film 69 having a hydrogen storage effect or the lower barrier metal portion 61 is removed or thinned, fluctuations in the threshold voltage can be particularly suppressed. By providing the first contact portion 54A in the first region 80-1, favorable contact resistance can be maintained, and the conduction and reverse recovery characteristics of the diode portion 80 can be adjusted.

[0176] 5D and 5E may be applied in combination with FIGS. 5A, 5B, and 5C. That is, a first region 70-1 and a second region 70-2 may be provided in the transistor section 70, and a first region 80-1 and a second region 80-2 may be provided in the diode section 80. By appropriately arranging the first regions 70-1 and 80-1 and the second regions 70-2 and 80-2 according to the application and specifications, it is possible to suppress fluctuations in the threshold voltage of the transistor section 70, suppress latch-up, and adjust the conduction and reverse recovery characteristics of the diode section 80. Furthermore, although the first regions 70-1 and 80-1 and the second regions 70-2 and 80-2 have been described as being alternately arranged along the trench arrangement direction, they may also be alternately arranged along the trench extension direction.

[0177] FIG. 6A is an enlarged view of a cross section of the semiconductor device 100. FIG. 6B is an enlarged view of a cross section of the semiconductor device 100. FIGS. 6A and 6B show enlarged views of a cross section in the vicinity of the contact hole 54. The cross section of FIG. 6A is an XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The cross section of FIG. 6B is an XZ cross section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the semiconductor device 100 having the first contact portion 54A shown in FIGS. 2A and 2B in that it includes a first trench contact portion 65A. The other structures may be any of the configurations described herein.

[0178] The first trench contact portion 65A has a contact hole 54 and is provided extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the lower end of the first trench contact portion 65A, i.e., the bottom surface 54b of the contact hole 54, is shallower than the lower end of the emitter region 12. The lower end of the first trench contact portion 65A may be deeper than the lower end of the emitter region 12. In this example, the lower end of the first trench contact portion 65A is shallower than the upper end of the gate conductive portion 44. The lower end of the first trench contact portion 65A may be deeper than the upper end of the gate conductive portion 44.

[0179] Although the interlayer insulating film 38 in this example has a single insulating film, it may have a layered structure in which multiple insulating films are stacked. By providing the first trench contact portion 65A, the semiconductor device 100 in this example can increase the contact area with the semiconductor substrate 10 and reduce contact resistance. By providing the first trench contact portion 65A in the transistor portion 70, it is possible to easily extract holes and suppress latch-up.

[0180] FIG. 7A is an enlarged view of a cross section of the semiconductor device 100. FIG. 7B is an enlarged view of a cross section of the semiconductor device 100. FIGS. 7A and 7B show enlarged views of a cross section in the vicinity of the contact hole 54. The cross section of FIG. 7A is an XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The cross section of FIG. 7B is an XZ cross section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the semiconductor device 100 having the second contact portion 54B shown in FIGS. 3A and 3B in that it includes a second trench contact portion 65B. The other structures may be any of the configurations described herein.

[0181] The second trench contact portion 65B has a contact hole 54 and is provided extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the lower end of the second trench contact portion 65B, i.e., the bottom surface 54b of the contact hole 54, is shallower than the lower end of the emitter region 12. The lower end of the second trench contact portion 65B may be deeper than the lower end of the emitter region 12. In this example, the lower end of the second trench contact portion 65B is shallower than the upper end of the gate conductive portion 44. The lower end of the second trench contact portion 65B may be deeper than the upper end of the gate conductive portion 44.

[0182] Although the interlayer insulating film 38 in this example has a single insulating film, it may have a layered structure in which multiple insulating films are stacked. By providing the second trench contact portion 65B, the semiconductor device 100 in this example can increase the contact area with the semiconductor substrate 10 and reduce contact resistance. By providing the second trench contact portion 65B in the transistor portion 70, it is possible to easily extract holes and suppress latch-up.

[0183] 8 is a flowchart showing an example of a manufacturing process for the semiconductor device 100. In step S100, an element structure on the front surface 21 side of the semiconductor device 100 is formed. Step S100 may include a step of forming a dummy trench portion 30 and a gate trench portion 40 as the element structure on the front surface 21 side. Step S100 may include a step of forming a base region 14, an emitter region 12, a contact region 15, and the like by ion implantation into the semiconductor substrate 10 as the element structure on the front surface 21 side.

[0184] In step S102, an interlayer insulating film 38 is formed above the semiconductor substrate 10. The interlayer insulating film 38 may be formed by stacking a plurality of insulating films. In step S104, contact holes are formed by etching the interlayer insulating film 38. In step S104, contact holes such as contact hole 54, contact hole 55, and contact hole 56 may be formed in the interlayer insulating film 38.

[0185] In step S106, a metal film 69 is deposited to form the lower barrier metal portion 61 and the first alloy layer 63. In this example, the metal film 69 is deposited on the sidewall 54w and bottom surface 54b of the contact hole 54. That is, the metal film 69 is formed so as to be in contact with the interlayer insulating film 38 and the semiconductor substrate 10. For example, the metal film 69 is a Ti film deposited by sputtering. The thickness of the metal film 69 may be 1 nm or more and 100 nm or less.

[0186] In step S108, the semiconductor substrate 10 is annealed in a nitrogen atmosphere. This forms a lower barrier metal portion 61 on the sidewall 54w of the contact hole 54 and a first alloy layer 63 on the bottom surface 54b. In this manner, the metal film 69 in contact with the interlayer insulating film 38 becomes the lower barrier metal portion 61, and the metal film 69 in contact with the semiconductor substrate 10 becomes the first alloy layer 63. In this example, the lower barrier metal portion 61 is a dense TiN film formed by annealing the Ti film on the sidewall 54w of the contact hole 54. In this example, the first alloy layer 63 is a titanium silicide film formed by annealing the Ti film on the bottom surface 54b of the contact hole 54. The annealing temperature may be 300°C or higher and 1100°C or lower. The annealing to form the lower barrier metal portion 61 may be performed before forming the upper barrier metal portion 62.

[0187] In step S110, after the first alloy layer 63 is formed on the bottom surface 54b of the contact hole 54, an oxide layer 66 is formed on the second contact portion 54B. The oxide layer 66 may be formed before the upper barrier metal portion 62 is formed. The oxide layer 66 is formed on the upper surface of the first alloy layer 63 in the contact hole 54. The oxide layer 66 may be formed on the entire exposed surface of the first alloy layer 63 in the contact hole 54. The step of forming the oxide layer 66 may include a wet etching step or a dry etching step.

[0188] When the oxide layer 66 is formed by etching, the unreacted metal film 69 and lower barrier metal portion 61 remaining on the sidewall 54w of the contact hole 54 may be etched in the process of forming the oxide layer 66. This may adjust the thickness of the metal film 69 and lower barrier metal portion 61 from the sidewall 54w of the contact hole 54 to a predetermined thickness. The lower barrier metal portion 61 may be etched to a thickness of 1 nm or more and 10 nm or less. The metal film 69 or lower barrier metal portion 61 may be completely removed by etching. That is, the portion from which the metal film 69 and lower barrier metal portion 61 have been completely removed corresponds to the second contact portion 54B in FIGS. 3A and 3B , while the portion from which no metal film 69 remains and the lower barrier metal portion 61 has been thinned to a predetermined thickness corresponds to the second contact portion 54B in FIGS. 3C and 3D .

[0189] Step S110 is a process for forming an oxide layer 66 on the second contact portion 54B and does not have to be applied to the first contact portion 54A. Therefore, the oxide layer 66 is not formed on the first contact portion 54A, and the metal film 69 may remain on the sidewall 54w of the contact hole 54. Therefore, the second contact portion 54B, on which the oxide layer 66 is formed and from which the metal film 69 has been removed, has a higher resistance than the first contact portion 54A.

[0190] In step S112, an upper barrier metal portion 62 is formed. The upper barrier metal portion 62 may be formed by laminating on the first alloy layer 63 in the first contact portion 54A, and may be formed by laminating on the oxide layer 66 in the second contact portion 54B. The upper barrier metal portion 62 may be formed by laminating on the metal film 69 or the lower barrier metal portion 61 on the sidewall 54w of the contact hole 54. When the metal film 69 or the lower barrier metal portion 61 is completely removed, the upper barrier metal portion 62 may be formed in contact with the interlayer insulating film 38 on the sidewall 54w of the contact hole 54. The upper barrier metal portion 62 in this example is a TiN film formed by sputtering.

[0191] In step S114, the semiconductor substrate 10 is annealed in a nitrogen atmosphere. The annealing conditions in step S114 may be the same as or different from the annealing conditions in step S108. The annealing in this example is performed after the upper barrier metal portion 62 is formed. The annealing of the upper barrier metal portion 62 may be performed before the plug layer 64 is formed. Note that step S114 does not necessarily have to be performed.

[0192] In step S116, the plug layer 64 is formed. In this example, tungsten is formed by CVD (Chemical Vapor Deposition) so as to fill the inside of the contact hole 54.

[0193] The oxide layer 66 of the second contact portion 54B is provided on the upper surface of the first alloy layer 63 and may function as a metal diffusion prevention layer when forming the plug layer 64. By providing the oxide layer 66, it is possible to prevent the plug layer 64 from penetrating into the first alloy layer 63 when the plug layer 64 is formed by CVD.

[0194] In step S118, the plug layer 64 is etched back. This may remove unnecessary tungsten film outside the contact hole 54. The etch-back may be performed by dry etching or CMP (Chemical Mechanical Polishing). When the tungsten film is removed, the metal film 69, the lower barrier metal portion 61, and the upper barrier metal portion 62 on the interlayer insulating film 38 may also be removed. The metal film 69, the lower barrier metal portion 61, and the upper barrier metal portion 62 on the interlayer insulating film 38 may be removed in a step separate from the etch-back of the plug layer 64. The metal film 69, the lower barrier metal portion 61, and the upper barrier metal portion 62 on the interlayer insulating film 38 do not have to be removed. Note that step S118 may be omitted, leaving the plug layer 64 outside the contact hole 54. Furthermore, steps S116 and S118 may be omitted, and the plug layer 64 need not be formed inside the contact hole 54 and on the interlayer insulating film 38.

[0195] After step S118, the emitter electrode 52 may be formed above the semiconductor substrate 10. Furthermore, after step S118, components on the back surface 23 side, such as the collector electrode 24, may be formed. After step S118, the back surface-side lifetime control region 151 and the front surface-side lifetime control region 152 may be formed.

[0196] FIG. 9 shows a flow diagram of a different manufacturing process from step S110 shown in FIG. 8 . In step S1100, an oxide layer 66 is formed on the bottom surfaces 54b of both the first contact portion 54A and the second contact portion 54B. The oxide layer 66 may be formed by etching the first alloy layer 63. Alternatively, the oxide layer 66 may be formed by depositing an oxide film or by oxidation through heating. The oxide layer 66 may also be formed in areas other than the bottom surface 54b. If the oxide film is deposited, it may be an oxide of the element that forms the first alloy layer, or a different oxide. At the completion of step S1100, the first contact portion 54A and the second contact portion 54B may have the same configuration and the same thickness. Next, in step S1102, the oxide film on the bottom surface 54b of the first contact portion 54A is removed. If unnecessary oxide layers 66 have been formed inside and around the contact holes 54 of the first contact portion 54A and the second contact portion 54B, or in other areas, they may be removed, or may be removed simultaneously. This method also makes it possible to form a structure in which the oxide layer 66 is formed on the second contact portion 54B, while the first contact portion 54A does not have the oxide layer 66. Upon completion of step S1102, the thickness and configuration of each portion constituting the first contact portion 54A and the second contact portion 54B may differ due to the removal of the unnecessary oxide film.

[0197] FIG. 10A is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of FIG. 10A is an XZ cross-section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, an enlarged cross-sectional view in the vicinity of the first contact portion 54A according to the modified example is shown. The first contact portion 54A in this example is different from the first contact portion 54A shown in FIG. 2B in the configuration of the first barrier metal layer 60. Here, the description will be centered on the differences from the first contact portion 54A shown in FIG. 2B, and the description of the common elements will be omitted as appropriate.

[0198] The first contact portion 54A in FIG. 10A is formed by etching the oxide layer 66 by the first alloy layer 63 and removing the oxide layer 66 in the manufacturing process flow shown in FIGS. 8 and 9. The first barrier metal layer 60 in this example does not have the metal film 69 and the lower barrier metal portion 61 below the upper barrier metal portion 62. That is, in the etching when forming the oxide layer 66 on the first alloy layer 63, all of the metal film 69 and the lower barrier metal portion 61 are removed.

[0199] Note that the XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10 is common to the XZ cross-section of FIG. 10A except that the emitter region 12 is provided instead of the contact region 15 in FIG. 10A, so the illustration is omitted. Also, when the metal film 69 and the lower barrier metal portion 61 are not all removed and remain in the etching when forming the oxide layer 66 on the first alloy layer 63, it becomes the same as the structure shown in FIG. 2B.

[0200] The cross-section of FIG. 10B is an XZ cross-section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, an enlarged cross-sectional view in the vicinity of the first contact portion 54A according to the modified example is shown. The first contact portion 54A in this example is different from the first contact portion 54A shown in FIG. 10A in that the first barrier metal layer 60 is provided above the interlayer insulating film 38 outside the contact hole 54. The other structures may be any of the configurations shown in this specification.

[0201] The first contact portion 54A in FIG. 10B is formed by etching the oxide layer 66 in the manufacturing process flow shown in FIGS. 8 and 9 and then removing the oxide layer 66. The first barrier metal layer 60 in this example does not have the metal film 69 and the lower barrier metal portion 61 below the upper barrier metal portion 62. That is, even in the structure where the first barrier metal layer 60 is provided above the interlayer insulating film 38 outside the contact hole 54, in the etching when forming the oxide layer 66 on the first alloy layer 63, all of the metal film 69 and the lower barrier metal portion 61 may be removed.

[0202] In addition, the XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10 is common to the XZ cross-section of FIG. 10B except that the emitter region 12 is provided instead of the contact region 15 in FIG. 10B, so the illustration is omitted. Also, when the metal film 69 and the lower barrier metal portion 61 remain without being completely removed in the etching when forming the oxide layer 66 on the first alloy layer 63, it is the same as the structure shown in FIG. 2C.

[0203] The cross-section of FIG. 10C is an XZ cross-section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, an enlarged view of the cross-section in the vicinity of the first contact portion 54A according to the modified example is shown. The first contact portion 54A in this example is different from the first contact portion 54A shown in FIG. 10B in that the plug layer 64 is provided above the interlayer insulating film 38 outside the contact hole 54. Other structures may be any of the configurations shown in this specification.

[0204] The first contact portion 54A in FIG. 10C is formed by etching the oxide layer 66 by the first alloy layer 63 in the manufacturing process flow shown in FIGS. 8 and 9, and the oxide layer 66 is removed. The first barrier metal layer 60 in this example does not have the metal film 69 and the lower barrier metal portion 61 below the upper barrier metal portion 62. That is, even in the structure where the plug layer 64 is provided above the interlayer insulating film 38 outside the contact hole 54, in the etching when forming the oxide layer 66 on the first alloy layer 63, all of the metal film 69 and the lower barrier metal portion 61 may be removed.

[0205] The XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10 is common to the XZ cross-section of FIG. 10C except that the emitter region 12 is provided instead of the contact region 15 in FIG. 10C, so the illustration is omitted. Also, when the metal film 69 and the lower barrier metal portion 61 are not all removed and remain in the etching when forming the oxide layer 66 on the first alloy layer 63, it is the same as the structure shown in FIG. 2D.

[0206] The cross-section of FIG. 10D is an XZ cross-section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, an enlarged view of the cross-section in the vicinity of the first contact portion 54A according to the modified example is shown. The first contact portion 54A in this example is different from the first contact portion 54A shown in FIG. 10B in that the first barrier metal layer 60 is provided above the interlayer insulating film 38 outside the contact hole 54 and does not have the plug layer 64 in the contact hole 54. Other structures may be any of the configurations shown in this specification.

[0207] 8 and 9 , the first contact portion 54A is formed by etching the first alloy layer 63 and then removing the oxide layer 66. The first barrier metal layer 60 of this example does not have a metal film 69 or a lower barrier metal portion 61 below the upper barrier metal portion 62. That is, even in a structure in which the first barrier metal layer 60 is provided above the interlayer insulating film 38 outside the contact hole 54 and no plug layer 64 is provided within the contact hole 54, the metal film 69 and the lower barrier metal portion 61 may all be removed in the etching that is performed to form the oxide layer 66 on the first alloy layer 63.

[0208] Furthermore, if the metal film 69 and the lower barrier metal portion 61 are not entirely removed during the etching process for forming the oxide layer 66 on the first alloy layer 63 and remain, the structure will be similar to that shown in FIG. 2E.

[0209] In the above example, the first contact portion 54A in the mesa portion of the transistor portion does not have the oxide layer 66 on the emitter region 12 and the contact region 15, and the second contact portion 54B has the oxide layer 66 on the emitter region 12 and the contact region 15, but this is not limiting. In the transistor portion 70, the first contact portion 54A and the second contact portion 54B may be distinguished by the presence or absence of the oxide layer 66 on the contact region 15.

[0210] The cross section of FIG. 11A is an XZ cross section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. This example shows an enlarged view of a cross section near the first contact portion 54A according to a modified example. This example describes a structure in which the contact region 15 is located at the center of the mesa portion and the emitter region 12 is provided in contact with the trench portion. This example differs from the structure shown in FIG. 10D in that an oxide layer 66 is provided on the emitter region 12. The other structures may have any of the configurations described herein. That is, the lower barrier metal portion 61, the metal film 69, the first barrier metal layer 60, the plug layer 64, and the emitter electrode 52 may have any of the configurations described herein.

[0211] The first contact portion 54A in Figure 11A is formed by etching the first alloy layer 63 in the manufacturing process flow shown in Figures 8 and 9, and then removing the oxide layer 66 from the upper part of the contact region 15 in the first contact portion 54A.

[0212] The cross section of FIG. 11B is an XZ cross section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. This example shows an enlarged view of a cross section near the second contact portion 54B according to a modified example. This example describes a structure in which the contact region 15 is located at the center of the mesa portion and the emitter region 12 is provided in contact with the trench portion. This example differs from the structure shown in FIG. 3E in that the oxide layer 66 is not present on the emitter region 12. The other structures may have any of the configurations described herein. That is, the lower barrier metal portion 61, the metal film 69, the second barrier metal layer 68, the plug layer 64, and the emitter electrode 52 may have any of the configurations described herein.

[0213] The second contact portion 54B in Figure 11B is formed by etching the first alloy layer 63 in the manufacturing process flow shown in Figures 8 and 9, and when the oxide layer 66 is removed from the first contact portion 54A, the oxide layer 66 is also removed from the upper part of the emitter region 12 of the second contact portion 54B.

[0214] The cross section of FIG. 12A is an XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. This example shows an enlarged view of a cross section in the vicinity of the first contact portion 54A according to a modified example. This example describes a structure in which the contact regions 15 and the emitter regions 12 are alternately arranged along the trench portion. This example differs from the structure shown in FIG. 10A in that an oxide film is present on the emitter region 12, in that an oxide film is present on the emitter region 12. The other structures may have any of the configurations described herein. That is, the first barrier metal layer 60, the plug layer 64, and the emitter electrode 52 may have any of the configurations described herein.

[0215] 8 and 9, the first contact portion 54A is obtained by forming an oxide layer 66 by etching the first alloy layer 63 and then removing the oxide layer 66 above the contact region 15 in the first contact portion 54A. At this time, the XZ cross section passing through the contact region 15 is as shown in FIG. 10A.

[0216] The cross section of FIG. 12B is an XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. In this example, an enlarged view of a cross section in the vicinity of the first contact portion 54A according to a modified example is shown. In this example, a structure in which the contact regions 15 and the emitter regions 12 are alternately arranged along the trench portion will be described. This example differs from FIG. 2A in that an oxide film is present on the emitter region 12. The other structures may have any of the configurations described herein. That is, the first barrier metal layer 60, the plug layer 64, and the emitter electrode 52 may have any of the configurations described herein.

[0217] 8 and 9 , the first contact portion 54A in FIG. 12B is formed by etching the first alloy layer 63, and then removing the oxide layer 66 from the upper portion of the contact region 15 in the first contact portion 54A. The XZ cross section passing through the contact region 15 at this time is as shown in FIG. 2B . In the first contact portion 54A of the emitter region 12 and the contact region 15 shown in FIGS. 12A and 10A , the lower barrier metal portion 61 and the metal film 69 are completely removed. However, the examples shown in FIGS. 12B and 2B show examples in which the lower barrier metal portion 61 and the metal film 69 remain without being completely removed. Alternatively, the oxide layer 66 may be formed by a method other than etching the first alloy layer 63, such as by forming the oxide layer 66 by deposition or the like and then partially removing it.

[0218] Alternatively, the XZ cross section passing through the emitter region 12 and the contact region 15 of the first contact portion 54A may be as shown in FIGS. 12A and 2A, or as shown in FIGS. 12B and 10A.

[0219] The cross section of FIG. 12C is an XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. This example shows an enlarged view of a cross section in the vicinity of the second contact portion 54B according to a modified example. This example will be described taking as an example a structure in which the contact regions 15 and the emitter regions 12 are alternately arranged along the trench portion. This example differs from FIG. 4A in that there is no oxide layer 66 on the emitter region 12. The other structures may have any of the configurations described herein. That is, the second barrier metal layer 68, the plug layer 64, and the emitter electrode 52 may have any of the configurations described herein.

[0220] The second contact portion 54B in FIG. 12C is an example in which, in the manufacturing process flow shown in FIG. 8 , the oxide layer 66 is formed by etching the first alloy layer 63 only on the contact region 15 of the second contact portion 54B. Alternatively, in the manufacturing process flow shown in FIGS. 8 and 9 , the oxide layer 66 is formed by etching the first alloy layer 63, and when removing the oxide layer 66 in the first contact portion 54A, the oxide layer 66 is also removed from above the emitter region 12 of the second contact portion 54B, resulting in the lower barrier metal portion 61 and the metal film 69 remaining without being completely removed. Alternatively, the oxide layer 66 may be formed by a method other than etching the first alloy layer 63, such as by forming the oxide layer 66 by deposition and then partially removing it. In this case, the XZ cross section passing through the contact region 15 is as shown in FIG. 3B or 4B .

[0221] The cross section of Figure 12D is an XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. This example shows an enlarged view of a cross section in the vicinity of the second contact portion 54B according to a modified example. This example will be described taking as an example a structure in which the contact regions 15 and the emitter regions 12 are alternately arranged along the trench portion. This example differs from Figure 3A in that there is no oxide layer 66 on the emitter region 12. The other structures may have any of the configurations described herein. That is, the second barrier metal layer 68, the plug layer 64, and the emitter electrode 52 may have any of the configurations described herein.

[0222] 8 and 9, the second contact portion 54B in Fig. 12D is formed by etching the first alloy layer 63, and when the oxide layer 66 is removed from the first contact portion 54A, the oxide layer 66 is also removed from the upper portion of the emitter region 12 of the second contact portion 54B. In this case, the XZ cross section passing through the contact region 15 is as shown in Fig. 3B.

[0223] Alternatively, the XZ cross section of the second contact portion 54B passing through the emitter region 12 and the contact region 15 may be as shown in FIG. 12D and FIG. 4B.

[0224] 13 shows another example of a top view of the semiconductor device 100. This figure is an enlarged view of the top surface of region A in FIG. 1A. The first contact portion 55A and the second contact portion 55B in this example refer to regions including the contact hole 55 and its internal structure, respectively, and have a structure common to the first contact portion 54A and the second contact portion 54B. The first contact portion 55A in this example is electrically connected to the gate trench portion 40 provided in the first region 70-1 via the connection portion 25, and the second contact portion 55B in this example is electrically connected to the gate trench portion 40 provided in the second region 70-2 via the connection portion 25.

[0225] The first contact portion 55A and the second contact portion 55B of the present example are provided below the gate metal layer 50 and are electrically connected to the gate metal layer 50. That is, the first contact portion 55A of the present example electrically connects the gate trench portion 40 provided in the first region 70-1 to the gate metal layer 50, and the second contact portion 55B of the present example electrically connects the gate trench portion 40 provided in the second region 70-2 to the gate metal layer 50. The connection portions 25 of the present example are not provided so as to extend in the X-axis direction as in FIG. 1B , but are provided corresponding to the respective contact holes 55.

[0226] FIG. 14A is an enlarged cross-sectional view of the semiconductor device 100. FIG. 14A is a YZ cross-section near the first contact portion 55A shown in FIG. 13. The first contact portion 55A of this example includes a contact hole 55, a first barrier metal layer 60, a first alloy layer 63, and a plug layer 64. For convenience, the description herein will refer to the inner wall of the contact hole 55, with the portion above the front surface 21 of the semiconductor substrate 10 as a sidewall 55w, and the portion below the front surface 21 of the semiconductor substrate 10 as a bottom surface 55b. The first contact portion 55A of this example has a structure similar to that of the first contact portion 54A of FIG. 2A. The first contact portion 55A of this example may have a structure similar to that of the first contact portion 54A or the first trench contact portion 65A described using FIG. 2B and subsequent figures.

[0227] The first contact portion 55A of the present example contacts the connection portion 25 at the bottom surface 55b of the contact hole 55. The connection portion 25 may be provided on the front surface 21 of the semiconductor substrate 10 via the gate insulating film 42. The connection portion 25 may be provided above the well region 17. The first contact portion 55A of the present example electrically connects the gate metal layer 50 and the connection portion 25.

[0228] 14B is an enlarged view of a cross section of the semiconductor device 100. FIG. 14B is a YZ cross section near the second contact portion 55B shown in FIG. 13. The second contact portion 55B of this example includes a contact hole 55, a second barrier metal layer 68, a first alloy layer 63, a plug layer 64, and an oxide layer 66. The second contact portion 55B of this example has a structure similar to that of the second contact portion 54B of FIG. 3A. The second contact portion 55B of this example may have a structure similar to that of the second contact portion 54B or the second trench contact portion 65B described using FIG. 3B and subsequent figures.

[0229] The second contact portion 55B of the present example contacts the connection portion 25 at the bottom surface 55b of the contact hole 55. The connection portion 25 may be provided on the front surface 21 of the semiconductor substrate 10 via the gate insulating film 42. The connection portion 25 may be provided above the well region 17. The second contact portion 55B of the present example electrically connects the gate metal layer 50 and the connection portion 25.

[0230] In this way, by further providing the first contact portion 55A and the second contact portion 55B, it is possible to suppress fluctuations in the threshold voltage of the transistor portion 70, suppress latch-up, and finely adjust the conduction of the diode portion 80 and the characteristics during reverse recovery.

[0231] 15 shows another example of a top view of the semiconductor device 100. This figure is an enlarged view of the top surface of region A in FIG. 1A. The semiconductor device 100 in FIG. 15 differs from FIG. 13 in that the first contact portion 55A and the second contact portion 55B are provided above the gate trench portion 40. Here, a description of the points in common with the semiconductor device 100 shown in FIG. 13 will be omitted, and the description will focus on the points of difference.

[0232] The semiconductor device 100 of this example does not include a connection portion 25. The first contact portion 55A of this example is connected to the gate trench portion 40 provided in the first region 70-1, and the second contact portion 55B of this example is connected to the gate trench portion 40 provided in the second region 70-2. In other words, the first contact portion 55A of this example electrically connects the gate trench portion 40 provided in the first region 70-1 to the gate metal layer 50, and the second contact portion 55B of this example electrically connects the gate trench portion 40 provided in the second region 70-2 to the gate metal layer 50.

[0233] 16A is an enlarged view of a cross section of the semiconductor device 100. Fig. 16A is a YZ cross section in the vicinity of the first contact portion 55A shown in Fig. 15. The first contact portion 55A of this example contacts the gate conductive portion 44 of the gate trench portion 40 at the bottom surface 55b of the contact hole 55. That is, the first contact portion 55A of this example is directly connected to the gate trench portion 40, and electrically connects the gate trench portion 40 to the gate metal layer 50.

[0234] 16B is an enlarged view of a cross section of the semiconductor device 100. Fig. 16B is a YZ cross section in the vicinity of the second contact portion 55B shown in Fig. 15. The second contact portion 55B of this example contacts the gate conductive portion 44 of the gate trench portion 40 at the bottom surface 55b of the contact hole 55. That is, the second contact portion 55B of this example is directly connected to the gate trench portion 40, and electrically connects the gate trench portion 40 to the gate metal layer 50.

[0235] FIG. 17 shows another example of a top view of the semiconductor device 100. This figure is an enlarged view of the top surface of region A in FIG. 1A. The gate trench portion 40 in FIG. 17 differs from that in FIG. 13 in that it includes a first gate trench portion 40A and a second gate trench portion 40B that extends longer than the first gate trench portion 40A. Furthermore, the gate metal layer 50 in this example includes a first gate metal layer 50-1 and a second gate metal layer 50-2 that extends outward (toward the negative Y-axis direction in FIG. 17) beyond the first gate metal layer 50-1 in a top view of the semiconductor substrate 10. Here, a description of the commonalities with the semiconductor device 100 shown in FIG. 15 will be omitted, and the following description will focus on the differences.

[0236] The first gate trench portion 40A in this example is a gate trench portion 40 provided in a first region 70-1 of the transistor portion 70, and the second gate trench portion 40B in this example is a gate trench portion 40 provided in a second region 70-2 of the transistor portion 70. The first gate trench portion 40A in this example is electrically connected to the first gate metal layer 50-1 via a first contact portion 55A, and the second gate trench portion 40B in this example extends beyond the first gate metal layer 50-1 in a top view of the semiconductor substrate 10 and is electrically connected to the second gate metal layer 50-2 via a second contact portion 55B. Note that, although both the first gate metal layer 50-1 and the second gate metal layer 50-2 are provided in each of the first region 70-1 and the second region 70-2 in this example, only one of them may be provided.

[0237] That is, in this example, the gate trench portion 40 provided in the first region 70-1 of the transistor portion 70 is electrically connected to a gate metal layer 50 different from the gate trench portion 40 provided in the second region 70-2. This makes it possible to suppress fluctuations in the threshold voltage of the transistor portion 70, suppress latch-up, and finely adjust the conduction and reverse recovery characteristics of the diode portion 80.

[0238] FIG. 18 shows another example of a top view of the semiconductor device 100. This figure is an enlarged view of the top surface of region A in FIG. 1A. The semiconductor device 100 in FIG. 18 is similar to FIG. 13 in that it includes a connection portion 25, but differs from FIG. 13 in that the gate metal layer 50 includes a first gate metal layer 50-1 and a second gate metal layer 50-2 that extends outward from the first gate metal layer 50-1 (toward the negative Y-axis direction in FIG. 18) when viewed from above on the semiconductor substrate 10. The semiconductor device 100 in FIG. 18 is similar to FIG. 17 in that it includes multiple gate metal layers 50, but differs from FIG. 17 in that the multiple gate trench portions 40 have the same length in the extension direction (Y-axis direction). Here, a description of the commonalities with the semiconductor device 100 shown in FIG. 13 or 17 will be omitted, and the following description will focus on the differences.

[0239] The first contact portion 55A of the present example is connected to the gate trench portion 40 provided in the first region 70-1 via the connection portion 25. The first contact portion 55A of the present example is in contact with the connection portion 25 at the bottom surface 55b of the contact hole 55, as shown in FIG. 14A. The second contact portion 54B of the present example is connected to the gate trench portion 40 provided in the second region 70-2 via the connection portion 25. The second contact portion 54B of the present example is in contact with the connection portion 25 at the bottom surface 55b of the contact hole 55, as shown in FIG. 14B.

[0240] The first gate metal layer 50-1 of the present example may extend in the same direction as the second gate metal layer 50-2 (the X-axis direction in FIG. 18 ) and have a protruding portion on the second gate metal layer 50-2 side in a top view of the semiconductor substrate 10, and the first contact portion 55A of the present example may be provided below the protruding portion of the first gate metal layer 50-1. The second gate metal layer 50-2 of the present example may have a protruding portion on the first gate metal layer 50-1 side, and the second contact portion 54B of the present example may be provided below the protruding portion of the second gate metal layer 50-2. The first contact portion 55A and the second contact portion 54B of the present example may be provided at the same position in the Y-axis direction.

[0241] The first contact portion 55A and the second contact portion 55B of the present example electrically connect different gate metal layers to the connection portion 25. The first contact portion 55A of the present example is provided below the protruding portion of the first gate metal layer 50-1 and is electrically connected to the first gate metal layer 50-1. The second contact portion 55B of the present example is provided below the protruding portion of the second gate metal layer 50-2 and is electrically connected to the second gate metal layer 50-2. In other words, the first contact portion 55A of the present example electrically connects the gate trench portion 40 provided in the first region 70-1 to the first gate metal layer 50-1, and the second contact portion 55B of the present example electrically connects the gate trench portion 40 provided in the second region 70-2 to the second gate metal layer 50-2.

[0242] In this way, even without providing gate trench portions 40 having different lengths, by providing protrusions on each of the first gate metal layer 50-1 and the second gate metal layer 50-2, multiple gate trench portions 40 can be electrically connected to multiple gate metal layers 50, respectively.

[0243] 19 shows an example of a top view of the gate pad 112. In the semiconductor device 100 of FIG. 19, the gate metal layer 50 has a first gate metal layer 50-1 and a second gate metal layer 50-2, as in FIG. 17 or 18, but in other examples, only one gate metal layer 50 may be connected to the gate pad 112. In this example, the gate pad 112, the first gate metal layer 50-1, and the second gate metal layer 50-2 are provided spaced apart from each other.

[0244] The gate pad 112 in this example may be an electrode containing a metal such as aluminum, similar to the emitter electrode 52. The gate pad 112 is provided separately from the emitter electrode 52 when viewed from above the semiconductor substrate 10. A protective film such as polyimide may be provided between the gate pad 112, the emitter electrode 52, the first gate metal layer 50-1, and the second gate metal layer 50-2, and above parts of the gate pad 112 and the emitter electrode 52, and above the first gate metal layer 50-1 and the second gate metal layer 50-2; however, in FIG. 19 , only the boundary indicating the opening region 114 of the gate pad 112 is shown. The gate pad 112 has an opening region 114 on its upper surface that is exposed by an opening in the protective film.

[0245] The semiconductor device 100 of this example includes a connection portion 225 provided below the gate pad 112. The connection portion 225 of this example is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film. The connection portion 225 of this example is made of a conductive material such as polysilicon doped with impurities. The connection portion 225 of this example is polysilicon (N+) doped with N-type impurities. The connection portion 225 of this example may have the same configuration as the connection portion 25. In another example, the connection portion 225 may be formed in a different process from the connection portion 25, and may have a different configuration including the underlying insulating film.

[0246] In this example, the connection portion 225 has a first connection portion 225 A and a second connection portion 225 B. In this example, the first connection portion 225 A is electrically connected to the first gate metal layer 50-1, and the second connection portion 225 B is electrically connected to the second gate metal layer 50-2.

[0247] A first contact portion 255A and a second contact portion 255B are provided below the connection portion 225. In this example, the first contact portion 255A and the second contact portion 255B respectively refer to regions including the contact hole 255 provided through the interlayer insulating film 38 and its internal structure, and have a structure common to the first contact portion 55A and the second contact portion 55B. In this example, the first contact portion 255A electrically connects the first connection portion 225A and the first gate metal layer 50-1, and the second contact portion 255B electrically connects the second connection portion 225B and the second gate metal layer 50-2.

[0248] The first connection portion 225A and the second connection portion 225B of the present example may be provided below the opening region 114 of the gate pad 112. In another example, the connection portion 225 does not have to be provided below the opening region 114. The first contact portion 255A and the second contact portion 255B of the present example may be provided below the opening region 114 of the gate pad 112 and below the protective film. In another example, the first contact portion 255A or the second contact portion 255B of the gate pad 112 may be provided only below the opening region 114 or below the protective film. The first connection portion 225A and the second connection portion 225B of the present example are formed to have the same outer shape, and the first contact portion 255A and the second contact portion 255B are provided at the same relative position in the Y-axis direction. In another example, the first contact portion 255A and the second contact portion 255B may be provided at relatively different positions in the Y-axis direction of the first connection portion 225A and the second connection portion 225B, and the first connection portion 225A and the second connection portion 225B may be configured with different shapes.

[0249] The first connection portion 225A and the second connection portion 225B in this example protrude from the gate pad 112 in the direction opposite to the active portion 120 (the positive side in the Y-axis direction, toward the end side 102) and are connected to the first gate metal layer 50-1 and the second gate metal layer 50-2 by the first contact portion 255A and the second contact portion 255B. In another example, the connection portion 225 may protrude from the gate pad 112 toward the active portion 120. The first connection portion 225A and the second connection portion 225B in this example are connected to the gate pad 112, the first gate metal layer 50-1, and the second gate metal layer 50-2 by the first contact portion 255A and the second contact portion 255B, respectively. In another example, only the contact hole 255 connecting the first gate metal layer 50-1 and the second gate metal layer 50-2 or the contact hole 255 connecting the gate pad 112 may have separate structures such as the first contact portion 255A and the second contact portion 255B.

[0250] In this example, the first contact portion 255A and the second contact portion 255B have their longitudinal lengths in the X-axis direction. In other examples, they may have their longitudinal lengths in any direction, may intersect with each other, or may have a curvature. Note that, in this example, the first contact portion 255A and the second contact portion 255B are provided near the gate pad 112. Therefore, even if the contact hole 55 connecting the gate trench portion 40 provided in the first region 70-1 to the first gate metal layer 50-1 or the connection portion 25 and the contact hole 55 connecting the gate trench portion 40 provided in the second region 70-2 to the second gate metal layer 50-2 or the connection portion 25 do not have separate structures like the first contact portion 55A and the second contact portion 55B, respectively, it is possible to fine-tune the characteristics.

[0251] 20A is a diagram showing an example of the bb' cross section of FIG. 19. The bb' cross section is a YZ cross section passing through the gate pad 112 and the first gate metal layer 50-1. In this example, the gate pad 112 and the first gate metal layer 50-1 are provided spaced apart from each other. The first contact portion 255A in this example has a structure similar to the first contact portion 54A or the first trench contact portion 65A described using FIG. 2A and subsequent figures.

[0252] The gate pad 112 of the present example is electrically connected to the first connection portion 225A via the first contact portion 255A. The first connection portion 225A may be provided on the front surface 21 of the semiconductor substrate 10 with the gate insulating film 42 interposed therebetween. The first gate metal layer 50-1 of the present example is also electrically connected to the first connection portion 225A via the first contact portion 255A. As a result, the gate pad 112 of the present example is provided at a distance from the first gate metal layer 50-1, but is electrically connected to the first gate metal layer 50-1.

[0253] 20B is a diagram showing an example of the cc' cross section of FIG. 19. The cc' cross section is a YZ cross section passing through the gate pad 112 and the second gate metal layer 50-2. In this example, the gate pad 112 and the second gate metal layer 50-2 are provided spaced apart from each other. The second contact portion 255B in this example has a structure similar to the second contact portion 54B or the second trench contact portion 65B described using FIG. 3A and subsequent figures.

[0254] 20B , the gate pad 112 is electrically connected to the second connection portion 225B via the second contact portion 255B. The second connection portion 225B may be provided on the front surface 21 of the semiconductor substrate 10 with the gate insulating film 42 interposed therebetween. The second gate metal layer 50-2 of this example is also electrically connected to the second connection portion 225B via the second contact portion 255B. As a result, the gate pad 112 of this example is electrically connected to the second gate metal layer 50-2 while being spaced apart from the second gate metal layer 50-2.

[0255] FIG. 21 shows another example of a top view of the gate pad 112. FIG. 21 differs from FIG. 19 in that it includes at least one connection trench 240 instead of the connection portion 225, i.e., a first connection trench 240A and a second connection trench 240B instead of the first connection portion 225A and the second connection portion 225B. The connection trench 240 includes a connection trench provided on the front surface 21 of the semiconductor substrate 10, a connection trench insulating film 242 such as an oxide film, and a conductive connection trench conductive portion 244. In this example, the connection trench insulating film 242 is formed to cover the inner wall of the connection trench. The connection trench conductive portion 244 is formed inside the connection trench, further inside than the connection trench insulating film 242. The connection trench conductive portion 244 in this example is insulated from the semiconductor substrate 10 via the connection trench insulating film 242 and the like. The connection trench conductive portion 244 may be made of impurity-doped polysilicon or the like. In this example, the connection trench conductive portion 244 is polysilicon (N+) doped with N-type impurities, and may otherwise have the structure described with reference to Figures 19, 20A, and 20B.

[0256] In this example, a first contact portion 255A is provided below the first gate metal layer 50-1, and a second contact portion 255B is provided below the second gate metal layer 50-2. In this example, the first contact portion 255A and the second contact portion 255B are provided below the gate pad 112.

[0257] A first connection trench portion 240A is provided below the first contact portion 255A provided below the first gate metal layer 50-1 and the first contact portion 255A provided below the gate pad 112. As a result, the gate pad 112 of this example is electrically connected to the first gate metal layer 50-1 via the first connection trench conductive portion 244A and the first contact portion 255A. Similarly, a second connection trench portion 240B is provided below the second contact portion 255B provided below the second gate metal layer 50-2 and the second contact portion 255B provided below the gate pad 112. As a result, the gate pad 112 of this example is electrically connected to the second gate metal layer 50-2 via the second connection trench conductive portion 244B and the second contact portion 255B.

[0258] The connection trench portion 240 may be formed simultaneously with the gate trench portion 40, may be insulated from the semiconductor substrate 10 by a gate insulating film 42, and may have a gate conductive portion 44 therein. In another example, the connection trench portion 240 may be formed separately from the gate trench portion 40 and may have a different structure. The connection trench portions 240 in this example are formed in stripes spaced apart from each other when viewed from above the semiconductor substrate 10. In another example, each connection trench portion 240 may be bent, branched, or intersecting at its end or in the middle when viewed from above the semiconductor substrate 10.

[0259] The connection trench portion 240 of this example is provided below the gate pad 112, between the first connection trench portion 240A and the second connection trench portion 240B when viewed from above the semiconductor substrate 10, and includes a dummy connection trench portion 245 that is connected only to the gate pad 112. The dummy connection trench portion 245 includes a dummy connection trench provided on the front surface 21 of the semiconductor substrate 10, a connection trench insulating film 242, and a conductive dummy connection trench conductive portion 249. The connection trench insulating film 242 of this example is formed to cover the inner wall of the dummy connection trench. The dummy connection trench conductive portion 249 of this example is formed inside the dummy connection trench, more inward than the connection trench insulating film 242. The dummy connection trench portion 245 is insulated from the semiconductor substrate 10 via the connection trench insulating film 242 and the like. The dummy connection trench conductive portion 249 may be polysilicon doped with impurities.

[0260] In another example, the dummy connection trench 245 may be provided only below the opening region 114 of the gate pad 112, or may be provided outside the gate pad 112. In another example, the dummy connection trench 245 may be provided between the first connection trenches 240A or between the second connection trenches 240B, or outside the first connection trenches 240A or the second connection trenches 240B, when viewed from above the semiconductor substrate 10. In this example, a contact hole 255 having the same size as the first contact portion 255A or the second contact portion 255B provided above the first connection trench 240A or the second connection trench 240B is provided above the dummy connection trench 245. However, in another example, a contact hole 255 having a different size from the first contact portion 255A or the second contact portion 255B provided above the first connection trench 240A or the second connection trench 240B may be provided. In this example, the first contact portion 255A is provided above the dummy connection trench portion 245, but in other examples, the second contact portion 255B may be provided, and the contact hole 255 may not be provided. In other examples, the dummy connection trench portion 245 may not be provided.

[0261] FIG. 22A is a diagram showing an example of the ff' cross section of FIG. 21. The ff' cross section is an XZ cross section passing through the gate pad 112, the first connection trench portion 240A, the second connection trench portion 240B, and the dummy connection trench portion 245. A first contact portion 255A is provided above the first connection trench portion 240A provided below the gate pad 112. The first contact portion 255A in this example may have a structure similar to the first contact portion 54A or the first trench contact portion 65A described using FIG. 2A and subsequent figures. As a result, the gate pad 112 in this example is electrically connected to the first gate metal layer 50-1 via the first connection trench conductive portion 244A and the first contact portion 255A. Similarly, a second contact portion 255B is provided above the second connection trench portion 240B provided below the gate pad 112. The second contact portion 255B of the present example may have a structure similar to the second contact portion 54B or the second trench contact portion 65B described with reference to Figures 3A and subsequent figures, thereby electrically connecting the gate pad 112 of the present example to the second gate metal layer 50-2 via the second connection trench conductive portion 244B and the second contact portion 255B.

[0262] Figure 22B is a diagram showing an example of the gg' cross section in Figure 21. The gg' cross section is a YZ cross section passing through the gate pad 112 and the first gate metal layer 50-1. In this example, the gate pad 112 and the first gate metal layer 50-1 are provided spaced apart from each other.

[0263] The gate pad 112 of the present example is electrically connected to the first connection trench conductive portion 244A via the first contact portion 255A. The first connection trench conductive portion 244A may be provided on the front surface 21 of the semiconductor substrate 10 via the connection trench insulating film 242. The first gate metal layer 50-1 of the present example is also electrically connected to the first connection portion 225A via the first contact portion 255A. As a result, the gate pad 112 of the present example is electrically connected to the first gate metal layer 50-1 while being spaced apart from the first gate metal layer 50-1.

[0264] Figure 22C is a diagram showing an example of the hh' cross section in Figure 21. The hh' cross section is a YZ cross section passing through the gate pad 112 and the second gate metal layer 50-2. In this example, the gate pad 112 and the second gate metal layer 50-2 are provided spaced apart from each other.

[0265] 22C , the gate pad 112 is electrically connected to the second connection trench conductive portion 244B via the second contact portion 255B. The second connection trench conductive portion 244B may be provided on the front surface 21 of the semiconductor substrate 10 via the connection trench insulating film 242. The second gate metal layer 50-2 of this example is also electrically connected to the second connection portion 225B via the second contact portion 255B. As a result, the gate pad 112 of this example is electrically connected to the second gate metal layer 50-2 while being spaced apart from the second gate metal layer 50-2.

[0266] FIG. 23 shows another example of a top view of a semiconductor device 100. The semiconductor device 100 in FIG. 23 has two active portions 120 arranged side by side in the Y-axis direction. When viewed from above on the semiconductor substrate 10, a first gate metal layer 50-1 and a second gate metal layer 50-2 surround each active portion 120. Here, "surrounding" does not necessarily mean that the first gate metal layer 50-1 and the second gate metal layer 50-2 surround each active portion 120 without interruption. As long as the gate trench portion 40 of the active portion 120 is arranged so as to be connected to at least one of the first gate metal layer 50-1 and the second gate metal layer 50-2, there may be an area where the gate metal layer 50 does not extend. In the active portion 120, an emitter electrode 52 is provided above the semiconductor substrate 10, but is omitted in FIG. 23. The emitter electrode 52, the first gate metal layer 50-1, and the second gate metal layer 50-2 are spaced apart from each other. In this example, when viewed from above the semiconductor substrate 10, the first gate metal layer 50-1 is provided on the inside (active section 120 side) and the second gate metal layer 50-2 is provided on the outside (edge ​​102 side).

[0267] The first gate metal layer 50-1 and the second gate metal layer 50-2 surrounding the active portion 120 on the positive side in the Y-axis direction are electrically connected to the gate pad 112 via a first connection portion 225A and a second connection portion 225B, respectively. The first connection portion 225A in this example is electrically connected to the gate pad 112 and the first gate metal layer 50-1 via a first contact portion 255A, similar to FIG. 20A . The second connection portion 225B in this example is electrically connected to the gate pad 112 and the second gate metal layer 50-2 via a second contact portion 255B, similar to FIG. 20B .

[0268] The first gate metal layer 50-1 and the second gate metal layer 50-2 surrounding the active portion 120 on the negative side in the Y-axis direction are electrically connected to the first gate metal layer 50-1 and the second gate metal layer 50-2 surrounding the active portion 120 on the positive side in the Y-axis direction via a first connection portion 225A and a second connection portion 225B, respectively. The first gate metal layer 50-1 and the second gate metal layer 50-2 extending between the active portion 120 and the edge 102, together with the first connection portion 225A and the second connection portion 225B, form the peripheral gate wiring 130, and the first gate metal layer 50-1 and the second gate metal layer 50-2 extending between the active portions 120 form the inter-active portion gate wiring 131. The first connection portion 225A connecting the first gate metal layers 50-1 to each other and the second connection portion 225B connecting the second gate metal layers 50-2 to each other will be described with reference to FIGS. 24A and 24B.

[0269] FIG. 24A is a diagram showing an example of the dd' cross section of FIG. 23. The dd' cross section is a YZ cross section passing through the first gate metal layer 50-1 and the second gate metal layer 50-2 at the intersection of the peripheral gate wiring 130 and the inter-active portion gate wiring 131. In this example, the first gate metal layer 50-1 and the second gate metal layer 50-2 are spaced apart from each other. The first contact portion 255A in this example is provided below the first gate metal layer 50-1 and electrically connects the first gate metal layer 50-1 and the first connection portion 225A. The first contact portion 255A in this example has a longitudinal axis in the Y-axis direction, but is not limited thereto. The first contact portion 255A in this example may have a structure similar to the first contact portion 54A or the first trench contact portion 65A described using FIG. 2A and subsequent figures.

[0270] The first gate metal layer 50-1 surrounding the active portion 120 on the negative side in the Y axis direction is electrically connected to the first connection portion 225A via the first contact portion 255A. Similarly, the first gate metal layer 50-1 surrounding the active portion 120 on the positive side in the Y axis direction is electrically connected to the first connection portion 225A via the first contact portion 255A. In other words, the first contact portion 255A and the first connection portion 225A form an underpass below the second gate metal layer 50-2, and the first gate metal layer 50-1 surrounding the active portion 120 on the negative side in the Y axis direction is electrically connected to the first gate metal layer 50-1 surrounding the active portion 120 on the positive side in the Y axis direction via this underpass, and is electrically connected to the gate pad 112 via the first gate metal layer 50-1 surrounding the active portion 120 on the positive side in the Y axis direction.

[0271] FIG. 24B is a diagram showing an example of the ee' cross section of FIG. 23. The ee' cross section is a YZ cross section passing through the second gate metal layer 50-2 at the intersection of the peripheral gate wiring 130 and the inter-active portion gate wiring 131. The second contact portion 255B of this example is provided below the second gate metal layer 50-2 and electrically connects the second gate metal layer 50-2 and the second connection portion 225B. The second contact portion 255B of this example has a longitudinal direction in the Y-axis direction, but is not limited thereto. The second contact portion 255B of this example may have a structure similar to the second contact portion 54B or the second trench contact portion 65B described using FIG. 3A and subsequent figures. Note that the length in the Y-axis direction of the second connection portion 225B in Figures 23 and 24B, i.e., the overall length in the Y-axis direction of the second connection portion 225B, or the distance between the second contact portions 255B, is shown as being the same as the length in the Y-axis direction of the first connection portion 225A in Figures 23 and 24A, i.e., the overall length in the Y-axis direction of the first connection portion 225A, or the distance between the first contact portions 255A, but the length in the Y-axis direction of the first connection portion 225A may be greater or smaller than the length in the Y-axis direction of the second connection portion 225B.

[0272] The second gate metal layer 50-2 surrounding the active portion 120 on the negative side in the Y axis direction is electrically connected to the second connection portion 225B via the second contact portion 255B. Similarly, the second gate metal layer 50-2 surrounding the active portion 120 on the positive side in the Y axis direction is electrically connected to the second connection portion 225B via the second contact portion 255B. In other words, the second contact portion 255B and the second connection portion 225B form an underpass below the interlayer insulating film 38, and the second gate metal layer 50-2 surrounding the active portion 120 on the negative side in the Y axis direction is electrically connected to the second gate metal layer 50-2 surrounding the active portion 120 on the positive side in the Y axis direction via this underpass, and is electrically connected to the gate pad 112 via the second gate metal layer 50-2 surrounding the active portion 120 on the positive side in the Y axis direction.

[0273] 23 , 24A, and 24B , the inter-active portion gate wiring 131 is composed of two first gate metal layers 50-1 and two second gate metal layers 50-2, but it may be composed of one first gate metal layer 50-1 and one second gate metal layer 50-2. That is, one first gate metal layer 50-1 and one second gate metal layer 50-2 may be connected to the gate trench portions 40 on both the positive side and the negative side in the Y-axis direction. Even in such a case, an underpass may be formed using either or both of the first connection portion 225A and the second connection portion 225B at the intersection of the peripheral gate wiring 130 and the inter-active portion gate wiring 131. Furthermore, since the first contact portion 255A and the second contact portion 255B are provided near the gate pad 112, it is possible to finely adjust the characteristics even when the contact holes 255 connecting the first connection portion 225A and the second connection portion 225B to the first gate metal layer 50-1 and the second gate metal layer 50-2 are either the first contact portion 255A or the second contact portion 255B, rather than being separate structures like the first contact portion 255A and the second contact portion 255B, respectively.

[0274] Figure 24C is a diagram showing another example of the dd' cross section of Figure 23. This example differs from Figure 24A in that a first connection trench portion 240A is provided instead of the first connection portion 225A. In other respects, the structure may be similar to the structure described using Figures 23 and 24A.

[0275] The first gate metal layer 50-1 surrounding the active portion 120 on the negative side in the Y axis direction is electrically connected to the first connection trench conductive portion 244A via the first contact portion 255A. Similarly, the first gate metal layer 50-1 surrounding the active portion 120 on the positive side in the Y axis direction is electrically connected to the first connection trench conductive portion 244A via the first contact portion 255A. In other words, the first contact portion 255A and the first connection trench conductive portion 244A form an underpass below the second gate metal layer 50-2. The first gate metal layer 50-1 surrounding the active portion 120 on the negative side in the Y axis direction is electrically connected to the first gate metal layer 50-1 surrounding the active portion 120 on the positive side in the Y axis direction via this underpass, and is electrically connected to the gate pad 112 via the first gate metal layer 50-1 surrounding the active portion 120 on the positive side in the Y axis direction.

[0276] Figure 24D is a diagram showing another example of the ee' cross section of Figure 23. This example differs from Figure 24B in that a second connection trench portion 240B is provided instead of the second connection portion 225B. In other respects, the structure may be similar to the structure described using Figures 23 and 24B.

[0277] The second gate metal layer 50-2 surrounding the active portion 120 on the negative side in the Y axis direction is electrically connected to the second connection trench conductive portion 244B via the second contact portion 255B. Similarly, the second gate metal layer 50-2 surrounding the active portion 120 on the positive side in the Y axis direction is electrically connected to the second connection trench conductive portion 244B via the second contact portion 255B. In other words, an underpass is formed inside the semiconductor substrate 10 by the second contact portion 255B and the second connection trench conductive portion 244B. The second gate metal layer 50-2 surrounding the active portion 120 on the negative side in the Y axis direction is electrically connected to the second gate metal layer 50-2 surrounding the active portion 120 on the positive side in the Y axis direction via this underpass, and is electrically connected to the gate pad 112 via the second gate metal layer 50-2 surrounding the active portion 120 on the positive side in the Y axis direction.

[0278] As described above, at the intersection of the peripheral gate wiring 130 with the inter-active portion gate wiring 131 and at the branch of the gate metal layer 50, the gate metal layers 50 surrounding the respective active portions 120 can be connected to each other via underpasses made of connection trenches 240 provided on the front surface 21 of the semiconductor substrate 10, instead of the connection portion 225 provided above the semiconductor substrate 10, as in the connection between the gate pad 112 and the gate metal layer 50. Furthermore, the connection portion 225 and the connection trenches 240 may be used in combination, for example, by configuring either the connection between the gate pad 112 and the gate metal layer 50 or the underpass at the branch of the gate metal layer 50 using the connection portion 225 provided on the front surface 21 of the semiconductor substrate 10, and the other using the connection trenches 240.

[0279] FIG. 25 shows another example of a top view of the semiconductor device 100. The semiconductor device 100 in FIG. 25 has two active portions 120 arranged side by side in the X-axis direction, and a first gate metal layer 50-1 and a second gate metal layer 50-2 are provided surrounding each active portion 120 when viewed from above the semiconductor substrate 10. In the active portions 120, an emitter electrode 52 is provided above the semiconductor substrate 10, but is omitted from FIG. 25. The emitter electrode 52, the first gate metal layer 50-1, and the second gate metal layer 50-2 are provided spaced apart from each other. In this example, when viewed from above the semiconductor substrate 10, the first gate metal layer 50-1 is provided on the inner side (the active portion 120 side), and the second gate metal layer 50-2 is provided on the outer side (the edge 102 side). In this example, in the active section 120, the gate trench section 40 has a longitudinal direction in the X-axis direction and may be connected to the peripheral gate wiring 130 and the inter-active section gate wiring 131 along the edge 102 in the X-axis direction.

[0280] The first gate metal layer 50-1 and the second gate metal layer 50-2 surrounding the active portion 120 are electrically connected to the gate pad 112 via a first connection portion 225A and a second connection portion 225B, respectively. The first connection portion 225A in this example is electrically connected to the gate pad 112 and the first gate metal layer 50-1 via a first contact portion 255A, similar to FIG. 20A. The second connection portion 225B in this example is electrically connected to the gate pad 112 and the second gate metal layer 50-2 via a second contact portion 255B, similar to FIG. 20B.

[0281] The first gate metal layer 50-1 and the second gate metal layer 50-2 extending between the active portion 120 and the edge 102, together with the first connection portion 225A and the second connection portion 225B, constitute the peripheral gate wiring 130, and the first gate metal layer 50-1 and the second gate metal layer 50-2 extending between the active portions 120 constitute the inter-active portion gate wiring 131. In the semiconductor device 100 of this example, the inter-active portion gate wiring 131 and all of the active portions 120 are adjacent to the gate pad 112, and therefore, by connecting the gate pad 112 to the inter-active portion gate wiring 131 surrounding each active portion 120 or the gate metal layer 50 constituting the peripheral gate wiring 130 via the connection portion 225, all of the gate metal layers 50 are electrically connected to the gate pad 112. 24A and 24B, the semiconductor device 100 of this example does not need to be provided with the first connection portion 225A connecting the first gate metal layers 50-1 to each other and the second connection portion 225B connecting the second gate metal layers 50-2 to each other. Also in this example, the gate pad 112 may be connected to the first gate metal layer 50-1 and the second gate metal layer 50-2 via the first connection trench portion 240A and the second connection trench portion 240B.

[0282] FIG. 26 shows another example of a top view of the semiconductor device 100. The semiconductor device 100 in FIG. 26 has three active portions 120 arranged side by side in the X-axis direction, and a first gate metal layer 50-1 and a second gate metal layer 50-2 are provided surrounding each active portion 120 when viewed from above the semiconductor substrate 10. In each active portion 120, an emitter electrode 52 is provided above the semiconductor substrate 10, but this is omitted from FIG. 26. The emitter electrode 52, the first gate metal layer 50-1, and the second gate metal layer 50-2 are provided spaced apart from each other. In this example, when viewed from above the semiconductor substrate 10, the first gate metal layer 50-1 is provided on the inner side (the active portion 120 side), and the second gate metal layer 50-2 is provided on the outer side (the edge 102 side).

[0283] The first gate metal layer 50-1 and the second gate metal layer 50-2 surrounding the active portion 120 located at the center in the X-axis direction are electrically connected to the gate pad 112 via a first connection portion 225A and a second connection portion 225B, respectively. The first connection portion 225A in this example is electrically connected to the gate pad 112 and the first gate metal layer 50-1 via a first contact portion 255A, similar to FIG. 20A . The second connection portion 225B in this example is electrically connected to the gate pad 112 and the second gate metal layer 50-2 via a second contact portion 255B, similar to FIG. 20B .

[0284] The first gate metal layer 50-1 and the second gate metal layer 50-2 surrounding the active portion 120 located on the outer side in the X-axis direction (the positive or negative side in the X-axis direction) are electrically connected to the first gate metal layer 50-1 and the second gate metal layer 50-2 surrounding the active portion 120 located in the center in the X-axis direction via a first connection portion 225A and a second connection portion 225B, respectively. The first gate metal layer 50-1 and the second gate metal layer 50-2 extending between the active portion 120 and the edge 102, together with the first connection portion 225A and the second connection portion 225B, constitute the peripheral gate wiring 130, and the first gate metal layer 50-1 and the second gate metal layer 50-2 extending between the active portions 120 constitute the inter-active portion gate wiring 131. The first connection portion 225A connects the first gate metal layers 50-1 to each other via a first contact portion 255A, as shown in FIG. 24A . 24B, the second connection portion 225B connects the second gate metal layer 50-2 to each other via the second contact portion 255B. In this example, the gate pad 112, the first gate metal layer 50-1, and the second gate metal layer 50-2 may also be connected via the first connection trench portion 240A and the second connection trench portion 240B instead of the first connection portion 225A and the second connection portion 225B.

[0285] 27 shows another example of a top view of the semiconductor device 100. In this example, the gate metal layers 50 of the peripheral gate wiring 130 located outside the two active portions 120 are connected and are separated from the gate metal layer 50 of the inter-active portion gate wiring 131, which is different from the example described in FIG. 23 . Even in this case, the first gate metal layer 50-1 and the second gate metal layer 50-2 of the peripheral gate wiring 130 can be connected to the first gate metal layer 50-1 and the second gate metal layer 50-2 of the inter-active portion gate wiring 131 via the first connection portion 225A and the second connection portion 225B, thereby electrically connecting the first gate metal layer 50-1 and the second gate metal layer 50-2 surrounding each active portion 120 to the gate pad 112. In another example, the first connection trench portion 240A and the second connection trench portion 240B may be used instead of the first connection portion 225A and the second connection portion 225B.

[0286] 28 shows another example of a top view of the semiconductor device 100. This example differs from the example described in FIG. 23 in that the gate metal layer 50 of the inter-active portion gate wiring 131 connected to the gate metal layer 50 of the peripheral gate wiring 130 surrounding one active portion 120 is separated into a gate metal layer 50 extending from the negative side in the X-axis direction and a gate metal layer 50 extending from the positive side in the X-axis direction, and is connected to the gate metal layer 50 extending from the negative side in the X-axis direction and the gate metal layer 50 extending from the positive side in the X-axis direction in the peripheral gate wiring 130 surrounding the other active portion 120, respectively. When the gate metal layers 50 are connected as one in this manner, there is no need to use the first connection portion 225A, the second connection portion 225B, etc. to connect the first gate metal layer 50-1 and the second gate metal layer 50-2 of the peripheral gate wiring 130 to the first gate metal layer 50-1 and the second gate metal layer 50-2 of the inter-active portion gate wiring 131. By connecting the first gate metal layer 50-1 and the second gate metal layer 50-2 to the gate pad 112 via the first connection portion 225A and the second connection portion 225B, respectively, in the vicinity of the gate pad 112, it is possible to electrically connect the first gate metal layer 50-1 and the second gate metal layer 50-2 surrounding each active portion 120 to the gate pad 112. In another example, a first connection trench portion 240A and a second connection trench portion 240B may be used instead of the first connection portion 225A and the second connection portion 225B.

[0287] In the inter-active portion gate wiring 131, when the gate metal layers 50 of both active portions 120 are connected in the Y-axis direction at a location corresponding to the first region 70-1, the second gate metal layer 50-2 extending from the positive side in the X-axis direction is connected in the Y-axis direction further to the positive side of the X-axis direction than the first gate metal layer 50-1 extending from the positive side in the X-axis direction, so that there is a region in the first region 70-1 where the first gate metal layer 50-1 extending from the positive side in the X-axis direction is connected to the Y-axis direction. Similarly, the second gate metal layer 50-2 extending from the negative side in the X-axis direction is connected to the Y-axis direction further to the negative side of the X-axis direction than the first gate metal layer 50-1 extending from the negative side in the X-axis direction, so that there is a region in the first region 70-1 where the first gate metal layer 50-1 extending from the negative side in the X-axis direction is connected to the Y-axis direction. However, there is no problem in this region because the gate trench portion 40 corresponding to the second gate metal layer 50-2 does not exist therein.

[0288] On the other hand, in the inter-active portion gate wiring 131, at a position where the gate metal layer 50 on one active portion 120 side and the gate metal layer 50 on the other active portion 120 side are connected, the first gate metal layer 50-1 extending from the negative side in the X-axis direction on one active portion 120 side may be connected to the first gate metal layer 50-1 extending from the negative side in the X-axis direction on the other active portion 120 side, more inward in the X-axis direction than the second gate metal layer 50-2. Therefore, in the first region 70-1, the first gate metal layer 50-1 can extend over the entire area in the X-axis direction, so that the first gate metal layer 50-1 and the corresponding gate trench portion 40 can be connected on a substantial extension of the gate trench portion 40 in the Y-axis direction. Note that even if there is a region where the first gate metal layer 50-1 does not extend in the X-axis direction, the first gate metal layer 50-1 and the gate trench portion 40 can be connected by, for example, extending the connection portion 25 in the X-axis direction.

[0289] In the gate wiring 131 between active portions, when the gate metal layers 50 of both active portions 120 are connected in the Y-axis direction at a location corresponding to the diode portion 80, the diode portion 80 does not have a corresponding gate trench portion 40, so there is no problem even if there is an area where the first gate metal layer 50-1 and the second gate metal layer 50-2 do not exist.

[0290] In the inter-active portion gate wiring 131, when the gate metal layers 50 of both active portions 120 are connected in the Y-axis direction at a location corresponding to the second region 70-2, there is no gate trench portion 40 corresponding to the first gate metal layer 50-1 in the second region 70-2, so there is no problem even if there is a region where the first gate metal layer 50-1 does not extend in the X-axis direction. In the region in the second region 70-2 where the second gate metal layer 50-2 does not extend in the X-axis direction, the second gate metal layer 50-2 cannot be connected to the corresponding gate trench portion 40 on a substantial extension of the gate trench portion 40 in the Y-axis direction, but the second gate metal layer 50-2 and the corresponding gate trench portion 40 can be connected by, for example, extending the connection portion 25 in the X-axis direction.

[0291] Alternatively, the gate metal layer 50 of the inter-active portion gate wiring 131 may be separated into a gate metal layer 50 extending from the negative side in the X-axis direction and a gate metal layer 50 extending from the positive side in the X-axis direction, and the emitter electrodes 52 on both active portions 120 may be connected to each other in the region where the gate metal layer 50 does not extend in the X-axis direction. Note that in order to connect the first gate metal layer 50-1 and the second gate metal layer 50-2 together, the gate metal layer 50 on one active portion 120 side and the gate metal layer 50 on the other active portion 120 side may be connected in a region other than the inter-active portion gate wiring 131, and in this case, a region where the first gate metal layer 50-1 or the second gate metal layer 50-2 does not extend may be provided in part of the periphery of the active portion 120.

[0292] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0293] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0294] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 17...Well region, 18...Drift region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 30...Dummy trench portion, 31...Extended portion, 32...Dummy insulating film, 33...Connection portion, 34...Dummy conductive portion, 38...Interlayer insulating film, 40...Gate trench portion, 41...Extended portion, 42...Gate insulating film, 4 3...Connection portion, 44...Gate conductive portion, 50...Gate metal layer, 50-1...First gate metal layer, 50-2...Second gate metal layer, 52...Emitter electrode, 54...Contact hole, 54A...First contact portion, 54B...Second contact portion, 54C...Third contact portion, 54D...Fourth contact portion, 54b...Bottom surface, 54w...Side wall, 55...Contact hole, 55A...First contact portion, 55B...Second contact portion, 56...Contact hole, 60...First barrier metal layer, 61...Lower barrier Rear metal portion, 62...upper barrier metal portion, 63...first alloy layer, 64...plug layer, 65A...first trench contact portion, 65B...second trench contact portion, 66...oxide layer, 68...second barrier metal layer, 69...metal film, 70...transistor portion, 70-1...first region, 70-2...second region, 71...mesa portion, 80...diode portion, 81...mesa portion, 82...cathode region, 85...extension region, 90...boundary portion, 91...mesa portion, 100...semiconductor device, 102...edge, 112... Gate pad, 114...opening region, 120...active portion, 130...peripheral gate wiring, 131...gate wiring between active portions, 140...edge termination structure portion, 151...back surface side lifetime control region, 152...front surface side lifetime control region, 225...connection portion, 225A...first connection portion, 225B...second connection portion, 240...connection trench portion, 240A...first connection trench portion, 240B...second connection trench portion, 242...connection trench insulating film, 244...connection trench conductive portion, 244A...first connection trench conductive portion,244B... second connection trench conductive portion, 245... dummy connection trench portion, 249... dummy connection trench conductive portion, 255... contact hole, 255A... first contact portion, 255B... second contact portion,

Claims

1. A semiconductor device comprising: a semiconductor substrate; an interlayer insulating film having a contact hole formed therein above the semiconductor substrate; and a first upper electrode formed above the interlayer insulating film, the semiconductor device having a first region having a first contact portion electrically connected to the first upper electrode through the contact hole; and a second region having a second contact portion electrically connected to the first upper electrode through the contact hole, the second contact portion having a higher resistance than the first contact portion.

2. The semiconductor device according to claim 1, wherein the first contact portion has: a first alloy layer containing a first metal provided on the bottom surface of the contact hole; and a first barrier metal layer containing the first metal provided inside the contact hole.

3. The semiconductor device according to claim 2, wherein the first barrier metal layer has a metal film containing the first metal.

4. The semiconductor device according to claim 2, wherein the first barrier metal layer has a lower barrier metal portion and an upper barrier metal portion stacked on the lower barrier metal portion, and the lower barrier metal portion is denser than the upper barrier metal portion.

5. The semiconductor device according to claim 4, wherein the upper barrier metal portion is provided in contact with an upper surface of the first alloy layer.

6. The semiconductor device according to claim 2, wherein the second contact portion comprises: a first alloy layer containing the first metal provided on the bottom surface of the contact hole; an oxide layer provided on the upper surface of the first alloy layer; and a second barrier metal layer provided inside the contact hole.

7. The semiconductor device according to claim 6, wherein the second barrier metal layer includes a nitride of the first metal.

8. The semiconductor device according to claim 6, wherein the first barrier metal layer has a metal film containing the first metal.

9. The semiconductor device described in claim 6, wherein the first barrier metal layer has a lower barrier metal portion provided on a side wall of the contact hole and an upper barrier metal portion stacked on the lower barrier metal portion, and the lower barrier metal portion is denser than the second barrier metal layer.

10. The semiconductor device according to claim 9, wherein the lower barrier metal portion is a nitride of the first metal.

11. The semiconductor device according to claim 1, comprising: a transistor portion and a diode portion, said transistor portion and said diode portion having an emitter electrode and a collector electrode between which a load current flows, and said first upper electrode is said emitter electrode.

12. The semiconductor device according to claim 11, wherein the first region is provided in the transistor portion and spaced apart from the diode portion, and the second region is provided in the transistor portion and adjacent to the diode portion.

13. The semiconductor device according to claim 11, wherein the first region is provided in the transistor portion and adjacent to the diode portion, and the second region is provided in the transistor portion and spaced apart from the diode portion.

14. The semiconductor device according to claim 12 or 13, wherein, in a top view of the semiconductor substrate, an area ratio of the second region in the transistor portion is higher than an area ratio of the first region in the transistor portion.

15. The semiconductor device according to claim 11, wherein the diode portion has the second region.

16. The semiconductor device according to claim 15, wherein a thickness of a first oxide layer provided on a bottom surface of the contact hole of the second contact portion in the second region in the diode section is greater than a thickness of a second oxide layer provided on a bottom surface of the contact hole of the second contact portion in the second region in the transistor section.

17. The semiconductor device described in claim 11, wherein the second contact portion of the second region in the transistor portion has a third contact portion and a fourth contact portion provided on the diode portion side of the third contact portion, and a thickness of a fourth oxide layer provided on the bottom surface of the contact hole of the fourth contact portion is greater than a thickness of a third oxide layer provided on the bottom surface of the contact hole of the third contact portion.

18. The semiconductor device according to any one of claims 6 to 10, wherein the oxide layer contains an oxide of an element constituting the first metal or first alloy layer.

19. The semiconductor device according to claim 2, wherein the first barrier metal layer includes a nitride of the first metal.

20. The semiconductor device according to any one of claims 2 to 10, wherein the first alloy layer contains a silicide of the first metal.

21. The semiconductor device according to any one of claims 2 to 10, wherein the first metal is titanium.

22. The semiconductor device according to claim 1, wherein the semiconductor substrate has a lifetime control region provided on a front surface side of the semiconductor substrate.

23. The semiconductor device according to claim 12 or 13, wherein the semiconductor substrate has a lifetime control region provided on the front surface side of the semiconductor substrate, and the lifetime control region extends from the diode portion to a boundary between the first region in the transistor portion and the second region in the transistor portion.

24. The semiconductor device according to claim 1, comprising: a gate trench portion provided on a front surface of the semiconductor substrate; and a connection portion provided above the gate trench portion and electrically connected to the gate trench portion, wherein the first upper electrode has a gate metal layer provided above the semiconductor substrate, and the first contact portion and the second contact portion electrically connect the gate metal layer and the connection portion.

25. The semiconductor device described in claim 24, wherein the first upper electrode has a plurality of gate metal layers provided above the semiconductor substrate, and the first contact portion and the second contact portion electrically connect different gate metal layers among the plurality of gate metal layers to the connection portion.

26. The semiconductor device according to claim 1, further comprising: a gate trench portion provided on a front surface of the semiconductor substrate; the first upper electrode having a gate metal layer provided above the gate trench portion; and the first contact portion and the second contact portion electrically connecting the gate metal layer and the gate trench portion.

27. The semiconductor device according to claim 1, wherein the first upper electrode has a gate pad provided above the semiconductor substrate, and at least one of the first contact portion and the second contact portion is provided below the gate pad.

28. The semiconductor device according to claim 27, wherein both the first contact portion and the second contact portion are provided below the gate pad.

29. The semiconductor device according to claim 1, further comprising a connection portion provided above the semiconductor substrate or a connection trench portion provided on the front surface of the semiconductor substrate, the first upper electrode having a plurality of gate metal layers extending above the connection portion, and at least one of the first contact portion or the second contact portion electrically connecting the plurality of gate metal layers to a connection trench conductive portion provided inside the connection portion or the connection trench portion.

30. The semiconductor device according to claim 1, comprising: a first gate trench portion provided on a front surface of the semiconductor substrate; and a second gate trench portion extending longer than the first gate trench portion; the first upper electrode has a first gate metal layer and a second gate metal layer extending outward beyond the first gate metal layer in a top view of the semiconductor substrate; the first gate trench portion is electrically connected to the first gate metal layer via the first contact portion; and the second gate trench portion extends beyond the first gate metal layer in a top view of the semiconductor substrate and is electrically connected to the second gate metal layer via the second contact portion.

31. A method for manufacturing a semiconductor device, comprising the steps of: forming an interlayer insulating film above a semiconductor substrate; forming a contact hole in the interlayer insulating film; forming a first upper electrode above the interlayer insulating film; forming a first contact portion in a first region; and forming a second contact portion in a second region, wherein the first contact portion is electrically connected to the first upper electrode through the contact hole and the second contact portion is electrically connected to the first upper electrode through the contact hole, and the second contact portion has a higher resistance than the first contact portion.

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