Display substrate and display apparatus

Abstract

A display substrate and a display apparatus, relating to the technical field of display. The display substrate comprises a base substrate, and a plurality of first signal lines and a plurality of second signal lines arranged on one side of the base substrate, the first signal lines extending in a first direction and the second signal lines extending in a second direction. The plurality of first signal lines and the plurality of second signal lines are arranged in different layers, and the plurality of first signal lines intersect with the plurality of second signal lines to define a plurality of sub-pixels. Each sub-pixel comprises at least one transistor, the transistor comprising an active layer, and the active layer comprising a channel part and a first connecting part and a second connecting part connected to two sides of the channel part. Orthographic projections of the channel part and the first signal line on the base substrate have a first overlapping area. In the first overlapping area, orthographic projections of the channel part and the second signal line on the base substrate overlap. The first direction and the second direction intersect with each other.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] As a prime example of next-generation information technology convergence and innovation, virtual reality (VR) technology is maturing, and the market is experiencing rapid growth. In recent years, the global commercialization of VR has become increasingly diverse. Beyond familiar applications like gaming and entertainment, VR is increasingly finding its way into new sectors like healthcare, education, and manufacturing, with increasing industry penetration.

[0003] Overview

[0004] The present disclosure provides a display substrate, comprising a base substrate, and a plurality of first signal lines extending along a first direction and a plurality of second signal lines extending along a second direction, arranged on one side of the base substrate, the plurality of first signal lines and the plurality of second signal lines being arranged in different layers, and the orthographic projections of the plurality of first signal lines on the base substrate intersect with the orthographic projections of the plurality of second signal lines on the substrate and define a plurality of sub-pixels; the base substrate comprises a display area and a non-display area surrounding the display area, and the sub-pixels are located in the display area; each of the sub-pixels comprises at least one transistor, the transistor comprises an active layer, the active layer comprises a channel portion and a first connecting portion and a second connecting portion connected to both sides of the channel portion; there is a first overlapping area between the channel portion and the orthographic projection of the first signal line on the base substrate; within the first overlapping area, the channel portion overlaps with the orthographic projection of the second signal line on the base substrate, and the first direction and the second direction intersect with each other.

[0005] In some embodiments, the end of the first connection portion of the active layer away from the channel portion is a first end portion, and the end of the second connection portion of the active layer away from the channel portion is a second end portion. Along a direction parallel to the second direction, the distance between the first end portion and the second end portion is greater than the arrangement period of the sub-pixels along the second direction.

[0006] In some embodiments, the first connecting portion is connected to the second signal line, at least a portion of the first connecting portion overlaps with the orthographic projection of the connected second signal line on the base substrate, and an extension direction of at least a portion of the first connecting portion is parallel to an extension direction of the second signal line.

[0007] In some embodiments, along the first direction, the width of the first connection portion is wd1, the width of the second signal line is wd2, and 0≤|wd1-wd2|≤1 μm.

[0008] In some embodiments, the first connecting portion and the second connecting portion both extend along the second direction, the channel portion extends along a third direction, and an angle between the third direction and the first direction is greater than or equal to 15° and less than or equal to 60°.

[0009] In some embodiments, the transistors of the odd-numbered rows of sub-pixels are first transistors, the transistors of the even-numbered rows of sub-pixels are second transistors, the active layer of the first transistors is a first active layer, the active layer of the second transistors is a second active layer, and the first active layer and the second active layer are in the same layer and are separated from each other;

[0010] The first direction is perpendicular to the first plane. In the orthographic projection on the first plane, the second connection portion of the first active layer overlaps with the first connection portion of the second active layer, and the second connection portion of the second active layer overlaps with the first connection portion of the first active layer.

[0011] In some embodiments, a pattern obtained by translating the first active layer along the second direction is mirror-symmetrical to the second active layer.

[0012] In some embodiments, the second signal line includes a first extension segment, a second extension segment, and a third extension segment, the second extension segment extends along the second direction and is connected between the first extension segment and the third extension segment, the first extension segment and the third extension segment both extend along the first direction and are located on the same side of the second extension segment; and

[0013] In the first overlapping region, the channel portion of the first active layer overlaps with an orthographic projection of the first extension segment on the base substrate, and the channel portion of the second active layer overlaps with an orthographic projection of the third extension segment on the base substrate.

[0014] In some embodiments, the display substrate further comprises:

[0015] a common signal line, disposed on a side of the first signal line and the second signal line away from the substrate, the common signal line comprising a first common signal line and a second common signal line intersecting each other, the first common signal line extending along the first direction, and the second common signal line extending along the second direction;

[0016] The orthographic projection of the first common signal line on the base substrate covers the orthographic projection of the first signal line on the base substrate at least in the second direction, and the orthographic projection of the second common signal line on the base substrate covers the orthographic projection of the second signal line on the base substrate at least in the first direction.

[0017] In some embodiments, the sub-pixel includes a pixel electrode and a common electrode stacked together, the common electrodes of a plurality of the sub-pixels are connected to each other, the pixel electrodes of different sub-pixels are spaced apart from each other, the pixel electrode is connected to the second connecting portion, and the common electrode is connected to the common signal line;

[0018] The pixel electrode is located on a side of the common signal line and the common electrode close to the base substrate, and is located on a side of the first signal line and the second signal line away from the base substrate.

[0019] In some embodiments, the common signal line is stacked between the pixel electrode and the common electrode, or the common electrode is stacked between the pixel electrode and the common signal line.

[0020] The present disclosure provides a display substrate, comprising a base substrate, and a plurality of first signal lines extending along a first direction and a plurality of second signal lines extending along a second direction, arranged on one side of the base substrate. The plurality of first signal lines and the plurality of second signal lines are arranged in different layers, and the orthographic projections of the plurality of first signal lines on the base substrate intersect with the orthographic projections of the plurality of second signal lines on the base substrate and define a plurality of sub-pixels. The base substrate comprises a display area and a non-display area surrounding the display area, and the sub-pixels are located in the display area. Each sub-pixel comprises at least one transistor, the transistor comprising an active layer, the active layer comprising a channel portion and a first connecting portion and a second connecting portion connected to both sides of the channel portion. The channel portion and the orthographic projection of the first signal line on the base substrate have a first overlapping region. Within the first overlapping region, the channel portion and the orthographic projection of the second signal line on the base substrate overlap, and the first direction and the second direction intersect with each other.

[0021] The transistors connecting two adjacent sub-pixels are located on different planes.

[0022] In some embodiments, the transistors of the sub-pixels in odd-numbered rows are first transistors, and the transistors of the sub-pixels in even-numbered rows are second transistors, and the first transistors and the second transistors are located in different planes;

[0023] The active layer of the first transistor is a first active layer, the active layer of the second transistor is a second active layer, and the first active layer and the second active layer are arranged in different layers.

[0024] In some embodiments, in an orthographic projection on the substrate, a pattern obtained by translating the first active layer along the second direction is mirror-symmetrical to the second active layer.

[0025] In some embodiments, a ratio of a size of the first active layer along the second direction to an arrangement period of the sub-pixels along the second direction is greater than or equal to 1 and less than or equal to 2;

[0026] A ratio of a size of the second active layer along the second direction to an arrangement period of the sub-pixels along the second direction is greater than or equal to 1 and less than or equal to 2.

[0027] In some embodiments, in the first overlapping area, the channel portion of the first active layer overlaps with the orthographic projection of the first connecting portion of the second active layer on the base substrate, and the channel portion of the second active layer overlaps with the orthographic projection of the first connecting portion of the first active layer on the base substrate.

[0028] In some embodiments, the gate of the first transistor is a first gate, and the gate of the second transistor is a second gate;

[0029] The first signal line includes: a first sub-signal line connected to the first gate, and a second sub-signal line connected to the second gate;

[0030] The second signal line includes:

[0031] a third sub-signal line connected to the first connection portion of the first active layer through a first via hole; and

[0032] a fourth sub-signal line connected to the first connection portion of the second active layer through a second via hole;

[0033] In an orthographic projection on the base substrate, the first sub-signal line at least partially covers the second via hole, and the second sub-signal line at least partially covers the first via hole.

[0034] In some embodiments, the display substrate further comprises:

[0035] a common signal line, arranged on a side of the first signal line and the second signal line away from the substrate, comprising a first common signal line and a second common signal line arranged to intersect, the first common signal line extending along the first direction, and the second common signal line extending along the second direction;

[0036] The orthographic projection of the first common signal line on the base substrate at least covers the orthographic projection of the first signal line on the base substrate in the second direction, and the orthographic projection of the second common signal line on the base substrate at least covers the orthographic projection of the second signal line on the base substrate in the first direction;

[0037] A width of at least a portion of the first common signal line in the second direction is greater than a width of the second common signal line in the first direction.

[0038] In some embodiments, the gate of the first transistor is a first gate, and the gate of the second transistor is a second gate;

[0039] The second signal line includes: a third sub-signal line connected to the first active layer, and a fourth sub-signal line connected to the second active layer; and

[0040] The first gate and the second gate are provided in different layers, and / or the third sub-signal line and the fourth sub-signal line are provided in different layers.

[0041] In some embodiments, an orthographic projection of the third sub-signal line on the base substrate overlaps with an orthographic projection of the fourth sub-signal line on the base substrate.

[0042] In some embodiments, the first signal line includes: a first sub-signal line connected to the first gate, and a second sub-signal line connected to the second gate;

[0043] In an orthographic projection on the base substrate, the first sub-signal lines and the second sub-signal lines are alternately arranged at equal intervals along the second direction.

[0044] In some embodiments, the first gate and the second gate are provided in different layers, and the third sub-signal line and the fourth sub-signal line are provided in different layers; and

[0045] The first gate and the first active layer are located on a side of the third sub-signal line close to the base substrate, the second gate and the second active layer are located on a side of the third sub-signal line away from the base substrate, and the fourth sub-signal line is located on a side of the second gate and the second active layer away from the base substrate.

[0046] In some embodiments, the first gate and the second gate are provided in different layers, and the third sub-signal line and the fourth sub-signal line are provided in the same layer; and

[0047] The second gate and the second active layer are located on a side of the first gate and the first active layer away from the base substrate, and the third sub-signal line and the fourth sub-signal line are located on a side of the second gate and the second active layer away from the base substrate.

[0048] In some embodiments, a plurality of the first active layers are arranged in an array along the first direction and the second direction, and a plurality of the second active layers are arranged in an array along the first direction and the second direction;

[0049] In the first direction, the arrangement period of the first active layer and the arrangement period of the second active layer are substantially equal to the arrangement period of the sub-pixels;

[0050] In the second direction, an arrangement period of the first active layer and an arrangement period of the second active layer are substantially equal to twice an arrangement period of the sub-pixels.

[0051] In some embodiments, the second signal line includes: a third sub-signal line connected to the first active layer, and a fourth sub-signal line connected to the second active layer, wherein the third sub-signal line and the fourth sub-signal line are provided in different layers and connected to different signal input terminals;

[0052] The gate of the first transistor is a first gate, the gate of the second transistor is a second gate, and the first signal line includes: a first sub-signal line connected to the first gate, and a second sub-signal line connected to the second gate;

[0053] The non-display area includes: a gate driving circuit including a plurality of shift registers cascaded to each other;

[0054] Wherein, the adjacent first sub-signal line and the second sub-signal line are connected to the same shift register.

[0055] In some embodiments, the second signal line includes: a third sub-signal line connected to the first active layer, and a fourth sub-signal line connected to the second active layer, wherein the third sub-signal line and the fourth sub-signal line are arranged in different layers and connected to the same signal input terminal, or the third sub-signal line and the fourth sub-signal line are arranged in the same layer;

[0056] The non-display area includes: a gate driving circuit including a plurality of shift registers cascaded to each other;

[0057] Different first signal lines are connected to different shift registers, and at least two shift registers connected to different first signal lines are located in the same row.

[0058] In some embodiments, the second signal line includes an extension segment extending along the first direction, and in the first overlapping region, the extension segment extending along the first direction overlaps with an orthographic projection of the channel portion on the base substrate.

[0059] In some embodiments, a width of the first signal line in the second direction is smaller than a width of the channel portion in the second direction;

[0060] The display area further includes: a plurality of transparent traces extending along the first direction, the transparent traces being connected to the first signal line and being located between the first signal line and the active layer, the orthographic projections of the transparent traces on the base substrate covering the orthographic projections of the first signal line on the base substrate at least in the second direction, and the orthographic projections of the transparent traces on the base substrate covering the orthographic projections of the channel portion on the base substrate; and

[0061] In the second direction, the width of the transparent wiring is greater than the width of the first signal line, and the width of the transparent wiring is substantially equal to the width of the channel portion.

[0062] In some embodiments, the display substrate further comprises:

[0063] a plurality of light-shielding traces extending along the first direction, located on a side of the active layer close to the base substrate, wherein the orthographic projections of the light-shielding traces on the base substrate cover the orthographic projections of the first signal line on the base substrate at least in the second direction;

[0064] The light-shielding traces at at least two locations have different widths in the second direction.

[0065] In some embodiments, the sub-pixel further includes a pixel electrode, the pixel electrode is connected to the second connection portion through a third via hole, and the second signal line is connected to the first connection portion through a fourth via hole;

[0066] The distance between the fourth via hole and the channel portion is a first distance, the distance between the third via hole and the channel portion is a second distance, and the first distance is greater than or equal to the second distance.

[0067] The present disclosure provides a display device, comprising:

[0068] The display substrate provided in any embodiment; and

[0069] The source driving circuit is connected to the display substrate and is used to drive the display substrate to perform display.

[0070] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.

[0071] BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for the description of the embodiments or related technologies. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.

[0073] FIG1a exemplarily shows a schematic planar structural diagram of a display substrate provided by the present disclosure;

[0074] FIG1b exemplarily shows a circuit layout diagram of a display area of ​​a display substrate;

[0075] FIG1c exemplarily shows a circuit layout diagram of common signal lines in a display area;

[0076] FIG1d exemplarily shows a schematic cross-sectional structure diagram of a common electrode, a common signal line, and a pixel electrode within a sub-pixel;

[0077] FIG2 exemplarily shows a circuit layout diagram of a display area provided by the present disclosure;

[0078] FIG3 exemplarily shows a schematic cross-sectional structure diagram of a first display area provided by the present disclosure;

[0079] FIG4 exemplarily shows a circuit layout diagram of each layer of the first display area provided by the present disclosure;

[0080] FIG5a exemplarily shows a schematic diagram of a partial cross-sectional structure of a first display area provided by the present disclosure;

[0081] FIG5 b exemplarily shows another partial cross-sectional structural schematic diagram of the first display area provided by the present disclosure;

[0082] FIG5 c exemplarily shows a circuit layout diagram of light-shielding wiring in the display area;

[0083] FIG6 exemplarily shows a partial circuit layout diagram of a first display area provided by the present disclosure;

[0084] FIG7 exemplarily shows a cross-sectional structural diagram of a second display area provided by the present disclosure;

[0085] FIG8 exemplarily shows a circuit layout diagram of each layer of the second display area provided by the present disclosure;

[0086] FIG9 exemplarily shows a topographical diagram of the second signal line near the fourth via hole and a display effect diagram;

[0087] FIG10 exemplarily shows a structural schematic diagram and a driving schematic diagram of two gate driving circuits provided by the present disclosure;

[0088] FIG11 exemplarily shows a structural schematic diagram and a driving schematic diagram of two other gate driving circuits provided by the present disclosure;

[0089] FIG12 exemplarily shows characteristic test results of two groups of thin film transistors;

[0090] FIG13 shows some characteristic values ​​of the first high PPI display substrate in the first example;

[0091] FIG14 shows some characteristic values ​​of the second high PPI display substrate in the first example;

[0092] FIG15 shows some characteristic values ​​of the third high PPI display substrate in the first example;

[0093] FIG16 shows the value ranges of some characteristic values ​​of the high PPI display substrate in the first example;

[0094] FIG17 shows some characteristic values ​​of the display substrate in the second example;

[0095] FIG18 shows the value ranges of some characteristic values ​​of the high PPI display substrate in the second example;

[0096] FIG19 shows a schematic planar structural diagram of a display device;

[0097] FIG20 shows a schematic diagram of a virtual display device;

[0098] FIG21 shows a schematic cross-sectional structure diagram of an OLED display panel.

[0099] Detailed description

[0100] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0101] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0102] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged.

[0103] The triangles, rectangles, trapezoids, pentagons or hexagons in the present disclosure are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0104] For VR display products, due to their small size, their resolution still needs to reach 2K or even 4K or above, which requires compressing the size of sub-pixels (such as a few microns), resulting in a significant reduction in the aperture ratio and transmittance of the sub-pixels, which in turn leads to increased power consumption and a decrease in display quality.

[0105] In the related art, the pixel circuit of the liquid crystal display panel (Liquid Crystal Display, LCD) includes one or two thin film transistors, which is relatively simple, so it can achieve ultra-high pixel density (Pixels Per Inch, PPI), that is, the number of pixels per inch. The liquid crystal display panel has a variety of display modes, such as ADS (Advanced Super Dimension Switch, in-plane conversion) mode, TN (twisted nematic) mode and VA (Vertical Alignment, vertical alignment) mode. In the ADS mode, the pixel electrode and the common electrode are both located on one side of the display substrate. In the TN mode and the VA mode, the pixel electrode and the common electrode are respectively arranged on opposite sides of the liquid crystal layer, the pixel electrode is located on one side of the display substrate, and the common electrode is located on the side of the opposing substrate.

[0106] The ADS mode operates on the principle that liquid crystal molecules lie in a plane parallel to the substrate. In the absence of voltage, light passing through the lower polarizer becomes linearly polarized, parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated, and is therefore absorbed by the upper polarizer and prevented from exiting. When voltage is applied, a transverse electric field forms on the liquid crystal, aligning the liquid crystal molecules along the direction of the electric field. Light passing through the lower polarizer and liquid crystal layer becomes elliptically polarized, allowing it to pass through the upper polarizer and exit.

[0107] The TN mode operates under the principle that in the absence of voltage, the liquid crystal molecules are twisted into a 90° alignment by the alignment films. Light passes through the lower polarizer and the liquid crystal molecules before exiting through the upper polarizer. When voltage is applied, most of the liquid crystal molecules, except for those near the alignment films on the upper and lower sides, align vertically. Light passing through the lower polarizer passes through the liquid crystal layer without deflection. However, since its polarization axis is parallel to the upper polarizer, the light is absorbed and cannot be emitted.

[0108] The VA mode operates on the principle that the liquid crystal molecules are aligned perpendicular to the substrate. When no voltage is applied, light passing through the lower polarizer forms linear polarization parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated and is therefore absorbed by the upper polarizer, preventing it from being emitted. When voltage is applied, the liquid crystal molecules are deflected along the electric field. Light passing through the lower polarizer and liquid crystal layer becomes elliptically polarized, allowing it to pass through the upper polarizer and be emitted.

[0109] The structure of the display substrate is described below using the ADS mode display substrate structure as an example.

[0110] The present disclosure provides a display substrate, as shown in FIG1a and FIG1b, the display substrate includes a base substrate 11 (not shown in FIG1a and FIG1b), and a plurality of first signal lines SC extending along a first direction f1 and a plurality of second signal lines DT extending along a second direction f2, arranged on one side of the base substrate 11, the plurality of first signal lines SC and the plurality of second signal lines DT being arranged in different layers, and the orthographic projections of the plurality of first signal lines SC on the base substrate 11 intersect with the orthographic projections of the plurality of second signal lines DT on the base substrate and define a plurality of sub-pixels PX; the base substrate 11 includes a display area AA and a surrounding display area In the non-display area NA of AA (as shown in FIG1a ), the sub-pixel PX is located in the display area AA; each sub-pixel PX includes at least one transistor, the transistor includes an active layer 21 / 22, and each active layer 21 / 22 includes a channel portion CH and a first connection portion D and a second connection portion S connected on both sides of the channel portion CH; there is a first overlapping area OLA between the channel portion CH and the orthographic projection of the first signal line SC on the base substrate 11; within the first overlapping area OLA, the channel portion CH and the orthographic projection of the second signal line DT on the base substrate 11 overlap, and the first direction f1 and the second direction f2 intersect with each other.

[0111] The first connection portion D is, for example, a first pole, and the second connection portion S is, for example, a second pole.

[0112] In the present disclosure, an example is given in which the first signal line SC is a gate line and the second signal line DT is a data line.

[0113] It should be noted that the left figure of FIG1b shows the active layer 21 / 22 and the first signal line SC, but does not show the second signal line DT. The right figure of FIG1b shows the active layer 21 / 22, the first signal line SC, and the second signal line DT.

[0114] In some embodiments, as shown in the left figure of Figure 1b, the end of the first connection portion D of the active layer 21 / 22 away from the channel portion CH is the first end portion, and the end of the second connection portion S of the active layer 21 / 22 away from the channel portion CH is the second end portion. Along the direction parallel to the second direction f2, the distance between the first end portion and the second end portion is greater than the arrangement period PXL of the sub-pixels PX along the second direction f2.

[0115] As shown in the left figure of FIG1b , the ratio of the size of the active layer 21 / 22 along the second direction f2 to the arrangement period PXL of the sub-pixels PX along the second direction f2 is greater than or equal to 1 and less than or equal to 2. That is, the size of the active layer 21 / 22 along the second direction f2 is greater than or equal to the arrangement period PXL of the sub-pixels PX along the second direction f2, and less than or equal to twice the arrangement period PXL of the sub-pixels PX along the second direction f2.

[0116] By increasing the size of the active layer 21 / 22 along the second direction f2 , the channel lengths of the first transistor T1 and the second transistor T2 can be increased, and the distance between the source-drain via holes and the channel portion CH can be increased.

[0117] In some embodiments, as shown in the right figure of Figure 1b, the first connection portion D is connected to the second signal line DT through a via, at least a portion of the first connection portion D overlaps with the orthographic projection of the connected second signal line DT on the base substrate 11, and the extension direction of at least a portion of the first connection portion D is parallel to the extension direction of the second signal line DT.

[0118] In some embodiments, as shown in the right figure of FIG. 1 b , along the first direction f1 , the width of the first connection portion D is wd1 , the width of the second signal line DT is wd2 , and 0≤|wd1−wd2|≤1 μm.

[0119] In some embodiments, as shown in the right figure of FIG1b , the first connecting portion D and the second connecting portion S both extend along the second direction f2, the channel portion CH extends along the third direction f3, and the angle between the third direction f3 and the first direction f1 is greater than or equal to 15° and less than or equal to 60°. For example, the angle between the third direction f3 and the first direction f1 is 30° or 45°.

[0120] In some embodiments, as shown in Figure 1b, the transistor of the odd-numbered row sub-pixel PX is the first transistor T1, the transistor of the even-numbered row sub-pixel PX is the second transistor T2, the active layer of the first transistor T1 is the first active layer 21, and the active layer of the second transistor T2 is the second active layer 22. The first active layer 21 and the second active layer 22 are in the same layer and are separated from each other.

[0121] As shown in the left figure of Figure 1b, the first direction f1 is perpendicular to the first plane (not shown in the figure), and in the orthographic projection on the first plane, the second connection portion S of the first active layer 21 overlaps with the first connection portion D of the second active layer 22, and the second connection portion S of the second active layer 22 overlaps with the first connection portion D of the first active layer 21.

[0122] Illustratively, in an orthographic projection on the first plane, the second connection portion S of the first active layer 21 of the sub-pixel PX located in the 2n+1th row overlaps with the first connection portion D of the second active layer 22 of the sub-pixel PX located in the 2n+2th row, and the second connection portion S of the second active layer 22 of the sub-pixel PX located in the 2n+2th row overlaps with the first connection portion D of the first active layer 21 of the sub-pixel PX located in the 2n+3th row. Here, n is a positive integer greater than or equal to 0.

[0123] In some embodiments, as shown in FIG. 1 b , a pattern obtained by translating the first active layer 21 along the second direction f2 is mirror-symmetrical to the second active layer 22 , and the axis of symmetry extends along the second direction f2 .

[0124] In some embodiments, as shown in the right figure of Figure 1b, the second signal line DT includes a first extension segment S1, a second extension segment S2 and a third extension segment S3, the second extension segment S2 extends along the second direction f2 and is connected between the first extension segment S1 and the third extension segment S3, the first extension segment S1 and the third extension segment S3 both extend along the first direction f1 and are located on the same side of the second extension segment S2; and in the first overlapping area OLA, the channel portion CH of the first active layer 21 overlaps with the orthographic projection of the first extension segment S1 on the base substrate 11, and the channel portion CH of the second active layer 22 overlaps with the orthographic projection of the third extension segment S3 on the base substrate 11.

[0125] As shown in the right figure of Figure 1b, in the first overlapping area OLA, the channel portion CH of the first active layer 21 and the orthographic projection of the portion of the first extension segment S1 close to the second extension segment S2 on the base substrate 11 overlap, and the channel portion CH of the second active layer 22 and the orthographic projection of the portion of the third extension segment S3 away from the second extension segment S2 on the base substrate 11 overlap.

[0126] In some embodiments, as shown in FIG1c , the display substrate further includes common signal lines 12 disposed on a side of the first signal lines SC and the second signal lines DT facing away from the base substrate 11. The common signal lines 12 include a first common signal line 121 and a second common signal line 122 intersecting each other. The first common signal line 121 extends along a first direction f1, and the second common signal line 122 extends along a second direction f2. The orthographic projection of the first common signal line 121 on the base substrate 11 overlaps the orthographic projection of the first signal line SC on the base substrate 11 at least in the second direction f2. The orthographic projection of the second common signal line 122 on the base substrate 11 overlaps the orthographic projection of the second signal line DT on the base substrate 11 at least in the first direction f1. As shown in FIG1c , the common signal lines 12 have a mesh structure.

[0127] For example, the common signal line 12 may be made of a metal material with high conductivity.

[0128] In some embodiments, as shown in FIG1d , a subpixel PX includes a stacked pixel electrode 31 and a common electrode 14. The common electrodes 14 of multiple subpixels PX are interconnected, and the pixel electrodes 31 of different subpixels PX are spaced apart from each other. The pixel electrode 31 is connected to the second connection portion S through a via hole, and the common electrode 14 is connected to the common signal line 12. The pixel electrode 31 is located on a side of the common signal line 12 and the common electrode 14 that is closer to the base substrate 11, and is located on a side of the first signal line SC and the second signal line DT that is away from the base substrate 11.

[0129] In some embodiments, as shown in FIG. 1 d , the common signal line 12 may be stacked between the pixel electrode 31 and the common electrode 14 (as shown in FIG. 1 d ), or the common electrode 14 may be stacked between the pixel electrode 31 and the common signal line 12 .

[0130] The present disclosure provides a display substrate, as shown in FIG2 and FIG4, comprising a base substrate 11, and a plurality of first signal lines SC extending along a first direction f1 and a plurality of second signal lines DT extending along a second direction f2, arranged on one side of the base substrate 11. The plurality of first signal lines SC and the plurality of second signal lines DT are arranged in different layers, and the orthographic projections of the plurality of first signal lines SC on the base substrate 11 intersect with the orthographic projections of the plurality of second signal lines DT on the substrate and define a plurality of sub-pixels PX. The base substrate 11 comprises a display area AA and a non-display area NA surrounding the display area AA. (As shown in Figure 1a), the sub-pixel PX is located in the display area AA; each sub-pixel PX includes at least one transistor, the transistor includes an active layer 21 / 22, the active layer 21 / 22 includes a channel portion CH and a first connection portion D and a second connection portion S connected on both sides of the channel portion CH; the channel portion CH and the orthographic projection of the first signal line SC on the base substrate 11 have a first overlapping area OLA; within the first overlapping area OLA, the channel portion CH and the orthographic projection of the second signal line DT on the base substrate 11 overlap, and the first direction f1 and the second direction f2 intersect with each other.

[0131] 3 and 7 illustrate schematic cross-sectional structures of two display areas AA provided by the present disclosure. As shown in FIG3 or FIG7 , the transistors connecting two adjacent sub-pixels PX are located in different planes, i.e., the distances between the transistors connecting two adjacent sub-pixels PX and the substrate 11 are unequal.

[0132] Exemplarily, as shown in FIG3 or FIG7 , the transistor active layers 21 / 22 connecting two adjacent sub-pixels PX are located in different planes, that is, the distances between the transistor active layers 21 / 22 connecting two adjacent sub-pixels PX and the base substrate 11 are not equal.

[0133] The first connection portion D is, for example, a first pole, and the second connection portion S is, for example, a second pole.

[0134] In the present disclosure, an example is given in which the first signal line SC is a gate line and the second signal line DT is a data line.

[0135] In some embodiments, the transistors of the odd-numbered sub-pixels PX are first transistors T1, and the transistors of the even-numbered sub-pixels PX are second transistors T2. The first transistors T1 and the second transistors T2 are located in different planes. As shown in FIG3 or FIG7 , the active layer of the first transistor T1 is a first active layer 21, and the active layer of the second transistor T2 is a second active layer 22. The first active layer 21 and the second active layer 22 are arranged in different layers. Specifically, multiple first active layers 21 are arranged in the same layer, and multiple second active layers 22 are arranged in the same layer.

[0136] By arranging the active layers 21 / 22 of adjacent rows of transistors in different layers, that is, adopting a double-layer design for the first active layer 21 and the second active layer 22, the design space of the first active layer 21 and the second active layer 22 in the second direction f2 can be increased, thereby increasing the length of the first active layer 21 and the second active layer 22 in the second direction f2, thereby facilitating the increase of the channel length of the first transistor T1 and the second transistor T2, and increasing the distance between the source-drain vias and the channel portion CH. Furthermore, this can prevent the spacing between the active layers 21 / 22 arranged in the same layer from exceeding equipment and process limitations.

[0137] In some embodiments, as shown in Figure e in Figure 4 or Figure c in Figure 8, in the orthographic projection on the base substrate 11, the pattern obtained by translating the first active layer 21 along the second direction f2 is mirror-symmetrical to the second active layer 22, and the axis of symmetry extends along the second direction f2.

[0138] For example, as shown in FIG. 4 e or FIG. 8 c , the first active layer 21 and the second active layer 22 have the same size and shape, thereby improving display uniformity.

[0139] In some embodiments, as shown in FIG2 , a ratio of a dimension 21L of the first active layer 21 along the second direction f2 to an arrangement period PXL of the sub-pixels PX along the second direction f2 is greater than or equal to 1 and less than or equal to 2. That is, the dimension 21L of the first active layer 21 along the second direction f2 is greater than or equal to the arrangement period PXL of the sub-pixels PX along the second direction f2, and less than or equal to twice the arrangement period PXL of the sub-pixels PX along the second direction f2.

[0140] In some embodiments, as shown in FIG2 , a ratio of a dimension 22L of the second active layer 22 along the second direction f2 to the arrangement period PXL of the sub-pixels PX along the second direction f2 is greater than or equal to 1 and less than or equal to 2. That is, the dimension 22L of the second active layer 22 along the second direction f2 is greater than or equal to the arrangement period PXL of the sub-pixels PX along the second direction f2, and less than or equal to twice the arrangement period PXL of the sub-pixels PX along the second direction f2.

[0141] In some embodiments, as shown in FIG. 2 , along the first direction f1 , the width of the first connection portion D is wd1 , the width of the second signal line DT is wd2 , and 0≤|wd1−wd2|≤1 μm.

[0142] In some embodiments, as shown in FIG2 , the first connecting portion D and the second connecting portion S both extend along the second direction f2, the channel portion CH extends along the third direction f3, and the angle between the third direction f3 and the first direction f1 is greater than or equal to 15° and less than or equal to 60°. For example, the angle between the third direction f3 and the first direction f1 is 30° or 45°.

[0143] In some embodiments, as shown in FIG. 2 , a plurality of first active layers 21 are arranged in an array along a first direction f1 and a second direction f2 , and a plurality of second active layers 22 are arranged in an array along the first direction f1 and the second direction f2 .

[0144] In some embodiments, as shown in FIG. 2 , in the first direction f1, the arrangement period 21P1 of the first active layer 21 is approximately equal to the arrangement period PXW of the sub-pixels PX; in the second direction f2, the arrangement period 21P2 of the first active layer 21 is approximately equal to twice the arrangement period PXL of the sub-pixels PX.

[0145] That is, the arrangement period 21P1 of the first active layer 21 in the first direction f1 is substantially equal to the arrangement period PXW of the sub-pixels PX in the first direction f1, and the arrangement period 21P2 of the first active layer 21 in the second direction f2 is substantially equal to twice the arrangement period PXL of the sub-pixels PX in the second direction f2.

[0146] In some embodiments, as shown in FIG. 2 , in the first direction f1, the arrangement period 22P1 of the second active layer 22 is approximately equal to the arrangement period PXW of the sub-pixels PX; in the second direction f2, the arrangement period 22P2 of the second active layer 22 is approximately equal to twice the arrangement period PXL of the sub-pixels PX.

[0147] That is, the arrangement period 22P1 of the second active layer 22 in the first direction f1 is substantially equal to the arrangement period PXW of the sub-pixels PX in the first direction f1, and the arrangement period 22P2 of the second active layer 22 in the second direction f2 is substantially equal to twice the arrangement period PXL of the sub-pixels PX in the second direction f2.

[0148] In some embodiments, as shown in FIG. 2 , the orthographic projection of the first active layer 21 on the base substrate 11 overlaps with the orthographic projection of the second active layer 22 on the base substrate 11 .

[0149] In some embodiments, as shown in FIG3 , within the first overlapping area OLA, the channel portion CH of the first active layer 21 of the sub-pixel PX in the 2n+1th row overlaps with the orthographic projection of the first connection portion D of the second active layer 22 of the sub-pixel PX in the 2n+2th row on the base substrate 11, and the channel portion CH of the second active layer 22 of the sub-pixel PX in the 2n+2th row overlaps with the orthographic projection of the first connection portion D of the first active layer 21 of the sub-pixel PX in the 2n+3th row on the base substrate 11. Here, n is a positive integer greater than or equal to 0.

[0150] That is, the first active layer 21 and the second active layer 22 are designed to be interlaced with each other, which can further increase the channel length and the distance between the source and drain vias and the channel while saving space.

[0151] In some embodiments, as shown in FIG3 or FIG7 , the gate of the first transistor T1 is a first gate G1, and the gate of the second transistor T2 is a second gate G2. The first signal line SC includes a first sub-signal line SC1 connected to the first gate G1, and a second sub-signal line SC2 connected to the second gate G2. The second signal line DT includes a third sub-signal line DT1 connected to the first connection portion D of the first active layer 21 via a first via HD1; and a fourth sub-signal line DT2 connected to the first connection portion D of the second active layer 22 via a second via HD2. In an orthographic projection on the base substrate 11, the first sub-signal line SC1 at least partially covers the second via HD2, and the second sub-signal line SC2 at least partially covers the first via HD1.

[0152] For example, when the third signal sub-line DT1 and the fourth signal sub-line DT2 are provided in different layers, the solution provided in this embodiment can be implemented.

[0153] In this embodiment, as shown in FIG. 4 , the first via hole HD1 is located at the intersection of the third sub-signal line DT1 and the second sub-signal line SC2 , and the second via hole HD2 is located at the intersection of the fourth sub-signal line DT2 and the first sub-signal line SC1 .

[0154] In this embodiment, as shown in FIG. 5 a , in the orthographic projection on the base substrate 11 , the first sub-signal line SC1 completely covers the second via hole HD2 , and the second sub-signal line SC2 completely covers the first via hole HD1 .

[0155] In some embodiments, as shown in Figure 1c or Figure 5a, the display substrate further includes: a common signal line 12, which is arranged on the side of the first signal line SC and the second signal line DT away from the base substrate 11, including a first common signal line 121 and a second common signal line 122 arranged crosswise, the first common signal line 121 extends along the first direction f1, and the second common signal line 122 extends along the second direction f2; the orthographic projection of the first common signal line 121 on the base substrate 11 covers the orthographic projection of the first signal line SC on the base substrate 11 at least in the second direction f2, and the orthographic projection of the second common signal line 122 on the base substrate 11 covers the orthographic projection of the second signal line DT on the base substrate 11 at least in the first direction f1; the width of at least a portion of the first common signal line 121 in the second direction f2 is greater than the width of the second common signal line 122 in the first direction f1.

[0156] Since the width of the first common signal line 121 in the second direction f2 is greater than the width of the second common signal line 122 in the first direction f1, the first common signal line 121 can better block the first via hole HD1 and the second via hole HD2, improve light leakage at the first via hole HD1 and the second via hole HD2, and do not affect the aperture ratio, which is beneficial to reducing power consumption and improving the brightness and contrast of the display substrate.

[0157] Exemplarily, as shown in FIG5a, in the orthographic projection on the base substrate 11, the first sub-signal line SC1 completely covers the second via HD2, and in the second direction f2, the boundary of the first sub-signal line SC1 expands outward by a distance A1 relative to the boundary of the second via HD2, and in the second direction f2, the boundary of the first common signal line 121 further expands outward relative to the boundary of the first sub-signal line SC1, and the first common signal line 121 has a shielding effect on the second via HD2.

[0158] Exemplarily, as shown in FIG5a, in the orthographic projection on the base substrate 11, the second sub-signal line SC2 completely covers the first via HD1, and in the second direction f2, the boundary of the second sub-signal line SC2 extends outward by a distance A1 relative to the boundary of the first via HD1, and in the second direction f2, the boundary of the first common signal line 121 further extends outward relative to the boundary of the second sub-signal line SC2, and the second sub-signal line SC2 and the first common signal line 121 have a double shielding effect on the first via HD1.

[0159] Exemplarily, the size of the first sub-signal line SC1 in the second direction f2 is greater than or equal to 1.2 microns and less than or equal to 2 microns, the size of the second sub-signal line SC2 in the second direction f2 is greater than or equal to 1.2 microns and less than or equal to 2 microns, and the width of the first common signal line 121 in the second direction f2 is, for example, 2.4 microns.

[0160] As shown in FIG. 1 c , the common signal line 12 has a mesh structure.

[0161] For example, the common signal line 12 may be made of a metal material with high conductivity.

[0162] In some embodiments, as shown in FIG1d , a subpixel PX includes a stacked pixel electrode 31 and a common electrode 14. The common electrodes 14 of multiple subpixels PX are interconnected, and the pixel electrodes 31 of different subpixels PX are spaced apart from each other. The pixel electrode 31 is connected to the second connection portion S through a via hole, and the common electrode 14 is connected to the common signal line 12. The pixel electrode 31 is located on a side of the common signal line 12 and the common electrode 14 that is closer to the base substrate 11, and is located on a side of the first signal line SC and the second signal line DT that is away from the base substrate 11.

[0163] In some embodiments, as shown in FIG. 1 d , the common signal line 12 may be stacked between the pixel electrode 31 and the common electrode 14 (as shown in FIG. 1 d ), or the common electrode 14 may be stacked between the pixel electrode 31 and the common signal line 12 .

[0164] In some embodiments, as shown in FIG3 or FIG7 , the gate of the first transistor T1 is a first gate G1, and the gate of the second transistor T2 is a second gate G2. The second signal line DT includes a third sub-signal line DT1 connected to the first active layer 21, and a fourth sub-signal line DT2 connected to the second active layer 22. The first gate G1 and the second gate G2 are disposed in different layers, and / or the third sub-signal line DT1 and the fourth sub-signal line DT2 are disposed in different layers.

[0165] In some embodiments, as shown in FIG. 4 , the second signal line DT includes an extension segment S1 / S3 extending along the first direction f1 . In the first overlapping area OLA, the extension segment S1 / S3 extending along the first direction f1 overlaps with the orthographic projection of the channel portion CH on the base substrate 11 .

[0166] Exemplarily, as shown in Figure 4, the second signal line DT includes a first extension segment S1, a second extension segment S2 and a third extension segment S3, the second extension segment S2 extends along the second direction f2 and is connected between the first extension segment S1 and the third extension segment S3, the first extension segment S1 and the third extension segment S3 both extend along the first direction f1 and are located on the same side of the second extension segment S2; and in the first overlapping area OLA, the channel portion CH of the first active layer 21 overlaps with the orthographic projection of the first extension segment S1 on the base substrate 11, and the channel portion CH of the second active layer 22 overlaps with the orthographic projection of the third extension segment S3 on the base substrate 11.

[0167] As shown in Figure 4, in the first overlapping area OLA, the channel portion CH of the first active layer 21 and the orthographic projection of the portion of the first extension segment S1 close to the second extension segment S2 on the base substrate 11 overlap, and the channel portion CH of the second active layer 22 and the orthographic projection of the portion of the third extension segment S3 away from the second extension segment S2 on the base substrate 11 overlap.

[0168] In some embodiments, as shown in Figure 5b, the width of the first signal line SC in the second direction f2 is smaller than the width of the channel portion CH in the second direction f2; the display area AA also includes: a plurality of transparent traces 51 extending along the first direction f1, the transparent traces 51 are connected to the first signal line SC, and are located between the first signal line SC and the active layer 21 / 22, the orthographic projection of the transparent trace 51 on the base substrate 11 covers the orthographic projection of the first signal line SC on the base substrate 11 at least in the second direction f2, and the orthographic projection of the transparent trace 51 on the base substrate 11 covers the orthographic projection of the channel portion CH on the base substrate 11; and in the second direction f2, the width of the transparent trace 51 is greater than the width of the first signal line SC, and the width of the transparent trace 51 is approximately equal to the width of the channel portion CH.

[0169] Exemplarily, the transparent trace 51 is made of a transparent conductive material, such as a metal oxide, for example, ITO, IZO, IGZO, IGO, ZTO, etc. Transparent conductive materials have a higher transmittance to visible light than metal materials.

[0170] Exemplarily, as shown in FIG11 , the plurality of sub-pixels PX located in the same pixel unit P include a red sub-pixel PXR, a green sub-pixel PXG, and a blue sub-pixel PXB.

[0171] In some embodiments, as shown in FIG5c , the display substrate further includes: a plurality of light-shielding traces 19 extending along a first direction f1, located on a side of the active layer 21 / 22 close to the base substrate 11, wherein the orthographic projections of the light-shielding traces 19 on the base substrate 11 overlap the orthographic projections of the first signal lines SC on the base substrate 11 at least in the second direction f2. The light-shielding traces 19 at at least two locations have different widths in the second direction f2.

[0172] By providing the light shielding wiring 19 , the aperture ratio of the sub-pixels PX can be adjusted, and the aperture ratio ratio relationship between the sub-pixels PX of different colors can be adjusted, thereby optimizing the display effect.

[0173] For example, as shown in Figure b in Figure 5c, the width of the light-shielding line 19 at the corresponding positions of the red sub-pixel PXR and the green sub-pixel PXG in the second direction f2 is the same, and the width is smaller than the width of the light-shielding line 19 at the corresponding position of the blue sub-pixel PXB in the second direction f2.

[0174] For example, as shown in Figure c in Figure 5c, the widths of the light-shielding traces 19 at the corresponding positions of the red sub-pixel PXR, the green sub-pixel PXG, and the blue sub-pixel PXB in the second direction f2 are different. For example, the width of the light-shielding trace 19 at the corresponding position of the blue sub-pixel PXB in the second direction f2 is greater than the width of the light-shielding trace 19 at the corresponding position of the red sub-pixel PXR in the second direction f2, and the width of the light-shielding trace 19 at the corresponding position of the red sub-pixel PXR in the second direction f2 is greater than the width of the light-shielding trace 19 at the corresponding position of the green sub-pixel PXG in the second direction f2.

[0175] For example, as shown in Figure a of FIG5c , the widths of the light-shielding traces 19 at different positions in the second direction f2 may also be the same, which is not limited in the present disclosure.

[0176] When the active layer 21 / 22 is made of a material with high light stability and high mobility (such as one or more materials of rare earth doped oxide (Ln-OS)), the light shielding wiring 19 can be eliminated, thereby further improving the pixel aperture ratio.

[0177] In specific implementations, the first gate G1 , the second gate G2 , the first active layer 21 , the second active layer 22 , the third sub-signal line DT1 and the fourth sub-signal line DT2 may be stacked in a variety of ways, which are exemplarily described below.

[0178] In a first example, as shown in FIG3 , the first gate G1 and the second gate G2 are disposed in different layers, and the third sub-signal line DT1 and the fourth sub-signal line DT2 are disposed in different layers.

[0179] As shown in Figure 3, the first gate G1 and the first active layer 21 are located on the side of the third sub-signal line DT1 close to the base substrate 11, the second gate G2 and the second active layer 22 are located on the side of the third sub-signal line DT1 away from the base substrate 11, and the fourth sub-signal line DT2 is located on the side of the second gate G2 and the second active layer 22 away from the base substrate 11.

[0180] As shown in FIG3 , the first active layer 21, the first gate G1, the third sub-signal line DT1, the second active layer 22, the second gate G2, and the fourth sub-signal line DT2 are stacked in sequence, with the first active layer 21 being disposed close to the base substrate 11. Furthermore, a plurality of pixel electrodes 31, corresponding to different sub-pixels PX, are disposed on a side of the fourth sub-signal line DT2 that faces away from the base substrate 11.

[0181] As shown in Figure 3 , the third sub-signal line DT1 is connected to the first active layer 21 via the first via hole HD1. The pixel electrode 31 in the odd-row sub-pixel PXO is connected to the first active layer 21 via the third via hole HP, completing the construction and connection of the first transistor T1. The third sub-signal line DT1 transmits the data signal through the first via hole HD1 to the first active layer 21, and then through the third via hole HP to the pixel electrode 31, thereby charging the odd-row sub-pixels PXO. The charging path of the odd-row sub-pixels PXO is shown in Figure k of Figure 4 .

[0182] As shown in Figure 3 , the fourth sub-signal line DT2 is connected to the second active layer 22 via the second via hole HD2. The pixel electrode 31 in the even-numbered sub-pixels PXE is connected to the second active layer 22 via the third via hole HP, completing the construction and connection of the second transistor T2. The fourth sub-signal line DT2 transmits the data signal to the second active layer 22 via the second via hole HD2, and then to the pixel electrode 31 via the third via hole HP, thereby charging the even-numbered sub-pixels PXE. The charging path of the even-numbered sub-pixels PXE is shown in Figure k of Figure 4 .

[0183] The display substrate provided in this example can be formed by, for example, 10 mask processes, as shown in FIG4 , which are, in order, the first active layer 21 (as shown in FIG4 a) → the first gate G1 (as shown in FIG4 b) → the first via HD1 (as shown in FIG4 c) → the third sub-signal line DT1 (as shown in FIG4 d) → the second active layer 22 (as shown in FIG4 e) → the second gate G2 (as shown in FIG4 f) → the second via HD2 (as shown in FIG4 g) → the fourth sub-signal line DT2 (as shown in FIG4 h) → the third via HP (as shown in FIG4 i) → the pixel electrode 31 (as shown in FIG4 k).

[0184] In order to reduce the number of mask steps, in the second example, as shown in FIG7 , the first gate G1 and the second gate G2 are provided in different layers, and the third sub-signal line DT1 and the fourth sub-signal line DT2 are provided in the same layer.

[0185] As shown in FIG7 , the second gate G2 and the second active layer 22 are located on a side of the first gate G1 and the first active layer 21 away from the base substrate 11 , and the third sub-signal line DT1 and the fourth sub-signal line DT2 are located on a side of the second gate G2 and the second active layer 22 away from the base substrate 11 .

[0186] As shown in Figure 7, the first active layer 21, the first gate G1, the second active layer 22, the second gate G2, and the second signal line DT are stacked in sequence, with the first active layer 21 positioned close to the base substrate 11. The second signal line DT includes a third sub-signal line DT1 and a fourth sub-signal line DT2. Furthermore, multiple pixel electrodes 31, corresponding to different sub-pixels PX, are disposed on the side of the second signal line DT facing away from the base substrate 11.

[0187] As shown in Figure 7, the third sub-signal line DT1 is connected to the first active layer 21 via the first via hole HD1, and the pixel electrode 31 in the odd-numbered sub-pixel PXO is connected to the first active layer 21 via the third via hole HP. This completes the construction and connection of the first transistor T1, thereby enabling electrical transmission in the odd-numbered sub-pixel PXO. The fourth sub-signal line DT2 is connected to the second active layer 22 via the second via hole HD2, and the pixel electrode 31 in the even-numbered sub-pixel PXE is connected to the second active layer 22 via the third via hole HP. This completes the construction and connection of the second transistor T2, thereby enabling electrical transmission in the even-numbered sub-pixel PXE.

[0188] The display substrate provided in this example can be formed using eight mask processes, as shown in FIG8 , which are, in order: first active layer 21 (as shown in FIG8 a) → first gate G1 (as shown in FIG8 b) → second active layer 22 (as shown in FIG8 c) → second gate G2 (as shown in FIG8 d) → first via HD1 and second via HD2 (as shown in FIG8 e) → third sub-signal line DT1 and fourth sub-signal line DT2 (as shown in FIG8 f) → third via HP (as shown in FIG8 g) → pixel electrode 31. Compared with the first example, the display substrate provided in this example can save two mask processes, simplifying the process steps.

[0189] In the first example, the second transistor T2 is disposed on a side of the first transistor T1 facing away from the substrate 11. The second transistor T2 and the first transistor T1 do not share a common film layer. This maximizes the design space for the first transistor T1 and the second transistor T2 in the second direction f2, which is beneficial for increasing the PPI of the display substrate. The maximum PPI achievable in the first example is greater than that achievable in the second example.

[0190] In some embodiments, as shown in FIG4 or FIG8 , the orthographic projection of the third sub-signal line DT1 on the base substrate 11 overlaps or completely overlaps with the orthographic projection of the fourth sub-signal line DT2 on the base substrate 11. This helps to increase the aperture ratio, thereby reducing power consumption and improving display brightness and contrast.

[0191] For example, as shown in FIG. 4 or FIG. 8 , the third sub-signal line DT1 and the fourth sub-signal line DT2 are both designed as zigzag lines to satisfy the Delta arrangement of the sub-pixels PX.

[0192] In some embodiments, as shown in Figure 4 or Figure 8, the first signal line SC includes: a first sub-signal line SC1 connected to the first gate G1, and a second sub-signal line SC2 connected to the second gate G2; in the orthographic projection on the base substrate 11, the first sub-signal line SC1 and the second sub-signal line SC2 are alternately arranged at equal intervals along the second direction f2.

[0193] As shown in FIG. 4 or FIG. 8 , the first gate G1 is a portion where the first sub-signal line SC1 overlaps with the first active layer 21 , and the second gate G2 is a portion where the second sub-signal line SC2 overlaps with the second active layer 22 .

[0194] Exemplarily, the arrangement period of the first sub-signal line SC1 along the second direction f2 is approximately equal to twice the arrangement period of the sub-pixel PX along the second direction f2, the arrangement period of the second sub-signal line SC2 along the second direction f2 is approximately equal to twice the arrangement period of the sub-pixel PX along the second direction f2, and the spacing between the first sub-signal line SC1 and the second sub-signal line SC2 is approximately equal to the arrangement period PXL of the sub-pixel PX along the second direction f2.

[0195] In some embodiments, as shown in FIG6 , the subpixel PX further includes a pixel electrode 31. The pixel electrode 31 is connected to the second connection portion S via a third via hole HP, and the second signal line DT is connected to the first connection portion D via a fourth via hole. The fourth via hole includes a first via hole HD1 and a second via hole HD2. The distances between the first and second via holes HD1 and HD2 and the channel portion CH are both a first distance A2, and the distance between the third via hole HP and the channel portion CH is a second distance A3. The first distance A2 is greater than or equal to the second distance A3.

[0196] Exemplarily, as shown in FIG. 4 or FIG. 8 , the third via hole HP is located in the opening region of the sub-pixel PX.

[0197] Exemplarily, the first distance A2 is greater than or equal to 0.5 micrometers and less than or equal to 6 micrometers, and the second distance A3 is greater than or equal to 0.5 micrometers and less than or equal to 2 micrometers.

[0198] Figure 12 shows the characteristics of two groups of transistors, one with A2 = A3 = 0.65-0.8 μm and the other with A2 = A3 = 2 μm. Comparing the test results, it can be seen that by setting larger first distance A2 and second distance A3, the threshold voltage Vth of the transistors can be prevented from being negatively biased, thus avoiding the short channel effect.

[0199] In some embodiments, the first via hole HD1, the second via hole HD2, and the third via hole HP are all via holes HD1 / HD2 / HP. As shown in FIG4 or FIG8 , in an orthographic projection on the base substrate 11, in a first direction f1, the boundary of the active layer 21 / 22 extends outward from the boundary of the via hole HD1 / HD2 / HP by a third distance (such as b3 / b7 / b9 in FIG4 or FIG8 ), and in a second direction f2, the boundary of the active layer 21 / 22 near the via hole HD1 / HD2 / HP extends outward from the boundary of the via hole HD1 / HD2 / HP by a fourth distance (such as c3 / c7 / c9 in FIG4 or FIG8 ), and the third distance is greater than or equal to the fourth distance.

[0200] For example, the third distance is greater than or equal to 0 microns and less than or equal to 0.5 microns. The fourth distance is greater than or equal to 0 microns and less than or equal to 0.5 microns. In this way, the active layer 21 / 22 can fully cover and wrap the vias HD1 / HD2 / HP, maximizing the contact area and avoiding half-hole overlap. This can reduce the contact resistance of the vias HD1 / HD2 / HP, improving display uniformity and yield.

[0201] Exemplarily, the fourth distance is greater than or equal to -0.25 micrometers and less than or equal to 0.5 micrometers. The fourth distance is -x micrometers, which means that the boundary of the active layer 21 / 22 near the via hole HD1 / HD2 / HP in the second direction f2 is indented by x micrometers relative to the boundary of the via hole HD1 / HD2 / HP.

[0202] By setting the boundaries of the active layer 21 / 22 close to the via hole HD1 / HD2 / HP in the second direction f2 to be retracted relative to the boundaries of the via hole HD1 / HD2 / HP, it is beneficial to reduce the arrangement period of the active layer 21 / 22 in the second direction f2, thereby further improving the PPI of the display substrate.

[0203] In some embodiments, the sizes of the first via hole HD1 and the second via hole HD2 are greater than or equal to 1.2 micrometers and less than or equal to 2 micrometers, and the size of the third via hole HP is greater than or equal to 1.2 micrometers and less than or equal to 2 micrometers.

[0204] In some embodiments, as shown in FIG. 10 and FIG. 11 a and b, the second signal line DT includes a third sub-signal line DT1 connected to the first active layer 21, and a fourth sub-signal line DT2 connected to the second active layer 22. The third sub-signal line DT1 and the fourth sub-signal line DT2 are disposed in different layers and are connected to different signal input terminals. The gate of the first transistor T1 is a first gate G1, and the gate of the second transistor T2 is a second gate G2. The first signal line SC includes a first sub-signal line SC1 connected to the first gate G1, and a second sub-signal line SC2 connected to the second gate G2.

[0205] As shown in Figures a and b of Figure 10 , the non-display area NA includes a gate driving circuit 100 including a plurality of shift registers GOA connected in cascade, wherein different first signal lines SC are connected to different shift registers GOA in the same gate driving circuit 100 .

[0206] In order to increase the design space of each shift register GOA in the second direction f2, illustratively, as shown in Figure a of Figure 10, the gate drive circuit 100 is divided into a first sub-circuit 100L1 and a second sub-circuit 100R1. The first sub-circuit 100L1 and the second sub-circuit 100R1 are located on opposite sides of the display area AA (the left and right sides as shown in Figure a of Figure 10). Among them, the shift register GOA connected to the first signal line SC of the odd row is located in the first sub-circuit 100L1, and the shift register GOA connected to the first signal line SC of the even row is located in the second sub-circuit 100R1. In this way, the space occupied by each shift register GOA in the second direction f2 is the arrangement period of two sub-pixels PX in the second direction f2. In this example, the first signal line SC is driven unilaterally, that is, each first signal line SC is connected to a shift register GOA located on its side.

[0207] In order to increase the design space of each shift register GOA in the second direction f2, illustratively, as shown in Figure b in Figure 10, the first signal line SC is driven on both sides, that is, each first signal line SC is connected to two shift registers GOA located on both sides thereof. In addition, at least two (two as shown in Figure b in Figure 10) shift registers GOA connected to different first signal lines SC are located in the same row. By arranging at least two columns of shift registers GOA in parallel, the space occupied by each shift register GOA in the second direction f2 is the arrangement period of at least two sub-pixels PX in the second direction f2. However, placing multiple columns of shift registers GOA in parallel will increase the size of the non-display area NA in the first direction f1, that is, the border width.

[0208] In the embodiments shown in Figures a and b of Figure 10 , illustratively, the third sub-signal line DT1 and the fourth sub-signal line DT2 are arranged on the same layer, or the third sub-signal line DT1 and the fourth sub-signal line DT2 are arranged on different layers and connected to the same signal input terminal. This can reduce the number of source driver chips. The source driver chips are used to provide data signals to the third sub-signal line DT1 and the fourth sub-signal line DT2.

[0209] In order to connect the third sub-signal line DT1 and the fourth sub-signal line DT2 disposed in different layers to the same signal input terminal, for example, the third sub-signal line DT1 and the fourth sub-signal line DT2 may be connected through a via hole in the non-display area NA.

[0210] For example, as shown in FIG. 10 c , different scan signals with different timings may be provided to different first signal lines SC, such as a scan signal gate1 and a scan signal gate2 .

[0211] In some embodiments, as shown in Figures a and b of Figure 11 , the non-display area NA includes a gate driver circuit 100 including a plurality of cascaded shift registers GOA. Two adjacent first signal lines SC are connected to the same shift register GOA, i.e., an adjacent first sub-signal line SC1 and a second sub-signal line SC2 are connected to the same shift register GOA.

[0212] In this embodiment, the third sub-signal line DT1 and the fourth sub-signal line DT2 are arranged in different layers and connected to different signal input terminals. For example, the third sub-signal line DT1 can be used to charge the sub-pixels PXO in odd rows, while the fourth sub-signal line DT2 can be used to charge the sub-pixels PXE in even rows. By connecting two adjacent first signal lines SC to the same shift register GOA, the scanning signals on the two adjacent first signal lines SC have the same timing, thereby charging the sub-pixels PXO in odd rows and the sub-pixels PXE in even rows simultaneously.

[0213] As shown in Figure 11(a), since two adjacent first signal lines SC are connected to the same shift register GOA, the number of shift registers GOA can be halved, increasing the design space of each shift register GOA in the second direction f2. This allows each shift register GOA to occupy the same space as the arrangement period of two sub-pixels PX in the second direction f2. This eliminates the need to place multiple shift registers GOA in parallel in the first direction f1, which helps reduce the border width. For example, the border width can be compressed from 2mm to 1.2mm. In Figure 11(a), the first signal lines SC are driven bilaterally, i.e., each first signal line SC is connected to two shift registers GOA located on either side of it.

[0214] Furthermore, as shown in FIG11(b), the gate drive circuit 100 is divided into a third sub-circuit 100L2 and a fourth sub-circuit 100R2. The third sub-circuit 100L2 and the fourth sub-circuit 100R2 are located on opposite sides of the display area AA (the left and right sides shown in FIG11(a). The shift register GOA connected to the first signal lines SC of odd rows is located in the third sub-circuit 100L2, while the shift register GOA connected to the first signal lines SC of even rows is located in the fourth sub-circuit 100R2. In this way, the first signal lines SC are driven unilaterally, i.e., each first signal line SC is connected to a shift register GOA located on one side of it. This further reduces the number of shift registers GOA by half, so that the space occupied by each shift register GOA in the second direction f2 is the same as the arrangement period of four sub-pixels PX in the second direction f2. This eliminates the need to place multiple shift registers GOA in parallel in the first direction f1, which helps further reduce the border width.

[0215] Exemplarily, as shown in FIG. 11 c, the timing of the scan signals (such as gate1 and gate2) on the first signal lines SC of adjacent odd and even rows is the same, so that the odd-row sub-pixels PXO and the even-row sub-pixels PXE are charged simultaneously.

[0216] In some embodiments, as shown in FIG11 , a plurality of sub-pixels PX are divided into a plurality of pixel units P, and the arrangement of the plurality of sub-pixels PX within the same pixel unit P may be a Delta arrangement (as shown in FIG1 , FIG2 , FIG4 , FIG8 , FIG10 , and FIG11 ), a Real arrangement, or a Pentile arrangement, etc.

[0217] In specific implementation, adopting the Delta arrangement helps to further improve the pixel aperture ratio and can also solve the pixel crosstalk and light leakage problems caused by the small arrangement period of the sub-pixels PX in the first direction f1 in the Real arrangement.

[0218] For example, the orthographic projection shape of the sub-pixel PX on the substrate 11 may include polygons such as rectangles and hexagons, and may also include circles, ellipses, sectors, and stars. The orthographic projection shape of the sub-pixel PX on the substrate 11 may be regular or irregular.

[0219] Exemplarily, the material of the first active layer 21 and the second active layer 22 may include at least one of the following: amorphous silicon, low-temperature polycrystalline silicon, and a metal oxide semiconductor material. The metal oxide semiconductor material may include one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), and rare earth doped oxide (Ln-OS). The material of the active layer 21 / 22 may be amorphous, partially crystalline, single crystal, or polycrystalline, and may also be a single layer or multilayer structure.

[0220] When the first active layer 21 and the second active layer 22 are made of low-temperature polysilicon, in order to reduce leakage current, the pixel circuit of each sub-pixel PX may include two transistors, which may result in a reduction in aperture ratio.

[0221] When the materials of the first active layer 21 and the second active layer 22 are metal oxides such as indium gallium zinc oxide, the pixel circuit of each sub-pixel PX may include one transistor, which is beneficial to improving the aperture ratio.

[0222] Figures 13 to 15 show some characteristic values ​​of the first, second, and third display substrates in the first example, respectively. Figure 16 shows the value ranges of some characteristic values ​​of the high-PPI display substrate in the first example. Figure 17 shows some characteristic values ​​of a display substrate in the second example, and Figure 18 shows the value ranges of some characteristic values ​​of the high-PPI display substrate in the second example.

[0223] During specific implementation, the characteristic value may be adjusted according to the size of the sub-pixel PX, the PPI, and the arrangement of the sub-pixels PX, etc., which is not limited in the present disclosure.

[0224] As shown in Figure 4 or Figure 8, a1 represents the width of the first active layer 21, b1 represents the length of the first connection portion D in the first active layer 21, c1 represents the length of the oblique channel in the first active layer 21, d1 represents the length of the second connection portion S in the first active layer 21, e1 is the spacing between adjacent first active layers 21, a2 represents the width of the first sub-signal line SC1, that is, the channel length L of the first transistor T1, b2 represents the same-layer spacing of the first sub-signal line SC1, that is, the spacing between two adjacent first sub-signal lines SC1, a3 represents the size of the first via HD1, the first via HD1 is located at the edge of the first connection portion D of the first active layer 21 away from the channel portion CH, b3 represents the third distance corresponding to the first via HD1, c3 represents the fourth distance corresponding to the first via HD1, a4 represents the width of the third sub-signal line DT1 at the non-bending position, b4 represents the width of the third sub-signal line DT1 at the bending position, and c4 represents the distance between the two bending positions in the third sub-signal line DT1.

[0225] As shown in Figure 4 or Figure 8, a5 represents the width of the second active layer 22, b5 represents the length of the first connection portion D in the second active layer 22, c5 represents the length of the oblique channel in the second active layer 22, d5 represents the length of the second connection portion S in the second active layer 22, e5 is the spacing between adjacent second active layers 22, a6 represents the width of the second sub-signal line SC2, that is, the channel length L of the second transistor T2, b6 represents the same-layer spacing of the second sub-signal line SC2, that is, the spacing between two adjacent second sub-signal lines SC2, a7 represents the size of the second via HD2, the second via HD2 is located at the edge of the first connection portion D of the second active layer 22 away from the channel portion CH, b7 represents the third distance corresponding to the second via HD2, c7 represents the fourth distance corresponding to the second via HD2, a8 represents the width of the fourth sub-signal line DT2 at the non-bending position, b8 represents the width of the fourth sub-signal line DT2 at the bending position, and c8 represents the distance between the two bending positions in the fourth sub-signal line DT2.

[0226] As shown in Figure 4 or Figure 8, a9 represents the size of the third via hole HP, and the third via hole HP is located at the edge of one end of the second connecting portion S away from the channel portion CH, b9 represents the third distance corresponding to the third via hole HP, c9 represents the fourth distance corresponding to the third via hole HP, b10 represents the size of the flat layer sleeve hole HT9 located outside the third via hole HP (as shown in Figure j in Figure 4), b10 represents the distance between the inner wall of the flat layer sleeve hole HT and the third via hole HP in the first direction f1, and c10 represents the distance between the inner wall of the flat layer sleeve hole HT and the third via hole HP in the second direction f2.

[0227] As shown in Figure 5a, A1 represents the distance between the boundary of the first sub-signal line SC1 and the boundary of the second via HD2 in the second direction f2, and the distance between the boundary of the second sub-signal line SC2 and the boundary of the first via HD1 in the second direction f2. As shown in Figure 6, A2 represents the distance between the first and second vias HD1 and HD2 and the channel portion CH, i.e., the first distance. A3 represents the distance between the third via HP and the channel portion CH, i.e., the second distance.

[0228] Exemplarily, the channel width w of the transistor 1 / T2 is greater than or equal to 1.5 micrometers and less than or equal to 2 micrometers, such as 1.8 micrometers.

[0229] As shown in FIG. 13 to FIG. 15 , the first distance A2 is greater than 4 μm, and the second distance A3 is greater than or equal to 1.2 μm, which can greatly reduce the impact of via-hole etching on the channel portion CH.

[0230] 10 , a dimension v1 of the sub-pixel PX in the first direction f1 is greater than or equal to 5 micrometers and less than or equal to 8 micrometers, such as 6 micrometers. A dimension h1 of the sub-pixel PX in the second direction f2 is greater than or equal to 6 micrometers and less than or equal to 10 micrometers, such as 8 micrometers, 7 micrometers, and 6 micrometers.

[0231] For example, the PPI can be further increased by compressing the size of the sub-pixel PX in the second direction f2. Specifically, the size of the sub-pixel PX in the second direction f2 can be compressed by compressing one or more characteristic values ​​such as the size of the first connection portion D and the second connection portion S in the second direction f2, the inter-layer spacing between the active layers 21 / 22, the fourth distance, the first distance A2, and the second distance A3.

[0232] It has been verified that in the first example, the aperture ratio of the second display substrate is greater than the aperture ratios of the first display substrate and the third display substrate.

[0233] Exemplarily, as shown in FIG13 , in the first display substrate, the third distances b3, b7 and b9 are all equal to 0.25 microns, and the fourth distances c3, c7 and c9 are all equal to 0.25 microns, that is, the active layer 21 / 22 fully wraps the first via hole HD1, the second via hole HD2 and the third via hole HP.

[0234] Exemplarily, as shown in FIG14 , in the second display substrate, the third distances b3, b7, and b9 are all equal to 0.25 microns, and the fourth distances c3, c7, and c9 are all equal to 0 microns, that is, the active layer 21 / 22 wraps the first via hole HD1, the second via hole HD2, and the third via hole HP in the first direction f1, and in the second direction f2, the boundaries of the active layer 21 / 22 near the first via hole HD1 and the second via hole HD2 are roughly aligned with the boundaries of the first via hole HD1 and the second via hole HD2, and the boundaries of the active layer 21 / 22 near the third via hole HP are roughly aligned with the boundary of the third via hole HP.

[0235] For example, as shown in FIG15 , in the third display substrate, the third distances b3, b7, and b9 are all equal to 0.25 microns, and the fourth distances c3, c7, and c9 are all equal to -0.25 microns, that is, the active layer 21 / 22 wraps the first via hole HD1, the second via hole HD2, and the third via hole HP in the first direction f1, and the boundaries of the active layer 21 / 22 close to the first via hole HD1 and the second via hole HD2 are indented by 0.25 microns relative to the boundaries of the first via hole HD1 and the second via hole HD2 in the second direction f2, and the boundaries of the active layer 21 / 22 close to the third via hole HP are indented by 0.25 microns relative to the boundaries of the third via hole HP, that is, in the second direction f2, the active layer 21 / 22 and the first via hole HD1, the second via hole HD2, and the third via hole HP are semi-overlappingly designed.

[0236] For example, in the first display substrate, the channel length a2 / L of the transistor 1 / T2 may be, for example, 3 micrometers. In the second display substrate, the channel length a2 / L may be, for example, 2.5 micrometers. In the third display substrate, the channel length a2 / L may be less than or equal to 2 micrometers.

[0237] For example, in the first display substrate, the size of the first via hole HD1, the second via hole HD2, and the third via hole HP is, for example, 1.8 microns; in the second display substrate, the size of the first via hole HD1, the second via hole HD2, and the third via hole HP is, for example, 1.8 microns; and in the third display substrate, the size of the first via hole HD1, the second via hole HD2, and the third via hole HP is, for example, less than or equal to 1.5 microns.

[0238] The present disclosure provides a display device, as shown in FIG19 , which includes: a display substrate 191 as provided in any embodiment; and a source driving circuit 192 connected to the display substrate 191 for driving the display substrate for display.

[0239] Those skilled in the art will appreciate that the display device provided by the present disclosure has the advantages of the above-mentioned display substrate.

[0240] Exemplarily, as shown in FIG19 , the source driving circuit is a source driving chip IC, and the source driving chip IC and the display substrate 191 may be connected via a flexible circuit board FPC.

[0241] The display device provided by the present disclosure can be: a high PPI (such as greater than 1500PPI) display panel, display module, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, car display device, smart watch, fitness wristband, personal digital assistant, and any other product or component with display function; it can also be used in virtual display devices XR such as AR / VR / MR, as shown in Figure 20.

[0242] The display panel may be a liquid crystal display panel or a self-luminous display panel. The self-luminous display panel has a built-in light-emitting device, such as an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a sub-millimeter light-emitting diode (Mini LED), or a micro light-emitting diode (Micro LED). In a self-luminous display panel, the display substrate provided in the present disclosure may be a driving backplane for the light-emitting device.

[0243] FIG21 shows a schematic cross-sectional structure of an OLED display panel. As shown in FIG21 , the display substrate 191 can serve as the driving backplane for the organic light-emitting diodes LD in the OLED display panel. As shown in FIG21 , the driving transistors TC located in adjacent sub-pixels PX are arranged as first and second transistors T1 and T2, respectively, in separate layers. The organic light-emitting diode LD includes an anode 21, a light-emitting layer 22, and a cathode 23. The anode 21 is positioned near the display substrate 191 and is connected to the driving transistor TC in the display substrate 191. The driving transistor TC is used to drive the organic light-emitting diode LD to emit light.

[0244] In an OLED display panel, the two transistors disposed in different layers can be different types of transistors within a sub-pixel PX, or can be the same type of transistors within two adjacent sub-pixels PX. The driving circuit of each sub-pixel PX may include multiple types of transistors, such as a drive transistor TC, a reset transistor, and a switch transistor.

[0245] For example, the two transistors disposed in different layers may be a driving transistor TC and a switching transistor located in one sub-pixel PX. The two transistors disposed in different layers may also be a reset transistor and a switching transistor located in one sub-pixel PX. The two transistors disposed in different layers may also be a reset transistor and a driving transistor TC located in one sub-pixel PX.

[0246] For example, the two transistors disposed in different layers may be driving transistors TC located in different sub-pixels PX, reset transistors located in different sub-pixels PX, or switching transistors located in different sub-pixels PX.

[0247] In the present disclosure, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0248] In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on the present disclosure.

[0249] In this disclosure, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus that includes the element.

[0250] References in this disclosure to "one embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "an example," "an example," "some examples," and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0251] In this disclosure, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0252] When describing some embodiments, the expressions "coupled" and "connected" may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this disclosure.

[0253] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0254] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0255] As used in this disclosure, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0256] The use of "for" or "configured to" in this disclosure is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0257] The use of "based on" or "according to" in this disclosure is intended to be open and inclusive. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values.

[0258] As used in this disclosure, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0259] As used in this disclosure, "parallel", "perpendicular", "equal", and "flush" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two being equal is less than or equal to 5% of either one. "Flush" includes absolute flushness and approximate flushness, wherein the acceptable deviation range of approximate flushness can be, for example, the distance between the two being flush is less than or equal to 5% of either one's size.

[0260] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0261] The present disclosure describes exemplary embodiments with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown in this disclosure, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0262] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A display substrate, comprising a substrate substrate, and a plurality of first signal lines extending along a first direction and a plurality of second signal lines extending along a second direction provided on one side of the substrate substrate. The plurality of first signal lines and the plurality of second signal lines are arranged in different layers, and the orthographic projections of the plurality of first signal lines on the substrate substrate intersect with the orthographic projections of the plurality of second signal lines on the substrate and define a plurality of sub-pixels; the substrate substrate includes a display area and a non-display area surrounding the display area, and the sub-pixels are located in the display area; each sub-pixel includes at least one transistor, and the transistor includes an active layer, and the active layer includes a channel portion and a first connection portion and a second connection portion connected to both sides of the channel portion; there is a first overlapping area between the channel portion and the orthographic projection of the first signal line on the substrate substrate; within the first overlapping area, there is an overlap between the channel portion and the orthographic projection of the second signal line on the substrate substrate, and the first direction and the second direction intersect with each other.

2. The display substrate according to claim 1, wherein, One end of the first connection portion of the active layer away from the channel portion is a first end portion, and one end of the second connection portion of the active layer away from the channel portion is a second end portion. Along a direction parallel to the second direction, the distance between the first end portion and the second end portion is greater than the arrangement period of the sub-pixels along the second direction.

3. The display substrate according to claim 2, wherein, The first connection portion is connected to the second signal line, at least a part of the first connection portion overlaps with the orthographic projection of the connected second signal line on the substrate substrate, and the extending direction of at least a part of the first connection portion is parallel to the extending direction of the second signal line.

4. The display substrate according to claim 3, wherein, Along the first direction, the width of the first connection portion is wd1, and the width of the second signal line is wd2, 0≤|wd1 - wd2|≤1μm.

5. The display substrate according to any one of claims 1 to 4, wherein, Both the first connection portion and the second connection portion extend along the second direction, the channel portion extends along a third direction, and the included angle between the third direction and the first direction is greater than or equal to 15° and less than or equal to 60°.

6. The display substrate according to any one of claims 1 to 5, wherein The transistors of the odd-numbered row sub-pixels are first transistors, and the transistors of the even-numbered row sub-pixels are second transistors. The active layer of the first transistor is a first active layer, and the active layer of the second transistor is a second active layer. The first active layer and the second active layer are in the same layer and are arranged separately from each other; The first direction is perpendicular to a first plane. In the orthographic projection on the first plane, the second connection portion of the first active layer overlaps with the first connection portion of the second active layer, and the second connection portion of the second active layer overlaps with the first connection portion of the first active layer.

7. The display substrate according to claim 6, wherein, The pattern obtained by translating the first active layer along the second direction is mirror-symmetric with the second active layer.

8. The display substrate according to claim 6 or 7, wherein The second signal line includes a first extension segment, a second extension segment, and a third extension segment. The second extension segment extends along the second direction and is connected between the first extension segment and the third extension segment. Both the first extension segment and the third extension segment extend along the first direction and are located on the same side of the second extension segment; and Within the first overlapping region, a channel portion of the first active layer overlaps a positive projection of the first extension section on the substrate, and a channel portion of the second active layer overlaps a positive projection of the third extension section on the substrate.

9. The display substrate according to any one of claims 1 to 8, wherein The display substrate further includes: Common signal lines disposed on a side of the first signal lines and the second signal lines away from the substrate. The common signal lines include first common signal lines and second common signal lines that are cross - arranged. The first common signal lines extend along the first direction, and the second common signal lines extend along the second direction; A positive projection of the first common signal lines on the substrate covers a positive projection of the first signal lines on the substrate at least in the second direction, and a positive projection of the second common signal lines on the substrate covers a positive projection of the second signal lines on the substrate at least in the first direction.

10. The display substrate according to claim 9, wherein, The sub - pixels include a pixel electrode and a common electrode that are stacked. Common electrodes of multiple sub - pixels are connected to each other, and pixel electrodes of different sub - pixels are separately arranged. The pixel electrode is connected to the second connection portion, and the common electrode is connected to the common signal lines; Wherein, the pixel electrode is located on a side of the common signal lines and the common electrode close to the substrate, and on a side of the first signal lines and the second signal lines away from the substrate.

11. The display substrate according to claim 10, wherein, The common signal lines are stacked between the pixel electrode and the common electrode, or the common electrode is stacked between the pixel electrode and the common signal lines.

12. A display substrate includes a substrate, and a plurality of first signal lines extending along a first direction and a plurality of second signal lines extending along a second direction disposed on one side of the substrate. The plurality of first signal lines and the plurality of second signal lines are disposed in different layers, and positive projections of the plurality of first signal lines on the substrate intersect positive projections of the plurality of second signal lines on the substrate and define a plurality of sub - pixels; the substrate includes a display area and a non - display area surrounding the display area, and the sub - pixels are located in the display area; each sub - pixel includes at least one transistor, and the transistor includes an active layer. The active layer includes a channel portion and first and second connection portions connected to both sides of the channel portion; there is a first overlapping region between the channel portion and a positive projection of the first signal lines on the substrate; within the first overlapping region, the channel portion overlaps a positive projection of the second signal lines on the substrate, and the first direction and the second direction intersect each other; Among them, Transistors connecting adjacent two sub - pixels are located in different planes.

13. The display substrate according to claim 12, wherein, Transistors of sub - pixels in odd rows are first transistors, and transistors of sub - pixels in even rows are second transistors. The first transistors and the second transistors are located in different planes; The active layer of the first transistor is a first active layer, and the active layer of the second transistor is a second active layer. The first active layer and the second active layer are disposed in different layers.

14. The display substrate according to claim 13, wherein, In the orthographic projection on the substrate, the pattern obtained by translating the first active layer along the second direction is mirror-symmetrical to the second active layer.

15. The display substrate according to claim 13 or 14, wherein, The ratio of the dimension of the first active layer along the second direction to the arrangement period of the sub-pixels along the second direction is greater than or equal to 1 and less than or equal to 2; The ratio of the dimension of the second active layer along the second direction to the arrangement period of the sub-pixels along the second direction is greater than or equal to 1 and less than or equal to 2.

16. The display substrate according to any one of claims 13 to 15, wherein, In the first overlapping region, the channel portion of the first active layer and the first connection portion of the second active layer overlap in the orthographic projection on the substrate, and the channel portion of the second active layer and the first connection portion of the first active layer overlap in the orthographic projection on the substrate.

17. The display substrate according to any one of claims 13 to 16, wherein, The gate of the first transistor is the first gate, and the gate of the second transistor is the second gate; The first signal line includes: a first sub-signal line connected to the first gate, and a second sub-signal line connected to the second gate; The second signal line includes: a third sub-signal line connected to the first connection portion of the first active layer through a first via; and a fourth sub-signal line connected to the first connection portion of the second active layer through a second via; In the orthographic projection on the substrate, at least a part of the first sub-signal line covers the second via, and at least a part of the second sub-signal line covers the first via.

18. The display substrate according to claim 17, wherein, The display substrate further includes: a common signal line disposed on a side of the first signal line and the second signal line away from the substrate, including a first common signal line and a second common signal line that are cross-set, the first common signal line extends along the first direction, and the second common signal line extends along the second direction; The orthographic projection of the first common signal line on the substrate covers at least the orthographic projection of the first signal line on the substrate in the second direction, and the orthographic projection of the second common signal line on the substrate covers at least the orthographic projection of the second signal line on the substrate in the first direction; At least a part of the first common signal line has a width greater than the width of the second common signal line in the first direction in the second direction.

19. The display substrate according to any one of claims 13 to 18, wherein, The gate of the first transistor is the first gate, and the gate of the second transistor is the second gate; The second signal line includes: a third sub-signal line connected to the first active layer, and a fourth sub-signal line connected to the second active layer; and The first gate and the second gate are disposed in different layers, and / or, the third sub-signal line and the fourth sub-signal line are disposed in different layers.

20. The display substrate according to claim 19, wherein The orthographic projection of the third sub-signal line on the substrate overlaps with the orthographic projection of the fourth sub-signal line on the substrate.

21. The display substrate according to claim 19 or 20, wherein The first signal line includes: a first sub-signal line connected to the first gate, and a second sub-signal line connected to the second gate; In the orthographic projection on the substrate, the first sub-signal line and the second sub-signal line are alternately arranged at equal intervals along the second direction.

22. The display substrate according to any one of claims 19 to 21, wherein, The first gate and the second gate are arranged in different layers, and the third sub-signal line and the fourth sub-signal line are arranged in different layers; and The first gate and the first active layer are located on one side of the third sub-signal line close to the substrate, the second gate and the second active layer are located on the side of the third sub-signal line away from the substrate, and the fourth sub-signal line is located on the side of the second gate and the second active layer away from the substrate.

23. The display substrate according to any one of claims 19 to 21, wherein, The first gate and the second gate are arranged in different layers, and the third sub-signal line and the fourth sub-signal line are arranged in the same layer; and The second gate and the second active layer are located on the side of the first gate and the first active layer away from the substrate, and the third sub-signal line and the fourth sub-signal line are located on the side of the second gate and the second active layer away from the substrate.

24. The display substrate according to any one of claims 13 to 23, wherein, A plurality of the first active layers are arranged in an array along the first direction and the second direction, and a plurality of the second active layers are arranged in an array along the first direction and the second direction; In the first direction, the arrangement period of the first active layer and the arrangement period of the second active layer are approximately equal to the arrangement period of the sub-pixels; In the second direction, the arrangement period of the first active layer and the arrangement period of the second active layer are approximately equal to twice the arrangement period of the sub-pixels.

25. The display substrate according to any one of claims 13 to 24, wherein, The second signal line includes: a third sub-signal line connected to the first active layer and a fourth sub-signal line connected to the second active layer. The third sub-signal line and the fourth sub-signal line are arranged in different layers and are connected to different signal input terminals; The gate of the first transistor is the first gate, the gate of the second transistor is the second gate, and the first signal line includes: a first sub-signal line connected to the first gate and a second sub-signal line connected to the second gate; The non-display area includes: a gate driving circuit including a plurality of cascaded shift registers; Among them, adjacent first sub-signal line and the second sub-signal line are connected to the same shift register.

26. The display substrate according to any one of claims 13 to 24, wherein The second signal line includes: a third sub-signal line connected to the first active layer and a fourth sub-signal line connected to the second active layer, wherein the third sub-signal line and the fourth sub-signal line are arranged in different layers and are connected to the same signal input terminal, or the third sub-signal line and the fourth sub-signal line are arranged in the same layer; The non-display area includes: a gate driving circuit including a plurality of cascaded shift registers; Among them, different first signal lines are connected to different shift registers, and at least two shift registers connected to different first signal lines are located in the same row.

27. The display substrate according to any one of claims 12 to 26, wherein The second signal line includes an extension section extending along the first direction. In the first overlapping area, the extension section extending along the first direction overlaps with the positive projection of the channel portion on the substrate.

28. The display substrate according to any one of claims 12 to 27, wherein, The width of the first signal line in the second direction is smaller than the width of the channel portion in the second direction; The display area further includes: a plurality of transparent traces extending along the first direction, the transparent traces being connected to the first signal line and located between the first signal line and the active layer, a positive projection of the transparent traces on the substrate at least covers a positive projection of the first signal line on the substrate in the second direction, and the positive projection of the transparent traces on the substrate covers a positive projection of the channel portion on the substrate; and In the second direction, a width of the transparent trace is greater than a width of the first signal line, and the width of the transparent trace is substantially equal to a width of the channel portion.

29. The display substrate according to any one of claims 12 to 28, wherein The display substrate further includes: a plurality of light-shielding traces extending along the first direction, located on a side of the active layer close to the substrate, and a positive projection of the light-shielding traces on the substrate at least covers a positive projection of the first signal line on the substrate in the second direction; wherein, widths of the light-shielding traces at at least two positions are different in the second direction.

30. The display substrate according to any one of claims 12 to 29, wherein, The sub-pixel further includes a pixel electrode, the pixel electrode is connected to the second connection portion through a third via, and the second signal line is connected to the first connection portion through a fourth via; wherein, a distance between the fourth via and the channel portion is a first distance, a distance between the third via and the channel portion is a second distance, and the first distance is greater than or equal to the second distance.

31. A display device, comprising: the display substrate according to any one of claims 1 to 30; and a source driver circuit, connected to the display substrate and configured to drive the display substrate to display.

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