Comparator circuit and combined comparator circuit

Abstract

Provided is a comparator circuit, comprising: a power supply voltage end; a reference voltage end; a first branch electrically connected between the power supply voltage end and the reference voltage end, the first branch comprising a first N-type transistor and a first P-type transistor, the first N-type transistor comprising a gate configured to receive a first input voltage, a drain electrically connected to the power supply voltage end, and a source electrically connected to a first node, and the first P-type transistor comprising a gate configured to receive a second input voltage, a drain electrically connected to the reference voltage end, and a source electrically connected to the first node; a second branch connected in parallel with the first branch between the power supply voltage end and the reference voltage end, and providing a comparison current; and a current mirror circuit electrically connected between the first branch and the second branch, and configured to, on the basis of an input current on the first branch, generate a mirrored output current on the second branch.

Description

Comparator circuits and combination comparator circuits

[0001] The present invention claims priority to Chinese patent application number 202311769591.4 filed with the Patent Office of China on December 20, 2023, entitled “Comparator Circuit and Combined Comparator Circuit”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of integrated circuits, and in particular to a comparator circuit and a combined comparator circuit. Background Art

[0003] In low-power comparator applications, the comparator input often doesn't constantly toggle. Instead, it receives a signal with a very low toggle frequency (return-to-zero code), and in most cases, the input differential is zero. Currently, many low-power scenarios (such as idle mode) often require the comparator's power consumption to be very low. However, the comparator's response speed is not fast enough, and even the comparator's power consumption is not low enough. Summary of the Invention

[0004] It would be advantageous to provide a mechanism that alleviates, mitigates, or even eliminates one or more of the above-mentioned problems.

[0005] According to one aspect of the present disclosure, a comparator circuit is provided, comprising: a power supply voltage terminal; a reference voltage terminal; a first branch electrically connected between the power supply voltage terminal and the reference voltage terminal, the first branch comprising a first N-type transistor and a first P-type transistor, the first N-type transistor comprising a gate configured to receive a first input voltage, a drain electrically connected to the power supply voltage terminal, and a source electrically connected to a first node, the first P-type transistor comprising a gate configured to receive a second input voltage, a drain electrically connected to the reference voltage terminal, and a source electrically connected to the first node; a second branch connected in parallel with the first branch between the power supply voltage terminal and the reference voltage terminal, the second branch providing a comparison current; and a current mirror circuit electrically connected between the first branch and the second branch, the current mirror circuit being configured to generate a mirrored output current on the second branch based on the input current on the first branch.

[0006] According to another aspect of the present disclosure, a combined comparator circuit is provided, comprising: a first comparator; and a second comparator, each of the first comparator and the second comparator comprising the comparator circuit as described above, wherein: the gate of the first P-type transistor of the first comparator and the gate of the first N-type transistor of the second comparator are configured to receive a third input voltage, the gate of the first N-type transistor of the first comparator and the gate of the first P-type transistor of the second comparator are configured to receive a fourth input voltage, and the first output voltage terminal of the first comparator and the first output voltage terminal of the second comparator constitute a differential output terminal.

[0007] According to yet another aspect of the present disclosure, a combined comparator circuit is provided, comprising: a first comparator; and a second comparator, each of the first comparator and the second comparator comprising the comparator circuit as described above, the combined comparator circuit further comprising: a second OR gate circuit comprising a third input terminal, a fourth input terminal and a second output terminal, wherein the third input terminal is used to receive a reset signal and the second output terminal is electrically connected to the reset circuit input terminal of the first comparator; a third OR gate circuit comprising a fifth input terminal, a sixth input terminal and a third output terminal, wherein the fifth input terminal is used to receive a reset signal and the third output terminal is electrically connected to the reset circuit input terminal of the second comparator; a third falling edge pulse trigger electrically connected between the second output voltage terminal and the sixth input terminal of the first comparator; and a fourth falling edge pulse trigger electrically connected between the second output voltage terminal and the fourth input terminal of the second comparator, wherein: the gate of the first P-type transistor of the first comparator and the gate of the first N-type transistor of the second comparator are configured to receive the fifth input voltage, the gate of the first N-type transistor of the first comparator and the gate of the first P-type transistor of the second comparator are configured to receive the sixth input voltage, and the first output voltage terminal of the first comparator and the first output voltage terminal of the second comparator constitute a differential output terminal.

[0008] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0010] FIG1 is a schematic circuit diagram illustrating a comparator according to an exemplary embodiment of the present disclosure;

[0011] 2 is a schematic circuit diagram illustrating a comparator including a reset circuit according to an exemplary embodiment of the present disclosure;

[0012] 3 is a schematic circuit diagram illustrating a comparator including a current source limiting dynamic circuit according to an exemplary embodiment of the present disclosure;

[0013] FIG4 is a schematic circuit diagram illustrating a variation of a comparator according to an exemplary embodiment of the present disclosure;

[0014] 5 is a schematic circuit diagram illustrating a variation of a comparator including a reset circuit according to an exemplary embodiment of the present disclosure;

[0015] 6 is a schematic circuit diagram illustrating a variation of a comparator including a current source limiting a dynamic circuit according to an exemplary embodiment of the present disclosure;

[0016] FIG7 is a schematic circuit diagram illustrating a comparator including two output branches according to an embodiment of the present disclosure;

[0017] FIG8 is a schematic circuit diagram illustrating a comparator including a buffer according to an embodiment of the present disclosure;

[0018] FIG9 is a schematic output waveform diagram illustrating a comparator including a buffer according to an embodiment of the present disclosure;

[0019] FIG10 is a schematic circuit diagram illustrating a combined comparator according to another embodiment of the present disclosure;

[0020] FIG11 is a schematic circuit diagram illustrating a comparator with an additional current mirror circuit according to another embodiment of the present disclosure;

[0021] FIG12 is a schematic circuit diagram illustrating a combined comparator with an additional current mirror circuit according to another embodiment of the present disclosure;

[0022] FIG13 is a schematic circuit diagram illustrating a combined comparator according to yet another embodiment of the present disclosure; and

[0023] FIG. 14 is a schematic circuit diagram illustrating a combined comparator with a bias circuit according to yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] It will be understood that although the terms first, second, third, etc. may be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Therefore, the first element, component, area, layer or part discussed below may be referred to as the second element, component, area, layer or part without departing from the teachings of the present disclosure.

[0025] Spatially relative terms such as "below," "beneath," "lower," "beneath," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "below," "beneath," or "beneath" another element or feature would be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "beneath" can encompass both orientations of "above" and "beneath." Terms such as "before," "before," and "after," or "followed by" can similarly be used, for example, to indicate the order in which light passes through elements. The device may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0026] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" when used in this specification specify the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, wholes, steps, operations, elements, parts and / or their groups or add one or more other features, wholes, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" includes only A, only B, and both A and B.

[0027] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, directly connected to, directly coupled to, or directly adjacent to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “directly adjacent to” another element or layer, no intervening elements or layers are present. However, in no case should “on” or “directly on” be interpreted as requiring that one layer completely cover the underlying layer.

[0028] Embodiments of the present disclosure are described herein with reference to schematic illustrations of idealized embodiments of the present disclosure (and intermediate structures). As such, variations from the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of the regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. Accordingly, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of a device and are not intended to limit the scope of the present disclosure.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0030] Exemplary embodiments of the present disclosure are described in detail below and may be used to advantage for a number of reasons, such as to alleviate or mitigate these undesirable side effects.

[0031] FIG. 1 is a schematic circuit diagram illustrating a comparator 100 according to an exemplary embodiment of the present disclosure. Referring to FIG. 1, the comparator circuit 100 includes: a power supply voltage terminal VDD; a reference voltage terminal GND; a first branch electrically connected between the power supply voltage terminal VDD and the reference voltage terminal GND. The first branch includes a first N-type transistor NM1 and a first P-type transistor PM1. The first N-type transistor NM1 includes a gate configured to receive a first input voltage VP, a drain electrically connected to the power supply voltage terminal VDD, and a source electrically connected to a first node 110. The first P-type transistor PM1 includes a gate configured to receive a second input voltage VN, a drain electrically connected to the reference voltage terminal GND, and a source electrically connected to the first node 110; a second branch connected in parallel with the first branch between the power supply voltage terminal VDD and the reference voltage terminal GND, and the second branch provides a comparison current i1; and a current mirror circuit electrically connected between the first branch and the second branch. The current mirror circuit is configured to generate a mirrored output current id on the second branch based on an input current i0 on the first branch.

[0032] In an example, when the comparator circuit 100 is in a static state, VP = VN. Since VP - VN = 0V is less than the sum of the threshold voltages of NM1 and PM1, Vthp + Vthn, at this time i0 = id = 0A, and the voltage Vx at the second node 120 is at a high level, and the comparator hardly consumes power. When VP - VN > Vthp + Vthn, NM1 and PM1 are turned on, generating a current i0, and i0 = id > 0A. At this time, if id < i1, Vx is at a high level. When VP and VN are separated to a certain extent such that VP - VN > Vthp + Vthn and id > i1, Vx is at a low level, and the comparator realizes output inversion and consumes power.

[0033] Thus, the comparator circuit hardly consumes power in a static state (such as an idle state), and in the case of a low frequency of flip signals, it can achieve fast triggering and reduce energy consumption.

[0034] It should be understood that "NM1" and "PM1" in FIG. 1 may be MOS field effect transistors, but they are only an example of "the first N-type transistor" and "the first P-type transistor". In other embodiments, the first N-type transistor and the first P-type transistor may be other types of field effect transistors or transistors, such as junction field effect transistors, bipolar junction transistors, etc. The same applies to NM2 to NM6 and PM2 to PM6 hereinafter and will not be elaborated.

[0035] It should be understood that the "GND" ground terminal in FIG. 1 is only an example of the "reference voltage terminal". In some embodiments, the reference voltage terminal may be a voltage terminal configured to receive a ground voltage, a negative power supply voltage, or a certain fixed potential.

[0036] Continuing with reference to FIG1 , in the comparator circuit 100 , the current mirror circuit includes: a third N-type transistor NM3 , including a source electrically connected to the reference voltage terminal GND, a gate electrically connected to the drain of the first P-type transistor PM1 , and a drain electrically connected to the drain of the first P-type transistor PM1 ; and a fourth N-type transistor NM4 , including a source electrically connected to the reference voltage terminal GND, a gate electrically connected to the drain of the first P-type transistor PM1 , and a drain electrically connected to the second node 120 .

[0037] In some examples, the current mirror circuit can be a common N-type MOS transistor current mirror circuit structure as shown in Figure 1. In other examples, NM3 can also be replaced with a resistor, which can also achieve the function of generating a mirrored output current id on the second branch based on the input current i0 on the first branch.

[0038] In some embodiments, the comparator circuit 100 further includes a reset circuit, which is electrically connected to the first branch and the second branch and configured to reset the comparator circuit 100 .

[0039] FIG. 2 is a schematic circuit diagram illustrating a comparator 100 including a reset circuit according to an exemplary embodiment of the present disclosure. 2 , in the comparator circuit 100 , the second branch includes a first current source I1 to provide a comparison current i1 , and wherein the reset circuit includes: a reset circuit input terminal configured to receive a reset signal RST; a second P-type transistor PM2 including a source electrically connected to a power supply voltage terminal VDD, a gate electrically connected to the reset circuit input terminal, and a drain electrically connected to the drain of the first N-type transistor NM1; a second N-type transistor NM2 including a source electrically connected to a reference voltage terminal GND, a gate electrically connected to the reset circuit input terminal, and a drain electrically connected between the drain of the first P-type transistor PM1 and the current mirror circuit; a third P-type transistor PM3 including a source electrically connected to the power supply voltage terminal VDD and a drain electrically connected to a second node 120, wherein the second node 120 is located between the first current source I1 and the current mirror circuit; and a first inverter U1 including an input terminal electrically connected to the reset circuit input terminal and an output terminal electrically connected to the gate of the third P-type transistor PM3.

[0040] In the example, after the reset circuit input receives the reset signal RST (for example, a positive pulse or a high level), the gate voltage of PM2 is high and PM2 is cut off; the gate voltage of NM2 is high and the gate voltage of PM3 is low, NM2 and PM3 are turned on, i0=id=0A, and a large current i2 is generated at the drain of PM3, so that i2+i1>id, Vx is reset to a high level, and the comparator is reset.

[0041] In some examples, the first current source I1 may be a resistor. The second current source I2 and the third current source I3 described below may also be resistors.

[0042] FIG3 is a schematic circuit diagram illustrating a comparator 100 including a current source for limiting a dynamic circuit according to an exemplary embodiment of the present disclosure. Referring to FIG3 , the comparator circuit 100 further includes a second current source I2 electrically connected between the power supply voltage terminal VDD and the drain of the first N-type transistor NM1.

[0043] In an example, as shown in FIG3 , because the comparator circuit 100 includes a first reset circuit, the second current source I2 can be electrically connected between the power supply voltage terminal VDD and the source of the second P-type transistor PM2. The second current source I2 is used to limit the dynamic current of the first branch, thereby protecting devices NM1 and PM1 on the first branch.

[0044] In some examples, the second current source I2 can be replaced by a resistor.

[0045] FIG. 4 is a schematic circuit diagram illustrating a variation 200 of the comparator 100 according to an exemplary embodiment of the present disclosure. 4 , the comparator circuit 200 includes: a power supply voltage terminal VDD; a reference voltage terminal GND; a first branch electrically connected between the power supply voltage terminal VDD and the reference voltage terminal GND, the first branch including a first N-type transistor NM1 and a first P-type transistor PM1, the first N-type transistor NM1 including a gate configured to receive a first input voltage VP, a drain electrically connected to the power supply voltage terminal VDD, and a source electrically connected to a first node 110, the first P-type transistor PM1 including a gate configured to receive a second input voltage VN, a drain electrically connected to the reference voltage terminal GND, and a source electrically connected to the first node 110; a second branch connected in parallel with the first branch between the power supply voltage terminal VDD and the reference voltage terminal GND, the second branch providing a comparison current i1; and a current mirror circuit electrically connected between the first branch and the second branch, the current mirror circuit being configured to generate a mirrored output current id on the second branch based on the input current i0 on the first branch.

[0046] In the example, when the comparator circuit 200 is in a static state, VP = VN. Since VP - VN = 0V is less than the sum of the threshold voltages of NM1 and PM1, Vthp + Vthn, at this time, i0 = id = 0A < i1, the voltage Vx at the second node 120 is at a low level, and the comparator does not consume power. When VP - VN > Vthp + Vthn, NM1 and PM1 are turned on, generating a current i0, and i0 = id > 0A. At this time, if id < i1, Vx is at a low level. When VP and VN are separated to a certain extent such that VP - VN > Vthp + Vthn and id > i1, Vx is at a high level, the comparator realizes output inversion and consumes power.

[0047] Continuing to refer to FIG. 4, different from the comparator circuit 100, in the comparator circuit 200, the current mirror circuit includes: a fifth P-type transistor PM5, including a source electrically connected to the power supply voltage terminal VDD, a gate electrically connected to the drain of the first N-type transistor NM1, and a drain electrically connected to the drain of the first N-type transistor NM1; and a sixth P-type transistor PM6, including a source electrically connected to the power supply voltage terminal VDD, a gate electrically connected to the drain of the first N-type transistor NM1, and a drain electrically connected to the second node 120.

[0048] In some examples, the current mirror circuit can be a common P-type MOS transistor current mirror circuit structure as shown in FIG. 4. In other examples, PM5 can also be replaced with a resistor, and the function of generating a mirrored output current id on the second branch based on the input current i0 on the first branch can still be achieved.

[0049] FIG. 5 is a schematic circuit diagram illustrating a variant 200 of the comparator 100 including a reset circuit according to an exemplary embodiment of the present disclosure. Referring to FIG. 5, in the comparator circuit 200, the second branch includes a first current source Ix to provide a comparison current i1, and wherein the reset circuit includes: a reset circuit input terminal configured to receive a reset signal RST; a fifth N-type transistor NM5, including a source electrically connected to the reference voltage terminal GND and a drain electrically connected to the drain of the first P-type transistor PM1; a fourth P-type transistor PM4, including a source electrically connected to the power supply voltage terminal VDD and a drain electrically connected between the drain of the first N-type transistor NM1 and the current mirror circuit; a sixth N-type transistor NMx, including a source electrically connected to the reference voltage terminal GND and a drain electrically connected to the second node 120, the second node 120 being located between the first current source I1 and the current mirror circuit; a second inverter U2, including an input terminal electrically connected to the reset circuit input terminal and an output terminal electrically connected to the gate of the fifth N-type transistor NM5 and the gate of the fourth P-type transistor PM4; and a third inverter U3, including an input terminal electrically connected to the output terminal of the second inverter U2 and an output terminal electrically connected to the gate of the sixth N-type transistor NMx.

[0050] In this example, after the reset circuit input receives a reset signal RST (e.g., a positive pulse or a high level), it is driven low by the second inverter U2. This causes the gate voltage of NM5 to be low, turning NM5 off. The gate voltage of PM4 is also low, while the gate voltage of NM6 is high, turning PM4 and NM6 on. At this point, i0 = id = 0A, and a large current i2 is generated at the drain of NM6, causing i2 + i1 to exceed id. This resets Vx to a low level, resetting the comparator.

[0051] FIG6 is a schematic circuit diagram illustrating a variation 200 of comparator 100 including a current source for limiting a dynamic circuit according to an exemplary embodiment of the present disclosure. Referring to FIG6 , comparator circuit 200 further includes a third current source I3 connected between a reference voltage terminal GND and the drain of first P-type transistor PM1.

[0052] In an example, as shown in FIG6 , because the comparator circuit 200 includes a second reset circuit, a third current source I3 can be electrically connected between the reference voltage terminal GND and the source of the fifth N-type transistor NM5. The third current source I3 is used to limit the dynamic current of the first branch, thereby protecting devices NM1 and PM1 on the first branch.

[0053] In some examples, the third current source I3 can be replaced by a resistor.

[0054] FIG7 is a schematic circuit diagram illustrating a comparator 100 or 200 including two output branches according to an embodiment of the present disclosure. Referring to FIG7 , the comparator 100 or 200 including a reset circuit further includes: a first output branch comprising a first number of inverters connected in series (one inverter in the figure), the first output branch electrically connected between a second node 120 in the second branch and a first output voltage terminal Q, to output a first output voltage V1 at the first output voltage terminal Q; and a second output branch comprising a second number of inverters connected in series (two inverters in the figure), the second output branch electrically connected between the second node 120 and a second output voltage terminal QN, to output a second output voltage V2 at the second output voltage terminal QN, the second output voltage V2 being in opposite phase to the first output voltage V1.

[0055] It should be understood that although the "first number" is 1 and the "second number" is 2 in FIG7 , the "first number" and the "second number" can be any combination of numbers that results in the second output voltage V2 being in opposite phase to the first output voltage V1. In one embodiment, the "first number" or the "second number" can also be set to zero.

[0056] FIG. 8 is a schematic circuit diagram showing the comparator 100 or 200 including a buffer according to an embodiment of the present disclosure. Referring to FIG. 8, the comparator 100 or 200 including a reset circuit further includes a first OR gate circuit OR1, including a first input terminal, a second input terminal, and a first output terminal, the first input terminal being configured to receive a reset signal RST, and the first output terminal being electrically connected to the reset circuit input terminal of the comparator circuit; a first buffer Buffer1, electrically connected between the first output voltage terminal Q and the third output voltage terminal OUTP to output a third output voltage V3 at the third output voltage terminal OUTP; and a first falling-edge pulse trigger and a second falling-edge pulse trigger, connected in series between the second output voltage terminal QN and the second input terminal.

[0057] FIG. 9 is a schematic output waveform diagram showing the comparator 100 or 200 including a buffer according to an embodiment of the present disclosure. Referring to FIG. 9 and in combination with FIG. 8, when (V+)-(V-)>VTH (VTH is the threshold voltage such that id>i1 + i2), QN flips from high level to low level, and a reset signal with a width of t0 is generated after the time point t0 via the first falling-edge pulse trigger and the second falling-edge pulse trigger and fed to the second input terminal, causing QN to flip from low level to high level at the time point t0 and remain for t0; at the time point 2*t0, (V+)-(V-) is still greater than VTH, and QN flips from high level to low level again; until (V+)-(V-)<VTH, QN keeps flipping between high and low levels, and its waveform is shown as waveform X in FIG. 9. Q is always inverted with respect to QN. Therefore, waveform Z (not shown) is always inverted with respect to waveform X. After waveform Z passes through the first buffer Buffer1, due to the falling-edge delay of 2*t0 of the first buffer Buffer1, waveform Y remains at high level when X flips and does not flip to low level until 2*t0 after the flipping of X stops.

[0058] Thus, by the output of the comparator itself, a pulse reset is generated, which can respond to some pulses with a relatively narrow width when the power consumption is too low.

[0059] FIG. 10 is a schematic circuit diagram showing the combined comparator 300 according to another embodiment of the present disclosure. Referring to FIG. 10, the combined comparator circuit 300 includes a first comparator and a second comparator. Each of the first comparator and the second comparator includes a comparator circuit 100 or 200. The gate of the first P-type transistor of the first comparator and the gate of the first N-type transistor of the second comparator are configured to receive a third input voltage V-, the gate of the first N-type transistor of the first comparator and the gate of the first P-type transistor of the second comparator are configured to receive a fourth input voltage V+, and the first output voltage terminal of the first comparator and the first output voltage terminal of the second comparator form differential output terminals OUTP and OUTN.

[0060] In the example, when (V+)-(V-) > VTH, the output of OUTP is high and the output of OUTN is low. When (V+)-(V-) < -VTH, the output of OUTP is low and the output of OUTN is high. When -VTH < (V+)-(V-) < VTH, the output of OUTP is low and the output of OUTN is low. Thus, the differential outputs of OUTP and OUTN form a three-state comparator.

[0061] FIG. 11 is a schematic circuit diagram illustrating a comparator with an additional current mirror circuit according to another embodiment of the present disclosure. FIG. 12 is a schematic circuit diagram illustrating a combined comparator with an additional current mirror circuit according to another embodiment of the present disclosure. Referring to FIGS. 11 and 12, in the combined comparator circuit 300, the first comparator further includes a first additional current mirror circuit (as shown in FIG. 11), and the first additional current mirror circuit is configured to generate a mirrored first additional output current Iadd1 based on the input current i1 on the first branch of the first comparator. The first additional output current Iadd1 is fed between the current mirror circuit of the second comparator and the first current source in the second branch (Iin of comparator 2 in FIG. 12). The second comparator further includes a second additional current mirror circuit, and the second additional current mirror circuit is configured to generate a mirrored second additional output current Iadd2 based on the input current (not shown) on the first branch of the second comparator. The second additional output current Iadd2 is fed between the current mirror circuit of the first comparator and the first current source I1 in the second branch (Iin of comparator 1 in FIG. 12).

[0062] Thus, the first comparator and the second comparator can output by comparing the currents of their respective first branches.

[0063] FIG13 is a schematic circuit diagram illustrating a combination comparator 400 according to another embodiment of the present disclosure. Referring to FIG13 , the combination comparator circuit 400 includes a first comparator and a second comparator. Each of the first comparator and the second comparator includes a comparator circuit 100 or 200 having two output branches. The combination comparator circuit further includes: a second OR gate circuit OR2, including a third input terminal, a fourth input terminal, and a second output terminal, wherein the third input terminal is used to receive a reset signal RST, and the second output terminal is electrically connected to the reset circuit input terminal of the first comparator; a third OR gate circuit OR3, including a fifth input terminal, a sixth input terminal, and a third output terminal, wherein the fifth input terminal is used to receive a reset signal RST, and the third output terminal is electrically connected to the reset circuit input terminal of the second comparator; a third falling edge pulse trigger, electrically connected between the second output voltage terminal and the sixth input terminal of the first comparator; and a fourth falling edge pulse trigger, electrically connected between the second output voltage terminal and the fourth input terminal of the second comparator. The gate of the first P-type transistor of the first comparator and the gate of the first N-type transistor of the second comparator are configured to receive a fifth input voltage V-, the gate of the first N-type transistor of the first comparator and the gate of the first P-type transistor of the second comparator are configured to receive a sixth input voltage V+, and the first output voltage terminal OUTP of the first comparator and the first output voltage terminal OUTN of the second comparator constitute a differential output terminal.

[0064] The combined comparator shown in Figure 10 triggers quickly and resets slowly. For example, when (V+)-(V-)>VTH, comparator 1 can trigger quickly, while comparator 2 resets relatively slowly.

[0065] Referring again to Figure 13, when (V+)-(V-)>VTH, QN of comparator 1 outputs a falling edge, which generates a positive pulse fed to the sixth input terminal via the third falling edge pulse flip-flop, thereby quickly resetting comparator 2. Similarly, when (V+)-(V-)<-VTH, QN of comparator 2 outputs a falling edge, which generates a positive pulse fed to the fourth input terminal via the fourth falling edge pulse flip-flop, thereby quickly resetting comparator 1.

[0066] Thus, a pulse signal is generated by rapidly triggering one of the two comparators, which rapidly resets the other comparator.

[0067] FIG14 is a schematic circuit diagram illustrating a combined comparator with a bias circuit according to yet another embodiment of the present disclosure. Referring to FIG14 , the combined comparator circuit 400 further includes: a first bias circuit electrically connected to the gate of the first P-type transistor of the first comparator and the gate of the first N-type transistor of the second comparator; and a second bias circuit electrically connected to the gate of the first P-type transistor of the second comparator and the gate of the first N-type transistor of the first comparator.

[0068] In an example, as shown in Figure 14, a first bias circuit includes a capacitor, a resistor, and an input terminal for receiving a REF- voltage, and a second bias circuit includes a capacitor, a resistor, and an input terminal for receiving a REF+ voltage. By adjusting the REF+ and REF- voltages, a trigger threshold different from vthp + vthn can be achieved.

[0069] Although the present disclosure has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description are to be considered illustrative and exemplary and not restrictive; the present disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments will be understood and effected by those skilled in the art in practicing the claimed subject matter by studying the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps that are not listed, the indefinite article "a" or "an" does not exclude a plurality, the term "plurality" means two or more, and the term "based on" should be interpreted as "based at least in part on". The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A comparator circuit, comprising: Power supply voltage terminal; Reference voltage terminal; a first branch, electrically connected between the power supply voltage terminal and the reference voltage terminal, the first branch comprising a first N-type transistor and a first P-type transistor, the first N-type transistor comprising a gate configured to receive a first input voltage, a drain electrically connected to the power supply voltage terminal, and a source electrically connected to a first node, the first P-type transistor comprising a gate configured to receive a second input voltage, a drain electrically connected to the reference voltage terminal, and a source electrically connected to the first node; A second branch, connected in parallel with the first branch between the power supply voltage terminal and the reference voltage terminal, the second branch providing a comparison current; as well as A current mirror circuit is electrically connected between the first branch and the second branch, and is configured to generate a mirrored output current on the second branch based on an input current on the first branch.

2. The comparator circuit of claim 1, further comprising a reset circuit electrically connected to the first branch and the second branch and configured to reset the comparator circuit.

3. The comparator circuit as claimed in claim 2, wherein: The second branch includes a first current source to provide the comparison current, and Wherein, the reset circuit comprises: Reset circuit input terminal; a second P-type transistor including a source electrically connected to the power supply voltage terminal, a gate electrically connected to the reset circuit input terminal, and a drain electrically connected to the drain of the first N-type transistor; a second N-type transistor, comprising a source electrically connected to the reference voltage terminal, a gate electrically connected to the input terminal of the reset circuit, and a drain electrically connected to the drain of the first P-type transistor and between the current mirror circuit; a third P-type transistor including a source electrically connected to the power supply voltage terminal and a drain electrically connected to a second node, the second node being located between the first current source and the current mirror circuit; and The first inverter includes an input terminal electrically connected to the input terminal of the reset circuit and an output terminal electrically connected to the gate of the third P-type transistor.

4. The comparator circuit as claimed in claim 3, wherein: The current mirror circuit comprises: a third N-type transistor including a source electrically connected to the reference voltage terminal, a gate electrically connected to the drain of the first P-type transistor, and a drain electrically connected to the drain of the first P-type transistor; and The fourth N-type transistor includes a source electrically connected to the reference voltage terminal, a gate electrically connected to the drain of the first P-type transistor, and a drain electrically connected to the second node.

5. The comparator circuit of claim 4, further comprising: A second current source is electrically connected between the power supply voltage terminal and the drain of the first N-type transistor.

6. The comparator circuit as claimed in claim 2, wherein: The second branch includes a first current source to provide the comparison current, and Wherein, the reset circuit comprises: Reset circuit input terminal; a fifth N-type transistor, comprising a source electrically connected to the reference voltage terminal and a drain electrically connected to the drain of the first P-type transistor; a fourth P-type transistor, comprising a source electrically connected to the power supply voltage terminal and a drain electrically connected between the drain of the first N-type transistor and the current mirror circuit; a sixth N-type transistor, comprising a source electrically connected to the reference voltage terminal and a drain electrically connected to a second node, wherein the second node is located between the first current source and the current mirror circuit; a second inverter including an input terminal electrically connected to the input terminal of the reset circuit and an output terminal electrically connected to the gate of the fifth N-type transistor and the gate of the fourth P-type transistor; and The third inverter includes an input terminal electrically connected to the output terminal of the second inverter and an output terminal electrically connected to the gate of the sixth N-type transistor.

7. The comparator circuit of claim 6, wherein: The current mirror circuit comprises: a fifth P-type transistor including a source electrically connected to the power supply voltage terminal, a gate electrically connected to the drain of the first N-type transistor, and a drain electrically connected to the drain of the first N-type transistor; and A sixth P-type transistor includes a source electrically connected to the power supply voltage terminal, a gate electrically connected to the drain of the first N-type transistor, and a drain electrically connected to the second node.

8. The comparator circuit of claim 7, further comprising: A third current source is connected between the reference voltage terminal and the drain of the first P-type transistor.

9. The comparator circuit according to any one of claims 2 to 8, further comprising: A first output branch, comprising a first number of inverters connected in series, the first output branch being electrically connected between the second node in the second branch and a first output voltage terminal to output a first output voltage at the first output voltage terminal; as well as The second output branch includes a second number of inverters connected in series. The second output branch is electrically connected between the second node and a second output voltage terminal to output a second output voltage at the second output voltage terminal. The second output voltage is inversely proportional to the first output voltage.

10. The comparator circuit of claim 9, further comprising: A first OR gate circuit, comprising a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal is configured to receive a reset signal, and the first output terminal is electrically connected to a reset circuit input terminal of the comparator circuit; A first buffer is electrically connected between the first output voltage terminal and a third output voltage terminal to output a third output voltage at the third output voltage terminal; as well as The first falling edge pulse trigger and the second falling edge pulse trigger are connected in series between the second output voltage terminal and the second input terminal.

11. A combined comparator circuit, comprising: a first comparator; as well as A second comparator, each of the first comparator and the second comparator comprises a comparator circuit as claimed in any one of claims 1 to 8, wherein: The gate of the first P-type transistor of the first comparator and the gate of the first N-type transistor of the second comparator are configured to receive a third input voltage, A gate of the first N-type transistor of the first comparator and a gate of the first P-type transistor of the second comparator are configured to receive a fourth input voltage, and The first output voltage terminal of the first comparator and the first output voltage terminal of the second comparator form a differential output terminal.

12. The combined comparator circuit of claim 11, wherein: The first comparator further comprises a first additional current mirror circuit, the first additional current mirror circuit being configured to generate a mirrored first additional output current based on an input current on the first branch of the first comparator, the first additional output current being fed between the current mirror circuit of the second comparator and the first current source in the second branch, and The second comparator further includes a second additional current mirror circuit, which is configured to generate a mirrored second additional output current based on the input current on the first branch of the second comparator, and the second additional output current is fed between the current mirror circuit of the first comparator and the first current source in the second branch.

13. A combined comparator circuit, comprising: a first comparator; as well as a second comparator, each of the first comparator and the second comparator comprising the comparator circuit of claim 9, the combined comparator circuit further comprising: A second OR gate circuit comprises a third input terminal, a fourth input terminal and a second output terminal, wherein the third input terminal is used to receive a reset signal, and the second output terminal is electrically connected to the reset circuit input terminal of the first comparator; A third OR gate circuit comprises a fifth input terminal, a sixth input terminal and a third output terminal, wherein the fifth input terminal is used to receive a reset signal, and the third output terminal is electrically connected to the reset circuit input terminal of the second comparator; a third falling edge pulse trigger, electrically connected between the second output voltage terminal of the first comparator and the sixth input terminal; and A fourth falling edge pulse trigger is electrically connected between the second output voltage terminal of the second comparator and the fourth input terminal, wherein: A gate of the first P-type transistor of the first comparator and a gate of the first N-type transistor of the second comparator are configured to receive a fifth input voltage, A gate of the first N-type transistor of the first comparator and a gate of the first P-type transistor of the second comparator are configured to receive a sixth input voltage, and The first output voltage terminal of the first comparator and the first output voltage terminal of the second comparator form a differential output terminal.

14. The combined comparator circuit of claim 13, further comprising: a first bias circuit electrically connected to a gate of a first P-type transistor of the first comparator and a gate of a first N-type transistor of the second comparator; as well as The second bias circuit is electrically connected to a gate of the first P-type transistor of the second comparator and a gate of the first N-type transistor of the first comparator.

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