Hysteresis comparator

Abstract

The invention provides a hysteresis comparator, and belongs to the technical field of electronics. The hysteresis comparator comprises an open-loop operational amplifier circuit and a positive feedback circuit; the positive feedback circuit comprises a switching tube device and a current source, the switching tube device is electrically connected with the open-loop operational amplifier circuit and the current source, and the positive feedback circuit is used for forming an internal positive feedback path with the open-loop operational amplifier circuit when the switching tube device is switched on and adjusting hysteresis voltage through the current source. According to the invention, the hysteresis voltage can be regulated through the current source, so that the stability of the hysteresis voltage is ensured.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technologies, and particularly to a hysteresis comparator. Background Art

[0002] In recent years, the hysteresis comparator has become one of the most important components in analog integrated circuits. The hysteresis comparator can compare an input voltage with a defined reference voltage and output a high level or a low level, thereby converting the input analog signal into a binary digital signal.

[0003] The hysteresis function of the hysteresis comparator is generally realized through an external positive feedback circuit, that is, the high level or the low level output by the hysteresis comparator is fed back to the input voltage to realize the hysteresis function.

[0004] However, the value of the finally obtained hysteresis voltage is related to the power supply voltage VDD of the hysteresis comparator, and the power supply voltage VDD has a voltage range, which causes the hysteresis voltage to fluctuate with the change of the power supply voltage VDD, and further causes the output of the hysteresis voltage to be unstable. Summary of the Invention

[0005] The present disclosure provides a hysteresis comparator, which can solve the problems in the related art. The technical solution is as follows:

[0006] The present disclosure provides a hysteresis comparator, which includes an open-loop operational amplifier circuit and a positive feedback circuit;

[0007] The positive feedback circuit includes a switching device and a current source. The switching device is electrically connected to the open-loop operational amplifier circuit and the current source. The positive feedback circuit is used to form an internal positive feedback path with the open-loop operational amplifier circuit when the switching device is turned on, and adjust the hysteresis voltage through the current source.

[0008] In a possible implementation manner, the open-loop operational amplifier circuit includes a first current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor. Among them, the fifth PMOS transistor and the sixth PMOS transistor are a pair of current mirror transistors, the seventh PMOS transistor and the eighth PMOS transistor are a pair of current mirror transistors, and the ninth NMOS transistor and the tenth NMOS transistor are a pair of current mirror transistors;

[0009] The gate and drain of the first NMOS transistor, the gate of the second NMOS transistor are electrically connected to the first current source. The source of the second NMOS transistor, the source of the first NMOS transistor, the source of the ninth NMOS transistor, and the source of the tenth NMOS transistor are all grounded. The drain of the second NMOS transistor, the source of the third NMOS transistor and the source of the fourth NMOS transistor are electrically connected. The gate of the third NMOS transistor is electrically connected to the reference voltage terminal. The gate of the fourth NMOS transistor is electrically connected to the input voltage terminal. The gate and drain of the fifth PMOS transistor, the drain of the third NMOS transistor are electrically connected to the gate of the sixth PMOS transistor. The source of the fifth PMOS transistor, the source of the sixth PMOS transistor, the source of the seventh PMOS transistor, and the source of the eighth PMOS transistor are all electrically connected to the positive power supply terminal. The gate and drain of the ninth NMOS transistor, the drain of the sixth PMOS transistor are electrically connected to the gate of the tenth NMOS transistor. The gate and drain of the seventh PMOS transistor, the drain of the fourth NMOS transistor are electrically connected to the gate of the eighth PMOS transistor. The drain of the tenth NMOS transistor, the drain of the eighth PMOS transistor are both electrically connected to the output terminal of the hysteresis comparator.

[0010] In a possible implementation, when the voltage of the input voltage terminal is much smaller than the voltage of the reference voltage terminal, the voltage of the output terminal of the hysteresis comparator is at a low level.

[0011] In a possible implementation, when the voltage of the input voltage terminal is much larger than the voltage of the reference voltage terminal, the voltage of the output terminal of the hysteresis comparator is at a high level.

[0012] In a possible implementation, the positive feedback circuit includes a first inverter, a second inverter, a second current source, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a third current source, a fourteenth NMOS transistor, a fifteenth NMOS transistor, and a sixteenth NMOS transistor. Among them, the eleventh NMOS transistor and the twelfth NMOS transistor are a pair of current mirror transistors, and the fourteenth NMOS transistor and the fifteenth NMOS transistor are a pair of current mirror transistors;

[0013] The gate and drain of the eleventh NMOS transistor, the gate of the twelfth NMOS transistor are electrically connected to the second current source. The source of the eleventh NMOS transistor, the source of the twelfth NMOS transistor are both grounded. The drain of the twelfth NMOS transistor is electrically connected to the source of the thirteenth NMOS transistor. The drain of the thirteenth NMOS transistor is electrically connected to the drain of the fourth NMOS transistor;

[0014] The gate and drain of the fourteenth NMOS transistor and the gate of the fifteenth NMOS transistor are electrically connected to the third current source. The source of the fourteenth NMOS transistor and the source of the fifteenth NMOS transistor are both grounded. The drain of the fifteenth NMOS transistor is electrically connected to the source of the sixteenth NMOS transistor, and the drain of the sixteenth NMOS transistor is electrically connected to the drain of the third NMOS transistor;

[0015] The input terminal of the first inverter is electrically connected to the drain of the eighth PMOS transistor. The output terminal of the first inverter and the input terminal of the second inverter are electrically connected to the gate of the sixteenth NMOS transistor. The output terminal of the second inverter is electrically connected to the gate of the thirteenth NMOS transistor, and the output terminal of the second inverter is the output terminal of the hysteresis comparator.

[0016] In a possible implementation, when the voltage of the input voltage terminal is much smaller than the voltage of the reference voltage terminal, the voltage of the output terminal of the hysteresis comparator is at a low level, the output terminal of the first inverter is at a high level, and the sixteenth NMOS transistor is turned on;

[0017] When the voltage of the input voltage terminal rises to be greater than the voltage of the reference voltage terminal, if the difference between the voltage of the input voltage terminal and the voltage of the reference voltage terminal is less than the rising-edge hysteresis voltage, the sixteenth NMOS transistor remains turned on, and the voltage of the output terminal of the hysteresis comparator remains at a low level. If the difference between the voltage of the input voltage terminal and the voltage of the reference voltage terminal is greater than the rising-edge hysteresis voltage, the sixteenth NMOS transistor is turned off, the thirteenth NMOS transistor is turned on, and the voltage of the output terminal of the hysteresis comparator flips to a high level.

[0018] In a possible implementation, when the voltage of the input voltage terminal is much greater than the voltage of the reference voltage terminal, the voltage of the output terminal of the hysteresis comparator is at a high level, the output terminal of the first inverter is at a low level, and the thirteenth NMOS transistor is turned on;

[0019] When the voltage of the input voltage terminal drops to be less than the voltage of the reference voltage terminal, if the difference between the voltage of the reference voltage terminal and the voltage of the input voltage terminal is less than the falling-edge hysteresis voltage, the thirteenth NMOS transistor remains turned on, and the voltage of the output terminal of the hysteresis comparator remains at a high level. If the difference between the voltage of the reference voltage terminal and the voltage of the input voltage terminal is greater than the falling-edge hysteresis voltage, the thirteenth NMOS transistor is turned off, the sixteenth NMOS transistor is turned on, and the voltage of the output terminal of the hysteresis comparator flips to a low level.

[0020] In a possible implementation, the fifth PMOS transistor and the sixth PMOS transistor have the same size, the seventh PMOS transistor and the eighth PMOS transistor have the same size, and the ninth NMOS transistor and the tenth NMOS transistor have the same size.

[0021] In a possible implementation, the eleventh NMOS transistor and the twelfth NMOS transistor have the same size, and the fourteenth NMOS transistor and the fifteenth NMOS transistor have the same size.

[0022] In a possible implementation, the output current of the second current source is equal to the output current of the third current source, so that the rising-edge hysteresis voltage and the falling-edge hysteresis voltage of the hysteresis comparator are equal.

[0023] The technical solution provided by the present disclosure has at least the following beneficial effects:

[0024] The present disclosure provides a hysteresis comparator, which can form an internal positive feedback path and adjust the hysteresis voltage through a current source, thereby ensuring the stability of the hysteresis voltage.

[0025] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1 It is a schematic diagram of the circuit topology of a hysteresis comparator shown in the embodiments of the present disclosure.

[0028] MARKING DESCRIPTION

[0029] I1, the first current source; I2, the second current source; I3, the third current source;

[0030] M1, the first NMOS transistor; M2, the second NMOS transistor; M3, the third NMOS transistor; M4, the fourth NMOS transistor; M5, the fifth PMOS transistor; M6, the sixth PMOS transistor; M7, the seventh PMOS transistor; M8, the eighth PMOS transistor; M9, the ninth NMOS transistor; M10, the tenth NMOS transistor;

[0031] M11, the eleventh NMOS transistor; M12, the twelfth NMOS transistor; M13, the thirteenth NMOS transistor;

[0032] M14, the fourteenth NMOS transistor; M15, the fifteenth NMOS transistor; M16, the sixteenth NMOS transistor;

[0033] INV1, the first inverter; INV2, the second inverter. Detailed implementation manners

[0034] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second", "third" and similar terms used in the specification and claims of this patent application of the disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a" or "an" do not denote a limitation of quantity, but mean that there is at least one. The terms such as "comprising" or "including" mean that the elements or items appearing before "comprising" or "including" cover the elements or items listed after "comprising" or "including" and their equivalents, and do not exclude other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", "right" are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationships may also change accordingly.

[0035] To make the objectives, technical solutions and advantages of this disclosure clearer, the following will further describe the embodiments of this disclosure in detail with reference to the accompanying drawings.

[0036] An embodiment of this disclosure provides a hysteresis comparator. Refer to Figure 1 , the hysteresis comparator includes a switched op-amp circuit and a positive feedback circuit.

[0037] The open-loop op-amp circuit has an input voltage terminal, a reference voltage terminal and an output terminal. When the voltage at the input voltage terminal is greater than the voltage at the reference voltage terminal, the output terminal of the open-loop op-amp circuit outputs a high level. When the voltage at the input voltage terminal is less than the voltage at the reference voltage terminal, the output terminal of the open-loop op-amp circuit outputs a low level.

[0038] The positive feedback circuit includes a switching device and a current source. The switching device is electrically connected to the open-loop op-amp circuit and the current source. The positive feedback circuit is used to form an internal positive feedback path with the open-loop op-amp circuit when the switching device is turned on, and adjust the hysteresis voltage through the current source.

[0039] In this way, the hysteresis comparator can form an internal positive feedback path and adjust the hysteresis voltage through the current source, thereby ensuring the stability of the hysteresis voltage.

[0040] In a possible implementation, referring to Figure 1 , the circuit topology of the open-loop operational amplifier circuit can be: the open-loop operational amplifier circuit includes a first current source I1, a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth NMOS transistor M9, and a tenth NMOS transistor M10.

[0041] Among them, the fifth PMOS transistor M5 and the sixth PMOS transistor M6 are a pair of current mirror transistors, the seventh PMOS transistor M7 and the eighth PMOS transistor M8 are a pair of current mirror transistors, and the ninth NMOS transistor M9 and the tenth NMOS transistor M10 are a pair of current mirror transistors.

[0042] In a possible implementation, the size ratios between the fifth PMOS transistor M5 and the sixth PMOS transistor M6, between the seventh PMOS transistor M7 and the eighth PMOS transistor M8, and between the ninth NMOS transistor M9 and the tenth NMOS transistor M10 can be adjusted according to requirements. For example, the fifth PMOS transistor M5 and the sixth PMOS transistor M6 have the same size, the seventh PMOS transistor M7 and the eighth PMOS transistor M8 have the same size, and the ninth NMOS transistor M9 and the tenth NMOS transistor M10 have the same size.

[0043] The gate and drain of the first NMOS transistor M1, and the gate of the second NMOS transistor M2 are electrically connected to the first current source I1. The source of the second NMOS transistor M2, the source of the first NMOS transistor M1, the source of the ninth NMOS transistor M9, and the source of the tenth NMOS transistor M10 are all grounded. The drain of the second NMOS transistor M2, the source of the third NMOS transistor M3, and the source of the fourth NMOS transistor M4 are electrically connected. The gate of the third NMOS transistor M3 is electrically connected to the reference voltage terminal VN, and the gate of the fourth NMOS transistor M4 is electrically connected to the input voltage terminal VP. The gate and drain of the fifth PMOS transistor M5, the drain of the third NMOS transistor M3, and the gate of the sixth PMOS transistor M6 are electrically connected. The source of the fifth PMOS transistor M5, the source of the sixth PMOS transistor M6, the source of the seventh PMOS transistor M7, and the source of the eighth PMOS transistor M8 are all electrically connected to the positive power supply terminal VDD. The gate and drain of the ninth NMOS transistor M9, the drain of the sixth PMOS transistor M6, and the gate of the tenth NMOS transistor M10 are electrically connected. The gate and drain of the seventh PMOS transistor M7, the drain of the fourth NMOS transistor M4, and the gate of the eighth PMOS transistor M8 are electrically connected. The drain of the tenth NMOS transistor M10 and the drain of the eighth PMOS transistor M8 are both electrically connected to the output terminal Vout of the hysteresis comparator.

[0044] In the above open-loop operational amplifier circuit, for the side of the input voltage terminal VP, the current flowing through the fourth NMOS transistor M4 is equal to the current flowing through the seventh PMOS transistor M7. Also, since the seventh PMOS transistor M7 and the eighth PMOS transistor M8 form a pair of current mirror transistors, the current flowing through the seventh PMOS transistor M7 is copied to the eighth PMOS transistor M8, so that the current flowing through the eighth PMOS transistor M8 is equal to the current flowing through the fourth NMOS transistor M4.

[0045] For the side of the reference voltage terminal VN, the current flowing through the third NMOS transistor M3 is equal to the current flowing through the fifth PMOS transistor M5. Also, since the fifth PMOS transistor M5 and the sixth PMOS transistor M6 form a pair of current mirror transistors, the current flowing through the fifth PMOS transistor M5 is copied to the sixth PMOS transistor M6. The current flowing through the sixth PMOS transistor M6 is equal to the current flowing through the ninth NMOS transistor M9. Also, since the ninth NMOS transistor M9 and the tenth NMOS transistor M10 are a pair of current mirror transistors, the current flowing through the ninth NMOS transistor M9 is copied to the tenth NMOS transistor M10, so that the current flowing through the tenth NMOS transistor M10 is equal to the current flowing through the third NMOS transistor M3.

[0046] Therefore, when the voltage VP of the input voltage terminal is much smaller than the voltage VN of the reference voltage terminal, the voltage of the output terminal Vout of the hysteresis comparator is at a low level. When the voltage VP of the input voltage terminal is much larger than the voltage VN of the reference voltage terminal, the voltage of the output terminal Vout of the hysteresis comparator is at a high level.

[0047] In a possible implementation, referring to Figure 1 , the circuit topology of the positive feedback circuit can be: the positive feedback circuit includes a first inverter INV1, a second inverter INV2, a second current source I2, an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, a thirteenth NMOS transistor M13, a third current source I3, a fourteenth NMOS transistor M14, a fifteenth NMOS transistor M15, and a sixteenth NMOS transistor M16.

[0048] Among them, the eleventh NMOS transistor M11 and the twelfth NMOS transistor M12 form a pair of current mirror transistors, and the fourteenth NMOS transistor M14 and the fifteenth NMOS transistor M15 form a pair of current mirror transistors.

[0049] In a possible implementation, the size ratio between the eleventh NMOS transistor M11 and the twelfth NMOS transistor M12, and the size ratio between the fourteenth NMOS transistor M14 and the fifteenth NMOS transistor M15 can be adjusted according to requirements. For example, the sizes of the eleventh NMOS transistor M11 and the twelfth NMOS transistor M12 are the same, and the sizes of the fourteenth NMOS transistor M14 and the fifteenth NMOS transistor M15 are the same.

[0050] The gate and drain of the eleventh NMOS transistor M11 and the gate of the twelfth NMOS transistor M12 are electrically connected to the second current source I2. The sources of the eleventh NMOS transistor M11 and the twelfth NMOS transistor M12 are both grounded. The drain of the twelfth NMOS transistor M12 is electrically connected to the source of the thirteenth NMOS transistor M13, and the drain of the thirteenth NMOS transistor M13 is electrically connected to the drain of the fourth NMOS transistor M4. Among them, the thirteenth NMOS transistor M13 is a switching device.

[0051] The gate and drain of the fourteenth NMOS transistor M14 and the gate of the fifteenth NMOS transistor M15 are electrically connected to the third current source I3. The sources of the fourteenth NMOS transistor M14 and the fifteenth NMOS transistor M15 are both grounded. The drain of the fifteenth NMOS transistor M15 is electrically connected to the source of the sixteenth NMOS transistor M16, and the drain of the sixteenth NMOS transistor M16 is electrically connected to the drain of the third NMOS transistor M3. Among them, the sixteenth NMOS transistor M16 is a switching device.

[0052] The input terminal of the first inverter INV1 is electrically connected to the drain of the eighth PMOS transistor M8. The output terminal VoutB of the first inverter INV1 and the input terminal of the second inverter INV2 are electrically connected to the gate of the sixteenth NMOS transistor M16. The output terminal of the second inverter INV2 is electrically connected to the gate of the thirteenth NMOS transistor M12, and the output terminal of the second inverter INV2 is the output terminal Vout of the hysteresis comparator.

[0053] In the above positive feedback circuit, when the voltage VP at the input voltage terminal is much smaller than the voltage VN at the reference voltage terminal, the voltage Vout at the output terminal of the hysteresis comparator is at a low level, and the output terminal VoutB of the first inverter INV1 is at a high level. Then, the thirteenth NMOS transistor M13 is turned off, and the sixteenth NMOS transistor M16 is turned on.

[0054] When the voltage VP at the input voltage terminal gradually increases but is still smaller than the voltage VN at the reference voltage terminal, since the sixteenth NMOS transistor M16 is turned on, the output current of the third current source I3 will flow through the fourteenth NMOS transistor M14. And since the fourteenth NMOS transistor M14 and the fifteenth NMOS transistor M15 are a pair of current mirror transistors, the current flowing through the fourteenth NMOS transistor M14 is copied to the fifteenth NMOS transistor M15, and this current flows into the fifth PMOS transistor M5 through the sixteenth NMOS transistor M16, and through the fifth PMOS transistor M5, the sixth PMOS transistor M6 and the ninth NMOS transistor M9, the current is copied to the tenth NMOS transistor M10, so that the current flowing through the tenth NMOS transistor M10 is greater than the current flowing through the eighth PMOS transistor M8. Therefore, the voltage Vout at the output terminal of the hysteresis comparator is still at a low level.

[0055] When the voltage VP at the input voltage terminal gradually rises to be equal to the voltage VN at the reference voltage terminal, the current of the fourteenth NMOS transistor M14 will pass through the fifteenth NMOS transistor M15, the sixteenth NMOS transistor M16, the fifth PMOS transistor M5, the sixth PMOS transistor M6, and the ninth NMOS transistor M9, and is copied to the tenth NMOS transistor M10, making the current flowing through the tenth NMOS transistor M10 greater than the current flowing through the eighth PMOS transistor M8. Therefore, the voltage Vout at the output terminal of the hysteresis comparator remains low.

[0056] When the voltage VP at the input voltage terminal gradually rises to be greater than the voltage VN at the reference voltage terminal, if the difference between the voltage VP at the input voltage terminal and the voltage VN at the reference voltage terminal is less than the rising-edge hysteresis voltage, the sixteenth NMOS transistor M16 remains conducting, and the voltage Vout at the output terminal of the hysteresis comparator remains low. If the difference between the voltage VP at the input voltage terminal and the voltage VN at the reference voltage terminal is greater than the rising-edge hysteresis voltage, the sixteenth NMOS transistor M16 turns off, and the thirteenth NMOS transistor M13 turns on, and the voltage Vout at the output terminal of the hysteresis comparator flips to high level.

[0057] When the voltage VP at the input voltage terminal is much greater than the voltage VN at the reference voltage terminal, the voltage Vout at the output terminal of the hysteresis comparator is high level, the output terminal VoutB of the first inverter INV1 is low level, then the thirteenth NMOS transistor M13 turns on, and the sixteenth NMOS transistor M16 turns off.

[0058] When the voltage VP at the input voltage terminal gradually decreases but is still greater than the voltage VN at the reference voltage terminal, since the thirteenth NMOS transistor M13 is conducting, the output current of the second current source I2 will flow through the eleventh NMOS transistor M11. And since the eleventh NMOS transistor M11 and the twelfth NMOS transistor M12 are a pair of current mirror transistors, the current flowing through the eleventh NMOS transistor M11 is copied to the twelfth NMOS transistor M12, and this current flows into the seventh PMOS transistor M7 through the thirteenth NMOS transistor M13 and is copied to the eighth PMOS transistor M8, making the current flowing through the eighth PMOS transistor M8 greater than the current flowing through the tenth NMOS transistor M10. Therefore, the voltage Vout at the output terminal of the hysteresis comparator remains high.

[0059] When the voltage VP at the input voltage terminal gradually decreases to be equal to the voltage VN at the reference voltage terminal, the current of the eleventh NMOS transistor M11 will pass through the twelfth NMOS transistor M12, the thirteenth NMOS transistor M13, and the seventh PMOS transistor M7, and is copied to the eighth PMOS transistor M8, making the current flowing through the eighth PMOS transistor M8 greater than the current flowing through the tenth NMOS transistor M10. Therefore, the voltage Vout at the output terminal of the hysteresis comparator remains high.

[0060] When the voltage VP at the input voltage terminal decreases to be less than the voltage VN at the reference voltage terminal, if the difference between the voltage VN at the reference voltage terminal and the voltage VP at the input voltage terminal is less than the falling-edge hysteresis voltage, the thirteenth NMOS transistor M13 remains conducting, and the voltage Vout at the output terminal of the hysteresis comparator remains high. If the difference between the voltage VN at the reference voltage terminal and the voltage VP at the input voltage terminal is greater than the falling-edge hysteresis voltage, the thirteenth NMOS transistor M13 turns off, and the sixteenth NMOS transistor M16 turns on, and the voltage Vout at the output terminal of the hysteresis comparator flips to low level.

[0061] Next, the calculation methods of the rising-edge hysteresis voltage and the falling-edge hysteresis voltage will be introduced:

[0062] The second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 are all in the subthreshold region, and the following formula (1) can be obtained:

[0063]

[0064] Among them, gm2 is the transconductance of the second NMOS transistor M2, gm3 is the transconductance of the third NMOS transistor M3, and gm4 is the transconductance of the fourth NMOS transistor M4.

[0065] When VP - VN = ΔV1, since the sizes of the seventh PMOS transistor M7 and the eighth PMOS transistor M8 are equal, the current flowing through the eighth PMOS transistor M8 is:

[0066]

[0067] Among them, I8 is the current flowing through the eighth PMOS transistor M8, Itail is the output current of the first current source I1, and ΔV1 is the rising-edge hysteresis voltage.

[0068] Combining formula (1) and formula (2) can obtain:

[0069]

[0070] Since the fifth PMOS transistor M5 and the sixth PMOS transistor M6 have the same size, and the ninth NMOS transistor M9 and the tenth NMOS transistor M10 have the same size, the current flowing through the tenth NMOS transistor M10 is:

[0071]

[0072] where, I 10 is the current flowing through the tenth NMOS transistor M10, and Ihyst1 is the output current of the third current source I3.

[0073] Combining formula (1) and formula (4), we can get:

[0074]

[0075] Since the eighth PMOS transistor M8 and the tenth NMOS transistor M10 are connected in series on the same branch, although the currents flowing through the eighth PMOS transistor M8 and the tenth NMOS transistor M10 may be different at the moment when the sixteenth NMOS transistor M16 is turned on, the currents flowing through the eighth PMOS transistor M8 and the tenth NMOS transistor M10 will eventually be equal. Therefore, the following equation can be obtained:

[0076] I8 = I 10 (6)

[0077] Combining formula (3), formula (5) and formula (6), the calculation formula for the rising-edge hysteresis voltage of the hysteresis comparator can be obtained as follows:

[0078]

[0079]

[0080]

[0081] where, ζ is a preset constant related to the process, K is the Boltzmann constant, T is the temperature, and Q is the electric charge of an electron.

[0082] Similarly, when VN - VP = ΔV2, since the fifth PMOS transistor M5 and the sixth PMOS transistor M6 have the same size, and the ninth NMOS transistor M9 and the tenth NMOS transistor M10 have the same size, the current flowing through the tenth PMOS transistor M10 is:

[0083]

[0084] where, ΔV2 is the falling-edge hysteresis voltage.

[0085] The seventh PMOS transistor M7 and the eighth PMOS transistor M8 have the same size. Therefore, the current flowing through the eighth PMOS transistor M8 is:

[0086]

[0087] Among them, Ihyst2 is the output current of the second current source I2.

[0088] Combining formula (10), formula (11) and formula (6), the calculation formula for the falling-edge hysteresis voltage of the hysteresis comparator is as follows:

[0089]

[0090] In summary, the total hysteresis voltage of the whole process is ΔV1 + ΔV2.

[0091] In a possible implementation, the output current of the second current source I2 and the output current of the third current source I3 can be equal, so that the rising-edge hysteresis voltage and the falling-edge hysteresis voltage of the hysteresis comparator are equal, thereby improving the output stability of the hysteresis comparator.

[0092] In summary, the technical solution provided by the present disclosure at least includes the following beneficial effects: The present disclosure provides a hysteresis comparator, which can form an internal positive feedback path and adjust the hysteresis voltage through a current source, thereby ensuring the stability of the hysteresis voltage.

[0093] The above are only optional embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A hysteresis comparator, characterized in that, The hysteresis comparator includes an open-loop operational amplifier circuit and a positive feedback circuit; The positive feedback circuit includes a switching device and a current source. The switching device is electrically connected to the open-loop operational amplifier circuit and the current source. The positive feedback circuit is configured to form an internal positive feedback path with the open-loop operational amplifier circuit when the switching device is turned on, and adjust the hysteresis voltage through the current source.

2. The hysteresis comparator according to claim 1, wherein The open-loop operational amplifier circuit includes a first current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor. Among them, the fifth PMOS transistor and the sixth PMOS transistor are a pair of current mirror transistors, the seventh PMOS transistor and the eighth PMOS transistor are a pair of current mirror transistors, and the ninth NMOS transistor and the tenth NMOS transistor are a pair of current mirror transistors; The gate and drain of the first NMOS transistor, and the gate of the second NMOS transistor are electrically connected to the first current source. The source of the second NMOS transistor, the source of the first NMOS transistor, the source of the ninth NMOS transistor, and the source of the tenth NMOS transistor are all grounded. The drain of the second NMOS transistor, the source of the third NMOS transistor, and the source of the fourth NMOS transistor are electrically connected. The gate of the third NMOS transistor is electrically connected to the reference voltage terminal, and the gate of the fourth NMOS transistor is electrically connected to the input voltage terminal. The gate and drain of the fifth PMOS transistor, and the drain of the third NMOS transistor are electrically connected to the gate of the sixth PMOS transistor. The source of the fifth PMOS transistor, the source of the sixth PMOS transistor, the source of the seventh PMOS transistor, and the source of the eighth PMOS transistor are all electrically connected to the positive power supply terminal. The gate and drain of the ninth NMOS transistor, and the drain of the sixth PMOS transistor are electrically connected to the gate of the tenth NMOS transistor. The gate and drain of the seventh PMOS transistor, and the drain of the fourth NMOS transistor are electrically connected to the gate of the eighth PMOS transistor. The drain of the tenth NMOS transistor and the drain of the eighth PMOS transistor are both electrically connected to the output terminal of the hysteresis comparator.

3. The hysteresis comparator according to claim 2, wherein When the voltage at the input voltage terminal is much smaller than the voltage at the reference voltage terminal, the voltage at the output terminal of the hysteresis comparator is at a low level.

4. The hysteresis comparator according to claim 2, characterized in that When the voltage at the input voltage terminal is much larger than the voltage at the reference voltage terminal, the voltage at the output terminal of the hysteresis comparator is at a high level.

5. The hysteresis comparator according to claim 2, wherein The positive feedback circuit includes a first inverter, a second inverter, a second current source, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a third current source, a fourteenth NMOS transistor, a fifteenth NMOS transistor, and a sixteenth NMOS transistor. Among them, the eleventh NMOS transistor and the twelfth NMOS transistor are a pair of current mirror transistors, and the fourteenth NMOS transistor and the fifteenth NMOS transistor are a pair of current mirror transistors; The gate and drain of the eleventh NMOS transistor, and the gate of the twelfth NMOS transistor are electrically connected to the second current source. The source of the eleventh NMOS transistor and the source of the twelfth NMOS transistor are both grounded. The drain of the twelfth NMOS transistor is electrically connected to the source of the thirteenth NMOS transistor, and the drain of the thirteenth NMOS transistor is electrically connected to the drain of the fourth NMOS transistor; The gate and drain of the fourteenth NMOS transistor, and the gate of the fifteenth NMOS transistor are electrically connected to the third current source. The source of the fourteenth NMOS transistor and the source of the fifteenth NMOS transistor are both grounded. The drain of the fifteenth NMOS transistor is electrically connected to the source of the sixteenth NMOS transistor, and the drain of the sixteenth NMOS transistor is electrically connected to the drain of the third NMOS transistor; The input terminal of the first inverter is electrically connected to the drain of the eighth PMOS transistor. The output terminal of the first inverter and the input terminal of the second inverter are electrically connected to the gate of the sixteenth NMOS transistor. The output terminal of the second inverter is electrically connected to the gate of the thirteenth NMOS transistor, and the output terminal of the second inverter is the output terminal of the hysteresis comparator.

6. The hysteresis comparator according to claim 5, characterized in that, When the voltage of the input voltage terminal is much smaller than the voltage of the reference voltage terminal, the voltage of the output terminal of the hysteresis comparator is at a low level, the output terminal of the first inverter is at a high level, and the sixteenth NMOS transistor is turned on; When the voltage of the input voltage terminal rises to be greater than the voltage of the reference voltage terminal, if the difference between the voltage of the input voltage terminal and the voltage of the reference voltage terminal is less than the rising-edge hysteresis voltage, the sixteenth NMOS transistor remains turned on, and the voltage of the output terminal of the hysteresis comparator remains at a low level. If the difference between the voltage of the input voltage terminal and the voltage of the reference voltage terminal is greater than the rising-edge hysteresis voltage, the sixteenth NMOS transistor is turned off, the thirteenth NMOS transistor is turned on, and the voltage of the output terminal of the hysteresis comparator flips to a high level.

7. The hysteresis comparator according to claim 5, characterized in that When the voltage of the input voltage terminal is much greater than the voltage of the reference voltage terminal, the voltage of the output terminal of the hysteresis comparator is at a high level, the output terminal of the first inverter is at a low level, and the thirteenth NMOS transistor is turned on; When the voltage of the input voltage terminal drops to be less than the voltage of the reference voltage terminal, if the difference between the voltage of the reference voltage terminal and the voltage of the input voltage terminal is less than the falling-edge hysteresis voltage, the thirteenth NMOS transistor remains turned on, and the voltage of the output terminal of the hysteresis comparator remains at a high level. If the difference between the voltage of the reference voltage terminal and the voltage of the input voltage terminal is greater than the falling-edge hysteresis voltage, the thirteenth NMOS transistor is turned off, the sixteenth NMOS transistor is turned on, and the voltage of the output terminal of the hysteresis comparator flips to a low level.

8. The hysteresis comparator according to claim 5, wherein The fifth PMOS transistor and the sixth PMOS transistor have the same size. The seventh PMOS transistor and the eighth PMOS transistor have the same size. The ninth NMOS transistor and the tenth NMOS transistor have the same size.

9. The hysteresis comparator according to claim 5, characterized in that, The eleventh NMOS transistor and the twelfth NMOS transistor have the same size, and the fourteenth NMOS transistor and the fifteenth NMOS transistor have the same size.

10. The hysteresis comparator according to claim 5, characterized in that, The output current of the second current source is equal to the output current of the third current source, so that the rising-edge hysteresis voltage of the hysteresis comparator is equal to the falling-edge hysteresis voltage.

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