Embedded power supply package

Abstract

The disclosure relates to an embedded power supply package (100), comprising: at least one input pin (111) for receiving an input power signal (11) and at least one output pin (112) for providing an output power signal (12) and at least one control pin (14) for receiving a control signal; a power circuitry (124) for converting the input power signal (11) to the output power signal (12); a driving circuitry (123) for energizing the power circuitry (124), wherein the driving circuitry (123) is configured to be driven based on the control signal; an input filter circuitry (125) comprising at least one capacitor for filtering the input power signal (11); and at least three substrate layers (110, 120, 130) stacked above each other. The power circuitry (124), the driving circuitry (123) and the input filter circuitry (125) are each embedded in one or more of the at least three substrate layers (110, 120, 130).

Description

[0001] EMBEDDED POWER SUPPLY PACKAGE

[0002] TECHNICAL FIELD

[0003] The disclosure relates to the field of Power Supplies in Package (PSiP) and specifically to an embedded power supply package. The disclosure particularly relates to Power Supplies in Package using advanced 3D stacking.

[0004] BACKGROUND

[0005] Power Supplies in Package (PSiP) for modem applications such as telecom, datacenter, consumer devices are required to feature high power conversion efficiencies in ultra-thin and small footprint dimensions. The current package technologies limit the achievable efficiencies and power densities at high currents, switching frequencies, and conversion ratios due to high parasitic components and thermal resistances.

[0006] SUMMARY

[0007] This disclosure provides a solution for an electronic package suitable forPSiPs which allows the use of more advanced power topologies while minimizing the increase of height, area, and parasitics.

[0008] The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

[0009] Embodiments as described in this disclosure introduce a novel system module (referred to as embedded power supply module hereinafter) that is composed of substrate (e.g., PCB) layers stacked above each other seamless connected together using sinter lamination, hybrid bonding or soldering and under filling technology and others. The presented 3D package supports component embedding in-between the core layers and blind vias, which allow for better volume optimization and reduction of the parasitic components. Double-side cooling is also supported.

[0010] The disclosed embedded power supply module provides a superior PSiP which can meet height specifications in ultra-flat designs, area requirements in ultra-compact designs. The disclosed embedded power supply module reduces losses and undesirable noise in more complex circuits.

[0011] Since all the components of the disclosed PSIP package are embedded in their respective substrates, the overall height of the PSiP solution will be lower than for conventional PSiP packages.

[0012] Since the components of the disclosed PSiP package are embedded in multiple vertical layers and interlayers, the footprint of the different components overlaps. This minimizes the overall footprint area of the PSiP and allows for the implementation of more complex (with more components) power stage topologies.

[0013] Since the position of components of the disclosed PSiP can be defined in the vertical and horizontal directions, they can be placed in the optimal location to reduce undesirable parasitic resistances and inductances. In contrast, the vertical degree of freedom for component placement is limited in conventional PSiP packages. In order to describe the disclosure in detail, the following terms and notations will be used.

[0014] PSiP Power Supplies in Package

[0015] PMIC Power Management Integrated Circuit

[0016] SMD Surface Mounted Device

[0017] PoL Point of Load

[0018] EV Electric Vehicle

[0019] SiP System in Package

[0020] IC Integrated Circuit

[0021] PCB Printed Circuit Board

[0022] Prepreg Pre-impregnated

[0023] PWM pulse width modulation

[0024] Power Supplies in Package (PSiP) are integrated modules used in several applications such as datacenters, automotive, consumer electronics, etc. These power supplies have to comply very stringent volume and area specifications, therefore feature a very high level of integration. For that reason, the power supply is operated at very high frequencies and requires advanced technologies in package and heat removal domains. A PSiP is usually composed of: Power Management circuitry (active devices) including power transistors, driving, and control circuitries; and sampling and filtering circuits (passive devices) including capacitors, inductors, transformers, and resistors.

[0025] According to a first aspect, the disclosure relates to an embedded power supply package, comprising: at least one input pin for receiving an input power signal and at least one output pin for providing an output power signal and at least one control pin for receiving a control signal; a power circuitry for converting the input power signal to the output power signal; a driving circuitry for energizing the power circuitry, wherein the driving circuitry is configured to be driven based on the control signal; an input filter circuitry comprising at least one capacitor for filtering the input power signal; and at least three substrate layers stacked above each other; wherein the power circuitry, the driving circuitry and the input filter circuitry are each embedded in one or more of the at least three substrate layers.

[0026] Such embedded power supply package is suitable for PSiPs and allows the use of more advanced power topologies while minimizing the increase of height, area, and parasitics. In particular, undesired parasitic components can be reduced resulting in power loss reduction and lower ringing EMC problems due to reduced parasitic resistances and inductances respectively. Ultra-thin designs can be achieved with no or only minimal increase of footprint. Thermal performance can be improved by using double side cooling.

[0027] In an exemplary implementation of the embedded power supply package, the embedded power supply package comprises: a control circuitry for controlling the driving circuitry; and an output filter circuitry for filtering the output power signal; wherein the control circuitry and the output filter circuitry are each embedded in one or more of the at least three substrate layers.

[0028] When the control circuitry is embedded in the power supply package, the output voltage control and / or phase current control is implemented locally, control paths can be shorter and reaction times canbe faster. On the other side, when an external control circuitry is implemented, footprint of the package can be reduced.

[0029] In an exemplary implementation of the embedded power supply package, the control signal comprises a reference signal for regulating an output voltage of the at least one output pin; and the control circuitry is configured to provide a pulse width modulation, PWM, signal based on the reference signal for use by the driving circuitry to drive the power circuitry. In that way, the power circuitry can be optimally adjusted for providing the correct output voltage and output power.

[0030] In an exemplary implementation of the embedded power supply package, the embedded power supply package comprises: one or more auxiliary passive electronic components for generating different voltage levels in the power circuitry, for usage as current sensors and / or for usage as resonant tanks; wherein the one or more auxiliary passive electronic components are each embedded in one or more of the at least three substrate layers.

[0031] By embedding the auxiliary passive electronic components together with the driving circuitry, the power circuitry and the control circuitry in the substrate layers, different functionalities can be implemented such as current sensing, input / output filtering, etc.

[0032] In an exemplary implementation of the embedded power supply package, each substrate layer comprises one or more vias, e.g., metal vias; wherein the one or more vias comprise through vias electrically connecting all substrate layers and / or blind vias electrically connecting only adjacent substrate layers of the at least three substrate layers.

[0033] These vias provide suitable electrical connections between the substrate layers in order to efficiently connect the embedded components by direct electrical paths which reduces parasitic effects.

[0034] In an exemplary implementation of the embedded power supply package, the one or more vias vertically connect the embedded electronic components of the at least three substrate layers with each other providing one or more vertical electrical current paths through the respective substrate layer.

[0035] These vertical electrical current paths provide direct current paths resulting in fast connection, reduced parasitics and fast switching, in particular when the embedded components are distributed over multiple substrate layers.

[0036] In an exemplary implementation of the embedded power supply package, at least part of a via of the one or more vias is formed by an embedded passive electronic component.

[0037] This allows reducing the footprint since the embedded passive electronic component which may be required for filtering can be implemented together with the via required for electrical connection.

[0038] In an exemplary implementation of the embedded power supply package, at least part of a via of the one or more vias is formed by an inductor.

[0039] This results in an efficient design since there is no need for extra connections in between layers in opposite direction of the main power flow.

[0040] In an exemplary implementation of the embedded power supply package, each substrate layer comprises a first main face and a second main face in opposite direction to the first main face; wherein each substrate layer comprises input and output pins arranged on the first main face and / or the second main face of the respective substrate layer for providing electrical contacts to embedded electronic components of the respective substrate layer.

[0041] This results in design flexibility since each substrate layer can be electrically connected by the input and output pins at its first and second main faces. In an exemplary implementation of the embedded power supply package, a first one and a second one of the at least three substrate layers are core substrate layers and a third one of the at least three substrate layers is an inter-substrate connection layer connecting the first substrate layer to the second substrate layer; or a first one, a second one and a third one of the at least three substrate layers are core substrate layers; wherein a fourth one of the at least three substrate layers is an inter-substrate connection layer connecting the first substrate layer to the second substrate layer; and wherein a fifth one of the at least three substrate layers is another inter-substrate connection layer connecting the first substrate layer to the third substrate layer.

[0042] This allows flexible designs with two substrate layers and one inter-substrate connection layer or with three substrate layers and two inter-substrate connection layers or with other configurations of substrate layers and inter-substrate connection layers.

[0043] In an exemplary implementation of the embedded power supply package, the inter-substrate connection layers each comprise one or a combination of the following: a sinter lamination layer, a hybrid bonding layer, a soldering and sintering lamination layer.

[0044] By such inter-substrate connection layers, efficient, robust and stable connection of the substrate layers can be achieved.

[0045] In an exemplary implementation of the embedded power supply package, each of the inter-substrate connection layers forms a non-remelting electrical and mechanical connection between their respective connecting substrate layers.

[0046] Such non-remelting electrical and mechanical connection forms a solid and durable connection between the substrate layers.

[0047] In an exemplary implementation of the embedded power supply package, at least one of the inter-substrate connection layers comprises embedded passive electronic components.

[0048] By that feature, the inter-substrate connection layers can be efficiently exploited, i.e., not only for connection of the substrate layers but also for embedding passive electronic components. This allows reducing the footprint of the embedded power supply package.

[0049] In an exemplary implementation of the embedded power supply package, the power circuitry, the driving circuitry and the control circuitry are integrated in a power management integrated circuit, the power management integrated circuit being embedded in one of the at least three substrate layers.

[0050] Such power management integrated circuit can efficiently manage and control the power switches for an efficient operation of the power supply.

[0051] In an exemplary implementation of the embedded power supply package, each of the at least three substrate layers is made of one of the following: a printed circuit board, a laminate material layer, a prepreg material layer, a ceramic substrate, an FR4 material layer.

[0052] Different manufacturing techniques and different materials can be flexible applied for producing the embedded power supply package.

[0053] In an exemplary implementation of the embedded power supply package, the embedded power supply package comprises: a number of N second power circuitries, a number of N second driving circuitries and a number of N second control circuitries embedded in the same substrate layers as the power circuitry, the driving circuitry and the control circuitry; or embedded in substrate layers stacked above the substrate layers embedding the power circuitry, the driving circuitry and the control circuitry. N can be any integer number, e.g., 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0054] This results in a high-performance solution when multiple power circuitries can be implemented in one package. Integration of multiple such circuitries in a single package may allow for higher power densities.

[0055] According to a second aspect, the disclosure relates to a method for manufacturing an embedded power supply package, the method comprising: stacking at least three substrate layers above each other; and embedding each of a power circuitry, a driving circuitry for energizing the power circuitry, and an input filter circuitry comprising at least one capacitor in one or more of the at least three substrate layers; wherein the power circuitry is configured to convert an input power signal received at one or more input pins of the embedded power supply package to an output power signal provided at one or more output pins of the embedded power supply package; wherein the driving circuitry is configured to be driven based on a control signal received at one or more control pins of the embedded power supply package; and wherein the input filter circuitry is configured to filter the input power signal.

[0056] Such a method allows manufacturing an embedded power supply package which is suitable for PSiPs and allows the use of more advanced power topologies while minimizing the increase of height, area, and parasitics. In particular, undesired parasitic components can be reduced resulting in power loss reduction and lower ringing EMC problems due to reduced parasitic resistances and inductances respectively. Ultra-thin designs can be manufactured by such method with no or only minimal increase of footprint. Thermal performance can be improved by using double side cooling.

[0057] The embedded power supply package presented in this disclosure allows for placement optimization of the components and reduction of undesired parasitic components, in particular power loss reduction due to reduced parasitic resistance; and lower ringing EMC problems due to reduced parasitic inductances.

[0058] The embedded power supply package presented in this disclosure allows for customization of embedding processes. Different types of components may be embedded in different boards. This allows to facilitate fabrication and mounting process. Each layer can be customized for specific component types. Each layer can be tested prior to lamination. A better system yield can be achieved and more components can be implemented per board.

[0059] The embedded power supply package presented in this disclosure can be used in more complex systems, such as systems with multiple layers with different functionalities. In such system no (or minimal) increase of footprint area is required and ultrathin designs can be implemented.

[0060] The embedded power supply package presented in this disclosure provides improved thermal performance. Double side cooling is possible. Components can be attached to heatsink or thermal vias. A direct heat path from top and bottom side heat sinks can be implemented. The system power density can be increased.

[0061] The embedded power supply package presented in this disclosure facilitates fabrication and mounting process. A reduced number of steps can be achieved with respective cost reduction.

[0062] The embedded power supply package presented in this disclosure allows better overall system protection by improved physical protection of the components, tracks, and vias; prevention against reverse engineering and counterfeiting; and shielding of components with metal layer and vias. The embedded power supply package presented in this disclosure allows for inter-substrate layers. Components can be embedded in-between substrate layers which adds to the compactness of the system.

[0063] The embedded power supply package presented in this disclosure provides a high reliability. A solderless assembly can be realized. All components are protected inside the module. Lower parasitic contributes to robustness of the power circuit.

[0064] The embedded power supply package presented in this disclosure provides a most prominent ultra-thin solution of PSiPs package for high power density applications.

[0065] BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Further embodiments of the disclosure will be described with respect to the following figures, in which:

[0067] Figure 1 shows a schematic diagram of an embedded power supply package 100 according to an embodiment;

[0068] Figure la shows two schematic diagrams illustrating an embedded power supply package 100a, 100b without control circuitry with input capacitor in layer 2 (left side) or in interlayer 1 (right side) according to an embodiment;

[0069] Figure lb shows two schematic diagrams illustrating an embedded power supply package 100c, lOOd with control circuitry and additional voltage sample port 113 with input capacitor in layer 2 (left side) or in interlayer 1 (right side) according to an embodiment;

[0070] Figure 1c shows two schematic diagrams illustrating an embedded power supply package 100c, lOOf with single input port and multiple output ports with input capacitor in layer 2 (left side) or in interlayer 1 (right side) according to an embodiment;

[0071] Figure Id shows two schematic diagrams illustrating an embedded power supply package 100g, lOOh with input capacitor in layer 2 and output capacitor in layer 1 (left side) or with input capacitor in interlayer 1 and output capacitor in interlayer 1 (right side) according to an embodiment;

[0072] Figure le shows two schematic diagrams illustrating an embedded power supply package lOOi, lOOj with multiple output ports and multiple output capacitors in layer 1 (left side) or in interlayer 1 (right side) according to an embodiment;

[0073] Figure If shows two schematic diagrams illustrating an embedded power supply package 100k, 1001 with control circuitry and additional voltage sample port 113 and resistive current sensor 117 and with input capacitor in layer 2 and output capacitor in layer 1 (left side) or with input and output capacitors in interlayer 1 (right side) according to an embodiment;

[0074] Figure 1g shows a schematic diagram illustrating an embedded power supply package 100m with control circuitry and additional voltage sample port 113 with input and output filters, current sensor 117 and auxiliary circuitry according to an embodiment;

[0075] Figure 2 shows two cross-section views of the embedded power supply package 100 shown in Figure 1 after production (upper view) and during production (lower view) according to an embodiment;

[0076] Figure 3 shows a schematic diagram of an embedded power supply package 300 according to an embodiment; Figure 4 shows two cross-section views of the embedded power supply package 300 shown in Figure 3 after production (upper view) and during production (lower view) according to an embodiment;

[0077] Figure 5 shows a schematic diagram of an embedded power supply package 500 according to an embodiment;

[0078] Figure 6 shows a cross-section view of the embedded power supply package 500 shown in Figure 5 according to an embodiment;

[0079] Figure 7 shows a schematic diagram of an embedded power supply package 700 according to an embodiment; and

[0080] Figure 8 shows a 3D view of an embedded power supply package 800 according to an embodiment.

[0081] DETAILED DESCRIPTION OF EMBODIMENTS

[0082] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the disclosure is defined by the appended claims.

[0083] It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

[0084] In this disclosure, hybrid bonding layers and hybrid bond sheets are described. A hybrid bonding layer is a layer produced by a hybrid bond sheet. Such hybrid bond sheet comprises: a thermally conductive core layer having an upper main face and a lower main face opposing the upper main face; a first bond layer formed at the upper main face of the core layer for bonding the hybrid bond sheet to a semiconductor power module, for example; and a second bond layer formed at the lower main face of the core layer for bonding the hybrid bond sheet to a heat sink, for example. The core layer is subdivided into a plurality of core metal sections and core polymer sections which are formed side-by-side between the upper main face and the lower main face, the subdivided core metal sections being configured to enable a uniform heat transfer between the semiconductor power module and the heat sink and to reduce thermal stress at interfaces between the hybrid bond sheet and the heat sink.

[0085] Figure 1 shows a schematic diagram of an embedded power supply package 100 according to an embodiment. Figure 1 shows an embodiment of the embedded power supply package 100 with embedded control circuitry 122. However, in a minimum configuration such control functionality can also be implemented in an external control circuitry, it is not required to be implemented in the embedded power supply package 100. Such a minimum configuration, also referred to as (most) basic configuration (or concept), is depicted in Figure la described below.

[0086] The embedded power supply package 100 comprises: at least one input pin 111 for receiving an input power signal 11 and at least one output pin 112 for providing an output power signal 12 and at least one control pin 14 for receiving a control signal. The embedded power supply package 100 comprises: a power circuitry 124 for converting the input power signal 11 to the output power signal 12; a driving circuitry 123 for energizing the power circuitry 124. The driving circuitry 123 is configured to be driven based on the control signal.

[0087] The embedded power supply package 100 comprises: an input filter circuitry 125 comprising at least one capacitor for filtering the input power signal 111; and at least three substrate layers 110, 120, 130 stacked above each other.

[0088] The power circuitry 124, the driving circuitry 123 and the input filter circuitry 125 are each embedded in one or more of the at least three substrate layers 110, 120, 130.

[0089] Figure 1 shows an exemplary implementation with a first substrate layer 110, a second substrate layer 120 and a third substrate layer 130 which is a first interlayer while Figure 5 shows an exemplary implementation with a first substrate layer 110, a second substrate layer 120, a third substrate layer 140, a fourth substrate layer 130 which is a first interlayer and a fifth substrate layer 150 which is a second interlayer.

[0090] The embedded power supply package may comprise: a control circuitry 122 for controlling the driving circuitry 123; and an output filter circuitry 115 for filtering the output power signal 112. The control circuitry 122 and the output filter circuitry 115 are each embedded in one or more of the at least three substrate layers 110, 120, 130.

[0091] The control signal may comprise a reference signal for regulating an output voltage of the at least one output pin 112. The control circuitry 122 may be configured to provide a pulse width modulation (PWM) signal based on the reference signal for use by the driving circuitry to drive the power circuitry 124.

[0092] The embedded power supply package 100 may comprise one or more auxiliary passive electronic components 116 for generating different voltage levels in the power circuitry, for usage as current sensors and / or for usage as resonant tanks. The one or more auxiliary passive electronic components 116 are each embedded in one or more of the at least three substrate layers 110, 120, 130.

[0093] Each substrate layer 110, 120, 130 may comprise one or more vias, e.g., metal vias 139, 159 (shown in Figure 5). These one or more vias 139, 159 may comprise through vias electrically connecting all substrate layers 110, 120, 130 and / or blind vias electrically connecting only adjacent substrate layers of the at least three substrate layers 110, 120, 130.

[0094] The one or more vias 139, 159 may vertically connect the embedded electronic components of the at least three substrate layers 110, 120, 130 with each other providing one or more vertical electrical current paths through the respective substrate layer 110, 120, 130.

[0095] At least part of a via 139, 159 of the one or more vias 139, 159 may be formed by an embedded passive electronic component 115.

[0096] At least part of a \ via 139, 159 of the one or more vias 139, 159 may be formed by an inductor 09 as shown in Figure 2.

[0097] Each substrate layer 110, 120, 130, 140, 150 may comprise a first main face 110a, 120a and a second main face 110b, 120b in opposite direction to the first main face 110a, 120a. Each substrate layer 110, 120, 130, 140, 150 may comprises input and output pins 119, 129 arranged on the first main face 110a, 120a and / or the second main face 110b, 120b of the respective substrate layer 110, 120, 130, 140, 150 for providing electrical contacts to embedded electronic components of the respective substrate layer 110, 120, 130, 140, 150.

[0098] A first one 110 and a second one 120 of the at least three substrate layers may be core substrate layers and a third one 130 of the at least three substrate layers may be an inter-substrate connection layer 130 connecting the first substrate layer 110 to the second substrate layer 120 as shown in the embodiments of Figure 1 and 2, Figures la to 1g, Figure 3 and 4.

[0099] Alternatively a first one 110, a second one 120 and a third one 140 of the at least three substrate layers may be core substrate layers, a fourth one 130 of the at least three substrate layers may be an inter-substrate connection layer 130 connecting the first substrate layer 110 to the second substrate layer 120; and a fifth one 150 of the at least three substrate layers may be another inter-substrate connection layer 150 connecting the first substrate layer 110 to the third substrate layer 140 as shown in the embodiments of Figure 5 and 6.

[0100] The inter-substrate connection layers 130, 150 may each comprise one or a combination of the following: a sinter lamination layer, a hybrid bonding layer, a soldering and sintering lamination layer.

[0101] Each of the inter-substrate connection layers 130, 150 may form a non-remelting electrical and mechanical connection between their respective connecting substrate layers 110, 120, 140.

[0102] At least one of the inter-substrate connection layers 130, 150 may comprise embedded passive electronic components 136, e.g., as shown in Figure 3.

[0103] The power circuitry 124, the driving circuitry 123 and the control circuitry 122 may be integrated in a power management integrated circuit 121. The power management integrated circuit 121 may be embedded in one of the at least three substrate layers 110, 120, 130.

[0104] Each of the at least three substrate layers 110, 120, 130 may be made of one of the following: a printed circuit board, a laminate material layer, a prepreg material layer, a ceramic substrate, an FR4 material layer.

[0105] The embedded power supply package 100 may comprise: a second power circuitry 124a, a second driving circuitry 123a and a second control circuitry 122 embedded in the same substrate layers 110, 120, 130 as the power circuitry 124, the driving circuitry 123 and the control circuitry 122; or embedded in substrate layers stacked above the substrate layers 110, 120, 130 embedding the power circuitry 124, the driving circuitry 123 and the control circuitry 122.

[0106] Embodiments with a second power circuitry 124a and a second driving circuitry 123a are shown in Figures 1c, le and 8.

[0107] Figure la shows two schematic diagrams illustrating an embedded power supply package 100a, 100b without control circuitry with input capacitor in layer 2 (left side) or in interlayer 1 (right side) according to an embodiment. As described above, such embedded power supply package 100a, 100b represents the basic configuration or structure of an embedded power supply package, where no control circuitry is required to be embedded in the package, since the control circuitry can be externally.

[0108] These embodiments of embedded power supply packages 100a, 100b correspond to the basic structure of such package without control circuitry 122 shown in Figure 1. In these embodiments, a driving signal, e.g., a PWM signal is received by the driving circuitry 123 from external, e.g., from an external control circuitry. The PWM signal is used by the driving circuitry 123 to control the respective switches of the power circuitry 124. In that way, the switches of the power circuitry 124 can switch according to the PWM signal. The driving signal (PWM) can be received at the same control pin 14 which receives the control signal for the control circuitry 122 as shown in Figure 1 or it can be received at another one of the control pins 14.

[0109] In the embedded power supply package 100a shown on the left side of F igure 1 a, the input capacitor forming the input filter circuitry 125 is arranged in layer 2.

[0110] In the embedded power supply package 100b shown on the right side of Figure la, the input capacitor forming the input filter circuitry 125 is arranged in interlayer 1.

[0111] Figure lb shows two schematic diagrams illustrating an embedded power supply package 100c, lOOd with control circuitry and additional voltage sample port 113 with input capacitor in layer 2 (left side) or in interlayer 1 (right side) according to an embodiment.

[0112] These embodiments of embedded power supply packages 100c, lOOd correspond to the basic structure of such package including control circuitry 122. In these embodiments, a voltage sample signal for regulation of the output voltage is received by the control circuitry 122 from external, e.g., from an external controller. In that way, the power circuitry 124 can be controlled to adjust the desired output voltage at the output pins 112. The voltage sample signal can be received at one or more voltage sample pins 113. These pins 113 can be separate pins or some of the control pins 14.

[0113] In the embedded power supply package 100c shown on the left side of Figure lb, the input capacitor forming the input filter circuitry 125 is arranged in layer 2.

[0114] In the embedded power supply package lOOd shown on the right side of Figure lb, the input capacitor forming the input filter circuitry 125 is arranged in interlayer 1.

[0115] Figure 1c shows two schematic diagrams illustrating an embedded power supply package 100c, lOOf with single input port and multiple output ports with input capacitor in layer 2 (left side) or in interlayer 1 (right side) according to an embodiment.

[0116] Each port is correlated to only one net of the circuit. One pin is correlated to one port (several different pins can be correlated to one port). In an exemplary configuration, a first port comprises a first pin, a second pin and a third pin; and a second port comprises a first pin, a second pin and a third pin. Other configurations can also be implemented for input and output ports.

[0117] These embodiments of embedded power supply packages 100c, lOOf are variations of the embedded power supply packages 100a, 100b shown in Figure la. In these embodiments, single input multiple output configurations are shown. That means a single input port 111 is implemented to receive the input power signal 11 that is provided to multiple power circuitries 124, 124a, e.g., a number of N power circuitries 124, 124a which may be implemented in Layer 2. The driving signal (PWM) that is received at the one or more control pins 14 is provided to a signal control entity 133 that may be implemented in Layer 2. The signal control entity 133 is configured to control multiple driving circuitries 123, 123a which may be implemented in Layer 2. The signal control entity 133 has the function to generate phase-shift for the driving circuitries 123, 123a based on which they can control the switches of the power circuitries 124, 124a. The output pins 112, 112a may also be connected in some cases.

[0118] In the embedded power supply package 100c shown on the left side of Figure 1c, the input capacitor forming the input filter circuitry 125 is arranged in layer 2. In the embedded power supply package lOOf shown on the right side of Figure 1c, the input capacitor forming the input filter circuitry 125 is arranged in interlayer 1.

[0119] Figure Id shows two schematic diagrams illustrating an embedded power supply package 100g, lOOh with input capacitor in layer 2 and output capacitor in layer 1 (left side) or with input capacitor in interlayer 1 and output capacitor in interlayer 1 (right side) according to an embodiment.

[0120] These embodiments of embedded power supply packages 100g, lOOh are variations of the embedded power supply packages 100a, 100b shown in Figure la.

[0121] In the embedded power supply package 100g shown on the left side of Figure Id, the input capacitor forming the input filter circuitry 125 is arranged in layer 2 and the inductor and capacitor forming the output filter circuitry 115 are arranged in layer 1.

[0122] In the embedded power supply package lOOh shown on the right side of Figure Id, the input capacitor forming the input filter circuitry 125 is arranged in interlayer 1 and the capacitor forming the output filter circuitry 115 (together with an inductor) is arranged in interlayer 1 while the inductor forming the output filter circuitry 115 (together with the above capacitor) is arranged in layer 1.

[0123] Figure le shows two schematic diagrams illustrating an embedded power supply package lOOi, lOOj with multiple output port and multiple output capacitors in layer 1 (left side) or in interlayer 1 (right side) according to an embodiment.

[0124] These embodiments of embedded power supply packages lOOi, lOOj are variations of the embedded power supply packages 100c, lOOf shown in Figure 1c with multiple outputs and corresponding output capacitors.

[0125] In the embedded power supply package lOOi shown on the left side of Figure le, the output capacitors forming with the corresponding inductors the output filter circuitries 115 are arranged in layer 1. The input capacitor forming the input filter circuitry 125 is arranged in layer 2.

[0126] In the embedded power supply package lOOj shown on the right side of Figure le, the output capacitors forming with the corresponding inductors the output filter circuitries 115 are arranged in interlayer 1 while the inductors of the output filter circuitries 115 are arranged in layer 1. The input capacitor forming the input filter circuitry 125 is arranged in interlayer 1.

[0127] Figure If shows two schematic diagrams illustrating an embedded power supply package 100k, 1001 with control circuitry and additional voltage sample port 113 and resistive current sensor 117 and with input capacitor in layer 2 and output capacitor in layer 1 (left side) or with input and output capacitors in interlayer 1 (right side) according to an embodiment.

[0128] These embodiments of embedded power supply packages 100k, 1001 are variations of the embedded power supply packages 100c, lOOd shown in Figure lb with input and output capacitors and resistive current sensor. Other types of current sensors can also be implemented.

[0129] In the embedded power supply package 100k shown on the left side of Figure If, the output filter circuitry 115 comprises a capacitor, an inductor and a resistive current sensor 117. The current sensor 117, the inductor and the capacitor of the output filter circuitry 115 are arranged in Layer 1. The input capacitor forming the input filter circuitry 125 is arranged in layer 2. In the embedded power supply package 1001 shown on the right side of Figure If, the output filter circuitry 115 comprises a capacitor, an inductor and a resistive current sensor 117. The current sensor 117 and the inductor of the output filter circuitry 115 are arranged in Layer 1 while the capacitor of the output filter circuitry 115 is arranged in interlayer 1. The input capacitor forming the input filter circuitry 125 is arranged in interlayer 1.

[0130] Figure 1g shows a schematic diagram illustrating an embedded power supply package 100m with control circuitry and additional voltage sample port 113 with input and output filters, current sensor 117 and auxiliary circuitry 117a according to an embodiment.

[0131] This embodiment of embedded power supply packages 100m is a variation of the embedded power supply packages 100c, lOOd shown in Figure lb with input and output filters, current sensor and auxiliary circuitry for more complex power converter topologies.

[0132] In the embedded power supply package 100m, the output filter circuitry 115 comprises a capacitor, an inductor and a resistive current sensor 117. The current sensor 117 and the inductor of the output filter circuitry 115 are arranged in Layer 1 while the capacitor of the output filter circuitry 115 is arranged in interlayer 1. The input capacitor forming the input filter circuitry 125 is arranged in interlayer 1. A further capacitor representing the auxiliary circuitry 117a is arranged in interlayer 1. This capacitor of auxiliary circuitry 117a may be configured to generate different voltage levels.

[0133] Figure 2 shows two cross-section views of the embedded power supply package 100 shown in Figure 1 after production (upper view) and during production (lower view) according to an embodiment.

[0134] That means, the upper view illustrates the final product while the lower view illustrates the intermediate product during production while connecting the first layer 100 to the second layer 120 by the first interlayer 130.

[0135] Figure 2 together with Figure 1 illustrate the main concept of the disclosed embedded power supply package as described in the following.

[0136] The reference signs in Figure 2 have the following meaning:

[0137] 01 : FR4 or ceramic substrate.

[0138] 02: Thermal interface material.

[0139] 03 : Surface mount capacitor.

[0140] 04 : Power Management IC, PMIC.

[0141] 05 : Solder connection.

[0142] 06 : Thick copper pillar vias / or copper blocks.

[0143] 07 : magnetic material.

[0144] 08 : Pre-preg with cutouts.

[0145] 09: Pre-packaged inductor.

[0146] 10: Thick copper traces / planes.

[0147] 11 : input power port.

[0148] 12 : output power port.

[0149] 13: Ground port.

[0150] 14: Signal port.

[0151] 15 : Copper via connection.

[0152] 16: Inter-substrate connection. 17: Sinter paste.

[0153] 18 : Sintered copper strip.

[0154] 19 : Silicon interposer.

[0155] Figure 1 shows the schematics of the basic PSiP concept and the division of components in different core substrate layers. Figure 2 depicts the cross section view of the presented PSiP package 100 corresponding to the schematic of Figure 1. The distinguishing features of the presented PSiP are described below and correlated to Figures 1 and 2.

[0156] A PSiP may contain at least a driving circuitry, power circuitry, auxiliary passives, input filter, output filter. The PSiP may contain other circuitries, e.g., control circuitry, sensing circuitry, protection circuitry, etc.

[0157] In Figure 1, the presented PSiP 100 is composed of a control circuitry 122, driving circuitry 123, power circuitry 124, auxiliary passives 116, input filter 125, output filter 115.

[0158] In Figure 2, the control circuitry 122, driving circuitry 123, power circuitry 124 are integrated in a PMIC 04. The input filter and auxiliary capacitors are of ceramic type embedded in layer 2. The output filter is composed of an inductor and a capacitor embedded in layer 1.

[0159] A PSiP contains at least an input power port, an output power port, a ground port, and a signal input port. The PSiP may contain other types of port and in different quantities.

[0160] In Figures 1 and 2, the input power port 11, output power port 12, ground port 13, and signal input port 14 are located in layer 1.

[0161] The basic PSiP concept is composed by minimum two core substrate layers and one interlayer in between (see Figures 5 and 6 for a number of layers greater than 2). The core layer may be made from different non-conductive substrates and the interlayers may be made of insulated prepreg materials which can be later sintered to connect the two core layers.

[0162] In Figure 1, layer 1 and layer 2 are the core layers and interlayer 1 is the interlayer in between layer 1 and layer 2.

[0163] In Figure 2, the core layers 1 and 2 are made from conventional PCB material (FR4) or ceramic and the interlayer is made of conventional prepreg material 08.

[0164] The core layers 01 may contain embedded components of one type or different types, through vias or no components. The interlayers may contain the interconnects between the layers on top and on bottom and may also contain embedded components (see Figures 1 and 2).

[0165] In Figure 1, layer 1 contains only passive components (inductors, capacitors). In Figure 2, the passive components may be composed of a pre-assembled inductor and a ceramic capacitor (3) composing the output filter of the PSiP. Since one terminal of the inductor may be connected to the top and the other on the bottom of its embedding layer, this component can act as a magnetic via for the main power path. Layer 1 may also contain through vias made of copper (06) which can be used to bring the input power, ground, and input signal from layer 1 to layer 2.

[0166] In Figure 1, Interlayer 1 may contain the interconnects between layer 1 and layer 2. In Figure 1, Layer 2 may contain active and passive components. In Figure 2, the active components can be monolithically integrated in the PMIC and the input filter ceramic capacitor may be embedded directly in layer 2.

[0167] The embedded components in the core layers may have connections to the layers’ port or can be connected only to components inside its own layer.

[0168] In Figure 1, the passive components of layer 2 can also be connected to the layers’ port (therefore also to other layers through vias), while some passive components of layer 1 may be connected only within its own layer.

[0169] In Figure 2, the input capacitor (capacitor connected to the input port) may be connected to input and ground ports which can be connected to layers 1 and 2 through interlayer 1. The positive terminal of the output capacitor (capacitor connected to the output port) may not be connected to layer 2 while the negative terminal may be connected to the ground port. The connections of the components to the metal layers of the substrate 10 can be done using soldering 05 or copper via 15, for example.

[0170] The electrical interconnects between the main core layers can be performed using several methods, including: sinter lamination, hybrid bonding or by soldering and under filling.

[0171] In Figure 2, the inter layer (inter substrate) connection 16 can be made of sinter paste 17 which is melted during the lamination process.

[0172] The PSiP 100 using the disclosed 3D package concept can be used in a lot of applications with very stringent volume and area specifications. Example of applications are: 1) PoL conversion for xPU systems in datacenters / telecom systems; 2) BMP supplies for datacenters / telecom systems; 3) PoL conversion for ASICs and xPU systems in EV applications; 4) DC-DC converters for battery voltage interface in EV applications; 5) PoL conversion for consumer business applications (smartphone, laptop, etc).

[0173] The presented solution is scalable in number of stacked layers (see Figures 5 and 6) and may contain components embedded in-between the main core layers (see Figure 1 to 4).

[0174] Figure 3 shows a schematic diagram of an embedded power supply package 300 according to an embodiment and Figure 4 shows two cross-section views of the embedded power supply package 300 shown in Figure 3 after production (upper view) and during production (lower view) according to an embodiment.

[0175] The presented PSiP may contain components embedded in the interlayers. This concept is shown in Figures 3 and 4. Figure 3 shows the schematics of the PSiP or embedded power supply package 300 according to an embodiment and the division of components in different core substrate layers and interlayer. Figure 4 depicts the cross section view of the PSiP 300 corresponding to the schematic of Figure 3. The distinguishing features of this embodiment are described below and corelated to Figures 3 and 4.

[0176] All the distinguishing features of the main idea described above with respect to Figures 1 and 2 are valid for this embodiment with the addition of the following distinguishing features: 1. Components of the PSiP circuitry may be embedded in the interlayers. a) Compared to Figure 1, in Figure 3 the capacitors of the input filter circuitry, output filter circuitry and auxiliary circuitry are moved from layer 2 to interlayer 1. Since the auxiliary circuitry and input filter circuitry need to be connected to the active devices of the PSiP (power circuitry, driving circuitry, control circuitry) they are bonded to layer 2. Since the capacitors of the output filter circuitry need to be connected to the output port of the PSiP, they are bonded to layer 1. b) In Figure 4, compared to Figure 2, the ceramic capacitors of the input filter circuitry, output filter circuitry and auxiliary circuitry are replaced by silicon capacitors embedded in silicon interposers (19) in order to keep a low profile. In order to compensate for the height of the embedded capacitors in the interlayers, copper strips / spacers (18) are added to the interconnects (16).

[0177] 2. Process for assembling the 3D stack with inter-layer components can be done by: a) Mounting the capacitors and copper spacers on top of the respective layer; b) Soldering / sintering the components and spacers on top of the PCB; c) Sinter laminating or hybrid bonding the layers together.

[0178] Figure 5 shows a schematic diagram of an embedded power supply package 500 according to an embodiment and Figure 6 shows a cross-section view of the embedded power supply package 500 shown in Figure 5 according to an embodiment.

[0179] The disclosed PSiP or embedded power supply package 500 may have more than two substrate layers with embedded components. This concept is shown in Figures 5 and 6. Figure 5 shows the schematics of the PSiP 500 and the division of components in different core substrate layers and interlayers. Figure 6 depicts the cross section view of the PSiP 500 corresponding to the schematic of Figure 5. The distinguishing features of the PSiP 500 according to this embodiment are described below and corelated to Figures 5 and 6.

[0180] All the distinguishing features of the main idea described above with respect to Figures 1 and 2 and of the embodiment described with respect to Figures 3 and 4 are valid for this embodiment with the addition of the following distinguishing features:

[0181] The disclosed PSiP 500 may contain more than 2 substrate layers with embedded components. Figure 5 and 6 depict the case in which the number of layers is equal to three and the number of interlayers is equal to two. The concept can be extended for number of layers being equal to n and number of interlayers being equal to n-1. a) Compared to Figures 1 and 3, Figure 5 contains three layers and two interlayers, all with embedded components. Compared to Figure 1 the capacitors of the input filters are placed in interlayers 1 and 2 to reduce the total input impedance. Since the auxiliary circuitry and input filter circuitry need to be connected to the active devices of the PSiP (power circuitry, driving circuitry, control circuitry) they are placed in interlayer 2 and bonded to layer 3. Since the capacitors of the output filter circuitry need to be connected to the output port of the PSiP, they are placed in interlayer 1 and bonded to layer 1. Since the inductor of the output filter is connected between the active part of the PSiP and the output capacitor, it is placed in layer 2. Figure 7 shows a schematic diagram of an embedded power supply package 700 according to an embodiment.

[0182] The power circuitry 124 which is implemented Layer 2 (120) may comprise multiple power switches. Each switch may be connected to a capacitor of the input filter circuitry 125. The capacitors may be embedded in Interlayer 1 (130). The input filter circuitry 125 which may be implemented by a capacitor, may be embedded in interlayer 1 (130) and Interlayer 2 (150). The output filter circuitry 115 with inductors and a capacitor (116) may be embedded in Layer 1 (110) and interlayer 2. Auxiliary passive electronic components (116a), e.g., capacitors to generate DC voltage levels may be embedded in Interlayer 1 (130).

[0183] Figure 8 shows a 3D view of an embedded power supply package 800 according to an embodiment.

[0184] In this embodiment the power supply package 800 comprises a second power circuitry 124a, a second driving circuitry 123a and a second control circuitry 122 which are embedded side-by-side in the same substrate layers 110, 120, 130 as the power circuitry 124, the driving circuitry 123 and the control circuitry 122 shown in Figures 1 and 2. Instead of only one second power circuitry 124a, second driving circuitry 123a and second control circuitry 122, a number of N second power circuitries 124a, a number of N second driving circuitries 123a and a number of N second control circuitries 122 may be embedded side-by-side in the same substrate layers 110, 120, 130.

[0185] In an alternative configuration (not shown here in Figure 8), the second power circuitry 124a, the second driving circuitry 123a and the second control circuitry 122 may be embedded in substrate layers stacked above the substrate layers 110, 120, 130 embedding the power circuitry 124, the driving circuitry 123 and the control circuitry 122.

[0186] Instead of only one second power circuitry 124a, second driving circuitry 123a and second control circuitry 122, a number of N second power circuitries 124a, a number of N second driving circuitries 123a and a number of N second control circuitries 122 may be embedded in substrate layers stacked above the substrate layers 110, 120, 130. A combination of embedding these second power circuitry 124a, second driving circuitry 123a and second control circuitry 122 side-by-side and in stacked substrate layers can also be implemented.

[0187] Embodiments of the embedded power supply package as described in this disclosure provide a PSiP using 3D stacking concept. The concept utilizes 3D stacking and direct metallic and blind connections between the components that are embedded inside pre-assembled substrates (e.g., PCBs). Such a design allows reduction of undesired parasitic components and provides power loss reduction due to reduced parasitic resistance; and lower ringing EMC problems due to reduced parasitic inductances. The PSiP can be designed with no or only minimal increase of footprint area and ultra-thin designs can be provided. Thermal performance can be improved and double side cooling can be implemented.

[0188] Embodiments of the embedded power supply package as described in this disclosure provide a PSiP using 3D stacking concept with inter-layer embedded components. The concept utilizes 3D stacking and direct metallic and blind connections between the components that are embedded inside pre-assembled substrates (e.g., PCBs) and laminated / soldered in-between the main core layers. SuchPSiPs can be used in more complex systems, e.g., systems with multiple layers with different functionalities.

[0189] Embodiments of the embedded power supply package as described in this disclosure provide a PSiP using 3D stacking concept with multiple layers and inter-layers. Such PSiPs can be used in more complex systems, e.g., systems with multiple layers with different functionalities.

[0190] While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g. " are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

[0191] Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and / or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

[0192] Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

[0193] Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the disclosure beyond those described herein. While the disclosure has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the disclosure. It is therefore to be understood that within the scope of the appended claims and their equivalents, the disclosure may be practiced otherwise than as specifically described herein.

Claims

CLAIMS1. An embedded power supply package (100), comprising:At least one input pin (111) for receiving an input power signal (11) and at least one output pin (112) for providing an output power signal (12) and at least one control pin (14) for receiving a control signal; a power circuitry (124) for converting the input power signal (11) to the output power signal (12); a driving circuitry (123) for energizing the power circuitry (124), wherein the driving circuitry (123) is configured to be driven based on the control signal; an input filter circuitry (125) comprising at least one capacitor for filtering the input power signal (111); and at least three substrate layers (110, 120, 130) stacked above each other; wherein the power circuitry (124), the driving circuitry (123) and the input filter circuitry (125) are each embedded in one or more of the at least three substrate layers (110, 120, 130).

2. The embedded power supply package (100) of claim 1, comprising: a control circuitry (122) for controlling the driving circuitry (123); and an output filter circuitry (115) for filtering the output power signal (112); wherein the control circuitry (122) and the output filter circuitry (115) are each embedded in one or more of the at least three substrate layers (110, 120, 130).

3. The embedded power supply package (100) of claim 2, wherein the control signal comprises a reference signal for regulating an output voltage of the at least one output pin (112); wherein the control circuitry (122) is configured to provide a pulse width modulation, PWM, signal based on the reference signal for use by the driving circuitry to drive the power circuitry (124).

4. The embedded power supply package (100) of any of the preceding claims, comprising: one or more auxiliary passive electronic components (117) for generating different voltage levels in the power circuitry (124), for usage as current sensors (117) and / or for usage as resonant tanks; wherein the one or more auxiliary passive electronic components (117) are each embedded in one or more of the at least three substrate layers (110, 120, 130).

5. The embedded power supply package (100) of any of the preceding claims, wherein each substrate layer (110, 120, 130) comprises one or more vias (139, 159);wherein the one or more vias (139, 159) comprise through vias electrically connecting all substrate layers (110, 120, 130) and / or blind vias electrically connecting only adjacent substrate layers of the at least three substrate layers (110, 120, 130).

6. The embedded power supply package (100) of claim 5, wherein the one or more vias (139, 159) vertically connect the embedded electronic components of the at least three substrate layers (110, 120, 130) with each other providing one or more vertical electrical current paths through the respective substrate layer (110, 120, 130).

7. The embedded power supply package (100) of claim 5 or 6, wherein at least part of avia (139, 159) of the one or more vias (139, 159) is formed by an embedded passive electronic component (115).

8. The embedded power supply package (100) of any of claims 5 to 7, wherein at least part of a via (139, 159) of the one or more vias (139, 159) is formed by an inductor (09).

9. The embedded power supply package (100) of any of the preceding claims, wherein each substrate layer (110, 120, 130, 140, 150) comprises a first main face (110a, 120a) and a second main face (110b, 120b) in opposite direction to the first main face (110a, 120a); wherein each substrate layer (110, 120, 130, 140, 150) comprises input and output pins (119, 129) arranged on the first main face (110a, 120a) and / or the second main face (110b, 120b) of the respective substrate layer (110, 120, 130, 140, 150) for providing electrical contacts to embedded electronic components of the respective substrate layer (110, 120, 130, 140, 150).

10. The embedded power supply package (100) of any of the preceding claims, wherein a first one (110) and a second one (120) of the at least three substrate layers are core substrate layers and a third one (130) of the at least three substrate layers is an inter-substrate connection layer (130) connecting the first substrate layer (110) to the second substrate layer (120); or wherein a first one (110), a second one (120) and a third one (140) of the at least three substrate layers are core substrate layers; wherein a fourth one (130) of the at least three substrate layers is an inter-substrate connection layer (130) connecting the first substrate layer (110) to the second substrate layer (120); and wherein a fifth one (150) of the at least three substrate layers is another inter-substrate connection layer (150) connecting the first substrate layer (110) to the third substrate layer (140).

11. The embedded power supply package (100) of claim 10, wherein the inter-substrate connection layers (130, 150) each comprise one or a combination of the following: a sinter lamination layer, a hybrid bonding layer,a soldering and sintering lamination layer.

12. The embedded power supply package (100) of claim 10 or 11, wherein each of the inter-substrate connection layers (130, 150) forms a non-remelting electrical and mechanical connection between their respective connecting substrate layers (110, 120, 140).

13. The embedded power supply package (100) of any of claims 10 to 12, wherein at least one of the inter-substrate connection layers (130, 150) comprises embedded passive electronic components (136).

14. The embedded power supply package (100) of any of the preceding claims referring back to claim 2, wherein the power circuitry (124), the driving circuitry (123) and the control circuitry (122) are integrated in a power management integrated circuit (121), the power management integrated circuit (121) being embedded in one of the at least three substrate layers (110, 120, 130).

15. The embedded power supply package (100, 100c, 100c) of any of the preceding claims referring back to claim 2, comprising: a number of N second power circuitries (124a), a number of N second driving circuitries (123a) and a number of N second control circuitries (122) embedded in the same substrate layers (110, 120, 130) as the power circuitry (124), the driving circuitry (123) and the control circuitry (122); or embedded in substrate layers stacked above the substrate layers (110, 120, 130) embedding the power circuitry (124), the driving circuitry (123) and the control circuitry (122).

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